WO2019007346A1 - 具有沟槽内渐变厚度的场板结构的半导体器件的制造方法 - Google Patents

具有沟槽内渐变厚度的场板结构的半导体器件的制造方法 Download PDF

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WO2019007346A1
WO2019007346A1 PCT/CN2018/094365 CN2018094365W WO2019007346A1 WO 2019007346 A1 WO2019007346 A1 WO 2019007346A1 CN 2018094365 W CN2018094365 W CN 2018094365W WO 2019007346 A1 WO2019007346 A1 WO 2019007346A1
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trench
silicon oxide
nitrogen
manufacturing
containing compound
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French (fr)
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祁树坤
孙贵鹏
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无锡华润上华科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • the present application relates to the field of semiconductor fabrication, and more particularly to a method of fabricating a semiconductor device having a field plate structure having a graded thickness within a trench.
  • MOSFET metal oxide semiconductor field effect transistor
  • MOSFETs having a trench field plate structure based on a constant thickness are particularly common.
  • the constant thickness of the field plate medium due to the constant thickness of the field plate medium, the uneven distribution of potential and electric field makes the device characteristics difficult to optimize.
  • a method of fabricating a semiconductor device having a field plate structure having a graded thickness within a trench is provided.
  • a method of fabricating a semiconductor device having a field plate structure having a gradual thickness in a trench comprising: step A, forming a trench on a surface of the wafer; and step B, filling the trench with silicon oxide by deposition; step C Removing a portion of the surface of the silicon oxide in the trench by etching; in step D, forming a silicon oxide corner structure at a corner of the top of the trench by thermal oxidation, the silicon oxide corner structure being downward from the corner and located in the trench a structure in which the silicon oxide inside the trench is gradually thickened; in step E, a nitrogen-containing compound is deposited on the surface of the wafer to cover the surface of the silicon oxide in the trench and the surface of the silicon oxide corner structure; step F, dry etching The nitrogen-containing compound removes a nitrogen-containing compound on the surface of the silicon oxide in the trench, and the surface of the silicon oxide corner structure forms a sidewall of the nitrogen-containing compound extending in the trench; and step G, the nitrogen-containing compound The sidewall remains as
  • the sidewall residue of the nitrogen-containing compound is further extended into the trench every time step F is performed, and the silicon oxide in the trench includes bottom silicon oxide and sidewall silicon oxide, and the thickness of the sidewall silicon oxide is from the trench
  • the top of the trench is gradually thickened to the bottom of the trench; in step H, the nitrogen-containing compound in the trench is removed; in step I, polysilicon is filled into the trench.
  • FIG. 1 is a flow chart showing a method of fabricating a semiconductor device having a field plate structure having a graded thickness within a trench in an embodiment
  • FIGS. 2 to 6 are cross-sectional views of a device manufactured by a method of fabricating a semiconductor device having a field plate structure having a graded thickness in a trench in a manufacturing process.
  • the vocabulary of the semiconductor field used herein is a technical vocabulary commonly used by those skilled in the art, for example, for P-type and N-type impurities, to distinguish the doping concentration, the simple P+ type represents a heavily doped concentration of the P-type, and the P-type represents P type with doping concentration, P-type represents P type with light doping concentration, N+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents light doping concentration N type.
  • a conventional semiconductor device having a field plate having a gradual thickness in a deep trench is formed by chemical vapor deposition (CVD) of a thin oxygen layer on a deep trench inner wall, and then forming a sacrificial layer, followed by etch-back Sacrificating the layer to a certain depth while etching the thin oxygen layer; the second oxide layer is formed by thermal oxidation, the sacrificial layer is formed again, and then the sacrificial layer is etched back and the oxide layer is etched, thereby making the first thin oxygen
  • a thicker oxide layer formed by a second thermal oxidation is added to the layer.
  • the subsequent oxide layer, sacrificial layer, and etching are similar to the above, until finally a multi-layered gradient in-slot field plate structure with a bottom thick oxygen and a top thin oxygen is formed.
  • the manufacturing method includes multiple oxidation and etching, which increases the back-diffusion of the substrate to the epitaxial layer to a certain extent, increases the process time, and reduces the production efficiency.
  • FIG. 1 is a flow chart of a method of fabricating a semiconductor device having a field plate structure having a graded thickness within a trench, including the following steps:
  • the deep trench may be etched on the surface of the wafer (in this embodiment, a silicon wafer) by a process known in the art, and the specific depth may be selected according to the design parameters of the device with reference to the prior art.
  • a silicon nitride film may be formed on the surface of the wafer before etching to form a trench, and then an etching window is patterned on the silicon nitride film through the photoresist, and then etched through the etching window.
  • a trench is formed through the silicon nitride film, and a silicon nitride layer is formed around the top of the trench after the etching is completed.
  • the trench is etched by using CHCl 3 and/or CH 2 Cl 2 as an etchant, and in other embodiments, other trench etchings known in the art may be used. The process is etched.
  • a low doping concentration epitaxial layer is epitaxially grown on a highly doped concentration substrate by an epitaxial process, and the etched trench is formed in the epitaxial layer.
  • step S120 is a deposition of silicon oxide by a high density plasma chemical vapor deposition (HDPCVD) process to obtain a better morphology.
  • a silicon oxide layer may also be deposited by other deposition processes known in the art according to actual needs.
  • the excess silicon oxide layer can be removed by chemical mechanical polishing (CMP), that is, the silicon oxide layer exposed outside the trench is removed.
  • CMP is to polish the silicon oxide layer to the silicon nitride layer.
  • step S130 is performed by a high density plasma etching process.
  • a special corner morphology is formed by oxidation after etching, that is, the surface of the silicon oxide in the trench is similar to a hemispherical shape. Concave. From the corner, the silicon oxide inside the trench gradually thickens to form a rounded corner, as shown in FIG. In Fig. 2, a trench is formed on the surface of the silicon wafer, the trench is filled with silicon oxide 202, and a silicon nitride layer 302 is formed around the top of the trench.
  • the silicon oxide corner structure is obtained by low temperature oxidation of 800 to 950 degrees Celsius.
  • Low temperature oxidation is used because the inventors have found that if a higher temperature (for example, sacrificial oxidation of 1000 degrees Celsius) is used, the doping ions in the high concentration substrate of the wafer are easily de-amplified into the low concentration epitaxial layer 102, the device Performance has a negative impact.
  • a higher temperature for example, sacrificial oxidation of 1000 degrees Celsius
  • a thin layer of nitrogen-containing compound is formed by chemical vapor deposition, which is subsequently used as a hard mask for etching.
  • the nitrogen-containing compound may be silicon nitride, silicon oxynitride, boron nitride, titanium nitride or the like, and silicon nitride which is commonly used in the art may be employed in view of universality.
  • the nitrogen-containing compound on the surface of the silicon oxide 202 in the trench is removed by the anisotropy of the dry etching, and the sidewall of the nitrogen-containing compound extending in the trench is formed on the surface of the silicon oxide corner structure.
  • the nitrogen-containing compound sidewall residue 304 serves as a sidewall structure of the trench together with a portion of the silicon oxide 202 in the trench.
  • the silicon oxide 202 is etched to a deeper depth due to etching, while the silicon oxide 202 at the sidewall portion of the trench is also retained by the barrier of the nitrogen-containing compound sidewall residue 304, and the remaining silicon oxide remains. 202 gradually thickens from the bottom of the nitrogen-containing compound sidewall residue 304.
  • the use of the nitrogen-containing compound sidewall residue 304 as a hard mask etch can eliminate the need for a lithographic plate and saves cost.
  • the step S170 may be dry etching, and in this embodiment, high-density plasma etching is employed.
  • step S170 If the etching in step S170 is too deep, the shape of the silicon oxide 202 of the sidewall cannot be ensured. Therefore, the steps of S150 to S170 above are sequentially repeated, and the etching is performed multiple times until the desired thickness of the bottom silicon oxide is obtained. See Figure 5. That is to say, the solution can conveniently adjust the thickness of the bottom silicon oxide, further increasing the space for reducing the feedback capacitance. The specific depth of each etch requires experimentation to collect data. After etching to the desired bottom silicon oxide thickness, the silicon oxide in the trench includes bottom silicon oxide and sidewall silicon oxide, and the thickness of the sidewall silicon oxide is gradually thickened from the top of the trench to the bottom of the trench.
  • wet etching may be employed, for example, etching with concentrated phosphoric acid as an etchant.
  • etching with concentrated phosphoric acid as an etchant.
  • the silicon nitride layer 302 and the nitrogen-containing compound sidewall residue 304 are removed together by concentrated phosphoric acid.
  • the polysilicon 404 is backfilled into the trench as shown in FIG.
  • the polysilicon 404 can be planarized by chemical mechanical polishing.
  • the field plate structure composed of the silicon oxide 202 is formed without performing thermal oxidation once every time, thereby reducing oxidation time and improving production. effectiveness. Moreover, the back diffusion of the substrate impurities to the epitaxial layer is reduced, and the process is simple, and the aspect ratio of the trench etching is not excessively strict.
  • the step of performing sidewall oxidation on the trench before the step S120 is further included.
  • the sidewall oxidation may serve to repair the defects of the trench etched in the inner wall of the trench and the silicon surface at the bottom of the trench in step S110, for example, defects caused by high-energy particle collision by reactive ion etching, eliminating the defect to generate gate oxide The negative impact.
  • the resulting silicon oxide may also be stripped after oxidation of the sidewalls.
  • step S230 is to grow a thin layer of high temperature oxide film (HTO).
  • HTO high temperature oxide film
  • the above-described method of fabricating a semiconductor device having a field plate structure having a gradual thickness in a trench is particularly suitable for a metal oxide semiconductor field effect transistor, and is also applicable to other semiconductor devices which can employ a trench field plate structure.

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Abstract

一种具有沟槽内渐变厚度的场板结构的半导体器件的制造方法，包括：步骤A，在晶圆表面形成沟槽；步骤 B，通过淀积向沟槽内填充氧化硅；步骤C，将沟槽内的氧化硅通过刻蚀去除掉表面的一部分；步骤 D，通过热氧化在沟槽顶部的拐角处形成氧化硅拐角结构；步骤 E，在晶圆表面淀积含氮化合物；步骤 F，干法刻蚀含氮化合物，氧化硅拐角结构表面形成向沟槽内延伸的含氮化合物侧壁残留；步骤 G，以含氮化合物侧壁残留为掩膜，通过刻蚀去除掉沟槽内的氧化硅表面的一部分；依次重复执行步骤E至步骤 G，直至将沟槽内的氧化硅刻蚀至所需的底部氧化硅厚度；步骤 H，去除沟槽内的含氮化合物；步骤 I，向沟槽内填入多晶硅。

Description

具有沟槽内渐变厚度的场板结构的半导体器件的制造方法 技术领域
本申请涉及半导体制造领域，特别是涉及一种具有沟槽内渐变厚度的场板结构的半导体器件的制造方法。
背景技术
为了降低能耗、节省能源，低压功率金属氧化物半导体场效应管(MOSFET)技术在进行持续的技术改进，场板、超结等器件结构也由高压功率器件移植到低压器件中，并加以改进和优化，以降低低压功率器件的比导通电阻。
这其中，基于恒定厚度的具有沟槽场板结构的MOSFET尤为常见。但正由于恒定的场板介质厚度导致了电势、电场的分布不均，使得器件特性难以优化。
基于已有的深槽刻蚀技术，如何简化工艺流程、节省mask层数，达到相同特性的多层渐变厚度的器件隔离结构，是业界持续改善、优化的方向。
发明内容
根据本申请的各种实施例，提供一种具有沟槽内渐变厚度的场板结构的半导体器件的制造方法。
一种具有沟槽内渐变厚度的场板结构的半导体器件的制造方法，包括：步骤A，在晶圆表面形成沟槽；步骤B，通过淀积向所述沟槽内填充氧化硅；步骤C，通过刻蚀去除掉沟槽内的氧化硅表面的一部分；步骤D，通过热氧化在沟槽顶部的拐角处形成氧化硅拐角结构，所述氧化硅拐角结构为从拐角处往下、位于沟槽内部的氧化硅逐渐变厚的结构；步骤E，在晶圆表面淀积 含氮化合物，覆盖所述沟槽内的氧化硅表面及所述氧化硅拐角结构表面；步骤F，干法刻蚀所述含氮化合物，将沟槽内的氧化硅表面的含氮化合物去除，所述氧化硅拐角结构表面形成向沟槽内延伸的含氮化合物侧壁残留；步骤G，以所述含氮化合物侧壁残留为掩膜，通过刻蚀去除掉沟槽内的氧化硅表面的一部分；依次重复执行步骤E至步骤G，直至将沟槽内的氧化硅刻蚀至所需的底部氧化硅厚度，每执行一次步骤F所述含氮化合物侧壁残留就进一步向沟槽内延伸，所述沟槽内的氧化硅包括底部氧化硅和侧壁氧化硅，所述侧壁氧化硅的厚度从沟槽顶部至沟槽底部逐渐增厚；步骤H，去除所述沟槽内的含氮化合物；步骤I，向所述沟槽内填入多晶硅。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是一实施例中具有沟槽内渐变厚度的场板结构的半导体器件的制造方法的流程图；
图2至图6是一实施例中采用具有沟槽内渐变厚度的场板结构的半导体器件的制造方法制造的器件在制造过程中的剖视图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技 术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
一种传统的具有深槽内渐变厚度的场板的半导体器件的制造方法是在深槽内壁化学气相淀积(CVD)薄氧层，然后形成一层牺牲层，之后etch-back(回刻)牺牲层至一定深度，同时并刻蚀该薄氧层；第二次氧化层通过热氧化形成、再次形成牺牲层、然后再次回刻牺牲层并刻蚀氧化层，由此在第一次薄氧层上累加第二次热氧化形成的较厚的氧化层。之后的氧化层、牺牲层、刻蚀与上述类似，直至最后形成底部厚氧、顶部薄氧的多层渐变厚度的槽内场板结构。
然而该制造方法包括多次氧化、回刻，一定程度上增加了衬底向外延层的杂质反扩、同时增加了工艺时间、降低了生产效率。
图1是一实施例中具有沟槽内渐变厚度的场板结构的半导体器件的制造方法的流程图，包括下列步骤：
S110，在晶圆表面形成沟槽。
可以采用本领域习知的工艺在晶圆(本实施例中为硅片)表面刻蚀出深槽，具体深度可以根据器件的设计参数参照现有技术进行选择。在本实施例中，刻蚀形成沟槽之前可以先在晶圆表面形成一层氮化硅膜，再于氮化硅膜上通过光刻胶图案化出刻蚀窗口，再通过刻蚀窗口刻穿氮化硅膜形成沟槽，刻蚀完成后沟槽顶部的周围形成有氮化硅层。在本实施例中，沟槽的刻蚀是采用CHCl 3和/或CH 2Cl 2作为刻蚀剂进行干法刻蚀，在其他实施例中也可以 采用其他本领域习知的沟槽刻蚀工艺进行刻蚀。
在一个实施例中，通过外延工艺在高掺杂浓度的衬底上外延出低掺杂浓度的外延层，刻蚀得到的沟槽是形成于外延层中。
S120，通过淀积向沟槽内填充氧化硅。
通过淀积工艺形成氧化硅(SiO x)层的速度远大于传统的通过热氧化生长氧化硅层的速度。在本实施例中，步骤S120是采用高密度等离子化学气相淀积(HDPCVD)工艺进行氧化硅的淀积，可以获得较好的形貌。在其他实施例中也可以根据实际需求采用其他本领域习知的淀积工艺淀积氧化硅层。
淀积完后可以通过化学机械研磨(CMP)将多余的氧化硅层去除，即将露出于沟槽外面的氧化硅层去除。对于步骤S110采用氮化硅作为硬掩膜刻蚀出沟槽的实施例，CMP是将氧化硅层研磨至该氮化硅层。
S130，通过刻蚀去除掉沟槽内的氧化硅表面的一部分。
可以采用干法刻蚀，利用其各向异性获得合适的形貌。在其中一个实施例中，步骤S130选用高密度等离子刻蚀的工艺进行刻蚀。
S140，通过氧化在沟槽顶部的拐角处形成氧化硅拐角结构。
为了后续步骤中得到的含氮化合物侧壁残留能形成本方案所需的形貌，在刻蚀后通过氧化形成特殊的拐角形貌，即在沟槽内的氧化硅表面形成类似于半球形的凹面。从拐角处往下、位于沟槽内部的氧化硅逐渐变厚，从而形成圆滑的拐角，如图2所示。图2中在硅片的表面形成有沟槽，沟槽内填充有氧化硅202，沟槽顶部的周围形成有氮化硅层302。在本实施例中通过800～950摄氏度的低温氧化来得到该氧化硅拐角结构。采用低温氧化是因为发明人发现若采用较高的温度(例如1000摄氏度的牺牲氧化)，则晶圆的高浓度衬底中的掺杂离子容易反扩至低浓度的外延层102中，对器件性能产生负面影响。
S150，在晶圆表面淀积氮化硅，覆盖沟槽内的氧化硅表面及氧化硅拐角结构表面。
在本实施例中是通过化学气相淀积形成一层薄的含氮化合物，后续作为 刻蚀的硬掩膜。该含氮化合物可以是氮化硅、氮氧化硅、氮化硼、氮化钛等，考虑到普适性，可以采用本领域常用的氮化硅。
S160，干法刻蚀含氮化合物，氧化硅拐角结构表面形成向沟槽内延伸的含氮化合物侧壁残留。
参见图3，利用干法刻蚀的各向异性，将沟槽内的氧化硅202表面的含氮化合物去除，同时在氧化硅拐角结构表面形成向沟槽内延伸的含氮化合物侧壁残留304。含氮化合物侧壁残留304与沟槽内的一部分氧化硅202共同作为沟槽的侧壁结构。
S170，以含氮化合物侧壁残留为掩膜，通过刻蚀去除掉沟槽内的氧化硅表面的一部分。
参见图4，氧化硅202由于刻蚀被刻至更深的深度，同时沟槽侧壁位置处的氧化硅202因含氮化合物侧壁残留304的阻挡也会被保留下来，并且保留下来的氧化硅202从含氮化合物侧壁残留304底部往下逐渐变厚。采用含氮化合物侧壁残留304作为硬掩膜刻蚀，可以不需要光刻版，能够节省成本。为了获得越往下侧壁越厚的氧化硅202，步骤S170可以采用干法刻蚀，本实施例中是采用高密度等离子刻蚀。
步骤S170的刻蚀如果刻得过深，则就不能保证侧壁的氧化硅202形貌，故需依次重复以上S150～S170的步骤，通过多次刻蚀直至获得所需的底部氧化硅厚度，参见图5。也就是说，本方案可以方便地调节底部氧化硅厚度，进一步增大了降低反馈电容的空间。每次刻蚀的具体深度需要通过实验来收集数据。刻蚀至所需的底部氧化硅厚度后，沟槽内的氧化硅包括底部氧化硅和侧壁氧化硅，侧壁氧化硅的厚度从沟槽顶部至沟槽底部逐渐增厚。
S210，去除沟槽内的含氮化合物。
为了将含氮化合物去除干净，可以采用湿法刻蚀，例如以浓磷酸为刻蚀剂进行刻蚀。本实施例中通过浓磷酸将氮化硅层302和含氮化合物侧壁残留304一并去除。
S220，向沟槽内填入多晶硅。
向沟槽内回填多晶硅404，如图6所示。
步骤S220完成后可以通过化学机械研磨对多晶硅404进行平坦化处理。
上述具有沟槽内渐变厚度的场板结构的半导体器件的制造方法，氧化硅202组成的场板结构无需通过每回刻一次就进行一次热氧化的方式来形成，减少了氧化时间，提高了生产效率。且减少了衬底杂质向外延层的反扩，同时工艺简单，对沟槽刻蚀的深宽比没有过分严格要求。
在一个实施例中，步骤S120之前还包括对沟槽进行侧壁氧化的步骤。侧壁氧化可以起到修复步骤S110的沟槽刻蚀在沟槽内壁和底部的硅表面产生的缺陷的作用，例如因反应离子刻蚀的高能粒子撞击产生的缺陷，消除该缺陷对栅氧产生的负面影响。在一个实施例中，侧壁氧化之后还可以将生成的氧化硅剥离。
在一个实施例中，步骤S230是生长薄层的高温氧化膜(HTO)。可以理解的，虽然图7中未示，但生长HTO时同样会在沟槽侧壁的氧化硅基础上再生成一薄层氧化硅。
上述具有沟槽内渐变厚度的场板结构的半导体器件的制造方法尤其适用于金属氧化物半导体场效应管，也适用于其他可以采用沟槽场板结构的半导体器件。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种具有沟槽内渐变厚度的场板结构的半导体器件的制造方法，包括：
    步骤A，在晶圆表面形成沟槽；
    步骤B，通过淀积向所述沟槽内填充氧化硅；
    步骤C，通过刻蚀去除掉沟槽内的氧化硅表面的一部分；
    步骤D，通过热氧化在沟槽顶部的拐角处形成氧化硅拐角结构，所述氧化硅拐角结构为从拐角处往下、位于沟槽内部的氧化硅逐渐变厚的结构；
    步骤E，在晶圆表面淀积含氮化合物，覆盖所述沟槽内的氧化硅表面及所述氧化硅拐角结构表面；
    步骤F，干法刻蚀所述含氮化合物，将沟槽内的氧化硅表面的含氮化合物去除，所述氧化硅拐角结构表面形成向沟槽内延伸的含氮化合物侧壁残留；
    步骤G，以所述含氮化合物侧壁残留为掩膜，通过刻蚀去除掉沟槽内的氧化硅表面的一部分；
    依次重复执行步骤E至步骤G，直至将沟槽内的氧化硅刻蚀至所需的底部氧化硅厚度，每执行一次步骤F所述含氮化合物侧壁残留就进一步向沟槽内延伸，所述沟槽内的氧化硅包括底部氧化硅和侧壁氧化硅，所述侧壁氧化硅的厚度从沟槽顶部至沟槽底部逐渐增厚；
    步骤H，去除所述沟槽内的含氮化合物；及
    步骤I，向所述沟槽内填入多晶硅。
  2. 根据权利要求1所述的制造方法，其中，所述步骤B之前还包括对所述沟槽进行侧壁氧化的步骤。
  3. 根据权利要求1所述的制造方法，其中，所述步骤B是采用高密度等离子化学气相淀积工艺填充氧化硅。
  4. 根据权利要求1所述的制造方法，其中，所述半导体器件是金属氧化物半导体场效应管。
  5. 根据权利要求1所述的制造方法，其中，所述步骤A之前在晶圆表 面形成有氮化硅层，所述步骤A是将所述氮化硅层刻穿形成所述沟槽。
  6. 根据权利要求1所述的制造方法，其中，所述去除所述沟槽内的含氮化合物的步骤是通过浓磷酸湿法去除含氮化合物。
  7. 根据权利要求1所述的制造方法，其中，所述在所述下层多晶硅上形成隔离氧化硅是生长高温氧化膜。
  8. 根据权利要求1所述的制造方法，其中，所述通过热氧化在沟槽顶部的拐角处形成氧化硅拐角结构的步骤中，氧化温度为800～950摄氏度。
  9. 根据权利要求5所述的制造方法，其中，所述步骤A和所述步骤F的刻蚀是采用CHCl 3和/或CH 2Cl 2作为刻蚀剂。
  10. 根据权利要求1所述的制造方法，其中，所述含氮化合物是氮化硅。
  11. 根据权利要求1所述的制造方法，其中，所述步骤B和步骤C之间，还包括将露出于所述沟槽外面的氧化硅去除的步骤。
  12. 根据权利要求5所述的制造方法，其中，所述步骤B和步骤C之间，还包括将所述氧化硅研磨至所述氮化硅层的步骤。
  13. 根据权利要求1所述的制造方法，其中，所述步骤C是采用高密度等离子刻蚀。
  14. 根据权利要求1所述的制造方法，其中，所述步骤G是采用高密度等离子刻蚀。
  15. 根据权利要求2所述的制造方法，其中，所述对所述沟槽进行侧壁氧化的步骤之后，还包括将所述侧壁氧化生成的氧化硅剥离的步骤。
PCT/CN2018/094365 2017-07-03 2018-07-03 具有沟槽内渐变厚度的场板结构的半导体器件的制造方法 WO2019007346A1 (zh)

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