WO2005045938A2

WO2005045938A2 - Insulated gate field-effect transistor

Info

Publication number: WO2005045938A2
Application number: PCT/IB2004/052346
Authority: WO
Inventors: Steven T. Peake; Philip Rutter
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2003-11-11
Filing date: 2004-11-09
Publication date: 2005-05-19
Also published as: WO2005045938A3; GB0326237D0

Abstract

The transistor has an insulating or semi-insulating semiconductor substrate (2), a source region (8), a body region (6), a drift region (4) and a drain region (10). Insulated field plate trenches (20) containing field plates (24) extend longitudinally and on either side of the drift region (4). In embodiments trenches (20) and drift regions (4) alternate laterally. The field plates (24) are connected to the source alone.

Description

DESCRIPTION

INSULATED GATE FIELD EFFECT TRANSISTOR The invention relates to an insulated gate field effect transistor.

Silicon-on-insulator (SOI) transistors have a number of desirable properties, namely low specific on-resistance, low gate-drain capacitance, and high breakdown voltage. A good SOI structure is described in WO-A- 01/17028. SOI structures in general suffer however from the disadvantage that they are expensive, because of the high cost of silicon-on-insulator substrates, as well as a number of difficulties in manufacturing, such as the requirement for long local oxididation of silicon, and the difficulties involved by so-called "bird's beaking" at the edge of field oxide. There is thus a need for a transistor structure that delivers the benefits of silicon-on-insulator but at lower cost. There are a number of prior arrangements aimed at improved results over conventional structures without using a silicon-on-insulator substrate. One previous form of semiconductor device is described in WO-A-

01/91190. In this device, a gate in a trench extends not merely adjacent to a body region of a FET but also adjacent to a drift region to form a field plate. Another previous form of semiconductor device is described in US-A- 6353252. In this device, a double diffused source and body are arranged next to longitudinally extending drift regions. On either side of the drift regions are provided SIPOS resistors in insulated trenches. One end of each trenched SIPOS resistor is connected to the source and one end to the drain. However, these prior art devices can be difficult to manufacture. There remains a need for a semiconductor device that can deliver the benefits of a silicon-on-insulator structure without requiring the high cost of a silicon-on-insulator substrate. According to the invention there is provided a insulated gate field effect transistor, comprising: an insulating or semi-insulating semiconductor substrate defining opposed first and second major surfaces; a body region of a first conductivity type; a source region of a second conductivity type opposite to the first conductivity type at the first major surface; a drift region of the second conductivity type; a drain region of the second conductivity type, and a higher doping concentration than the drift region, the source region, body region, drift region and drain region arranged longitudinally along a current path; insulated field plate trenches containing field plates extending longitudinally and arranged laterally on either side of the drift region; and an insulated gate separate from the field plates arranged to control conduction in a channel region in the body region between the source and drift regions; wherein field plates are of highly doped conductive polysilicon connected to the source alone. The structure delivers the benefits of a silicon-on-insulator structure without the need for expensive silicon-on-insulator substrates. Instead, a conventional insulating or semi-insulating substrate is used. The substrate may be of the first conductivity type. The use of the field plate allows the doping in the drift region to be higher than it would otherwise be and hence to allow the device to have a lower on-resistance without the gate. The substrate does not conduct. This gives rise to significant benefits when integrating a number of devices onto a single substrate, since such integrated devices are isolated from one another. For example, instead of needing four separate semiconductor dies to make a full-bridge rectifier using a conductive substrate it is possible to integrate all four on a single insulating substrate. In the structure of WO-A-01/91190, the amount of gate polysilicon is large and this contributes to large gate-drain capacitance and hence switching losses. This may be avoided in the present invention in which the field plates are connected to the source. Further, the on-resistance of the invention may be better than that of WO-A-01/91 190 because the device of WO-A-01/91190 requires a significant number of layers of metal. A further benefit is the ease of connecting the source connected field plate by connecting it to the source metallisation thereby avoiding the need for multiple layers of metal. This leads to a cheaper process and an enhanced performance compared to connecting each field plate to the respective gate. Compared with devices with SIPOS regions, such as that described in US-A-6353252, the device has the considerable advantage that it avoids the use of semi-insulating SIPOS layers. Such SIPOS layers need to be charged up with a charge up time having a significant time constant before the device can switch, and this time constant is generally long and has a detrimental effect on device switching performance. The drift region and field plates have a drain end adjacent to the drain and a body end adjacent to the body. The thickness of the insulator between the field plates and the drift region may be greater at the drain end of the field plates than at the body end. This allows a higher breakdown voltage to be achieved, all other things being equal, than would otherwise be the case. In a preferred embodiment, a plurality of field plate trenches alternate laterally with drift regions across the first major surface. Note that the pattern of the plurality of laterally arranged cells may be repeated across the surface of the semiconductor in a practical device, as will be appreciated by those skilled in the art. In a particularly preferred arrangement the device has a number of cells. It is convenient to provide these cells by arranging the plurality of trenches to alternate with drift regions laterally across the device at the first major surface, and for the source region to include a plurality of source diffusions arranged laterally across the device in line with the drift regions between trenches. Preferably, the gate is arranged above the first major surface, and separated from the body region by a gate oxide layer on the first major surface. This may be considered to be double-diffused MOS type gate (DMOS-type) structure. The combination of a DMOS-type gate and a longitudinal trench field plate allows for simpler manufacturing. The gate can be connected as in conventional devices and the source metallisation can be extended to connect to the gate. The capacitance between gate and drain is minimised. The body region may be an implant of first conductivity type in the drift region of second conductivity type and the source region an implant of second conductivity type in the body region. It will be appreciated that in a practical device a number of devices may be arranged effectively in parallel on a substrate to improve current handling. In alternate arrangements, the gate may be contained in a longitudinally extending gate trench extending from the source region to the drift region past the drift region, the gate trench being a separate trench from the field plate trench. In this case, field plate trenches may alternate laterally with drift regions across the first major surface with a separate gate trench arranged longitudinally in line with each drift region. In a particularly preferred embodiment the first conductivity type may be p-type and the second conductivity type is n-type, the substrate being a semi- insulating p -type substrate.

For a better understanding of the invention, embodiments will now be described, purely by way of example, with reference to the accompanying drawings, in which: Figure 1 shows a first embodiment of the invention in top view; Figure 2 shows the first embodiment in side section along line A-A in Figure 1 ; and Figure 3 shows a second embodiment of the invention in top view. Like reference numerals are used for the same or similar features in different embodiments. Note that the Figures are schematic and not to scale. Referring to Figures 1 and 2, a semi-insulating p^" -type substrate 2 has an n - type epilayer 4. The top side of the epilayer defines a first major surface 12 and the rear side 14 of the substrate defines a second major surface. A p- type body layer 6 is diffused at one longitudinal end of the device extending laterally across the width of the device. A plurality of n+-type source regions 8 are then diffused within the body region 6. An n+-type drain region 10 extending laterally across the device is diffused at the other end of the drift region from the source and body regions 6,8. Note that the source region does not extend laterally across the whole device, but a plurality of source regions are deposited. Each source region provides the source for a single cell. The source region 8, body region 6, drift region 4 and drain region 10 are arranged in that order longitudinally along a path defined at the first major surface for each cell. Gate insulator 18 is deposited over the first major surface 12, extending from source region 8 over the body region 6 to over the drift region 4. A gate

16 is provided over the gate insulator for forming a channel in the body region

6. The gate extends laterally across the first major surface 12 as shown in

Figure 1. Field plate trenches 20 are formed extending through the drift region 4. As can be seen in Figure 1 , the trenches 20 alternate with drift regions 4 laterally across the first major surface 12. The trenches 20 include field plate insulator 22 on the sidewalls and base of the trenches 20 and are filled with conductive polysilicon 24. The insulator 22 is thinner at the body end nearer the body region 6 than at the drain end nearer the drain region 10. The drift regions 4 between trenches 20 are arranged in line with the source regions 8. Each drift region 4 and respective source region 8 defines a single cell of the device. A source metallisation 26 acting as a source contact connects to the source regions 8 and to the body region 6. A drain metallisation acting as drain contact 28 connects to the drain region 10. The polysilicon 24 in the trench is connected to the source metallisation 26 by an extension of that metallisation (not shown). The sizes of the various components will of course depend on the required breakdown voltage. For example, for a 600V breakdown voltage, the following parameters apply. The distance from body region 6 to drain region 10 should be of order 50 microns. The separation between adjacent trenches should be of order 0.5 micron i.e. 0.2 to 0.8 micron. The depth of the trenches is also be of order 0.5 micron, again 0.2 to 0.8 micron. This relatively shallow depth makes it easier to fill the trench with field oxide. The lateral width of each trench should be from 1 to 5 microns, preferably of order 3 microns. Thus, although Figure 1 shows the width of the semiconductor drift region 4 being roughly equal to the width of the trenches 20, this is purely for clarity in the figure and in fact the width of the trenches is nearly ten times the width of the semiconductor drift region. In the preferred embodiment shown, the trench 20 is etched into the p- type substrate as indicated by the dotted lines in Figure 2 to maximise the RESURF effect. The depth of the body region 4 should at least reach the p-type substrate. The thickness of the oxide 22 within the trench varies from about 0.5 micron on each sidewall near the body 6/drift region 4 junction to about 1 micron on each sidewall near the drift region 4 / drain region 10 junction for maximum RESURF effect. In use, voltage applied to the gate controls conduction of carriers in a channel from the source region 8 to the drift region 4. When the device is switched off and a voltage is applied between source and drain, the field plate connected to the source voltage depletes the drift region between the trenches. This allows the drift region to have a higher doping than it would otherwise have and still be depleted. This higher doping in turn reduces the on-resistance in the on state. The use of a source connected field plate minimises the capacitance between gate and drain which improves the switching time and reduces switching powering losses. The use of the DMOS-type gate in combination with trenched field plate allows for easier manufacturing. The source metallisation can be simply connected to the field plate in the trench and the gate can be connected in the normal manner used in DMOS. Since the gate extends laterally across the device connection to the gate is straightforward. In a modification of the first embodiment the field plate is connected to the gate, not the drain. This is again readily achieved, this time by connecting the gate electrode to the polysilicon in the trenches. In an second embodiment, illustrated in Figure 3, the DMOS -type gate structure of gate insulator 18 and gate 16 is replaced by a trenched gate structure. In this, a gate trench 30 is provided in the body region 6 adjacent to each source diffusion 8. The gate contains thin gate insulator 32 on the sidewalls and base and a conductive polysilicon gate 34 within the trench. Note that each gate is aligned with a respective drift region 4 between trenches 20. The other features of the device are the same as in the first embodiment. From reading the present disclosure, other variations and modifications will be apparent to persons skilled in the art. Such variations and modifications may involve equivalent and other features which are already known in the design, manufacture and use of semiconductor devices and which may be used in addition to or instead of features described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of disclosure also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to any such features and/or combinations of such features during the prosecution of the present application or of any further applications derived therefrom. In particular, the conductivity types of the n- type and p-type regions in the embodiments described may be switched.

Claims

1. An insulated gate field effect transistor, comprising: an insulating or semi-insulating semiconductor substrate (2) defining opposed first and second major surfaces; a body region (6) of a first conductivity type; a source region (8) of a second conductivity type opposite to the first conductivity type at the first major surface; a drift region (4) of the second conductivity type; a drain region (10) of the second conductivity type, and a higher doping concentration than the drift region (4), the source region (8), body region (6), drift region (4) and drain region (10) being arranged longitudinally along a current path; insulated field plate trenches (20) containing field plates (24) extending longitudinally and arranged laterally on either side of the drift region (4); and an insulated gate (16,34) separate from the field plates (24) arranged to control conduction in a channel region in the body region (6) between the source (8) and drift regions (4); wherein field plates (24) are of highly doped conductive polysilicon connected to the source alone.

2. A transistor according to claim 1 wherein the plurality of field plate trenches (20) alternate laterally with drift regions (4) across the first major surface (12).

3. A transistor according to claim 2 wherein the field plate trenches (20) have a width of between 1 and 5 microns and the drift regions (4) between the trenches (20) have a width of between 0.2 and 1 micron.

4. A transistor according to claim 2 or claim 3 wherein the source region includes a plurality of source diffusions (8) arranged laterally across the transistor in line with the drift regions (4) between trenches (20).

5. A transistor according to any preceding claim wherein the field plates (24) have a drain end adjacent to the drain and a body end adjacent to the body and the thickness of the insulator (22) between the field plates and the drift region (4) is greater at the drain end of the field plates (24) than at the body end.

6. A transistor according to any preceding claim wherein the insulated gate (16) is arranged above the first major surface of the body region separated from the body region by a gate oxide layer (18) on the first major surface (12).

7. A transistor according to claim 6 wherein the body region (6) is an implant of first conductivity type in the drift region (4) of second conductivity type and the source region (8) is an implant of second conductivity type in the body region (6).

8. A transistor according to any of claims 1 to 5 wherein the gate (34) is contained in a longitudinally extending gate trench (20) extending from the source region (8) through the body region (6) to the drift region (4), the gate trench (30) being a separate trench from the field plate trench (20).

9. A transistor according to claim 8 when dependent on claim 2 wherein a separate gate trench (30) is arranged longitudinally in line with each drift region.

10. A transistor according to any preceding claim wherein the first conductivity type is p-type and the second conductivity type is n-type.