WO2018223771A1 - 像素电路及其驱动方法、显示面板及显示装置 - Google Patents
像素电路及其驱动方法、显示面板及显示装置 Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G2300/0857—Static memory circuit, e.g. flip-flop
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- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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- G—PHYSICS
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
Definitions
- Embodiments of the present disclosure relate to a pixel circuit and a driving method thereof, a display panel, and a display device.
- AMOLED active matrix organic light emitting diodes
- TFT-LCD Thin Film Transistor-Liquid Crystal Display
- the circuit structure of a general AMOLED pixel circuit includes: a driving transistor m1, a switching transistor m2, a storage capacitor c, and an organic light emitting diode OLED; wherein a gate of the driving transistor m1 and a drain of the switching transistor m2, respectively The pole is connected to one end of the storage capacitor c, the source is connected to the anode of the organic light emitting diode OLED, and the drain is respectively connected to the other end of the storage capacitor c and the high level signal terminal VDD; the gate and the gate signal end of the switching transistor m2 The gate line is connected, the source is connected to the data signal terminal Data line, and the cathode of the organic light emitting diode OLED is connected to the low level signal terminal VSS.
- FIG. 2 is a timing chart showing the operation of the pixel circuit shown in FIG. 1 in one frame display time.
- the gate signal gate line inputs a high level signal, and the switching transistor m2 is turned on.
- the data signal on the data signal end Data line is written to the storage capacitor c, and the driving transistor m1 is driven.
- the gate electrode causes the driving transistor m1 to be turned on, and the organic light emitting diode OLED starts to work and emit light; during the time period t2, the gate signal terminal Gate line inputs a low level signal, and the switching transistor m2 is turned off.
- the gate of the driving transistor m1 will maintain a high level state, the driving transistor m1 will continue to be turned on, and the organic light emitting diode OLED will continue to operate to emit light until the next frame display data signal is input to ensure the continuity of the display picture.
- the pixel circuit shown in FIG. 1 needs to repeatedly refresh the data signal on the data signal data line in each frame display time. This leads to a large power consumption of the pixel circuit.
- a pixel circuit provided by an embodiment of the present disclosure includes: an input control sub-circuit, a switch control sub-circuit, a latch sub-circuit, and an illuminating sub-circuit;
- the input control sub-circuit is configured to write the data signal provided by the data signal end to the first node under the control of the gate signal end;
- the switch control sub-circuit is configured to conduct a first end or a second end of the latch sub-circuit with the first node under control of a control end of the switch signal;
- the latch sub-circuit is configured to output a high-level signal provided by the high-level signal terminal to the first node when the first node is turned on with the first end of the latch sub-circuit And outputting a low level signal provided by the low level signal terminal to the first node when the first node is turned on with the second end of the latch subcircuit;
- the illuminating sub-circuit emits light when the first node is a high level signal.
- a control end of the input control sub-circuit is connected to the gate signal end, and an input end is connected to the data signal end, and the output is
- the terminal is connected to the first node;
- the control end of the switch control sub-circuit is connected to the switch signal control end, the first end is connected to the first node, and the second end is connected to the latch sub-circuit One end is connected, and the third end is connected to the second end of the latch sub-circuit; the third end of the latch sub-circuit is connected to the high-level signal end, and the fourth end and the low-level signal
- the terminals are connected; and the illuminating sub-circuit is connected between the first node and the low-level signal end.
- a length of the first end of the latch sub-circuit is electrically connected to the first node, and a length of the latch sub-circuit The duration at which the two terminals are conducting with the first node is related to the voltage of the data signal.
- the voltage difference between the data signal and the high level signal is smaller, and the latch sub-circuit is displayed within one frame display time. The longer the first end of the first end is conductive with the first node.
- the input control sub-circuit includes: a first switching transistor and a capacitor;
- a gate of the first switching transistor is connected to the gate signal terminal, a source is connected to the data signal end, and a drain is connected to the first node;
- the first end of the capacitor is connected to the first node, and the second end is grounded.
- the switch control sub-circuit includes: a second switching transistor and a third switching transistor that are oppositely doped;
- a gate of the second switching transistor and a gate of the third switching transistor are respectively connected to the control end of the switching signal
- a source of the second switching transistor and a drain of the third switching transistor are respectively connected to the first node;
- a drain of the second switching transistor is connected to a first end of the latch sub-circuit
- a source of the third switching transistor is coupled to a second end of the latch subcircuit.
- the second switching transistor is an N-type transistor
- the third switching transistor is a P-type transistor
- the switching signal control terminal input The longer the high level signal duration, the longer the first end of the latch subcircuit is turned on with the first node; or
- the second switching transistor is a P-type transistor
- the third switching transistor is an N-type transistor
- the longer the duration of the low-level signal input by the control terminal of the switching signal, the first end of the latching sub-circuit The longer the duration at which the first node is turned on.
- the latch sub-circuit includes: a fourth switching transistor and a fifth switching transistor that are oppositely doped, and the sixth opposite is doped a switching transistor and a seventh switching transistor;
- a gate of the fourth switching transistor and a gate of the fifth switching transistor are respectively connected to a second end of the latch sub-circuit;
- a drain of the fourth switching transistor and a drain of the fifth switching transistor are respectively connected to the first end of the latch sub-circuit;
- a gate of the sixth switching transistor and a gate of the seventh switching transistor are respectively connected to the first end of the latch sub-circuit;
- a drain of the sixth switching transistor and a drain of the seventh switching transistor are respectively connected to a second end of the latch sub-circuit;
- a source of the fourth switching transistor and a source of the sixth switching transistor are respectively connected to the low-level signal end;
- a source of the fifth switching transistor and a source of the seventh switching transistor are respectively connected to the high-level signal terminal.
- the fourth switching transistor and the sixth switching transistor are an N-type transistor, the fifth switching transistor, and the seventh
- the switching transistor is a P-type transistor; or,
- the fourth switching transistor and the sixth switching transistor are P-type transistors, and the fifth switching transistor and the seventh switching transistor are N-type transistors.
- the illuminating sub-circuit includes: a light emitting diode
- the anode of the light emitting diode is connected to the first node, and the cathode is connected to the low level signal end.
- the light emitting diode comprises an organic light emitting diode or a quantum dot light emitting diode.
- the embodiment of the present disclosure further provides a driving method of the foregoing pixel circuit, including:
- the first node When the first node is electrically connected to the first end of the latch sub-circuit, outputting a high-level signal provided by the high-level signal terminal to the first node through the latch sub-circuit; When the first node is turned on with the second end of the latch sub-circuit, the low-level signal provided by the low-level signal terminal is output to the first node through the latch sub-circuit;
- the light emitting sub-circuit emits light.
- the voltage difference between the data signal and the high level signal is smaller, and the latch is displayed within one frame display time. The longer the first end of the circuit is conducting with the first node.
- the data signal end loads the data signal only during the first frame display time;
- the switch signal control terminal loads the switch control signal of the same duty ratio.
- Embodiments of the present disclosure also provide a display panel including the above pixel circuit.
- Embodiments of the present disclosure also provide a display device including the above display panel.
- FIG. 1 is a schematic structural view of a pixel circuit in the prior art
- FIG. 2 is a timing chart showing the operation of the pixel circuit shown in FIG. 1;
- FIG. 3 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
- FIG. 4 is a schematic structural diagram of a timing control sub-circuit provided by an embodiment of the present disclosure
- 5a is one of operation timing diagrams of the pixel circuit shown in FIG. 3 in one frame display time according to an embodiment of the present disclosure
- 5b is a timing chart of operation of the pixel circuit shown in FIG. 3 in a multi-frame display time according to an embodiment of the present disclosure
- 5c is a second operation timing diagram of the pixel circuit shown in FIG. 3 in one frame display time according to an embodiment of the present disclosure
- FIG. 6 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure.
- the embodiments of the present disclosure provide a pixel circuit and a driving method thereof, a display panel, and a display device, which are used to solve the problem of how to reduce the power consumption of a pixel circuit when displaying a static grayscale fixed picture in the prior art.
- the switch control sub-circuit can control the first end or the second end of the latch sub-circuit according to the switch control signal loaded by the control end of the switch signal. The duration of the first node being turned on, thereby achieving the gray scale corresponding to the illuminating sub-circuit in one frame display time.
- the data signal can be loaded through the data signal end only in the display time of the first frame; and the same is loaded by the control end of the switch signal during each frame display time.
- the switching control signal of the duty cycle so that the first or second end of the latch sub-circuit is controlled by the switch control sub-circuit within the display time of each frame under the trigger of the data signal loaded during the display time of the first frame.
- a pixel circuit provided by an embodiment of the present disclosure includes an input control sub-circuit 301, a switch control sub-circuit 302, a latch sub-circuit 303, and an illuminating sub-circuit 304.
- control terminal of the input control sub-circuit 301 is connected to the gate signal Gate line, the input terminal is connected to the data signal terminal Data line, and the output terminal is connected to the first node N1.
- the input control sub-circuit 301 is configured to write the data signal supplied from the data signal terminal Data line to the first node N1 under the control of the gate signal terminal Gate line.
- the control end of the switch control sub-circuit 302 is connected to the switch signal control terminal S1, the first end is connected to the first node N1, the second end is connected to the first end Q of the latch sub-circuit 303, and the third end is connected to the latch sub-circuit The second end P of the 303 is connected.
- the switch control sub-circuit 302 is configured to turn on the first terminal Q or the second end P of the latch sub-circuit 303 with the first node N1 under the control of the switch signal control terminal S1; wherein the latch sub-circuit 303
- the length of time at which the first terminal Q or the second terminal P is turned on with the first node N1 is related to the voltage of the data signal.
- the third end of the latch sub-circuit 303 is connected to the high-level signal terminal VDD, and the fourth end is connected to the low-level signal terminal VSS.
- the latch sub-circuit 303 is configured to output a high-level signal provided by the high-level signal terminal VDD to the first node N1 when the first node N1 and the first terminal Q of the latch sub-circuit 303 are turned on; When the first node N1 and the second terminal P of the latch sub-circuit 303 are turned on, the low-level signal supplied from the low-level signal terminal VSS is output to the first node N1.
- the illuminating sub-circuit 304 is connected between the first node N1 and the low-level signal terminal VSS; the illuminating sub-circuit 304 emits light when the first node N1 is at a high level signal.
- the switch control sub-circuit 302 can control the latch sub-circuit 303 according to the switch control signal loaded by the switch signal control terminal S1 due to the triggering of the data signal within one frame display time.
- the data signal can be loaded through the data signal end Data line only in the display time of the first frame; and in the display time of each frame, the control end of the switch signal S1 loads the switch control signal of the same duty ratio so that the first end of the latch sub-circuit 303 can be controlled by the switch control sub-circuit 302 within each frame display time under the trigger of the data signal loaded during the display time of the first frame.
- the duration of P or the second terminal Q being electrically connected to the first node N1, so that the data signal required for each frame display time does not have to be repeatedly refreshed, thereby reducing the power consumption of the pixel circuit.
- the switching signal control terminal S1 controls the opening or closing of the second switching transistor M2 or the third switching transistor M3 through only one switching signal control line.
- the gray scale reflects the light depth level of the display screen, the higher the level, the greater the brightness of the display screen, and the larger the voltage of the corresponding data signal, the light emission of the light emitting sub-circuit 304 needs to be controlled within one frame display time.
- the time of the non-lighting time is longer. Therefore, in the above pixel circuit provided by the embodiment of the present disclosure, the smaller the voltage difference between the data signal and the high level signal, the first end of the latch sub-circuit 303 is displayed within one frame display time.
- the longer the duration of Q conduction with the first node N1 in this case, the shorter the duration at which the second terminal P of the latch sub-circuit 303 is turned on with the first node N1).
- the duty ratio of the switch control signal loaded by the switch signal control terminal S1 can be set according to the voltage of the data signal, thereby controlling the first end Q or the second end P of the latch sub-circuit 303 and the first one in one frame display time.
- the length of time that the node N1 is turned on, and the display screen of different gray levels is realized.
- the duty ratio of the switch control signal may be set according to the voltage of the data signal, thereby controlling the duration of the first terminal Q of the latch sub-circuit 303 being electrically connected to the first node N1 during a frame display time, and the second end P.
- the duration of the conduction with the first node N1 realizes display screens of different gray levels.
- the input control sub-circuit 301 includes: a first switching transistor M1 and a capacitor C1.
- the gate of the first switching transistor M1 is connected to the gate signal Gate line, the source is connected to the data signal terminal Data line, and the drain is connected to the first node N1;
- the first end of the capacitor C1 is connected to the first node N1, and the second end is grounded.
- the first switching transistor M1 is turned on under the control of the scan signal input by the gate signal terminal Gate line, and the data signal supplied from the data signal terminal Data line is written into the first node N1.
- the scan signal input by the gate signal Gate line is a high level signal
- the first switching transistor M1 is an N-type thin film transistor; or the scan signal input by the gate signal Gate line is a low level signal, first
- the switching transistor M1 is a P-type thin film transistor.
- FIG. 3 is an example in which the first switching transistor M1 is a P-type thin film transistor.
- the specific structure of the input control sub-circuit 301 is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, and may be other structures known to those skilled in the art. I will not repeat them here.
- the switch control sub-circuit 302 includes: a second switching transistor M2 and a third switching transistor M3 that are oppositely doped.
- the second switching transistor M2 is an N-type transistor
- the third switching transistor M3 is a P-type transistor.
- the second switching transistor M2 is a P-type transistor
- the third switching transistor M3 is an N-type transistor.
- a gate of the second switching transistor M2 and a gate of the third switching transistor M3 are respectively connected to the switching signal control terminal S1;
- a source of the second switching transistor M2 and a drain of the third switching transistor M3 are respectively connected to the first node N1;
- the drain of the second switching transistor M2 is connected to the first terminal Q of the latch sub-circuit 303;
- the source of the third switching transistor M3 is connected to the second terminal P of the latch sub-circuit 303.
- the second switching transistor M2 and the third switching transistor M3 respectively control the first end Q or the second end P of the latch sub-circuit 303 with the first node under the control of the switch control signal input by the switching signal control terminal S1.
- N1 is turned on to realize transmitting the data signal of the first node N1 to the first terminal Q or the second terminal P of the latch sub-circuit 303; or, implementing a high level of the first terminal Q of the latch sub-circuit 303
- the signal or the low level signal of the second terminal P is transmitted to the first node N1.
- the second switching transistor M2 is an N-type transistor
- the third switching transistor M3 is a P-type transistor
- the switching signal control terminal S1 inputs a high voltage.
- the longer the flat signal duration the longer the duration at which the first terminal Q of the latch sub-circuit 303 is turned on and the first node N1.
- the second switching transistor M2 is a P-type transistor
- the third switching transistor M3 is an N-type transistor
- the above is only a specific structure of the switch control sub-circuit 302.
- the specific structure of the switch control sub-circuit 302 is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, and may be other structures known to those skilled in the art. I will not repeat them here.
- the latch sub-circuit 303 which may specifically include:
- a gate of the fourth switching transistor M4 and a gate of the fifth switching transistor M5 are respectively connected to the second terminal P of the latch sub-circuit 303;
- the drain of the fourth switching transistor M4 and the drain of the fifth switching transistor M5 are respectively connected to the first terminal Q of the latch sub-circuit 303;
- a gate of the sixth switching transistor M6 and a gate of the seventh switching transistor M7 are respectively connected to the first terminal Q of the latch sub-circuit 303;
- the drain of the sixth switching transistor M6 and the drain of the seventh switching transistor M7 are respectively connected to the second terminal P of the latch sub-circuit 303;
- a source of the fourth switching transistor M4 and a source of the sixth switching transistor M6 are respectively connected to the low level signal terminal VSS;
- the source of the fifth switching transistor M5 and the source of the seventh switching transistor M7 are respectively connected to the high-level signal terminal VDD.
- the fourth switching transistor M4 and the sixth switching transistor M6 are N-type transistors
- the fifth switching transistor M5 and the seventh switching transistor M7 are P-type transistors, as shown in FIG. Shown.
- the fourth switching transistor M4 and the sixth switching transistor M6 are P-type transistors, and the fifth switching transistor M5 and the seventh switching transistor M7 are N-type transistors.
- the above is only a specific structure of the latch sub-circuit 303.
- the specific structure of the latch sub-circuit 303 is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, and may be other structures known to those skilled in the art. I will not repeat them here.
- the illuminating sub-circuit 304 includes a light emitting diode (for example, an organic light emitting diode OLED).
- a light emitting diode for example, an organic light emitting diode OLED.
- the anode of the organic light emitting diode OLED is connected to the first node N1, and the cathode is connected to the low level signal terminal VSS.
- the organic light emitting diode OLED involved in the above pixel circuit provided by the embodiment of the present disclosure is an active matrix type electroluminescent device, and thus the light emitting sub circuit 304 is not limited to the organic light emitting diode OLED, and may be a quantum dot light emitting diode QLED. , not limited here.
- the one-to-one correspondence between the driving timing of the switching control signal provided by the switching signal control terminal S1 and the data signal may be pre-stored to a look-up table of the timing control sub-circuit as shown in FIG. 4 .
- the timing control sub-circuit may include a scan signal generation sub-circuit and a data signal generation sub-circuit.
- the scan signal (Gate voltage) supplied from the first output terminal M of the timing control sub-circuit to the gate signal gate line shown in FIG. 3 is a low level signal
- the second output terminal N of the timing control sub-circuit The data signal terminal Data line shown in FIG.
- the timing control sub-circuit determines the driving timing of the switch control signal corresponding to the data signal pre-stored in the lookup table, and passes The third output terminal O of the timing control sub-circuit outputs the driving timing to the switching signal control terminal S1 shown in FIG. 3, so that the switching control sub-circuit 302 controls the first terminal Q of the latch sub-circuit 303 or according to the driving timing.
- the pixel circuit shown in FIG. 3 is provided in the embodiment of the present disclosure in conjunction with the pixel circuit shown in FIG. 3 and the operation timing chart shown in FIG. 5 for the pixel circuit shown in FIG. The working process during the frame display time is described.
- the high level signal provided by the high level signal terminal VDD is 5V
- the low level signal provided by the low level signal terminal VSS is - 5V
- the data signal output by the data signal end Data line is a 4V high level signal.
- the first switching transistor M1 is turned on.
- the data signal terminal Data line provides a 4V high level signal and is written into the first node.
- the timing control sub-circuit shown in FIG. 5a when the scan signal provided by the gate signal Gate line is a low level signal, the first switching transistor M1 is turned on. At this time, the data signal terminal Data line provides a 4V high level signal and is written into the first node.
- the driving sequence may be that the high-level signal input by the switching signal control terminal S1 is maintained for one time in a frame display time, and the low-level signal input by the switching signal control terminal S1 is displayed in one frame. Keep the T2 duration in time.
- the first node N1 is turned on with the first terminal Q of the latch sub-circuit 303, and the illuminating sub-circuit 304 is lit;
- the low-level signal input by the switching signal control terminal S1 is maintained for a period of T2 in one frame display time.
- the first node N1 and the second terminal P of the latch sub-circuit 303 are turned on, and the illuminating sub-circuit 304 does not emit light.
- the gray level corresponding to the illuminating sub-circuit 304 of the data signal of 4 V in one frame display time can be obtained.
- FIG. 5b an operation timing diagram of the pixel circuit shown in FIG. 3 is displayed in a multi-frame display time according to an embodiment of the present disclosure. From FIG. 5b, it can be seen that only the high-level signal of 4V is loaded through the data signal end Data line during the display time of the first frame, and the data signal is not loaded in the display time of each subsequent frame; During the display time of each frame, the switch signal control terminal S1 is loaded with the same duty cycle switch control signal (ie, during each frame display time, the high level signal in the switch control signal is maintained for T1 duration, low level signal Both maintain T2 duration).
- the switch control sub-circuit 302 controls the first end Q or the second end P of the latch sub-circuit 303 and the first node N1 in each frame display time.
- the duration of the conduction is performed, and the static picture corresponding to the gray level of the 4V data signal is displayed in the multi-frame time, it is not necessary to repeatedly refresh the data signal required for each frame display time, thereby reducing the power consumption of the pixel circuit.
- the first node N1 and the second terminal P of the latch sub-circuit 303 are controlled to be turned on according to the driving timings, thereby controlling the potential of the first node N1, so that the illuminating sub-circuit 304 is under different data signals.
- Different gray levels can be realized, so that different gray scale display images can be realized.
- the illuminating sub-circuit 304 when the data signal end Data line inputs a high level signal, The illuminating sub-circuit 304 is illuminated in the T1 duration in which the first terminal Q of the latch sub-circuit 303 is electrically connected to the first node N1, and the T2 duration of the second terminal P of the latch sub-circuit 303 is electrically connected to the first node N1.
- the inner illuminator circuit 304 does not emit light.
- the latch sub-circuit 303 can also be implemented in the latch sub-circuit 303 when the data signal terminal Data line inputs a low-level signal in one frame display time.
- the first end Q and the first node N1 are turned on by the T1 duration inner illuminating sub-circuit 304, and the illuminating sub-circuit 304 is illuminated at the second end P of the latch sub-circuit 303 and the T2 duration of the first node N1.
- FIG. 5c it is not limited herein.
- switching transistors mentioned in the above pixel circuit may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Semiconductor). This is not limited.
- TFT thin film transistor
- MOS metal oxide semiconductor field effect transistor
- the source and drain of the switching transistors are fabricated in the same process, and are interchangeably named, which can be changed in name according to the direction of the voltage, and no specific distinction is made here.
- the embodiment of the present disclosure further provides a display panel including any of the above pixel circuits and a timing control sub-circuit.
- Embodiments of the present disclosure also provide a display device including the above display panel.
- the display device may further include a touch panel.
- the display device includes, but is not limited to, a mobile phone, a tablet computer, a television, a display sub-circuit, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, and the like.
- a product or part that displays functionality includes, but is not limited to, a mobile phone, a tablet computer, a television, a display sub-circuit, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, and the like.
- a product or part that displays functionality includes, but is not limited to, a mobile phone, a tablet computer, a television, a display sub-circuit, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, and the like.
- an embodiment of the present disclosure provides a driving method of the above pixel circuit.
- the principle of solving the problem in the driving method is similar to the principle in which the pixel circuit solves the problem. Therefore, the implementation of the driving method provided by the embodiment of the present disclosure may refer to the implementation of the foregoing pixel circuit provided by the embodiment of the present disclosure, and the repetition is no longer repeated. Narration.
- the driving method of the foregoing pixel circuit provided by the embodiment of the present disclosure, as shown in FIG. 6, specifically includes the following steps:
- the data signal end loads the data signal in the first frame display time; in each frame display time, the switch signal control end loads the same Switching control signal for duty cycle. In this way, it is not necessary to repeatedly refresh the data signal in the display time of each frame, so that the power consumption of the pixel circuit can be reduced.
- the switch control sub-circuit controls the switch control signal loaded by the switch according to the switch signal under the trigger of the data signal within one frame display time.
- the length of time that the first end or the second end of the latch sub-circuit is electrically connected to the first node can be controlled, thereby implementing gray scale corresponding to the illuminating sub-circuit in one frame display time. Therefore, when a static picture with a fixed gray level is displayed in the multi-frame display time, the data signal can be loaded through the data signal end only in the display time of the first frame; and the same is loaded by the control end of the switch signal during each frame display time.
- the switching control signal of the duty cycle so that the first or second end of the latch sub-circuit is controlled by the switch control sub-circuit within the display time of each frame under the trigger of the data signal loaded during the display time of the first frame
- the duration of the first node being turned on, so that the data signal required for each frame display time does not have to be repeatedly refreshed, thereby reducing the power consumption of the pixel circuit.
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Abstract
Description
Claims (16)
- 一种像素电路,包括:输入控制子电路,开关控制子电路,锁存子电路,以及发光子电路;其中,所述输入控制子电路被配置为在栅极信号端的控制下,将数据信号端提供的数据信号写入第一节点;所述开关控制子电路被配置为在开关信号控制端的控制下,将所述锁存子电路的第一端或第二端与所述第一节点导通;所述锁存子电路被配置为:在所述第一节点与所述锁存子电路的第一端导通时,将高电平信号端提供的高电平信号输出至所述第一节点;以及在所述第一节点与所述锁存子电路的第二端导通时,将低电平信号端提供的低电平信号输出至所述第一节点;以及所述发光子电路被配置为在所述第一节点为高电平信号时发光。
- 如权利要求1所述的像素电路,其中,所述输入控制子电路的控制端与所述栅极信号端相连,输入端与所述数据信号端相连,输出端与所述第一节点相连;所述开关控制子电路的控制端与所述开关信号控制端相连,第一端与所述第一节点相连,第二端与所述锁存子电路的第一端相连、第三端与所述锁存子电路的第二端相连;所述锁存子电路的第三端与所述高电平信号端相连,第四端与所述低电平信号端相连;以及所述发光子电路连接于所述第一节点和所述低电平信号端之间。
- 如权利要求1所述的像素电路,其中,所述锁存子电路的第一端与所述第一节点导通的时长和所述锁存子电路的第二端与所述第一节点导通的时长均与所述数据信号的电压相关。
- 如权利要求3所述的像素电路,其中,所述数据信号与所述高电平信号的电压差越小,在一帧显示时间内所述锁存子电路的第一端与所述第一节点导通的时长越长。
- 如权利要求1-4任一项所述的像素电路,其中,所述输入控制子电路,包括:第一开关晶体管和电容;所述第一开关晶体管的栅极与所述栅极信号端相连,源极与所述数据信号端相连,漏极与所述第一节点相连;以及所述电容的第一端与所述第一节点相连,第二端接地。
- 如权利要求1-5任一项所述的像素电路,其中,所述开关控制子电路包括:掺杂相反的第二开关晶体管和第三开关晶体管;所述第二开关晶体管的栅极和所述第三开关晶体管的栅极分别与所述开关信号控制端相连;所述第二开关晶体管的源极和所述第三开关晶体管的漏极分别与所述第一节点相连;所述第二开关晶体管的漏极与所述锁存子电路的第一端相连;以及所述第三开关晶体管的源极与所述锁存子电路的第二端相连。
- 如权利要求6所述的像素电路,其中,所述第二开关晶体管为N型晶体管,所述第三开关晶体管为P型晶体管,所述开关信号控制端输入的高电平信号时长越长,所述锁存子电路的第一端与所述第一节点导通的时长越长;或,所述第二开关晶体管为P型晶体管,所述第三开关晶体管为N型晶体管,所述开关信号控制端输入的低电平信号时长越长,所述锁存子电路的第一端与所述第一节点导通的时长越长。
- 如权利要求1-7任一项所述的像素电路,其中,所述锁存子电路包括:掺杂相反的第四开关晶体管和第五开关晶体管,掺杂相反的第六开关晶体管和第七开关晶体管;其中,所述第四开关晶体管的栅极和第五开关晶体管的栅极分别与所述锁存子电路的第二端相连;所述第四开关晶体管的漏极和第五开关晶体管的漏极分别与所述锁存子电路的第一端相连;所述第六开关晶体管的栅极和第七开关晶体管的栅极分别与所述锁存子电路的第一端相连;所述第六开关晶体管的漏极和第七开关晶体管的漏极分别与所述锁存子电路的第二端相连;所述第四开关晶体管的源极和所述第六开关晶体管的源极分别与所述低 电平信号端相连;以及所述第五开关晶体管的源极和所述第七开关晶体管的源极分别与所述高电平信号端相连。
- 如权利要求8所述的像素电路,其中,所述第四开关晶体管和所述第六开关晶体管为N型晶体管,所述第五开关晶体管和所述第七开关晶体管为P型晶体管;或,所述第四开关晶体管和所述第六开关晶体管为P型晶体管,所述第五开关晶体管和所述第七开关晶体管为N型晶体管。
- 如权利要求1-9任一项所述的像素电路,其中,所述发光子电路包括:发光二极管;所述发光二极管的阳极与所述第一节点相连,阴极与所述低电平信号端相连。
- 如权利要求10所述的像素电路,其中,所述发光二极管包括有机发光二极管或量子点发光二极管。
- 一种如权利要求1-11任一项所述的像素电路的驱动方法,包括:在栅极信号端的控制下,通过输入控制子电路将数据信号端提供的数据信号写入第一节点;在开关信号控制端的控制下,通过开关控制子电路将锁存子电路的第一端或第二端与所述第一节点导通;在所述第一节点与所述锁存子电路的第一端导通时,通过所述锁存子电路将高电平信号端提供的高电平信号输出至所述第一节点;在所述第一节点与所述锁存子电路的第二端导通时,通过所述锁存子电路将低电平信号端提供的低电平信号输出至所述第一节点;以及在所述第一节点为高电平信号时,通过所述发光子电路发光。
- 如权利要求12所示的驱动方法,其中,所述数据信号与所述高电平信号的电压差越小,在一帧显示时间内所述锁存子电路的第一端与所述第一节点导通的时长越长。
- 如权利要求12或13所示的驱动方法,其中,在显示静态画面时,仅在第一帧显示时间内,所述数据信号端加载数据信号;在每帧显示时间内,所述开关信号控制端加载相同占空比的开关控制信号。
- 一种显示面板,包括如权利要求1-11任一项所述的像素电路。
- 一种显示装置,包括如权利要求15所述的显示面板。
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CN108389548B (zh) * | 2018-03-16 | 2020-03-20 | 京东方科技集团股份有限公司 | 一种像素电路、其驱动方法及显示面板 |
CN111433839A (zh) * | 2018-10-23 | 2020-07-17 | 京东方科技集团股份有限公司 | 像素驱动电路、方法、以及显示设备 |
CN109961736B (zh) * | 2019-04-30 | 2022-07-22 | 成都辰显光电有限公司 | 一种数字驱动像素电路及其驱动方法和显示装置 |
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US11170701B2 (en) | 2019-10-12 | 2021-11-09 | Boe Technology Group Co., Ltd. | Driving circuit, driving method thereof, display panel and display device |
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