WO2020233491A1 - 像素电路及其驱动方法、阵列基板及显示装置 - Google Patents

像素电路及其驱动方法、阵列基板及显示装置 Download PDF

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Publication number
WO2020233491A1
WO2020233491A1 PCT/CN2020/090202 CN2020090202W WO2020233491A1 WO 2020233491 A1 WO2020233491 A1 WO 2020233491A1 CN 2020090202 W CN2020090202 W CN 2020090202W WO 2020233491 A1 WO2020233491 A1 WO 2020233491A1
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Prior art keywords
circuit
transistor
terminal
light
driving
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PCT/CN2020/090202
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English (en)
French (fr)
Inventor
王志冲
李付强
冯京
刘鹏
栾兴龙
孙高明
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US17/265,828 priority Critical patent/US11232749B2/en
Publication of WO2020233491A1 publication Critical patent/WO2020233491A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the embodiments of the present disclosure relate to a pixel circuit and a driving method thereof, an array substrate and a display device.
  • OLED Organic Light-Emitting Diode
  • At least one embodiment of the present disclosure provides a pixel circuit including a driving circuit, an input circuit, a compensation circuit, a reset circuit, a data writing circuit, and a light emitting element.
  • the driving circuit includes a control terminal, a first terminal, and a second terminal, and is configured to control a driving current flowing through the first terminal and the second terminal for driving the light-emitting element to emit light; the input circuit configuration In order to transmit a reset voltage and a data signal in response to the first scan signal; the reset circuit is configured to apply the reset voltage transmitted by the input circuit to the control terminal of the drive circuit in response to the second scan signal; the compensation The circuit is configured to store the data signal and electrically connect the control terminal and the second terminal of the driving circuit in response to a third scan signal; the data writing circuit is configured to respond to the third scan signal to connect the The data signal transmitted by the input circuit is applied to the compensation circuit.
  • the pixel circuit provided by some embodiments of the present disclosure further includes: a light emission control circuit configured to apply the data signal stored in the compensation circuit to the control terminal of the drive circuit in response to the light emission control signal, so that the The driving circuit generates the driving current, and applies the driving current corresponding to the data signal to the light emitting element in response to the light emission control signal.
  • a light emission control circuit configured to apply the data signal stored in the compensation circuit to the control terminal of the drive circuit in response to the light emission control signal, so that the The driving circuit generates the driving current, and applies the driving current corresponding to the data signal to the light emitting element in response to the light emission control signal.
  • the light emission control circuit includes a first light emission control circuit and a second light emission control circuit, and the first light emission control circuit is configured to respond to the light emission control signal.
  • the data signal stored by the compensation circuit is applied to the control terminal of the driving circuit, so that the driving circuit generates the driving current, and the second light emission control circuit is configured to respond to the light emission control signal A driving current is applied to the light emitting element.
  • the driving circuit includes a first transistor, and the gate of the first transistor is connected to the first node as the control terminal of the driving circuit, and the first transistor
  • the first pole of the drive circuit is connected to the first power supply terminal to receive the first power supply voltage
  • the second pole of the first transistor is connected to the second node as the second terminal of the drive circuit.
  • the compensation circuit includes a second transistor and a storage capacitor, and the gate of the second transistor is connected to a third scan signal terminal to receive the third scan signal,
  • the first electrode of the second transistor is connected to the second node
  • the second electrode of the second transistor is connected to the first node
  • the first end of the storage capacitor is connected to the gate of the first transistor.
  • the second end of the storage capacitor is connected to the third node.
  • the reset circuit includes a third transistor, and the gate of the third transistor is connected to the second scan signal terminal to receive the second scan signal, and the first The first pole of the three transistor is connected to the fourth node, and the second pole of the third transistor is connected to the first node.
  • the input circuit includes a fourth transistor, and the gate of the fourth transistor is connected to the first scan signal terminal to receive the first scan signal, and the The first pole of the four transistor is connected to the data signal terminal to receive the reset voltage and the data signal, and the second pole of the fourth transistor is connected to the fourth node.
  • the data writing circuit includes a fifth transistor, and the gate of the fifth transistor is connected to the third scan signal terminal to receive the third scan signal.
  • the first pole of the fifth transistor is connected to the fourth node, and the second pole of the fifth transistor is connected to the third node.
  • the first light emission control circuit includes a sixth transistor, and the gate of the sixth transistor is connected to the light emission control signal terminal to receive the light emission control signal.
  • the first pole of the sixth transistor is connected to the reference voltage terminal to receive the reference voltage, and the second pole of the sixth transistor is connected to the third node.
  • the second light emission control circuit includes a seventh transistor, and the gate of the seventh transistor is connected to the light emission control signal terminal to receive the light emission control signal,
  • the first electrode of the seventh transistor is connected to the second node
  • the second electrode of the seventh transistor is connected to the first electrode of the light-emitting element
  • the second electrode of the light-emitting element is connected to a second power supply terminal. Connect to receive the second power supply voltage.
  • the reference voltage is the same as the first power supply voltage.
  • the driving circuit includes a first transistor
  • the compensation circuit includes a second transistor and a storage capacitor
  • the reset circuit includes a third transistor
  • the input circuit includes a first transistor.
  • the data writing circuit includes a fifth transistor
  • the gate of the first transistor is connected to a first node as the control terminal of the driving circuit, and the first electrode of the first transistor is used as the driving circuit
  • the first terminal of the first transistor is connected to the first power terminal to receive the first power voltage
  • the second terminal of the first transistor is connected to the second node as the second terminal of the driving circuit
  • the third scan signal terminal is connected to receive the third scan signal
  • the first electrode of the second transistor is connected to the second node
  • the second electrode of the second transistor is connected to the first node
  • the scan signal end is connected to receive the first scan signal
  • the first electrode of the fourth transistor is connected to the data signal end to receive the reset voltage and the data signal
  • the second electrode of the fourth transistor is connected to the data signal.
  • the fourth node is connected; the gate of the fifth transistor is connected to the third scan signal terminal to receive the third scan signal, the first pole of the fifth transistor is connected to the fourth node, so The second electrode of the fifth transistor is connected to the third node.
  • At least one embodiment of the present disclosure further provides an array substrate including a plurality of pixel units arranged in an array.
  • Each of the pixel units includes a pixel circuit provided according to any embodiment of the present disclosure.
  • the array substrate provided by some embodiments of the present disclosure further includes a plurality of data signal lines.
  • Each column of pixel units corresponds to two data signal lines
  • the input circuit in the pixel circuit of the odd sequence in this column of pixel units is connected to one of the corresponding two data signal lines
  • the even sequence of pixel units in this column The input circuit in the pixel circuit is connected to the other of the corresponding two data signal lines.
  • the two data signal lines corresponding to each column of pixel units are arranged on the same side or different sides of the column of pixel units.
  • At least one embodiment of the present disclosure further provides a display device including the array substrate provided by any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure further provides a driving method corresponding to the pixel circuit provided in any embodiment of the present disclosure, including: a reset phase, a data writing and compensation phase, a holding phase, and a light-emitting phase.
  • a driving method corresponding to the pixel circuit provided in any embodiment of the present disclosure, including: a reset phase, a data writing and compensation phase, a holding phase, and a light-emitting phase.
  • the reset phase the first scan signal and the second scan signal are input, the input circuit and the reset circuit are turned on, and the control terminal of the drive circuit is controlled by the input circuit and the reset circuit.
  • Reset in the data writing and compensation stage, input the first scan signal and the third scan signal, turn on the input circuit, the data writing circuit, the drive circuit, and the compensation circuit , Writing the data signal into the compensation circuit through the input circuit and the data writing circuit, and compensating the driving circuit through the compensation circuit; in the holding phase, inputting the third scan Signal, turn on the drive circuit and the compensation circuit, continue to compensate the drive circuit through the compensation circuit; in the light-emitting phase, turn on the drive circuit, and drive the light-emitting element to emit light through the drive circuit .
  • the pixel circuit further includes: a first light emission control circuit and a second light emission control circuit, the first light emission control circuit is configured to respond to the light emission control signal
  • the data signal stored by the compensation circuit is applied to the control terminal of the drive circuit to cause the drive circuit to generate the drive current
  • the second light emission control circuit is configured to drive the drive current in response to the light emission control signal Applied to the light-emitting element
  • in the light-emitting phase turning on the driving circuit, and driving the light-emitting element to emit light through the driving circuit, includes: in the light-emitting phase, inputting the light-emitting control signal to turn on the A light emission control circuit, the second light emission control circuit, and the drive circuit.
  • the data signal stored in the compensation circuit is applied to the control terminal of the drive circuit through the first light emission control circuit to make the The driving circuit generates the driving current, and the driving current is applied to the light-emitting element through the second light-emitting control circuit to cause the light-emitting element to emit light.
  • FIG. 1A is a schematic diagram of a 2T1C pixel circuit
  • FIG. 1B is a schematic diagram of another 2T1C pixel circuit
  • FIG. 2 is a schematic block diagram of a pixel circuit provided by at least one embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a circuit structure of a specific implementation example of the pixel circuit shown in FIG. 2;
  • FIG. 4 is a signal timing diagram of a method for driving a pixel circuit provided by at least one embodiment of the present disclosure
  • 5 to 8 are circuit diagrams of the pixel circuit shown in FIG. 3 corresponding to the four stages in FIG. 4;
  • FIG. 9A is a schematic diagram of an array substrate provided by at least one embodiment of the present disclosure.
  • FIG. 9B is a schematic diagram of another array substrate provided by at least one embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • the pixel circuit in the OLED display panel generally adopts a matrix driving method, and is divided into active matrix (AM) driving and passive matrix (PM) driving according to whether switching elements are introduced in each pixel unit.
  • AMOLED integrates a set of thin film transistors and storage capacitors in the pixel circuit of each pixel. By driving and controlling the thin film transistors and storage capacitors, the current flowing through the OLED is controlled, so that the OLED emits light as needed. Therefore, AMOLED requires small driving current, low power consumption, and longer life, which can meet the needs of large-scale display with high resolution and multiple grayscale.
  • AMOLED has obvious advantages in terms of viewing angle, color restoration, power consumption, and response time, and is suitable for display devices with high information content and high resolution.
  • the basic pixel circuit used in the AMOLED display panel is usually a 2T1C pixel circuit, that is, two TFTs (Thin-film Transistors) and a storage capacitor Cs are used to realize the basic function of driving the OLED to emit light.
  • Figures 1A and 1B respectively show schematic diagrams of two 2T1C pixel circuits.
  • a 2T1C pixel circuit includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cs.
  • the gate of the switching transistor T0 is connected to the scan line to receive the scan signal Scan1, for example, the source is connected to the data signal line to receive the data signal Vdata, the drain is connected to the gate of the driving transistor N0; the source of the driving transistor N0 is connected To the first voltage terminal to receive the first voltage Vdd (high voltage), the drain is connected to the positive terminal of the OLED; one end of the storage capacitor Cs is connected to the drain of the switching transistor T0 and the gate of the driving transistor N0, and the other end is connected to The source of the driving transistor N0 and the first voltage terminal; the negative terminal of the OLED is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage).
  • the driving method of the 2T1C pixel circuit is to control the brightness (gray scale) of the pixel through two TFTs and a storage capacitor Cs.
  • the scanning signal Scan1 is applied through the scanning line to turn on the switching transistor T0
  • the data signal Vdata sent by the data driving circuit through the data signal line will charge the storage capacitor Cs through the switching transistor T0, thereby storing the data signal Vdata in the storage capacitor Cs
  • the stored data signal Vdata controls the conduction degree of the driving transistor N0, thereby controlling the current flowing through the driving transistor to drive the OLED to emit light, that is, the current determines the gray scale of the pixel's light emission.
  • the switching transistor T0 is an N-type transistor and the driving transistor N0 is a P-type transistor.
  • another 2T1C pixel circuit also includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cs, but the connection mode is slightly changed, and the driving transistor N0 is an N-type transistor.
  • the changes of the pixel circuit of FIG. 1B relative to FIG. 1A include: the positive terminal of the OLED is connected to the first voltage terminal to receive the first voltage Vdd (high voltage), and the negative terminal is connected to the drain of the driving transistor N0.
  • the source of N0 is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage).
  • the working mode of the 2T1C pixel circuit is basically the same as that of the pixel circuit shown in FIG. 1A, and will not be repeated here.
  • the switching transistor T0 is not limited to an N-type transistor, but may also be a P-type transistor, so that the polarity of the scan signal Scan1 that is controlled to be turned on or off is changed accordingly. can.
  • An AMOLED display panel usually includes a plurality of pixel units arranged in an array, and each pixel unit may include the aforementioned pixel circuit, for example.
  • the threshold voltage of the driving transistor in each pixel circuit may be different due to the manufacturing process, and the threshold voltage of the driving transistor may drift due to external factors such as long-term voltage application and high temperature. For example, due to different display screens, the threshold voltage drift of the driving transistors of each part of the display panel is different, which will cause the display brightness difference. This difference is related to the image displayed before, so it often appears as an afterimage phenomenon, which is commonly referred to as Afterimage.
  • an OLED display device lights up a black and white screen for a period of time, and then switches to a screen with the same grayscale, it is easy to produce afterimages, which will naturally disappear after a period of time. This phenomenon is called short-term afterimages.
  • the pixel circuit includes a driving circuit, an input circuit, a compensation circuit, a reset circuit, a data writing circuit, and a light emitting element.
  • the driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to control a driving current flowing through the first terminal and the second terminal for driving the light-emitting element to emit light;
  • the input circuit is configured to transmit a reset voltage in response to the first scan signal And the data signal;
  • the reset circuit is configured to apply the reset voltage transmitted by the input circuit to the control terminal of the drive circuit in response to the second scan signal;
  • the compensation circuit is configured to store the data signal, and the control terminal of the drive circuit is configured to respond to the third scan signal Electrically connected to the second terminal;
  • the data writing circuit is configured to apply the data signal transmitted by the input circuit to the compensation circuit in response to the third scan signal.
  • Some embodiments of the present disclosure also provide a driving method, an array substrate, and a display device corresponding to the aforementioned pixel circuit.
  • the pixel circuit and the driving method thereof, the array substrate and the display device provided by at least one embodiment of the present disclosure can compensate the threshold voltage of the driving circuit.
  • the driving circuit can be reset to make the driving circuit
  • the control terminal is in the same bias state, which can suppress the occurrence of short-term afterimages.
  • FIG. 2 is a schematic block diagram of a pixel circuit provided by at least one embodiment of the present disclosure.
  • the pixel circuit 10 may be used in sub-pixels of an AMOLED display panel.
  • the pixel circuit 10 includes a driving circuit 100, an input circuit 400, a compensation circuit 200, a reset circuit 300, a data writing circuit 500, and a light emitting element 700.
  • the driving circuit 100 includes a control terminal 110, a first terminal 120, and a second terminal 130, and is configured to control a driving current flowing through the first terminal 120 and the second terminal 130 for driving the light emitting element 700 to emit light.
  • the driving circuit 100 may provide a driving current to the light-emitting element 700 to drive the light-emitting element 700 to emit light, and may display the gray scale according to the need (different gray scales correspond to different data signals) Provide corresponding drive current to emit light.
  • the light-emitting element 700 may be an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), an inorganic light-emitting diode, etc.
  • OLED organic light-emitting diode
  • QLED quantum dot light-emitting diode
  • inorganic light-emitting diode etc.
  • the embodiments of the present disclosure include but are not limited thereto.
  • the input circuit 400 is configured to transmit the reset voltage Vinitial and the data signal Vdata in response to the first scan signal SN1.
  • the switch circuit 400 in the reset phase, is turned on in response to the first scan signal SN1, thereby transmitting the reset voltage Vinitial to the reset circuit 300, and applies the reset voltage Vinitial to the driving circuit 100 via the reset circuit 300.
  • the switch circuit 400 is still turned on in response to the first scan signal SN1, thereby transmitting the data signal Vdata to the data writing circuit 500,
  • the data signal Vdata is written and stored in the compensation circuit 200 via the data writing circuit 500, so that the driving circuit 100 generates a driving current for driving the light emitting element 700 to emit light according to the data signal Vdata during the light emitting phase.
  • the data writing and compensation phase immediately follows the reset phase, so that the first scan signal is a continuous pulse signal during the reset phase and the data writing and compensation phase.
  • the reset circuit 300 is configured to apply the reset voltage Vinitial transmitted by the input circuit 400 to the control terminal 110 of the driving circuit 100 in response to the second scan signal SN2.
  • the reset circuit 300 in the reset phase, is turned on in response to the second scan signal SN2, so that the reset voltage Vinitial transmitted from the input circuit 400 can be applied to the control terminal 110 of the driving circuit 100 to drive The circuit 100 performs a reset operation.
  • the data writing circuit 500 is configured to apply the data signal Vdata transmitted by the input circuit 400 to the compensation circuit 200 in response to the third scan signal SN3.
  • the data writing circuit 500 is turned on in response to the third scan signal SN3, so that the data signal Vdata transmitted from the input circuit 400 can be written and stored in the compensation circuit.
  • the driving circuit 100 generates a driving current for driving the light-emitting element 700 to emit light according to the data signal Vdata during the light-emitting phase.
  • the compensation circuit 200 is configured to store the written data signal Vdata, and electrically connect the control terminal 110 and the second terminal 130 of the driving circuit 100 in response to the third scan signal SN3.
  • the compensation circuit 200 includes a storage capacitor; in the data writing and compensation phase, the storage capacitor may receive and store the data signal Vdata written by the data writing circuit 500, and at the same time, the compensation circuit 200 responds to the third scan
  • the signal SN3 is turned on to electrically connect the control terminal 110 and the second terminal 130 of the driving circuit 100, so that the information related to the threshold voltage Vth of the driving circuit is correspondingly stored in the storage capacitor, and the stored information can be used in the light-emitting phase.
  • the voltage including information such as the data signal Vdata and the threshold voltage Vth controls the driving circuit 100 so that the driving circuit 100 generates a driving current for driving the light-emitting element 700 to emit light according to the data signal Vdata under compensation.
  • the pixel circuit 10 may further include a light emission control circuit 600.
  • the light emission control circuit 600 is configured to apply the data signal Vdata stored in the compensation circuit 200 to the control terminal 110 of the driving circuit 100 in response to the light emission control signal EM, so that the driving circuit 100 generates a driving current according to the data signal Vdata, and simultaneously responds to the light emission
  • the control signal EM applies a driving current corresponding to the data signal Vdata to the light-emitting element 700, so that the light-emitting element 700 is driven to emit light, thereby displaying the gray scale to be displayed.
  • the light emission control circuit 600 may include a first light emission control circuit 610 configured to apply the data signal Vdata stored by the compensation circuit 200 in response to the light emission control signal EM. To the control terminal 110 of the driving circuit 100 to make the driving circuit 100 generate a driving current.
  • the first light-emission control circuit in the light-emitting phase, is turned on in response to the light-emission control signal EM, so that the reference voltage Vref can be applied to one end of the storage capacitor in the compensation circuit 200, and then pass the The bootstrap effect applies a voltage including information such as the data signal Vdata and the threshold voltage Vth to the control terminal 110 of the driving circuit 100 to control the driving circuit 100 to generate a driving current for driving the light-emitting element 700 to emit light according to the data signal Vdata under compensation.
  • the reference voltage Vref may be a driving voltage, such as a high voltage.
  • the light emission control circuit 600 may further include a second light emission control circuit 620 configured to apply a driving current to the light emitting element 700 in response to the light emission control signal EM.
  • the second light-emitting control circuit 620 is turned on in response to the light-emitting control signal EM, so that the driving circuit 100 can apply a driving current to the light-emitting element 700 through the second light-emitting control circuit 620 to make it emit light;
  • the second light-emitting control circuit 620 is turned off in response to the light-emitting control signal EM to prevent the light-emitting element 700 from emitting light, thereby improving the contrast of the corresponding display device.
  • the first scan signal SN1, the second scan signal SN2, and the third scan signal SN3 described in the embodiment of the present disclosure are used to distinguish three control signals (eg, scan signals) with different timings.
  • the first scan signal SN1 may be a control signal for controlling the input circuit 400 in the pixel circuit 10 of the current row;
  • the scan signal SN2 can be a control signal for controlling the input circuit 400 in the pixel circuit 10 of the previous row.
  • the second scan signal SN2 also controls the reset circuit 300 in the pixel circuit 10 of the current row; the third scan signal SN3 can be used to control the next row.
  • the control signal of the input circuit 400 in the pixel circuit 10, and at the same time, the third scan signal SN3 also controls the data writing circuit 500 and the compensation circuit 200 in the pixel circuit 10 of the current row.
  • FIG. 3 is a schematic diagram of a circuit structure of a specific implementation example of the pixel circuit shown in FIG. 2.
  • the pixel circuit 10 includes: first to seventh transistors T1, T2, T3, T4, T5, T6, T7, a storage capacitor Cs, and a light emitting element LE.
  • the first transistor T1 is used as a driving transistor
  • the other second to seventh transistors are used as switching transistors.
  • the light-emitting element LE may be an OLED.
  • the embodiments of the present disclosure include but are not limited to this. The following embodiments are all described by taking OLED as an example, and will not be repeated.
  • the OLED can be of various types, such as top emission, bottom emission, etc., and can emit red light, green light, blue light, or white light, which is not limited in the embodiments of the present disclosure.
  • the following embodiments also take the transistors as P-type transistors as an example for description, but this does not constitute a limitation to the embodiments of the present disclosure.
  • the driving circuit 100 may be implemented as a first transistor T1.
  • the gate of the first transistor T1 serves as the control terminal 110 of the driving circuit 100 and is connected to the first node N1
  • the first pole of the first transistor T1 serves as the first terminal 120 of the driving circuit 100 and is connected to the first power terminal ELVDD to receive the first With the power supply voltage VDD
  • the second electrode of the first transistor T1 serves as the second terminal 130 of the driving circuit 100 and is connected to the second node N2.
  • the first power supply voltage VDD may be a driving voltage, such as a high voltage.
  • the compensation circuit 200 may be implemented as a second transistor T2 and a storage capacitor Cs.
  • the gate of the second transistor T2 is connected to the third scan signal terminal to receive the third scan signal SN3, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the first node N1 Connected, the first end of the storage capacitor Cs is coupled to the gate of the first transistor T1 (that is, connected to the first node N1), and the second end of the storage capacitor Cs is connected to the third node N3.
  • the storage capacitor Cs can store the potential difference between the first node N1 and the third node N3. Specifically, the first end of the storage capacitor Cs stores the potential of the first node N1, and the second end of the storage capacitor Cs stores the third node. The potential of node N3.
  • the reset circuit 300 may be implemented as a third transistor T3.
  • the gate of the third transistor T3 is connected to the second scan signal terminal to receive the second scan signal SN2, the first electrode of the third transistor T3 is connected to the fourth node N4, and the second electrode of the third transistor T3 is connected to the first node N1 connection.
  • the input circuit 400 may be implemented as a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the first scan signal terminal to receive the first scan signal SN1, and the first electrode of the fourth transistor T4 is connected to the data signal terminal DATA to receive the reset voltage Vinitial and the data signal at different times during operation.
  • Vdata the second pole of the fourth transistor T4 is connected to the fourth node N4.
  • the reset voltage Vinitial can be a zero voltage or a ground voltage, and can also be other fixed levels, such as a low voltage, which is not limited in the embodiments of the present disclosure.
  • the data writing circuit 500 may be implemented as a fifth transistor T5.
  • the gate of the fifth transistor T5 is connected to the third scan signal terminal to receive the third scan signal SN3, the first electrode of the fifth transistor T5 is connected to the fourth node N4, and the second electrode of the fifth transistor T5 is connected to the third node N3 connection.
  • the first light emission control circuit 610 may be implemented as a sixth transistor T6.
  • the gate of the sixth transistor T6 is connected to the emission control signal terminal to receive the emission control signal EM
  • the first pole of the sixth transistor T6 is connected to the reference voltage terminal to receive the reference voltage Vref
  • the second pole of the sixth transistor T6 is connected to the third Node N3 is connected.
  • the reference voltage Vref may be a driving voltage, such as a high voltage.
  • the reference voltage Vref may be the same as the first power supply voltage VDD.
  • the second light emission control circuit 620 may be implemented as a seventh transistor T7.
  • the gate of the seventh transistor T7 is connected to the emission control signal terminal to receive the emission control signal EM
  • the first pole of the seventh transistor T6 is connected to the second node N2
  • the second pole of the seventh transistor T7 is connected to the first pole of the light emitting element LE.
  • the electrode for example, the anode
  • the second electrode for example, the cathode
  • the second power supply voltage VSS may be a low voltage
  • the second power supply terminal ELVSS may be grounded, so that the second power supply voltage VSS may be a zero voltage.
  • the fourth transistor T4 and the third transistor T3 can be turned on at the same time, At this time, the data signal terminal DATA provides a reset voltage Vinitial, so that the reset voltage can be applied to the control terminal of the first transistor T1 through the fourth transistor T4 and the third transistor T3 to perform a reset operation.
  • the fourth transistor T4 and the fifth transistor T5 can be turned on at the same time.
  • the data signal terminal DATA provides the data signal Vdata, which can pass through the fourth transistor T4.
  • the fifth transistor T5 stores the data signal Vdata in the storage capacitor Cs.
  • the second transistor T2 When the third scan signal SN3 is at an active level, the second transistor T2 can be turned on, thereby connecting the gate (first node N1) of the first transistor T1 and the second electrode (second node N2) of the first transistor T1 At this time, the first transistor T1 is in a diode connection mode, and the threshold voltage Vth of the first transistor T1 (driving transistor) can be compensated by itself.
  • the storage capacitor Cs can be a capacitive device manufactured by a process, for example, a capacitor device can be realized by making a special capacitor electrode, and each electrode of the capacitor can be through a metal layer, a semiconductor layer ( For example, doped polysilicon), etc., and the capacitance can also be a parasitic capacitance between various devices, which can be realized by the transistor itself and other devices and circuits.
  • the connection method of the capacitor is not limited to the method described above, and may also be other applicable connection methods, as long as the level of the corresponding node can be stored.
  • the first node N1, the second node N2, the third node N3, and the fourth node N4 do not indicate components that must actually exist, but indicate related electrical connections in the circuit diagram. The meeting point.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • the transistors in the embodiments of the present disclosure are all described by taking a P-type transistor as an example.
  • the first electrode of the transistor is the source and the second electrode is the drain.
  • the present disclosure includes but is not limited to this.
  • one or more transistors in the pixel circuit 10 provided by the embodiments of the present disclosure can also be N-type transistors.
  • the first electrode of the transistor is the drain and the second electrode is the source.
  • the poles of the transistors are connected correspondingly with reference to the poles of the corresponding transistors in the embodiments of the present disclosure, and the corresponding voltage terminals provide the corresponding high voltage or low voltage.
  • indium gallium zinc oxide Indium Gallium Zinc Oxide, IGZO
  • crystalline silicon can effectively reduce the size of the transistor and prevent leakage current.
  • the cathode of the light-emitting element LE is connected to the second power supply voltage VSS (low voltage) as an example for description, and the embodiments of the present disclosure include but are not limited to this.
  • the anode of the light-emitting element LE may be connected to the first power supply voltage VDD (high voltage), and the cathode thereof may be directly or indirectly connected to the driving circuit.
  • VDD high voltage
  • the cathode thereof may be directly or indirectly connected to the driving circuit.
  • the 2T1C pixel circuit shown in FIG. 1B refer to the 2T1C pixel circuit shown in FIG. 1B.
  • the "effective level” refers to a level that enables the operated transistor included in it to be turned on
  • the "invalid level” refers to The level at which the operated transistor included in it cannot be turned on (that is, the transistor is turned off).
  • the effective level may be higher or lower than the inactive level. For example, in the embodiment of the present disclosure, when each transistor is a P-type transistor, the effective level is a low level and the ineffective level is a high level.
  • At least one embodiment of the present disclosure also provides a driving method of the pixel circuit.
  • 4 is a signal timing diagram of a pixel circuit driving method provided by at least one embodiment of the present disclosure.
  • the driving method of the pixel circuit 10 provided by the embodiment of the present disclosure will be described below in conjunction with the signal timing diagram shown in FIG. 4.
  • the level of the potential in the signal timing diagram shown in FIG. 4 is only illustrative, and does not represent the true potential value or relative ratio. It corresponds to the embodiment of the present disclosure, and the low-level signal corresponds to the P-type transistor.
  • the turn-on signal, and the high-level signal corresponds to the turn-off signal of the P-type transistor.
  • FIGS. 5 to 8 are circuit diagrams of the pixel circuit shown in FIG. 3 corresponding to the four stages in FIG. 4 respectively.
  • the following takes the pixel circuit shown in FIG. 2 (the pixel circuit shown in FIG. 2 is specifically implemented as the circuit structure shown in FIG. 3) as an example, and the driving method of the pixel circuit is described in detail in conjunction with FIGS. 5 to 8. .
  • the driving method provided by this embodiment may include four phases, namely, a reset phase t1, a data writing and compensation phase t2, a holding phase t3, and a light-emitting phase t4.
  • the timing waveform of each signal in each phase may include four phases, namely, a reset phase t1, a data writing and compensation phase t2, a holding phase t3, and a light-emitting phase t4.
  • FIG. 5 is a schematic diagram of the circuit when the pixel circuit shown in FIG. 3 is in the reset stage t1
  • FIG. 6 is a schematic diagram of the circuit when the pixel circuit shown in FIG. 3 is in the data writing and compensation stage t2
  • FIG. 7 is The pixel circuit shown in FIG. 3 is a schematic circuit diagram when it is in the holding phase t3
  • FIG. 8 is a schematic circuit diagram when the pixel circuit shown in FIG. 3 is in the light-emitting phase t4.
  • the transistors marked with dotted lines in FIGS. 5 to 8 all indicate that they are in the off state in the corresponding stage.
  • the transistors shown in FIGS. 5 to 8 are all P-type transistors as examples, that is, the gate of each transistor is turned on when the low level is connected, and turned off when the high level is connected. The following embodiments are the same as this and will not be repeated here.
  • the first scan signal SN1 and the second scan signal SN2 are input, the input circuit 400 and the reset circuit 300 are turned on (ie, turned on), and the control terminal of the driving circuit 100 is reset through the input circuit 400 and the reset circuit 300.
  • the fourth transistor T4 is turned on by the low level of the first scan signal SN1
  • the third transistor T3 is turned on by the low level of the second scan signal SN2; at the same time,
  • the second transistor T2 and the fifth transistor T5 are turned off by the high level of the third scan signal SN3, and the sixth transistor T6 and the seventh transistor T7 are turned off by the high level of the light emission control signal EM.
  • a reset path is formed (as shown by the dotted line with an arrow in Figure 5). Since the reset voltage Vinitial is low (for example, it can be grounded or other low levels), the storage capacitor Cs is discharged through the reset path (that is, the fourth transistor T4 and the third transistor T3), so that the potential of the first end of the storage capacitor Cs and the gate of the first transistor T1 (that is, the first node N1) becomes Vinitial, thereby
  • the display device adopting the above-mentioned pixel circuit resets the driving circuit every time the screen is switched, so that the short-term afterimage phenomenon can be suppressed.
  • the first scan signal SN1 and the third scan signal SN3 are input, the input circuit 400, the data writing circuit 500, the driving circuit 100 and the compensation circuit 200 are turned on, and the input circuit 400 and the data writing circuit 500 writes the data signal into the compensation circuit 200, and compensates the driving circuit 100 through the compensation circuit 200.
  • the second transistor T2 is turned on by the low level of the third scan signal SN1, and the fifth transistor T5 and the second transistor T2 are turned on by the third scan signal SN3.
  • the first transistor T1 is in a diode connection mode (the gate of the first transistor T1 is connected to the second electrode); at the same time, the third transistor T3 is The high level of the second scan signal SN2 is turned off, and the sixth transistor T6 and the seventh transistor T7 are turned off by the high level of the light emission control signal EM.
  • a data writing path and a compensation path are formed (as shown by the dotted line with arrows in Figure 6, the dotted line on the left represents the data writing path, and the one on the right The dashed line represents the compensation path).
  • the data signal Vdata discharges the second terminal (that is, the third node N3) of the storage capacitor Cs through the data writing path (that is, the fourth transistor T4 and the fifth transistor T5), so that the potential of the second terminal of the storage capacitor Cs becomes Vdata ;
  • the first power supply voltage terminal ELVDD providing the first power supply voltage VDD
  • the compensation path that is, the first transistor T1 and the second transistor T2
  • the first terminal of the storage capacitor Cs that is, the first node N1, that is, the first transistor
  • Vth represents the threshold voltage of the first transistor. Since in the present disclosure, the first transistor T1 is described as a P-type transistor, the threshold voltage Vth here may be a negative value.
  • the potential of the second terminal of the storage capacitor Cs is Vdata
  • the potential of the first terminal of the storage capacitor Cs is VDD+Vth
  • the potential difference between the two ends of the storage capacitor Cs is VDD+Vth-Vdata . That is to say, the voltage information with the data signal Vdata and the threshold voltage Vth is stored in the storage capacitor Cs, so as to provide gray-scale display data and perform the threshold voltage of the first transistor T1 during the light-emitting phase. make up.
  • the third scan signal SN3 is input, the driving circuit 100 and the compensation circuit 200 are turned on, and the compensation circuit 200 continues to compensate the driving circuit 100.
  • the second transistor T2 is turned on by the low level of the third scan signal SN3, and the first transistor T1 is in a diode connection mode; at the same time, the third transistor T3 is secondly scanned The high level of the signal SN2 is turned off, the fourth transistor T4 is turned off by the high level of the first scan signal SN1, and the sixth transistor T6 and the seventh transistor T7 are turned off by the high level of the light emission control signal EM; in addition, although the fifth transistor T5 is also turned on by the low level of the third scan signal SN3, but the discharge path of the second end of the storage capacitor Cs is not formed. Therefore, the potential of the second end of the storage capacitor Cs is maintained at the potential of the previous stage, that is, Vdata.
  • the first transistor T1 is diode-connected due to the conduction of the second transistor T2, so that the compensation path formed in the previous phase is maintained in this phase (the arrow in Figure 7 Shown by the dashed line).
  • This can avoid the problem that the potential of the first end of the storage capacitor Cs does not reach VDD+Vth due to insufficient charging time in the data writing and compensation phase t2, thereby ensuring that the first end of the storage capacitor Cs is at the beginning of the light-emitting phase t4.
  • the potential at one end reaches and remains at VDD+Vth.
  • the driving circuit 100 is turned on, and the light-emitting element 700 is driven to emit light through the driving circuit 100.
  • the pixel circuit 10 including the aforementioned first light emission control circuit 610 and the second light emission control circuit 620 as an example, in the light emission stage t4, the light emission control signal EM is input, and the first light emission control circuit 610 and the second light emission control circuit 620 are turned on.
  • the driving circuit 100, the data signal Vdata stored in the compensation circuit 200 is applied to the control terminal of the driving circuit 100 through the first light emission control circuit 610 to make the driving circuit 100 generate a driving current, and the driving current is applied to the second light emission control circuit 620
  • the light-emitting element 700 causes the light-emitting element 700 to emit light.
  • the second transistor T2 and the fifth transistor T5 are turned off by the high level of the third scan signal SN3, and the third transistor T3 is turned off by the high level of the second scan signal SN2 ,
  • the fourth transistor T4 is turned off by the high level of the first scan signal SN1;
  • the sixth transistor and the seventh transistor T7 are turned on by the low level of the emission control signal EM, and the first transistor T1 is also kept on at this stage status.
  • a drive control path and a drive light-emitting path are formed (as shown by the dashed line with arrows in Figure 8, the dashed line on the left represents the drive control path, and the dashed line on the right represents the drive light-emitting path. ).
  • the reference voltage Vref charges the second end of the storage capacitor Cs through the drive control path (ie, the sixth transistor T6), so that the potential of the second end of the storage capacitor Cs changes from Vdata to Vref.
  • I LE K(Vgs-Vth) 2
  • I LE represents the driving current
  • Vth represents the threshold voltage of the first transistor T1
  • Vgs represents the voltage difference between the gate of the first transistor T1 and the first electrode such as the source
  • K is a constant value. It can be seen from the above formula that the driving current ILE flowing through the light-emitting element LE is no longer related to the threshold voltage Vth of the first transistor T1, but is only related to the data signal Vdata that controls the gray scale of the pixel circuit to emit light.
  • the compensation of the pixel circuit solves the problem of the threshold voltage drift of the driving transistor (the first transistor T1 in the embodiment of the present disclosure) due to the process and long-term operation and use, and eliminates its impact on the driving current I LE Influence, which can improve the display effect.
  • the reference voltage Vref may be the same as the first power supply voltage VDD, and embodiments of the present disclosure include but are not limited to this.
  • the above-mentioned driving current I LE is applied to the light emitting element LE through the light emitting control path, so that the light emitting element LE emits light under the action of the driving current flowing through the first transistor T1.
  • the signal timing diagram shown in FIG. 4 is schematic.
  • the signal timing during operation may be determined according to actual needs, and the present disclosure does not limit this.
  • FIG. 9A is a schematic diagram of an array substrate provided by at least one embodiment of the present disclosure
  • FIG. 9B is a schematic diagram of another array substrate provided by at least one embodiment of the present disclosure.
  • the array substrate 1 includes a plurality of pixel units 50 arranged in an array, a plurality of scanning signal lines, a plurality of light emitting control signal lines, and a plurality of data signal lines. It should be noted that only part of the pixel unit 50, scanning signal lines, light emission control signal lines, and data signal lines are shown in FIGS. 9A and 9B.
  • G_N-1, G_N, G_N+1, and G_N+2 represent the scanning signal lines used for the N-1th, Nth, N+1, and N+2th rows of the array, respectively
  • E_N-1 , E_N, E_N+1, and E_N+2 represent the light-emitting control signal lines for the N-1th, Nth, N+1, and N+2th rows of the array, respectively
  • D1_M and D2_M represent the light-emitting control signal lines for the array
  • D1_M+1 and D2_M+1 represent the data signal lines for the M+1th column of the array.
  • N is, for example, an integer greater than 1
  • M is, for example, an integer greater than 0.
  • each pixel unit 50 includes the pixel circuit 10 provided by any of the above-mentioned embodiments of the present disclosure, for example, includes the pixel circuit 10 shown in FIG. 3.
  • the input circuit 400 in the pixel circuit 10 of each row is connected to the scan signal line of the current row to receive the first scan signal SN1; the reset circuit 300 in the pixel circuit 10 of each row is connected to the scan signal line of the previous row to receive The second scan signal SN2, for another example, for the reset circuit 300 in the pixel circuit 10 of the first row, there may be an additional scan signal line to provide the second scan signal SN2; the compensation circuit in the pixel circuit 10 of each row 200 and the data writing circuit 500 are both connected to the scanning signal line of the next row to receive the third scanning signal SN3.
  • the compensation circuit 200 and the data writing circuit 500 in the pixel circuit 10 of the last row there may be another additional
  • the scan signal line of the pixel circuit 10 provides the third scan signal SN3; the first light emission control circuit 610 and the second light emission control circuit 620 in the pixel circuit 10 of each row are connected to the light emission control signal line of the row to receive the light emission control signal EM.
  • each column of pixel units corresponds to two data signal lines
  • the input circuit 400 in the pixel circuit 10 of the odd sequence in the pixel unit of this column is connected to one of the corresponding two data signal lines
  • the even number of pixel units in this column is
  • the input circuit 400 in the pixel circuit 10 of the sequence is connected to the other of the corresponding two data signal lines, so that the input circuit 400 in each pixel circuit 10 can receive the reset voltage Vinitial from the data signal line corresponding to it.
  • the data signal Vdata the data signal
  • the two data signal lines corresponding to each column of pixel units may be arranged on the same side of the column of pixel units; or, as shown in FIG. 9B, the two data signal lines corresponding to each column of pixel units may be Set on different sides of the pixel unit in this column.
  • the embodiment of the present disclosure does not limit the specific arrangement and position of the multiple data signal lines.
  • the embodiment of the present disclosure does not limit the specific arrangement and position of the multiple scanning signal lines and the multiple light-emitting control signal lines.
  • FIG. 10 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • the display device 1000 may include the array substrate 1 provided by any one of the above-mentioned embodiments of the present disclosure, and may also include a scan driving circuit 2 and a data driving circuit 3.
  • the scan driving circuit 2 may be connected to a plurality of scan signal lines GL (ie, G_N-1, G_N, G_N+1, G_N+2, etc.) to provide scan signals (for example, the first scan signal SN1, the second scan signal SN2, the third scan signal SN3); at the same time, the scan driving circuit 2 can also be connected with multiple light emission control signal lines E1 (ie E_N-1, E_N, E_N+1, E_N+2, etc.) to provide the light emission control signal EM.
  • the first scan signal SN1, the second scan signal SN2, and the third scan signal SN3 are all relative terms.
  • the first scan signal SN1 of the pixel circuit 10 of a certain row may be the pixel circuit of the next row.
  • the second scan signal SN2 of 10 may also be the third scan signal SN3 of the pixel circuit 10 of the previous row.
  • the scan drive circuit can be implemented by a bonded integrated circuit drive chip, or the scan drive circuit can be directly integrated on the display panel to form a GOA (Gate Driver On Array).
  • the data driving circuit 3 may be connected to a plurality of data signal lines DL (ie, D1_M, D2_M, D1_M+1, D2_M+1, etc.) to provide the reset voltage Vinitial and the data signal Vdata.
  • the data driving circuit can be implemented by a bonded integrated circuit driving chip.
  • the display device 1000 may also include other components, such as a timing controller, a signal decoding circuit, a voltage conversion circuit, etc. These components, for example, may adopt conventional components or structures, which will not be repeated here.
  • control signals such as scanning signals and light-emitting control signals are applied row by row according to the timing signal.
  • the pixel circuit in the N-2th row (not shown in FIGS. 9A and 9B) is in data writing and In the compensation phase, at this time, the data signal line D1 (that is, D1_M, D1_M+1, etc. shown in FIGS.
  • 9A and 9B provides the data signal of the pixel circuit of the N-2th row, and the reset circuit of the pixel circuit of the Nth row
  • the scan signal (ie, the second scan signal SN2) of the pixel circuit in the N-1th row is turned on by the low level, but the input circuit 400 of the pixel circuit in the Nth row is turned on by the scan signal of the pixel circuit in the Nth row ( That is, the first scan signal SN1) is turned off, so the pixel circuit of the Nth row will not be affected.
  • the pixel circuit of the N-2th row is in the holding stage; the pixel circuit of the N-1th row is in the data writing and compensation stage, at this time, the data signal line D2 ( That is, D2_M, D2_M+1, etc. shown in FIGS. 9A and 9B provide the data signal of the pixel circuit of the N-1th row; at the same time, the reset voltage Vinitial is provided on the data signal line D1, so that the pixel circuit of the Nth row Perform a reset operation (refer to related descriptions in Figure 4 and Figure 5).
  • the pixel circuit of the N-2th row is in the light-emitting phase, and the pixel circuit of the N-1th row is in the holding phase;
  • the data signal line D1 provides the Nth The data signal of the pixel circuit of the row, thus, the pixel circuit of the Nth row performs data writing and compensation operations (refer to the related description of FIG. 4 and FIG. 6); at the same time, a reset voltage Vinitial is provided on the data signal line D2 for The pixel circuit in the N+1th row performs a reset operation (refer to the related description of FIG. 4 and FIG. 5).
  • the pixel circuit of the N-1th row is in the light-emitting phase; the pixel circuit of the Nth row performs the holding operation (refer to the related description of FIG. 4 and FIG. 7); data signal The reset voltage Vinitial is provided on the line D1 for the pixel circuit of the N+2th row to perform the reset operation; the pixel circuit of the N+1th row is in the data writing and compensation stage, at this time, the data signal D2 is provided with the N+1th Data signal of the pixel circuit of the row.
  • the pixel circuit in the Nth row performs a light-emitting operation (refer to the related descriptions of FIG. 4 and FIG. 8); the pixel circuit in the N+1th row is in the holding phase; The pixel circuit of the +2 row is in the data writing and compensation stage, and the data signal of the pixel circuit of the N+2 row is provided on the data signal line D1.
  • the pixel circuit of the N+1th row is in the light-emitting stage.
  • the light-emitting stage of the pixel circuit in the Nth row immediately follows the light-emitting stage of the pixel circuit in the N-1th row, and the light-emitting stage of the pixel circuit in the N+1th row immediately follows the light emission of the pixel circuit in the Nth row. After the stage.
  • the display device realizes progressive scan display.
  • the display device in this embodiment may be any product or component with a display function, such as a display, a TV, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc.
  • the display device may also include other conventional components or structures.
  • a person skilled in the art can set other conventional components or structures according to specific application scenarios. This is not limited.

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  • Electroluminescent Light Sources (AREA)

Abstract

一种像素电路（10）及其驱动方法、阵列基板及显示装置。该像素电路（10）包括驱动电路（100）、输入电路（400）、补偿电路（200）、复位电路（300）、数据写入电路（500）和发光元件（700）。驱动电路（100）包括控制端（110）、第一端（120）和第二端（130），配置为控制流经第一端（120）和第二端（130）的用于驱动发光元件（700）发光的驱动电流；输入电路（400）配置为响应于第一扫描信号（SN1）传输复位电压（Vinitial）和数据信号（Vdata）；复位电路（300）配置为响应于第二扫描信号（SN2）将输入电路（400）传输的复位电压（Vinitial）施加至驱动电路（100）的控制端；补偿电路（200）配置为存储数据信号（Vdata），响应于第三扫描信号（SN3）将驱动电路（100）的控制端（110）和第二端（130）电连接；数据写入电路（500）配置为响应于第三扫描信号（SN3）将输入电路（400）传输的数据信号（Vdata）施加至补偿电路（200）。

Description

像素电路及其驱动方法、阵列基板及显示装置
本申请要求于2019年5月17日递交的中国专利申请第201910411012.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种像素电路及其驱动方法、阵列基板及显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板具有薄、轻、宽视角、主动发光、发光颜色连续可调、成本低、响应速度快、能耗小、驱动电压低、工作温度范围宽、生产工艺简单、发光效率高及可柔性显示等优点，在手机、平板电脑、数码相机等显示领域的应用越来越广泛。
发明内容
本公开至少一实施例提供一种像素电路，包括驱动电路、输入电路、补偿电路、复位电路、数据写入电路和发光元件。所述驱动电路包括控制端、第一端和第二端，且配置为控制流经所述第一端和所述第二端的用于驱动所述发光元件发光的驱动电流；所述输入电路配置为响应于第一扫描信号传输复位电压和数据信号；所述复位电路配置为响应于第二扫描信号将所述输入电路传输的所述复位电压施加至所述驱动电路的控制端；所述补偿电路配置为存储所述数据信号，且响应于第三扫描信号将所述驱动电路的控制端和第二端电连接；所述数据写入电路配置为响应于所述第三扫描信号将所述输入电路传输的所述数据信号施加至所述补偿电路。
例如，本公开一些实施例提供的像素电路还包括：发光控制电路，配置为响应于发光控制信号将所述补偿电路存储的所述数据信号施加至所述驱动电路的控制端，以使所述驱动电路产生所述驱动电流，以及响应于所述发光控制信号将对应于所述数据信号的所述驱动电流施加至所述发光元件。
例如，在本公开一些实施例提供的像素电路中，所述发光控制电路包括第一发光控制电路和第二发光控制电路，所述第一发光控制电路配置为响应于所述发光控制信号将所述补偿电路存储的所述数据信号施加至所述驱动电路的控制端，以使所述驱动电路产生所述驱动电流，所述第二发光控制电路配置为响应于所述发光控制信号将所述驱动电流施加至所述发光元件。
例如，在本公开一些实施例提供的像素电路中，所述驱动电路包括第一晶体管，所述第一晶体管的栅极作为所述驱动电路的控制端与第一节点连接，所述第一晶体管的第一极作为所述驱动电路的第一端与第一电源端连接以接收第一电源电压，所述第一晶体管的第 二极作为所述驱动电路的第二端与第二节点连接。
例如，在本公开一些实施例提供的像素电路中，所述补偿电路包括第二晶体管和存储电容，所述第二晶体管的栅极和第三扫描信号端连接以接收所述第三扫描信号，所述第二晶体管的第一极与所述第二节点连接，所述第二晶体管的第二极与所述第一节点连接，所述存储电容的第一端与所述第一晶体管的栅极耦接，所述存储电容的第二端与第三节点连接。
例如，在本公开一些实施例提供的像素电路中，所述复位电路包括第三晶体管，所述第三晶体管的栅极与第二扫描信号端连接以接收所述第二扫描信号，所述第三晶体管的第一极与第四节点连接，所述第三晶体管的第二极与所述第一节点连接。
例如，在本公开一些实施例提供的像素电路中，所述输入电路包括第四晶体管，所述第四晶体管的栅极与第一扫描信号端连接以接收所述第一扫描信号，所述第四晶体管的第一极与数据信号端连接以接收所述复位电压和所述数据信号，所述第四晶体管的第二极与所述第四节点连接。
例如，在本公开一些实施例提供的像素电路中，所述数据写入电路包括第五晶体管，所述第五晶体管的栅极与所述第三扫描信号端连接以接收所述第三扫描信号，所述第五晶体管的第一极与所述第四节点连接，所述第五晶体管的第二极与所述第三节点连接。
例如，在本公开一些实施例提供的像素电路中，所述第一发光控制电路包括第六晶体管，所述第六晶体管的栅极与发光控制信号端连接以接收所述发光控制信号，所述第六晶体管的第一极与参考电压端连接以接收参考电压，所述第六晶体管的第二极与所述第三节点连接。
例如，在本公开一些实施例提供的像素电路中，所述第二发光控制电路包括第七晶体管，所述第七晶体管的栅极与所述发光控制信号端连接以接收所述发光控制信号，所述第七晶体管的第一极与所述第二节点连接，所述第七晶体管的第二极与所述发光元件的第一极连接，所述发光元件的第二极与第二电源端连接以接收第二电源电压。
例如，在本公开一些实施例提供的像素电路中，所述参考电压与所述第一电源电压相同。
例如，在本公开一些实施例提供的像素电路中，所述驱动电路包括第一晶体管，所述补偿电路包括第二晶体管和存储电容，所述复位电路包括第三晶体管，所述输入电路包括第四晶体管，所述数据写入电路包括第五晶体管，所述第一晶体管的栅极作为所述驱动电路的控制端与第一节点连接，所述第一晶体管的第一极作为所述驱动电路的第一端与第一电源端连接以接收第一电源电压，所述第一晶体管的第二极作为所述驱动电路的第二端与第二节点连接；所述第二晶体管的栅极和第三扫描信号端连接以接收所述第三扫描信号，所述第二晶体管的第一极与所述第二节点连接，所述第二晶体管的第二极与所述第一节点连接，所述存储电容的第一端与所述第一晶体管的栅极耦接，所述存储电容的第二端与第三节点连接；所述第三晶体管的栅极与第二扫描信号端连接以接收所述第二扫描信号，所 述第三晶体管的第一极与第四节点连接，所述第三晶体管的第二极与所述第一节点连接；所述第四晶体管的栅极与第一扫描信号端连接以接收所述第一扫描信号，所述第四晶体管的第一极与数据信号端连接以接收所述复位电压和所述数据信号，所述第四晶体管的第二极与所述第四节点连接；所述第五晶体管的栅极与所述第三扫描信号端连接以接收所述第三扫描信号，所述第五晶体管的第一极与所述第四节点连接，所述第五晶体管的第二极与所述第三节点连接。
本公开至少一实施例还提供一种阵列基板，包括阵列排布的多个像素单元。每个所述像素单元包括根据本公开任一实施例提供的像素电路。
例如，本公开一些实施例提供的阵列基板还包括：多条数据信号线。每一列像素单元对应两条数据信号线，本列像素单元中的奇数序列的像素电路中的输入电路与对应的所述两条数据信号线中的一条连接，本列像素单元中的偶数序列的像素电路中的输入电路与对应的所述两条数据信号线中的另一条连接。
例如，在本公开一些实施例提供的阵列基板中，每一列像素单元对应的所述两条数据信号线设置在本列像素单元的同一侧或不同侧。
本公开至少一实施例还提供一种显示装置，包括本公开任一实施例提供的阵列基板。
本公开至少一实施例还提供一种对应于本公开任一实施例提供的像素电路的驱动方法，包括：复位阶段、数据写入和补偿阶段、保持阶段和发光阶段。在所述复位阶段，输入所述第一扫描信号和所述第二扫描信号，开启所述输入电路和所述复位电路，通过所述输入电路和所述复位电路对所述驱动电路的控制端进行复位；在所述数据写入和补偿阶段，输入所述第一扫描信号和所述第三扫描信号，开启所述输入电路、所述数据写入电路、所述驱动电路和所述补偿电路，通过所述输入电路和所述数据写入电路将所述数据信号写入所述补偿电路，通过所述补偿电路对所述驱动电路进行补偿；在所述保持阶段，输入所述第三扫描信号，开启所述驱动电路和所述补偿电路，通过所述补偿电路持续对所述驱动电路进行补偿；在所述发光阶段，开启所述驱动电路，通过所述驱动电路驱动所述发光元件发光。
例如，在本公开一些实施例提供的驱动方法中，所述像素电路还包括：第一发光控制电路和第二发光控制电路，所述第一发光控制电路配置为响应于发光控制信号将所述补偿电路存储的所述数据信号施加至所述驱动电路的控制端以使所述驱动电路产生所述驱动电流，所述第二发光控制电路配置为响应于所述发光控制信号将所述驱动电流施加至所述发光元件；在所述发光阶段，开启所述驱动电路，通过所述驱动电路驱动所述发光元件发光，包括：在所述发光阶段，输入所述发光控制信号，开启所述第一发光控制电路、所述第二发光控制电路和所述驱动电路，通过所述第一发光控制电路将所述补偿电路存储的所述数据信号施加至所述驱动电路的控制端以使所述驱动电路产生所述驱动电流，通过所述第二发光控制电路将所述驱动电流施加至所述发光元件以使所述发光元件发光。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种2T1C像素电路的示意图；
图1B为另一种2T1C像素电路的示意图；
图2为本公开至少一实施例提供的一种像素电路的示意框图；
图3为图2中所示的像素电路的一种具体实现示例的电路结构示意图；
图4为本公开至少一实施例提供的一种像素电路的驱动方法的信号时序图；
图5至图8分别为图3中所示的像素电路对应于图4中四个阶段的电路示意图；
图9A为本公开至少一实施例提供的一种阵列基板的示意图；
图9B为本公开至少一实施例提供的另一种阵列基板的示意图；以及
图10为本公开至少一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面通过几个具体的实施例对本公开进行说明。为了保持本公开实施例的以下说明清楚且简明，可省略已知功能和已知部(元)件的详细说明。当本公开实施例的任一部(元)件在一个以上的附图中出现时，该部(元)件在每个附图中由相同或类似的参考标号表示。
OLED显示面板中的像素电路一般采用矩阵驱动方式，根据每个像素单元中是否引入开关元器件分为有源矩阵(Active Matrix，AM)驱动和无源矩阵(Passive Matrix，PM)驱动。其中，AMOLED在每一个像素的像素电路中都集成了一组薄膜晶体管和存储电容，通过对薄膜晶体管和存储电容的驱动控制，实现对流过OLED的电流的控制，从而使OLED根据需要发光。因此，AMOLED所需驱动电流小、功耗低、寿命更长，可以满足高分辨率多灰 度的大尺寸显示需求。同时，AMOLED在可视角度、色彩的还原、功耗以及响应时间等方面具有明显的优势，适用于高信息含量、高分辨率的显示装置。
AMOLED显示面板中使用的基础像素电路通常为2T1C像素电路，即利用两个TFT(Thin-film transistor，薄膜晶体管)和一个存储电容Cs来实现驱动OLED发光的基本功能。图1A和图1B分别示出了两种2T1C像素电路的示意图。
如图1A所示，一种2T1C像素电路包括开关晶体管T0、驱动晶体管N0以及存储电容Cs。例如，该开关晶体管T0的栅极连接扫描线以接收扫描信号Scan1，例如源极连接到数据信号线以接收数据信号Vdata，漏极连接到驱动晶体管N0的栅极；驱动晶体管N0的源极连接到第一电压端以接收第一电压Vdd(高电压)，漏极连接到OLED的正极端；存储电容Cs的一端连接到开关晶体管T0的漏极以及驱动晶体管N0的栅极，另一端连接到驱动晶体管N0的源极以及第一电压端；OLED的负极端连接到第二电压端以接收第二电压Vss(低电压，例如接地电压)。该2T1C像素电路的驱动方式是将像素的明暗(灰阶)经由两个TFT和存储电容Cs来控制。当通过扫描线施加扫描信号Scan1以开启开关晶体管T0时，数据驱动电路通过数据信号线送入的数据信号Vdata将经由开关晶体管T0对存储电容Cs充电，由此将数据信号Vdata存储在存储电容Cs中，且此存储的数据信号Vdata控制驱动晶体管N0的导通程度，由此控制流过驱动晶体管以驱动OLED发光的电流大小，即此电流决定该像素发光的灰阶。在图1A所示的2T1C像素电路中，开关晶体管T0为N型晶体管而驱动晶体管N0为P型晶体管。
如图1B所示，另一种2T1C像素电路也包括开关晶体管T0、驱动晶体管N0以及存储电容Cs，但是其连接方式略有改变，且驱动晶体管N0为N型晶体管。图1B的像素电路相对于图1A的变化之处包括：OLED的正极端连接到第一电压端以接收第一电压Vdd(高电压)，而负极端连接到驱动晶体管N0的漏极，驱动晶体管N0的源极连接到第二电压端以接收第二电压Vss(低电压，例如接地电压)。存储电容Cs的一端连接到开关晶体管T0的漏极以及驱动晶体管N0的栅极，另一端连接到驱动晶体管N0的源极以及第二电压端。该2T1C像素电路的工作方式基本上与图1A所示的像素电路基本相同，这里不再赘述。
此外，对于图1A和图1B所示的像素电路，开关晶体管T0不限于N型晶体管，也可以为P型晶体管，由此控制其导通或截止的扫描信号Scan1的极性进行相应地改变即可。
AMOLED显示面板通常包括阵列排布的多个像素单元，每个像素单元例如可以包括上述像素电路。在AMOLED显示面板中，各个像素电路中的驱动晶体管的阈值电压由于制备工艺可能存在差异，以及由于例如长时间加电压和高温等外部因素的影响，驱动晶体管的阈值电压都可能会产生漂移现象。例如，由于显示画面不同，显示面板各部分驱动晶体管的阈值电压漂移量不同，会造成显示亮度差异，这种差异与之前显示的图像有关，因此常呈现为残影现象，也就是通常所说的残像。例如，OLED显示装置在点亮黑白相间的画面一段时间后，再切换为同一灰阶的画面时，容易产生残像，该残像经过一段时间后会自然消失，这种现象称为短期残像。
由于各个驱动晶体管的阈值电压的不同可能会导致显示不良(例如显示不均匀)，所以就需要对阈值电压进行补偿。因此，在上述2T1C的基本像素电路的基础上，还发展出了其他具有例如补偿功能、复位功能等的像素电路。
本公开至少一实施例提供一种像素电路。该像素电路包括驱动电路、输入电路、补偿电路、复位电路、数据写入电路和发光元件。驱动电路包括控制端、第一端和第二端，且配置为控制流经第一端和第二端的用于驱动发光元件发光的驱动电流；输入电路配置为响应于第一扫描信号传输复位电压和数据信号；复位电路配置为响应于第二扫描信号将输入电路传输的复位电压施加至驱动电路的控制端；补偿电路配置为存储数据信号，且响应于第三扫描信号将驱动电路的控制端和第二端电连接；数据写入电路配置为响应于第三扫描信号将输入电路传输的数据信号施加至补偿电路。
本公开的一些实施例还提供对应于上述像素电路的驱动方法、阵列基板及显示装置。
本公开的至少一实施例提供的像素电路及其驱动方法、阵列基板及显示装置，可以对驱动电路的阈值电压进行补偿，同时每次切换画面时，还可以对驱动电路进行复位，使驱动电路的控制端处于同样的偏压状态下，从而可以抑制短期残像现象的发生。
下面结合附图对本公开的一些实施例及其示例进行详细说明。
图2为本公开至少一实施例提供的一种像素电路的示意框图。例如，像素电路10可以用于AMOLED显示面板的子像素中。如图2所示，像素电路10包括驱动电路100、输入电路400、补偿电路200、复位电路300、数据写入电路500和发光元件700。
例如，驱动电路100包括控制端110、第一端120和第二端130，且配置为控制流经第一端120和第二端130的用于驱动发光元件700发光的驱动电流。例如，在一些示例中，在发光阶段，驱动电路100可以向发光元件700提供驱动电流以驱动发光元件700进行发光，且可以根据需要显示的灰阶(不同的灰阶对应于不同的数据信号)提供相应的驱动电流发光。例如，发光元件700可以采用有机发光二极管(OLED)、量子点发光二极管(QLED)、无机发光二极管等，本公开的实施例包括但不限于此。
例如，输入电路400配置为响应于第一扫描信号SN1传输复位电压Vinitial和数据信号Vdata。例如，在一些示例中，在复位阶段，开关电路400响应于第一扫描信号SN1而导通，从而将复位电压Vinitial传输至复位电路300，并经由复位电路300将复位电压Vinitial施加至驱动电路100的控制端110，以对驱动电路100进行复位操作；在数据写入和补偿阶段，开关电路400仍然响应于第一扫描信号SN1而导通，从而将数据信号Vdata传输至数据写入电路500，并经由数据写入电路500将数据信号Vdata写入并存储于补偿电路200中，以在发光阶段时使驱动电路100根据该数据信号Vdata产生驱动发光元件700发光的驱动电流。
例如，在一些示例中，数据写入和补偿阶段紧随在复位阶段之后，从而第一扫描信号在复位阶段与数据写入和补偿阶段是一个连续的脉冲信号。
例如，复位电路300配置为响应于第二扫描信号SN2将输入电路400传输的复位电压 Vinitial施加至驱动电路100的控制端110。例如，在一些示例中，在复位阶段，复位电路300响应于第二扫描信号SN2而导通，从而可以将输入电路400传输过来的复位电压Vinitial施加至驱动电路100的控制端110，以对驱动电路100进行复位操作。
例如，数据写入电路500配置为响应于第三扫描信号SN3将输入电路400传输的数据信号Vdata施加至补偿电路200。例如，在一些示例中，在数据写入和补偿阶段，数据写入电路500响应于第三扫描信号SN3而导通，从而可以将输入电路400传输过来的数据信号Vdata写入并存储于补偿电路200中，以在发光阶段时使驱动电路100根据该数据信号Vdata产生驱动发光元件700发光的驱动电流。
例如，补偿电路200配置为存储写入的数据信号Vdata，且响应于第三扫描信号SN3将驱动电路100的控制端110和第二端130电连接。例如，在一些示例中，补偿电路200包括存储电容；在数据写入和补偿阶段，存储电容可以接收并存储数据写入电路500写入的数据信号Vdata，同时，补偿电路200响应于第三扫描信号SN3而导通，将驱动电路100的控制端110和第二端130电连接，从而使驱动电路的阈值电压Vth的相关信息也相应地存储在存储电容中，进而在发光阶段可以利用存储的包括数据信号Vdata以及阈值电压Vth等信息的电压对驱动电路100进行控制，使得驱动电路100在得到补偿的情况下根据数据信号Vdata产生驱动发光元件700发光的驱动电流。
例如，在本公开的至少一个实施例中，如图2所示，像素电路10还可以包括发光控制电路600。发光控制电路600配置为响应于发光控制信号EM将补偿电路200存储的数据信号Vdata施加至驱动电路100的控制端110，以使驱动电路100根据该数据信号Vdata产生驱动电流，以及同时响应于发光控制信号EM将对应于数据信号Vdata的驱动电流施加至发光元件700，从而使驱动发光元件700发光，进而显示需要显示的灰阶。
例如，在本实施例的至少一个示例中，如图2所示，发光控制电路600可以包括第一发光控制电路610，其配置为响应于发光控制信号EM将补偿电路200存储的数据信号Vdata施加至驱动电路100的控制端110，以使驱动电路100产生驱动电流。例如，在一些示例中，在发光阶段，第一发光控制电路响应于发光控制信号EM而导通，从而可以将参考电压Vref施加至补偿电路200中的存储电容的一端，进而通过该存储电容的自举效应将包括数据信号Vdata以及阈值电压Vth等信息的电压施加至驱动电路100的控制端110，以控制驱动电路100在得到补偿的情况下根据数据信号Vdata产生驱动发光元件700发光的驱动电流。例如，参考电压Vref可以是驱动电压，例如高电压。
例如，在本实施例的至少一个示例中，如图2所示，发光控制电路600还可以包括第二发光控制电路620，其配置为响应于发光控制信号EM将驱动电流施加至发光元件700。例如，在发光阶段，第二发光控制电路620响应于发光控制信号EM而导通，从而驱动电路100可以通过第二发光控制电路620将驱动电流施加至发光元件700以使其发光；而在非发光阶段，第二发光控制电路620响应于发光控制信号EM而截止，避免发光元件700发光，从而可以提高相应的显示装置的对比度。
需要说明的是，在本公开的实施例中所述的第一扫描信号SN1、第二扫描信号SN2和第三扫描信号SN3是为了区别三个时序不同的控制信号(例如，扫描信号)。例如，如下所述，在一种示例性的显示装置中，当像素电路10呈阵列排布时，第一扫描信号SN1可以为控制本行像素电路10中的输入电路400的控制信号；第二扫描信号SN2可以为控制上一行像素电路10中的输入电路400的控制信号，同时，第二扫描信号SN2还控制本行像素电路10中的复位电路300；第三扫描信号SN3可以为控制下一行像素电路10中的输入电路400的控制信号，同时，第三扫描信号SN3还控制本行像素电路10中的数据写入电路500和补偿电路200。
图3为图2中所示的像素电路的一种具体实现示例的电路结构示意图。如图3所示，该像素电路10包括：第一至第七晶体管T1、T2、T3、T4、T5、T6、T7以及存储电容Cs和发光元件LE。例如，第一晶体管T1被用作驱动晶体管，其他的第二至第七晶体管被用作开关晶体管。例如，发光元件LE可以采用OLED，本公开的实施例包括但不限于此，以下实施例均以OLED为例进行说明，不再赘述。该OLED可以为各种类型，例如顶发射、底发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。另外，还需要说明的是，以下实施例还以各晶体管为P型晶体管为例进行说明，但这并不构成对本公开的实施例的限制。
例如，如图3所示，驱动电路100可以实现为第一晶体管T1。第一晶体管T1的栅极作为驱动电路100的控制端110和第一节点N1连接，第一晶体管T1的第一极作为驱动电路100的第一端120和第一电源端ELVDD连接以接收第一电源电压VDD，第一晶体管T1的第二极作为驱动电路100的第二端130和第二节点N2连接。例如，第一电源电压VDD可以是驱动电压，例如高电压。
例如，如图3所示，补偿电路200可以实现为第二晶体管T2和存储电容Cs。第二晶体管T2的栅极和第三扫描信号端连接以接收第三扫描信号SN3，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第一节点N1连接，存储电容Cs的第一端与第一晶体管T1的栅极耦接(即与第一节点N1连接)，存储电容Cs的第二端与第三节点N3连接。例如，存储电容Cs可以存储第一节点N1和第三节点N3之间的电位差，具体地，存储电容Cs的第一端存储第一节点N1的电位，存储电容Cs的第二端存储第三节点N3的电位。
例如，如图3所示，复位电路300可以实现为第三晶体管T3。第三晶体管T3的栅极与第二扫描信号端连接以接收第二扫描信号SN2，第三晶体管T3的第一极与第四节点N4连接，第三晶体管T3的第二极与第一节点N1连接。
例如，如图3所示，输入电路400可以实现为第四晶体管T4。第四晶体管T4的栅极与第一扫描信号端连接以接收第一扫描信号SN1，第四晶体管T4的第一极与数据信号端DATA连接以在操作中的不同时刻接收复位电压Vinitial和数据信号Vdata，第四晶体管T4的第二极与第四节点N4连接。例如，复位电压Vinitial可以为零电压或接地电压，也可以 为其他固定的电平，例如低电压等，本公开的实施例对此不作限制。
例如，如图3所示，数据写入电路500可以实现为第五晶体管T5。第五晶体管T5的栅极与第三扫描信号端连接以接收第三扫描信号SN3，第五晶体管T5的第一极与第四节点N4连接，第五晶体管T5的第二极与第三节点N3连接。
例如，如图3所示，第一发光控制电路610可以实现为第六晶体管T6。第六晶体管T6的栅极与发光控制信号端连接以接收发光控制信号EM，第六晶体管T6的第一极与参考电压端连接以接收参考电压Vref，第六晶体管T6的第二极与第三节点N3连接。例如，参考电压Vref可以是驱动电压，例如高电压。例如，在一些示例中，参考电压Vref可以与第一电源电压VDD相同。
例如，如图3所示，第二发光控制电路620可以实现为第七晶体管T7。第七晶体管T7的栅极与发光控制信号端连接以接收发光控制信号EM，第七晶体管T6的第一极与第二节点N2连接，第七晶体管T7的第二极与发光元件LE的第一极(例如，阳极)连接，所述发光元件LE的第二极(例如，阴极)与第二电源端ELVSS连接以接收第二电源电压VSS。例如第二电源电压VSS可以为低电压，例如，第二电源端ELVSS可以接地，从而第二电源电压VSS可以为零电压。
对于如图3所示的像素电路10，在第一扫描信号SN1和第二扫描信号SN2同时处于有效电平(例如，低电压)时，第四晶体管T4和第三晶体管T3可以同时导通，此时数据信号端DATA提供复位电压Vinitial，从而可以通过第四晶体管T4和第三晶体管T3对第一晶体管T1的控制端施加该复位电压，以进行复位操作。
在第一扫描信号SN1和第二扫描信号SN3同时处于有效电平时，第四晶体管T4和第五晶体管T5可以同时导通，此时数据信号端DATA提供数据信号Vdata，从而可以通过第四晶体管T4和第五晶体管T5将数据信号Vdata存储在存储电容Cs中。
在第三扫描信号SN3处于有效电平时，第二晶体管T2可以导通，从而将第一晶体管T1的栅极(第一节点N1)和第一晶体管T1的第二极(第二节点N2)连接，此时第一晶体管T1呈二极管连接方式，第一晶体管T1(驱动晶体管)的阈值电压Vth可以通过其自身得到补偿。
需要说明的是，在本公开的实施例中，存储电容Cs可以是通过工艺制程制作的电容器件，例如通过制作专门的电容电极来实现电容器件，电容的各个电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现，并且，电容也可以是各个器件之间的寄生电容，可以通过晶体管本身与其他器件、线路来实现。电容的连接方式不局限于上面描述的方式，也可以为其他适用的连接方式，只要能存储相应节点的电平即可。
需要说明的是，在本公开的实施例的说明中，第一节点N1、第二节点N2、第三节点N3和第四节点N4并非表示必须实际存在的部件，而是表示电路图中相关电连接的汇合点。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用 的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，在本公开的实施例中的晶体管均以P型晶体管为例进行说明，此时，晶体管的第一极是源极，第二极是漏极。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的像素电路10中的一个或多个晶体管也可以采用N型晶体管，此时，晶体管第一极是漏极，第二极是源极，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接，并且使相应的电压端提供对应的高电压或低电压即可。当采用N型晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
需要说明的是，在本公开的实施例中，均是以发光元件LE的阴极接入第二电源电压VSS(低电压)为例进行说明的，本公开的实施例包括但不限于此。例如，还可以使发光元件LE的阳极接入第一电源电压VDD(高电压)，而其阴极则直接或间接地连接到驱动电路，例如可以参考图1B所示的2T1C像素电路。
需要说明的是，在本公开的实施例提供的像素电路中，“有效电平”指的是能够使得其包括的***作晶体管被导通的电平，相应地“无效电平”指的是不能使得其包括的***作晶体管被导通(即，该晶体管被截止)的电平。根据移位寄存器单元的电路结构中的晶体管的类型(N型或P型)等因素，有效电平可以比无效电平高或者低。例如，在本公开实施例中，当各个晶体管均为P型晶体管时，有效电平为低电平，无效电平为高电平。
本公开至少一实施例还提供一种像素电路的驱动方法。图4为本公开至少一实施例提供的一种像素电路的驱动方法的信号时序图。下面结合图4所示的信号时序图，对本公开实施例提供的像素电路10的驱动方法进行说明。需要说明的是，图4中所示的信号时序图的电位的高低仅是示意性的，不代表真实电位值或相对比例，对应于本公开的实施例，低电平信号对应于P型晶体管的导通信号，而高电平信号对应于P型晶体管的截止信号。
图5至图8分别为图3中所示的像素电路对应于图4中四个阶段的电路示意图。下面以图2所示的像素电路(其中，图2所示的像素电路具体实现为图3所示的电路结构)为例，并结合图5至图8对该像素电路的驱动方法进行详细说明。
例如，如图4所示，本实施例提供的驱动方法可以包括四个阶段，分别为复位阶段t1、数据写入和补偿阶段t2、保持阶段t3以及发光阶段t4，图4中示出了每个阶段中各个信号的时序波形。
需要说明的是，图5为图3所示的像素电路处于复位阶段t1时的电路示意图，图6为图3所示的像素电路处于数据写入和补偿阶段t2时的电路示意图，图7为图3所示的像素电路处于保持阶段t3时的电路示意图，图8为图3所示的像素电路处于发光阶段t4时的电路示意图。另外，图5至图8中用虚线标识的晶体管均表示在对应阶段内处于截止状态， 图5至图8中带箭头的虚线表示像素电路在对应阶段内的电流路径(箭头方向并不表示电流方向)。图5至图8中所示的晶体管均以P型晶体管为例，即各个晶体管的栅极在接入低电平时导通，而在接入高电平时截止。以下实施例与此相同，不再赘述。
在复位阶段t1，输入第一扫描信号SN1和第二扫描信号SN2，开启(即导通)输入电路400和复位电路300，通过输入电路400和复位电路300对驱动电路100的控制端进行复位。
如图4和图5所示，在复位阶段1，第四晶体管T4被第一扫描信号SN1的低电平导通，第三晶体管T3被第二扫描信号SN2的低电平导通；同时，第二晶体管T2和第五晶体管T5被第三扫描信号SN3的高电平截止，第六晶体管T6和第七晶体管T7被发光控制信号EM的高电平截止。
如图5所示，在复位阶段1，形成一条复位路径(如图5中带箭头的虚线所示)，由于复位电压Vinitial为低电平(例如可以接地或为其他低电平)，存储电容Cs通过复位路径(即第四晶体管T4和第三晶体管T3)进行放电，使存储电容Cs的第一端和第一晶体管T1的栅极(也即第一节点N1)的电位变为Vinitial，从而采用上述像素电路的显示装置在每次切换画面时均会对驱动电路进行复位，进而可以抑制短期残像现象的发生。
在数据写入和补偿阶段t2，输入第一扫描信号SN1和第三扫描信号SN3，开启输入电路400、数据写入电路500、驱动电路100和补偿电路200，通过输入电路400和数据写入电路500将数据信号写入补偿电路200，通过补偿电路200对驱动电路100进行补偿。
如图4和图6所示，在数据写入和补偿阶段t2，第二晶体管T2被第三扫描信号SN1的低电平导通，第五晶体管T5和第二晶体管T2被第三扫描信号SN3的低电平导通，此时，由于第二晶体管T2的导通，第一晶体管T1呈二极管连接方式(第一晶体管T1的栅极和第二极连接)；同时，第三晶体管T3被第二扫描信号SN2的高电平截止，第六晶体管T6和第七晶体管T7被发光控制信号EM的高电平截止。
如图6所示，在数据写入和补偿阶段t2，形成一条数据写入路径和一条补偿路径(如图6中带箭头的虚线所示，左侧的虚线代表数据写入路径，右侧的虚线代表补偿路径)。数据信号Vdata经过数据写入路径(即第四晶体管T4和第五晶体管T5)对存储电容Cs的第二端(即第三节点N3)进行放电，使存储电容Cs的第二端的电位变为Vdata；第一电源电压端ELVDD(提供第一电源电压VDD)通过补偿路径(即第一晶体管T1和第二晶体管T2)对存储电容Cs的第一端(即第一节点N1，也即第一晶体管T1的栅极)进行充电，同时，根据第一晶体管T1的自身特性，当存储电容Cs的第一端的电位增大到VDD+Vth时，第一晶体管T1截止，充电过程结束。需要说明的是，Vth表示第一晶体管的阈值电压，由于在本公开中，第一晶体管T1是以P型晶体管为例就行说明的，所以此处阈值电压Vth可以是负值。
经过数据写入和补偿阶段t2后，存储电容Cs的第二端的电位为Vdata，存储电容Cs的第一端的电位为VDD+Vth，从而存储电容Cs的两端的电位差为VDD+Vth-Vdata。也就 是说，将带有数据信号Vdata和阈值电压Vth的电压信息存储在了存储电容Cs中，以用于后续在发光阶段时，提供灰度显示数据和对第一晶体管T1自身的阈值电压进行补偿。
在保持阶段t3，输入第三扫描信号SN3，开启驱动电路100和补偿电路200，通过补偿电路200持续对驱动电路100进行补偿。
如图4和图7所示，在保持阶段t3，第二晶体管T2被第三扫描信号SN3的低电平导通，第一晶体管T1呈二极管连接方式；同时，第三晶体管T3被第二扫描信号SN2的高电平截止，第四晶体管T4被第一扫描信号SN1的高电平截止，第六晶体管T6和第七晶体管T7被发光控制信号EM的高电平截止；另外，虽然第五晶体管T5也被第三扫描信号SN3的低电平导通，但是并未形成存储电容Cs的第二端的放电路径，因此，存储电容Cs的第二端的电位保持为上一阶段的电位即Vdata。
如图7所示，在保持阶段t3，第一晶体管T1由于第二晶体管T2的导通而呈二极管连接方式，从而上一阶段形成的补偿路径在本阶段得以保持(如图7中带箭头的虚线所示)。这样可以避免例如由于数据写入和补偿阶段t2的充电时间不足而导致存储电容Cs的第一端的电位未达到VDD+Vth的问题，从而可以确保在发光阶段t4开始时，存储电容Cs的第一端的电位达到且保持为VDD+Vth。
在发光阶段t4，开启驱动电路100，通过驱动电路100驱动发光元件700发光。具体地，以像素电路10包括前述第一发光控制电路610和第二发光控制电路620为例，在发光阶段t4，输入发光控制信号EM，开启第一发光控制电路610、第二发光控制电路620和驱动电路100，通过第一发光控制电路610将补偿电路200存储的数据信号Vdata施加至驱动电路100的控制端以使驱动电路100产生驱动电流，通过第二发光控制电路620将驱动电流施加至发光元件700以使发光元件700发光。
如图4和图8所示，在发光阶段t4，第二晶体管T2和第五晶体管T5被第三扫描信号SN3的高电平截止，第三晶体管T3被第二扫描信号SN2的高电平截止，第四晶体管T4被第一扫描信号SN1的高电平截止；第六晶体管和第七晶体管T7被发光控制信号EM的低电平导通，同时第一晶体管T1在此阶段也保持为导通状态。
如图8所示，在发光阶段t4，形成一条驱动控制路径和一条驱动发光路径(如图8中带箭头的虚线所示，左侧的虚线代表驱动控制路径，右侧的虚线代表驱动发光路径)。参考电压Vref经过驱动控制路径(即第六晶体管T6)对存储电容Cs的第二端进行充电，使存储电容Cs的第二端的电位从Vdata变为Vref，由于存储电容Cs的自举效应，存储电容Cs两端的电位差保持不变(即保持为VDD+Vth-Vdata)，从而存储电容Cs的第一端的电位从VDD+Vth变为Vref+VDD+Vth-Vdata。也就是说，第一晶体管T1(即驱动晶体管)的栅极的电压变为Vref+VDD+Vth-Vdata，从而，第一晶体管T1产生的驱动电流可以根据下述公式得出：
I LE＝K(Vgs-Vth) 2
＝K[(Vref+VDD+Vth-Vdata-VDD)-Vth] 2
＝K(Vref-Vdata) 2
在上述公式中，I LE表示驱动电流，Vth表示第一晶体管T1的阈值电压，Vgs表示第一晶体管T1的栅极和第一极例如源极之间的电压差，K为一常数值。从上述公式可以看出，流经发光元件LE的驱动电流ILE不再与第一晶体管T1的阈值电压Vth有关，而只与控制该像素电路发光的灰度的数据信号Vdata有关，由此可以实现对该像素电路的补偿，解决了驱动晶体管(在本公开的实施例中为第一晶体管T1)由于工艺制程及长时间的操作使用造成的阈值电压漂移的问题，消除其对驱动电流I LE的影响，从而可以改善显示效果。需要说明的是，在一些示例中，参考电压Vref可以与第一电源电压VDD相同，本公开的实施例包括但不限于此。
上述驱动电流I LE经过发光控制路径施加至发光元件LE，从而发光元件LE在流经第一晶体管T1的驱动电流的作用下发光。
需要说明的是，图4所示的信号时序图是示意性的，对于本公开的实施例提供的像素电路，其工作时的信号时序可以根据实际需要而定，本公开对此不作限制。例如，在一些示例中，考虑到数据信号线的电压降(IR DROP)的影响以及实际提供的第一扫描信号SN1可能并非完美的方波信号，实际提供的数据信号可能为如图4中虚线所示的Vdata1(为显示清楚，图4中Vdata1低于Vdata，但实际上Vdata1＝Vdata)，其下降沿位于保持阶段t3中，从而即使存在电压降或/和实际提供的第一扫描信号SN1偏离完美的方波信号的影响，在数据写入和补偿阶段结束时，写入存储电容Cs的第二端的数据信号仍可确定为Vdata。
本公开的实施例提供的像素电路的驱动方法的技术效果参考上述实施例中关于像素电路10的相应描述，在此不再赘述。
本公开至少一实施例还提供一种阵列基板。图9A为本公开至少一实施例提供的一种阵列基板的示意图，图9B为本公开至少一实施例提供的另一种阵列基板的示意图。
如图9A和图9B所示，该阵列基板1包括阵列排布的多个像素单元50，多条扫描信号线、多条发光控制信号线和多条数据信号线。需要说明的是，在图9A和图9B中仅示出了部分的像素单元50、扫描信号线、发光控制信号线和数据信号线。例如，G_N-1、G_N、G_N+1和G_N+2分别表示用于阵列的第N-1行、第N行、第N+1行和第N+2行的扫描信号线，E_N-1、E_N、E_N+1和E_N+2分别表示用于阵列的第N-1行、第N行、第N+1行和第N+2行的发光控制信号线；D1_M和D2_M表示用于阵列的第M列的数据信号线，D1_M+1和D2_M+1表示用于阵列的第M+1列的数据信号线。这里，N例如为大于1的整数，M例如为大于0的整数。
例如，每个像素单元50包括本公开上述任一实施例提供的像素电路10，例如包括图3中所示的像素电路10。
例如，每一行的像素电路10中的输入电路400与本行的扫描信号线连接以接收第一扫描信号SN1；每一行的像素电路10中的复位电路300与上一行的扫描信号线连接以接收第二扫描信号SN2，又例如，对于第一行的像素电路10中的复位电路300，可以有一条额外 的扫描信号线为其提供第二扫描信号SN2；每一行的像素电路10中的补偿电路200和数据写入电路500均与下一行的扫描信号线连接以接收第三扫描信号SN3，例如，对于最后一行的像素电路10中的补偿电路200和数据写入电路500，可以有另一条额外的扫描信号线为其提供第三扫描信号SN3；每一行的像素电路10中的第一发光控制电路610和第二发光控制电路620与本行的发光控制信号线连接以接收发光控制信号EM。
例如，每一列像素单元对应两条数据信号线，本列像素单元中的奇数序列的像素电路10中的输入电路400与对应的两条数据信号线中的一条连接，本列像素单元中的偶数序列的像素电路10中的输入电路400与对应的两条数据信号线中的另一条连接，从而，每个像素电路10中的输入电路400可以从与之对应连接的数据信号线接收复位电压Vinitial和数据信号Vdata。
例如，如图9A所示，每一列像素单元对应的两条数据信号线可以设置在本列像素单元的同一侧；或者，如图9B所示，每一列像素单元对应的两条数据信号线可以设置在本列像素单元的不同侧。需要说明的是，本公开的实施例对多条数据信号线的具体设置方式和位置不作限制。另外，本公开的实施例对多条扫描信号线和多条发光控制信号线的具体设置方式和位置亦不作限制。
本公开的至少一实施例提供的阵列基板1的技术效果可以参考上述实施例中关于像素电路10的相应描述，在此不再赘述。
本公开至少一实施例还提供一种显示装置。图10为本公开至少一实施例提供的一种显示装置的示意图。例如，如图10所示，该显示装置1000可以包括本公开上述任一实施例提供的阵列基板1，还可以包括扫描驱动电路2和数据驱动电路3。
例如，扫描驱动电路2可以与多条扫描信号线GL(即G_N-1、G_N、G_N+1和G_N+2等)连接，以提供扫描信号(例如，第一扫描信号SN1、第二扫描信号SN2、第三扫描信号SN3)；同时，扫描驱动电路2还可以与多条发光控制信号线El(即E_N-1、E_N、E_N+1和E_N+2等)连接以提供发光控制信号EM。需要说明的是，第一扫描信号SN1、第二扫描信号SN2、第三扫描信号SN3都是相对而言的，例如，某一行的像素电路10的第一扫描信号SN1可以是下一行的像素电路10的第二扫描信号SN2，还可以是上一行的像素电路10的第三扫描信号SN3。例如，扫描驱动电路可以通过绑定的集成电路驱动芯片实现，也可以将扫描驱动电路直接集成在显示面板上构成GOA(Gate driver On Array)。
例如，数据驱动电路3可以与多条数据信号线DL(即D1_M、D2_M、D1_M+1、D2_M+1等)连接，以提供复位电压Vinitial和数据信号Vdata。例如，数据驱动电路可以通过绑定的集成电路驱动芯片实现。
该显示装置1000还可以包括其他部件，例如时序控制器、信号解码电路、电压转换电路等，这些部件例如可以采用常规部件或结构，在此不再赘述。
下面结合图4所示实施例中的驱动方法对该显示装置的逐行扫描过程进行描述，本实施例中的各个阶段可参考图4所示实施例中的相应描述。需要说明的是，在逐行扫描过程 过程中，控制信号例如扫描信号和发光控制信号都是根据时序信号逐行施加的。
例如，在第N行的像素电路的复位阶段t1之前的一个阶段t0(如图4所示)，第N-2行的像素电路(图9A和图9B中未示出)处于数据写入和补偿阶段，此时，数据信号线D1(即图9A和图9B所示的D1_M、D1_M+1等)上提供第N-2行的像素电路的数据信号，第N行的像素电路的复位电路被第N-1行的像素电路的扫描信号(即第二扫描信号SN2)的低电平导通，但是由于第N行的像素电路的输入电路400被第N行的像素电路的扫描信号(即第一扫描信号SN1)截止，因此，第N行的像素电路不会受到影响。
例如，在第N行的像素电路的复位阶段t1，第N-2行的像素电路处于保持阶段；第N-1行的像素电路处于数据写入和补偿阶段，此时，数据信号线D2(即图9A和图9B所示的D2_M、D2_M+1等)上提供第N-1行的像素电路的数据信号；同时，数据信号线D1上提供复位电压Vinitial，从而，第N行的像素电路进行复位操作(可以参考图4和图5的相关描述)。
例如，在第N行的像素电路的数据写入和补偿阶段t2，第N-2行的像素电路处于发光阶段，第N-1行的像素电路处于保持阶段；数据信号线D1上提供第N行的像素电路的数据信号，从而，第N行的像素电路进行数据写入和补偿操作(可以参考图4和图6的相关描述)；同时，数据信号线D2上提供复位电压Vinitial，以供第N+1行的像素电路进行复位操作(可以参考图4和图5的相关描述)。
例如，在第N行的像素电路的保持阶段t3，第N-1行的像素电路处于发光阶段；第N行的像素电路进行保持操作(可以参考图4和图7的相关描述)；数据信号线D1上提供复位电压Vinitial，以供第N+2行的像素电路进行复位操作；第N+1行的像素电路处于数据写入和补偿阶段，此时，数据信号D2上提供第N+1行的像素电路的数据信号。
例如，在第N行的像素电路的发光阶段t4，第N行的像素电路进行发光操作(可以参考图4和图8的相关描述)；第N+1行的像素电路处于保持阶段；第N+2行的像素电路处于数据写入和补偿阶段，数据信号线D1上提供第N+2行的像素电路的数据信号。
例如，在第N行的像素电路的发光阶段t4之后的一个阶段(图4中未示出)，第N+1行的像素电路处于发光阶段。
综合上述，第N行的像素电路的发光阶段紧跟在第N-1行的像素电路的发光阶段之后，第N+1行的像素电路的发光阶段紧跟在第N行的像素电路的发光阶段之后。依次类推，从而该显示装置实现了逐行扫描显示。
例如，本实施例中的显示装置可以为：显示器、电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。需要说明的是，该显示装置还可以包括其他常规部件或结构，例如，为实现显示装置的必要功能，本领域技术人员可以根据具体应用场景设置其他的常规部件或结构，本公开的实施例对此不做限制。
本公开的至少一实施例提供的显示装置的技术效果可以参考上述实施例中关于像素电 路10的相应描述，在此不再赘述。
对于本公开，有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围由所附的权利要求确定。

Claims (18)

  1. 一种像素电路，包括：驱动电路、输入电路、补偿电路、复位电路、数据写入电路和发光元件；其中，
    所述驱动电路包括控制端、第一端和第二端，且配置为控制流经所述第一端和所述第二端的用于驱动所述发光元件发光的驱动电流；
    所述输入电路配置为响应于第一扫描信号传输复位电压和数据信号；
    所述复位电路配置为响应于第二扫描信号将所述输入电路传输的所述复位电压施加至所述驱动电路的控制端；
    所述补偿电路配置为存储所述数据信号，且响应于第三扫描信号将所述驱动电路的控制端和第二端电连接；
    所述数据写入电路配置为响应于所述第三扫描信号将所述输入电路传输的所述数据信号施加至所述补偿电路。
  2. 根据权利要求1所述的像素电路，还包括：发光控制电路，配置为响应于发光控制信号将所述补偿电路存储的所述数据信号施加至所述驱动电路的控制端，以使所述驱动电路产生所述驱动电流，以及响应于所述发光控制信号将对应于所述数据信号的所述驱动电流施加至所述发光元件。
  3. 根据权利要求2所述的像素电路，其中，所述发光控制电路包括第一发光控制电路和第二发光控制电路，
    所述第一发光控制电路配置为响应于所述发光控制信号将所述补偿电路存储的所述数据信号施加至所述驱动电路的控制端，以使所述驱动电路产生所述驱动电流，
    所述第二发光控制电路配置为响应于所述发光控制信号将所述驱动电流施加至所述发光元件。
  4. 根据权利要求3所述的像素电路，其中，所述驱动电路包括第一晶体管，
    所述第一晶体管的栅极作为所述驱动电路的控制端与第一节点连接，所述第一晶体管的第一极作为所述驱动电路的第一端与第一电源端连接以接收第一电源电压，所述第一晶体管的第二极作为所述驱动电路的第二端与第二节点连接。
  5. 根据权利要求4所述的像素电路，其中，所述补偿电路包括第二晶体管和存储电容，
    所述第二晶体管的栅极和第三扫描信号端连接以接收所述第三扫描信号，所述第二晶体管的第一极与所述第二节点连接，所述第二晶体管的第二极与所述第一节点连接，
    所述存储电容的第一端与所述第一晶体管的栅极耦接，所述存储电容的第二端与第三节点连接。
  6. 根据权利要求5所述的像素电路，其中，所述复位电路包括第三晶体管，
    所述第三晶体管的栅极与第二扫描信号端连接以接收所述第二扫描信号，所述第三晶体管的第一极与第四节点连接，所述第三晶体管的第二极与所述第一节点连接。
  7. 根据权利要求6所述的像素电路，其中，所述输入电路包括第四晶体管，
    所述第四晶体管的栅极与第一扫描信号端连接以接收所述第一扫描信号，所述第四晶体管的第一极与数据信号端连接以接收所述复位电压和所述数据信号，所述第四晶体管的第二极与所述第四节点连接。
  8. 根据权利要求7所述的像素电路，其中，所述数据写入电路包括第五晶体管，
    所述第五晶体管的栅极与所述第三扫描信号端连接以接收所述第三扫描信号，所述第五晶体管的第一极与所述第四节点连接，所述第五晶体管的第二极与所述第三节点连接。
  9. 根据权利要求8所述的像素电路，其中，所述第一发光控制电路包括第六晶体管，
    所述第六晶体管的栅极与发光控制信号端连接以接收所述发光控制信号，所述第六晶体管的第一极与参考电压端连接以接收参考电压，所述第六晶体管的第二极与所述第三节点连接。
  10. 根据权利要求9所述的像素电路，其中，所述第二发光控制电路包括第七晶体管，
    所述第七晶体管的栅极与所述发光控制信号端连接以接收所述发光控制信号，所述第七晶体管的第一极与所述第二节点连接，所述第七晶体管的第二极与所述发光元件的第一极连接，
    所述发光元件的第二极与第二电源端连接以接收第二电源电压。
  11. 根据权利要求9或10所述的像素电路，其中，所述参考电压与所述第一电源电压相同。
  12. 根据权利要求1或2所述的像素电路，其中，所述驱动电路包括第一晶体管，所述补偿电路包括第二晶体管和存储电容，所述复位电路包括第三晶体管，所述输入电路包括第四晶体管，所述数据写入电路包括第五晶体管，
    所述第一晶体管的栅极作为所述驱动电路的控制端与第一节点连接，所述第一晶体管的第一极作为所述驱动电路的第一端与第一电源端连接以接收第一电源电压，所述第一晶体管的第二极作为所述驱动电路的第二端与第二节点连接；
    所述第二晶体管的栅极和第三扫描信号端连接以接收所述第三扫描信号，所述第二晶体管的第一极与所述第二节点连接，所述第二晶体管的第二极与所述第一节点连接，所述存储电容的第一端与所述第一晶体管的栅极耦接，所述存储电容的第二端与第三节点连接；
    所述第三晶体管的栅极与第二扫描信号端连接以接收所述第二扫描信号，所述第三晶体管的第一极与第四节点连接，所述第三晶体管的第二极与所述第一节点连接；
    所述第四晶体管的栅极与第一扫描信号端连接以接收所述第一扫描信号，所述第四晶体管的第一极与数据信号端连接以接收所述复位电压和所述数据信号，所述第四晶体管的第二极与所述第四节点连接；
    所述第五晶体管的栅极与所述第三扫描信号端连接以接收所述第三扫描信号，所述第五晶体管的第一极与所述第四节点连接，所述第五晶体管的第二极与所述第三节点连接。
  13. 一种阵列基板，包括：阵列排布的多个像素单元；其中，
    每个所述像素单元包括根据权利要求1-12任一项所述的像素电路。
  14. 根据权利要求13所述的阵列基板，还包括：多条数据信号线；其中，
    每一列像素单元对应两条数据信号线，本列像素单元中的奇数序列的像素电路中的输入电路与对应的所述两条数据信号线中的一条连接，本列像素单元中的偶数序列的像素电路中的输入电路与对应的所述两条数据信号线中的另一条连接。
  15. 根据权利要求14所述的阵列基板，其中，每一列像素单元对应的所述两条数据信号线设置在本列像素单元的同一侧或不同侧。
  16. 一种显示装置，包括：根据权利要求13-15任一项所述的阵列基板。
  17. 一种像素电路的驱动方法，其中，所述像素电路包括驱动电路、输入电路、补偿电路、复位电路、数据写入电路和发光元件，所述驱动电路包括控制端、第一端和第二端，且配置为控制流经所述第一端和所述第二端的用于驱动所述发光元件发光的驱动电流，所述输入电路配置为响应于第一扫描信号传输复位电压和数据信号，所述复位电路配置为响应于第二扫描信号将所述输入电路传输的所述复位电压施加至所述驱动电路的控制端，所述补偿电路配置为存储所述数据信号，且响应于第三扫描信号将所述驱动电路的控制端和第二端电连接，所述数据写入电路配置为响应于所述第三扫描信号将所述输入电路传输的所述数据信号施加至所述补偿电路，
    所述驱动方法包括：复位阶段、数据写入和补偿阶段、保持阶段和发光阶段；其中，
    在所述复位阶段，输入所述第一扫描信号和所述第二扫描信号，开启所述输入电路和所述复位电路，通过所述输入电路和所述复位电路对所述驱动电路的控制端进行复位；
    在所述数据写入和补偿阶段，输入所述第一扫描信号和所述第三扫描信号，开启所述输入电路、所述数据写入电路、所述驱动电路和所述补偿电路，通过所述输入电路和所述数据写入电路将所述数据信号写入所述补偿电路，通过所述补偿电路对所述驱动电路进行补偿；
    在所述保持阶段，输入所述第三扫描信号，开启所述驱动电路和所述补偿电路，通过所述补偿电路持续对所述驱动电路进行补偿；
    在所述发光阶段，开启所述驱动电路，通过所述驱动电路驱动所述发光元件发光。
  18. 根据权利要求17所述的驱动方法，其中，所述像素电路还包括：第一发光控制电路和第二发光控制电路，所述第一发光控制电路配置为响应于发光控制信号将所述补偿电路存储的所述数据信号施加至所述驱动电路的控制端以使所述驱动电路产生所述驱动电流，所述第二发光控制电路配置为响应于所述发光控制信号将所述驱动电流施加至所述发光元件；
    在所述发光阶段，开启所述驱动电路，通过所述驱动电路驱动所述发光元件发光，包括：
    在所述发光阶段，输入所述发光控制信号，开启所述第一发光控制电路、所述第二发光控制电路和所述驱动电路，通过所述第一发光控制电路将所述补偿电路存储的所述数据 信号施加至所述驱动电路的控制端以使所述驱动电路产生所述驱动电流，通过所述第二发光控制电路将所述驱动电流施加至所述发光元件以使所述发光元件发光。
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