WO2018149166A1 - 低温漂基准电压电路 - Google Patents

低温漂基准电压电路 Download PDF

Info

Publication number
WO2018149166A1
WO2018149166A1 PCT/CN2017/106875 CN2017106875W WO2018149166A1 WO 2018149166 A1 WO2018149166 A1 WO 2018149166A1 CN 2017106875 W CN2017106875 W CN 2017106875W WO 2018149166 A1 WO2018149166 A1 WO 2018149166A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
voltage
resistor
pmos transistor
reference voltage
Prior art date
Application number
PCT/CN2017/106875
Other languages
English (en)
French (fr)
Inventor
冯玉明
张亮
彭新朝
徐以军
李健勋
谢育桦
范世容
周佳
杨文解
Original Assignee
珠海格力电器股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 珠海格力电器股份有限公司 filed Critical 珠海格力电器股份有限公司
Priority to US16/486,800 priority Critical patent/US10831227B2/en
Priority to ES17896753T priority patent/ES2959784T3/es
Priority to PL17896753.5T priority patent/PL3584667T3/pl
Priority to FIEP17896753.5T priority patent/FI3584667T3/fi
Priority to EP17896753.5A priority patent/EP3584667B1/en
Publication of WO2018149166A1 publication Critical patent/WO2018149166A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/22—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only
    • G05F3/222—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only with compensation for device parameters, e.g. Early effect, gain, manufacturing process, or external variations, e.g. temperature, loading, supply voltage
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage

Definitions

  • the present application relates to the field of semiconductor integrated circuits, and in particular to a low temperature drift reference voltage circuit.
  • Hybrid integrated circuit design as the brain of portable devices, is faced with more complex and varied requirements and challenges while being widely used.
  • the cornerstone of hybrid integrated circuits - the performance of the reference voltage directly affects the performance experience of the terminal portable device.
  • the temperature characteristic of the reference voltage directly determines the operating temperature range of the terminal equipment, while the minimum operating voltage of the reference circuit limits another important performance of the terminal equipment - endurance.
  • the traditional design of the bandgap reference voltage is to generate the voltages of the positive and negative temperature coefficients respectively, and then calculate the reference voltage of the zero temperature coefficient. Negative temperature coefficient voltage generation is convenient, but the positive temperature coefficient reference voltage is not easy to obtain.
  • Conventional implementations can be implemented using the difference in base-emitter voltages of two transistors operating at unequal current densities.
  • the circuit design of the operational amplifiers it contains is difficult to operate at low voltages, such as voltages below 2V. In order to reduce the matching error, a larger size and a larger number of transistors are usually selected, so that the integrated circuit layout is larger and costly.
  • the depletion tube structure is used to realize the normal operation of the circuit under extremely low voltage, but since the temperature coefficient cannot be guaranteed, the output reference voltage fluctuates greatly with temperature, and the temperature has a great influence on the output of the reference voltage. Difficult to meet high-precision application needs.
  • a low temperature drift reference voltage circuit comprising a first voltage unit, a second voltage unit and a K times amplification unit;
  • the first voltage unit is configured to generate a first voltage, and the first end thereof is grounded;
  • the K-times amplifying unit is configured to amplify the first voltage by K times, a first end thereof is connected to a second end of the first voltage unit, and a second end is connected to a first end of the second voltage unit Connection, where K is a constant greater than zero;
  • the second voltage unit is configured to generate a second voltage, the first end of which is connected to the current source circuit, and the second end is connected to the third end of the first voltage unit to serve as an output end of the reference voltage.
  • the first voltage unit comprises an NMOS transistor MN
  • the second voltage unit comprises a PMOS transistor MP
  • the K-times amplifying unit comprises a resistor R1 and a resistor R2, wherein:
  • the source of the NMOS transistor MN is connected to the first end of the resistor R2 and grounded.
  • the gate of the NMOS transistor MN is connected to the second end of the resistor R2 and connected to the first end of the resistor R1.
  • the drain of the NMOS transistor MN is connected to the drain and the gate of the PMOS transistor MP as an output terminal of the reference voltage;
  • the source of the PMOS transistor MP is connected to the second terminal of the resistor R1 and then connected to the current source circuit.
  • the first voltage unit comprises an NPN-type transistor QN
  • the second voltage unit comprises a PNP-type transistor QP
  • the K-times amplifying unit comprises a resistor R1 and a resistor R2, wherein:
  • the emitter of the NPN transistor QN is connected to the first end of the resistor R2 and grounded.
  • the base of the NPN transistor QN is connected to the second end of the resistor R2 and the first of the resistor R1. End connection, the collector of the NPN transistor QN is connected to the collector and the base of the PNP transistor QP as an output terminal of the reference voltage;
  • the emitter of the PNP transistor QP is connected to the second terminal of the resistor R1 and then connected to the current source circuit.
  • the current source circuit comprises a current mirror circuit.
  • the current mirror circuit includes a PMOS transistor MP1, a PMOS transistor MP2, a PMOS transistor MP3, an NMOS transistor MN1, an NMOS transistor MN2, and a resistor Rs, wherein:
  • the PMOS transistor MP1, the PMOS transistor MP2 and the source of the PMOS transistor MP3 are connected to the same power source, and the gates of the PMOS transistor MP2 and the PMOS transistor MP3 are connected to the gate of the PMOS transistor MP1. And the gate of the PMOS transistor MP3 is connected to the drain of the PMOS transistor MP2;
  • a drain of the PMOS transistor MP1 is connected to a drain and a gate of the NMOS transistor MN1, and a source of the NMOS transistor MN1 is grounded;
  • a drain of the PMOS transistor MP2 is connected to a drain of the NMOS transistor MN2, a gate of the NMOS transistor MN2 is connected to a gate of the NMOS transistor MN1, and a source of the NMOS transistor MN2 is The resistor Rs is grounded after being connected;
  • the drain of the PMOS transistor MP3 is connected to the first end of the second voltage unit.
  • the application also provides a low temperature drift reference voltage circuit, the system comprising a first voltage unit, a second voltage unit and a K times amplification unit;
  • the first voltage unit is configured to generate a first voltage, and the first end thereof is grounded;
  • the K-times amplifying unit is configured to amplify the first voltage by K times, a first end thereof is connected to a second end of the first voltage unit, and a second end is connected to a third end of the first voltage unit Connected to the current source circuit, where K is a constant greater than zero;
  • the second voltage unit is configured to generate a second voltage, the first end of which is connected to the third end of the first voltage unit and is connected to the current source circuit, and the second end is used as an output end of the reference voltage.
  • the first voltage unit includes a PMOS transistor MP and a MOS transistor M1
  • the second voltage unit includes an NMOS transistor MN and a MOS transistor M2
  • the K-times amplifying unit includes a resistor R1 and a resistor R2. among them:
  • the gate of the PMOS transistor MP is connected to the first end of the resistor R1 and the first end of the resistor R2, and the source of the PMOS transistor MP is connected to the second end of the resistor R1 and then connected to the current.
  • a source circuit a drain of the PMOS transistor MP is connected to a gate and a drain of the MOS transistor M1, a source of the MOS transistor M1 is grounded, and a second end of the resistor R2 is grounded;
  • a gate and a drain of the NMOS transistor MN are connected to the current source circuit, a source of the NMOS transistor MN is used as an output end of the reference voltage, and is connected to a drain of the MOS transistor M2.
  • the gate of the MOS transistor M2 is connected to the gate and drain of the MOS transistor M1, and the source of the MOS transistor M2 is grounded.
  • the first voltage unit comprises a PNP type transistor QP and a transistor Q1
  • the second voltage unit comprises an NPN type transistor QN and a transistor Q2
  • the K times amplifying unit comprises a resistor R1 and a resistor R2, wherein:
  • a base of the PNP-type transistor QP is connected to a first end of the resistor R1 and a first end of the resistor R2, and an emitter of the PNP-type transistor QP is connected to a second end of the resistor R1 a current source circuit, a collector of the PNP transistor QP is connected to a base and a collector of the transistor Q1, an emitter of the transistor Q1 is grounded, and a second end of the resistor R2 is grounded;
  • a base and a collector of the NPN-type transistor QN are connected to the current source circuit, and an emitter of the NPN-type transistor QN serves as an output end of the reference voltage and is connected to a collector of the transistor Q2.
  • the base of the transistor Q2 is connected to the base and collector of the transistor Q1, and the emitter of the transistor Q2 is grounded.
  • the current source circuit comprises a current mirror circuit.
  • the current mirror circuit includes a PMOS transistor MP1, a PMOS transistor MP2, a PMOS transistor MP3, an NMOS transistor MN1, an NMOS transistor MN2, and a resistor Rs, wherein:
  • the PMOS transistor MP1, the PMOS transistor MP2 and the source of the PMOS transistor MP3 are connected to the same power source, and the gates of the PMOS transistor MP2 and the PMOS transistor MP3 are connected to the gate of the PMOS transistor MP1. And the gate of the PMOS transistor MP3 is connected to the drain of the PMOS transistor MP2;
  • a drain of the PMOS transistor MP1 is connected to a drain and a gate of the NMOS transistor MN1, and a source of the NMOS transistor MN1 is grounded;
  • the drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN2, and the gate of the NMOS transistor MN2 a pole is connected to a gate of the NMOS transistor MN1, and a source of the NMOS transistor MN2 is connected to the resistor Rs and grounded;
  • the drain of the PMOS transistor MP3 is connected to the first end of the second voltage unit.
  • the above low temperature drift reference voltage circuit directly utilizes two first voltage units and second voltage units having the same positive temperature coefficient or the same negative temperature coefficient, and is calculated and made K value, then design a calculated K value of the K times the amplification unit, and K times the amplification unit into the circuit, so that the output reference voltage and temperature dependence is extremely low, or even irrelevant, to achieve the circuit in the pole
  • FIG. 1 is a circuit diagram of a low temperature drift reference voltage circuit in one embodiment
  • FIG. 2 is a circuit diagram of a specific embodiment of the low temperature drift reference voltage circuit shown in FIG. 1;
  • FIG. 3 is a circuit diagram of another embodiment of the low temperature drift reference voltage circuit shown in FIG. 1;
  • FIG. 4 is a circuit diagram of still another embodiment of the low temperature drift reference voltage circuit shown in FIG. 1;
  • FIG. 5 is a circuit diagram of a low temperature drift reference voltage circuit including a current source circuit in one embodiment
  • FIG. 6 is a circuit diagram of a low temperature drift reference voltage circuit in another embodiment
  • FIG. 7 is a circuit diagram of a specific embodiment of the low temperature drift reference voltage circuit shown in FIG. 6;
  • FIG. 9 is a temperature analysis diagram of a low temperature drift reference voltage circuit in one embodiment
  • Fig. 10 is a diagram showing a power supply rejection ratio analysis of the low temperature drift reference voltage circuit in one embodiment.
  • a low temperature drift reference voltage circuit including a first voltage unit, a second voltage unit, and a K times amplification unit.
  • a first voltage unit for generating a first voltage, the first end of which is grounded;
  • a K times amplifying unit for amplifying the first voltage by K times, the first end of which is connected to the second end of the first voltage unit, and the second The terminal is connected to the first end of the second voltage unit, wherein K is a constant greater than zero;
  • the second voltage unit is configured to generate a second voltage, the first end of which is connected to the current source circuit, and the second end is connected to the first voltage
  • the third terminal of the unit is connected as the output of the reference voltage end.
  • the first voltage unit in the low temperature drift reference voltage circuit in this embodiment generates a first voltage V 1 when operating, and the second voltage unit generates a second voltage V 2 when the second voltage unit operates, and the voltage VA at point A in the circuit is amplified by K times.
  • the temperature coefficients of the voltages of the first and second voltage units, such as MOS tubes and transistors, are generally decreased as the temperature increases, that is, the first and second voltage units that are generally used have the same direction.
  • the value of K needs to be a constant greater than zero to be possible (if the value of K is negative, then the two sides of the equation cannot be equal), that is, according to Size calculation
  • the established K value is then designed according to the size of the K value, so that the output reference voltage V REF is independent of temperature.
  • the low temperature drift reference voltage circuit in this embodiment directly utilizes two first voltage units and second voltage units having the same positive temperature coefficient or the same negative temperature coefficient, and is calculated and made K value, and then design a calculated K value of the K times magnification unit, connected between the second end of the first voltage unit and the first end of the second voltage unit, so that the output reference voltage is temperature dependent Extremely low, even irrelevant, that is, the output reference voltage has no difference even at different temperatures, can meet the high-precision application requirements, and its circuit structure design is simple, the required device types are extremely small, greatly reduced The design difficulty and risk are small, and it has very high practicability and versatility in the field of integrated circuit circuits.
  • the first voltage unit and the second voltage unit may be MOS tubes or triodes, respectively.
  • the first voltage unit includes an NMOS transistor MN
  • the second voltage unit includes a PMOS transistor MP
  • the K-fold amplification unit includes a resistor R1 and a resistor R2.
  • the source of the NMOS transistor MN is connected to the first end of the resistor R2 and grounded
  • the gate of the NMOS transistor MN is connected to the second end of the resistor R2 and then connected to the first end of the resistor R1
  • the drain of the NMOS transistor MN is The drain and the gate of the PMOS transistor MP are connected as an output terminal of the reference voltage.
  • the source of the PMOS transistor MP is connected to the second terminal of the resistor R1 and then connected to the current source circuit.
  • This embodiment is a specific circuit structure for realizing the circuit diagram shown in FIG. 1, which is a preferred embodiment.
  • this circuit mainly comprises a PMOS transistor MP (corresponding to a second voltage unit), an NMOS transistor MN (corresponding to a first voltage unit) and proportional resistors R1 and R2 (corresponding to a K-times amplifying unit).
  • the current source circuit When the power is turned on, the current source circuit generates a current I, and the current I first flows through the proportional resistors R1 and R2.
  • V REF (1 + R1/R2) Vgsn - —Vgsp —, where Vgsp is the gate-source voltage of the PMOS transistor MP.
  • Vgsn Vdsatn+Vthn
  • Vgsp— —Vdsatp ⁇ + ⁇ Vthp—
  • Vdsatn the change value of the voltage of the NMOS transistor
  • Vdsatp the variation value of the voltage of the PMOS transistor.
  • the reference voltage VREF is independent of the supply voltage.
  • the current I is constant, when the width-to-length ratio of the NMOS transistor MN and the PMOS transistor MP is sufficiently large, the voltage variation values Vdsatn and Vdsatp have little influence on the NMOS transistor MN and the PMOS transistor MP (similar to the water pipe, when the water pipe width ratio is sufficient)
  • Vgsn, -Vgsp - has little correlation with current I, mainly determined by Vthn and -Vthp - and Vthn and -Vthp - are controlled by NMOS tube MN and The process of PMOS tube MP production is determined.
  • the low temperature drift reference voltage circuit in this embodiment is operated by using two voltages having the same negative temperature coefficient to obtain a zero temperature coefficient voltage.
  • the power supply voltage only needs to be higher than (1+R1/R2)Vgsn ⁇ Vthn+Vthp to generate the reference voltage, and the circuit in this embodiment only needs four devices of the PMOS transistor MP, the NMOS transistor MN, and the resistors R1 and R2. It can be realized, the structure is extremely simple and easy to implement, and the layout of the integrated circuit is small in size and has high industrial application value.
  • the first voltage unit includes an NPN type transistor QN
  • the second voltage unit includes a PNP type transistor QP
  • the K times amplifying unit includes a resistor R1 and a resistor R2.
  • the emitter of the NPN transistor QN is connected to the first end of the resistor R2 and grounded, and the base of the NPN transistor QN is connected to the second end of the resistor R2 and connected to the first end of the resistor R1, and the NPN transistor QN
  • the collector is connected to the collector and base of the PNP transistor QP and serves as the output terminal of the reference voltage.
  • the emitter of the PNP transistor QP is connected to the second terminal of the resistor R1 and then connected to the current source circuit.
  • This embodiment is a specific circuit structure for realizing the circuit diagram shown in FIG. 1.
  • the use of a triode in place of the MOS tube in the foregoing embodiment can save the cost of the circuit device. Since it is similar to the principle in the foregoing embodiment, it will not be described again here.
  • the low temperature drift reference voltage circuit can be a hybrid of a triode and a MOS transistor to achieve a reference voltage independent of temperature.
  • the current source circuit includes a current mirror circuit.
  • the current mirror circuit includes a PMOS transistor MP1, a PMOS transistor MP2, a PMOS transistor MP3, an NMOS transistor MN1, an NMOS transistor MN2, and a resistor Rs.
  • the source of the PMOS transistor MP1, the PMOS transistor MP2 and the PMOS transistor MP3 are connected to the same power source, the PMOS transistor MP2 and The gate of the PMOS transistor MP3 is connected to the gate of the PMOS transistor MP1, and the gate of the PMOS transistor MP3 is connected to the drain of the PMOS transistor MP2.
  • the drain of the PMOS transistor MP1 is connected to the drain and the gate of the NMOS transistor MN1, and the source of the NMOS transistor MN1 is grounded.
  • the drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN2, the gate of the NMOS transistor MN2 is connected to the gate of the NMOS transistor MN1, and the source of the NMOS transistor MN2 is connected to the resistor Rs and grounded.
  • the drain of the PMOS transistor MP3 is connected to the first terminal of the second voltage unit.
  • a specific circuit structure for generating a current I the current mirror circuit capable of generating a stable power-independent current I. It mainly includes PMOS transistors MP1 and MP2 and NMOS transistors MN1 and MN2 and a resistor Rs, wherein the PMOS transistors MP1 and MP2 have the same geometrical size, and the geometric ratio of the NMOS transistors MN1 and MN2 is 1:k.
  • Vgs1 Vgs2 + I * Rs, where I is the current flowing through the NMOS transistors MN1 and MN2.
  • Vgs1 and Vgs2 are the gate voltages of the NMOS transistors MN1 and MN2, respectively.
  • I 2 / (u n C ox (W / L) N ) * 1 / (Rs ⁇ 2) * (1-1 / ⁇ k) ⁇ 2,
  • W/L is the aspect ratio of the NMOS transistor
  • U n is the electron transfer rate of the NMOS transistor
  • C ox is the gate oxide capacitance per unit area of the NMOS transistor. It is not difficult to see from this formula.
  • the current I is independent of the supply voltage (but is still a function of temperature and process) and its magnitude is determined by the resistance of the resistor Rs and the size scaling factor k of the NMOS transistors MN2, MN1.
  • the PMOS transistors MP, MP3, NMOS transistor MN and the proportional resistors R1, R2 in the circuit of FIG. 5 are mainly used to generate the reference voltage V REF .
  • the PMOS transistor MP3 and the PMOS transistors MP1 and MP2 have the same size and form a current mirror structure.
  • the current output by the PMOS transistor MP3 is equal to the current I of the PMOS transistors MP1 and MP2.
  • the circuit includes a first voltage unit, a second voltage unit, and a K times amplification unit.
  • the first voltage unit is configured to generate a first voltage, the first end of which is grounded.
  • a K-times amplifying unit configured to amplify the first voltage by K times, the first end of which is connected to the second end of the first voltage unit, and the second end is connected to the third end of the first voltage unit, and then is connected to the current source circuit, Where K is a constant greater than zero.
  • the second voltage unit is configured to generate a second voltage, the first end of which is connected to the third end of the first voltage unit and then connected to the current source circuit, and the second end is used as an output end of the reference voltage.
  • the working principle of the low temperature drift reference voltage circuit in this embodiment is similar to the low temperature drift reference voltage circuit in the foregoing embodiment.
  • the reference voltage V REF is independent of temperature and needs to be made Even
  • the temperature coefficients of the voltages of the first and second voltage units, such as MOS tubes and transistors, are generally decreased as the temperature increases, that is, the first and second voltage units that are generally used have the same direction.
  • the low temperature drift reference voltage circuit in this embodiment directly utilizes two first voltage units and second voltage units having the same positive temperature coefficient or the same negative temperature coefficient, and is calculated and made The K value, then design a K-magnification unit of the calculated K value, and connect the K-times amplifying unit into the circuit, so that the reference voltage of the output has a very low or even temperature dependence, that is, the output is realized.
  • the reference voltage has no large difference effect even at different temperatures, can meet the high-precision application requirements, and its circuit structure design is simple, and the required device types are few, which greatly reduces the design difficulty and risk.
  • the circuit circuit field has very high practicability and versatility.
  • the first voltage unit includes a PMOS transistor MP and a MOS transistor M1
  • the second voltage unit includes an NMOS transistor MN and a MOS transistor M2
  • the K-times amplifying unit includes a resistor R1 and a resistor R2.
  • the gate of the PMOS transistor MP is connected to the first end of the resistor R1 and the first end of the resistor R2
  • the source of the PMOS transistor MP is connected to the second end of the resistor R1 and then connected to the current source circuit
  • the pole is connected to the gate and the drain of the MOS transistor M1, the source of the MOS transistor M1 is grounded, and the second end of the resistor R2 is grounded.
  • the gate and the drain of the NMOS transistor MN are connected to the current source circuit.
  • the source of the NMOS transistor MN serves as the output terminal of the reference voltage, and is connected to the drain of the MOS transistor M2.
  • This embodiment is a specific circuit structure for realizing the circuit diagram shown in FIG. 6, which is a preferred embodiment.
  • the circuit mainly includes a PMOS transistor MP and a MOS transistor M1 (corresponding to a first voltage unit), an NMOS transistor MN and a MOS transistor M2 (corresponding to a second voltage unit), and proportional resistors R1 and R2 (corresponding to a K-times amplifying unit).
  • the current source circuit When the power is turned on, the current source circuit generates a current I, and the current first flows through the proportional resistors R1 and R2.
  • the gate voltage of the PMOS transistor MP is smaller than the source due to the voltage drop of the resistor R1.
  • the gate voltages of the MOS transistors M1 and M2 are preferably NMOS transistors are pulled high. At this time, the MOS transistors M1 and M2 are turned on, and after the MOS transistor M2 is turned on, the source voltage of the NMOS transistor MN is pulled down, and the gate thereof is turned off.
  • the voltage is the voltage at point A.
  • the NMOS transistor MN When the gate-source voltage Vgsn of the NMOS transistor MN is Vthn>Vthn, the NMOS transistor MN is also turned on. At this time, the PMOS transistor MP and the NMOS transistor MN divide the current I to reduce the flow through the proportional resistors R1 and R2. Current. When the current flowing through the proportional resistors R1 and R2 is too small, the voltage drop caused by the resistor R1 will decrease.
  • V REF (1 + R1/R2) Vgsp - - Vgsn -.
  • Vgsn Vdsatn+Vthn
  • Vgsp— —Vdsatp ⁇ + ⁇ Vthp—
  • Vdsatn is the change value of the voltage of the NMOS transistor
  • Vdsatp is the variation value of the voltage of the PMOS transistor.
  • Vgsn and -Vgsp- have little effect on the NMOS transistor MN and the PMOS transistor MP, and Vgsn, -Vgsp-, and current I
  • the correlation is small, mainly determined by Vthn and -Vthp, and Vthn and -Vthp are determined by the process of NMOS tube MN and PMOS tube MP.
  • the low temperature drift reference voltage circuit in this embodiment is operated by using two voltages having the same negative temperature coefficient to obtain a zero temperature coefficient voltage.
  • the power supply voltage only needs to be higher than (1+R1/R2)Vgsp ⁇ Vthn+Vthp, so that the reference voltage can be generated, and the circuit in this embodiment only needs the PMOS transistor MP, the NMOS transistor MN, the MOS transistor M1, the MOS transistor M2, and the like.
  • the resistors R1 and R2 can be realized by four devices, and the structure is extremely simple and easy to implement.
  • the layout of the integrated circuit is small in size and has high industrial application value.
  • the first voltage unit includes a PNP type transistor QP and a transistor Q1
  • the second voltage unit includes an NPN type transistor QN and a transistor Q2
  • the K times amplifying unit includes a resistor R1 and a resistor R2.
  • the base of the PNP type transistor QP is connected to the first end of the resistor R1 and the first end of the resistor R2
  • the emitter of the PNP type transistor QP is connected to the second end of the resistor R1 and then connected to the current source circuit
  • the PNP type transistor The collector of the QP is connected to the base and collector of the transistor Q1, the emitter of the transistor Q1 is grounded, and the second end of the resistor R2 is grounded.
  • the base and collector of the NPN transistor QN are connected to the current source circuit.
  • the emitter of the NPN transistor QN serves as the output terminal of the reference voltage and is connected to the collector of the transistor Q2.
  • the base of the transistor Q2 and the base of the transistor Q1 are The collector is connected, and the emitter of the transistor Q2 is grounded.
  • This embodiment is a specific circuit structure for realizing the circuit diagram shown in FIG. 6.
  • the use of a triode in place of the MOS tube in the foregoing embodiment can save the cost of the circuit device. Since it is similar to the principle in the foregoing embodiment, it will not be described again here.
  • the current source circuit includes a current mirror circuit.
  • the current mirror circuit includes a PMOS transistor MP1, a PMOS transistor MP2, a PMOS transistor MP3, an NMOS transistor MN1, an NMOS transistor MN2, and a resistor Rs.
  • the source of the PMOS transistor MP1, the PMOS transistor MP2 and the PMOS transistor MP3 are connected to the same power source, and the gates of the PMOS transistor MP2 and the PMOS transistor MP3 are connected to the gate of the PMOS transistor MP1, and the gate of the PMOS transistor MP3 and the PMOS The drain of the transistor MP2 is connected.
  • the drain of the PMOS transistor MP1 is connected to the drain and the gate of the NMOS transistor MN1, and the source of the NMOS transistor MN1 is grounded.
  • the drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN2, the gate of the NMOS transistor MN2 is connected to the gate of the NMOS transistor MN1, and the source of the NMOS transistor MN2 is connected to the resistor Rs and grounded.
  • the drain of the PMOS transistor MP3 is connected to the first terminal of the second voltage unit.
  • This embodiment is a specific circuit structure for generating a stable power-independent current I, and the principle of generating the current I is already in the front. It is described in detail in the embodiment, and details are not described herein again.
  • FIG. 8 is a DC voltage analysis of the low temperature drift reference voltage circuit in one embodiment.
  • the figure shows the change of the reference voltage from 1V to 6V.
  • the line in the top box of the figure simulates the change of the power supply voltage. It can be seen from the figure that the simulated power supply voltage change is consistent with the actual power supply voltage.
  • the change of the power supply voltage is 4.4V, that is, the power supply voltage is from The 1.607V change is 6V.
  • the line in the middle of the figure simulates the change of the reference voltage with the power supply voltage.
  • the M5 point indicates that the corresponding reference voltage is 679.1mV when the power supply voltage is 1.595V.
  • the circuit is in the process of establishing. The circuit is in an unstable state; the M6 point indicates that the reference voltage corresponding to the power supply voltage is 4.724V is 702.6mV; the M3 point indicates that the change value of the reference voltage when the power supply voltage changes by 4.4V is 37.91mV.
  • the line in the lower box of the figure simulates the change of the reference current with the power supply voltage.
  • the M9 point indicates that the reference current corresponding to the power supply voltage at 1.598V is 1.696 ⁇ A, and the M10 point indicates the corresponding reference current when the power supply voltage is 5V.
  • the M6 point represents a corresponding reference current change of 565.6nA when the power supply voltage changes 4.396V.
  • the reference voltage can work normally when the power supply voltage is 1.595V, that is, the reference voltage can operate at a very low power supply voltage, and the operating voltage of the reference voltage can be as low as 1.595V.
  • FIG. 9 is a temperature analysis diagram of a low temperature drift reference voltage circuit in an embodiment, which shows a relationship between a reference voltage and a temperature, wherein the M0 point represents a reference corresponding to a temperature change of 95.2 ° C at a positive temperature coefficient.
  • the voltage change is 13.75 mV.
  • the reference voltage changes only a little, that is, the temperature has little influence on the data of the reference voltage, and the correlation between the output reference voltage and the temperature is extremely low.
  • FIG. 10 is a power supply rejection ratio analysis diagram of the low temperature drift reference voltage circuit in one embodiment, which shows that when the frequency is lower than 43.13 kHz, the noise signal of the power supply can be reduced to 1% (-41.97 dB), thereby
  • the circuit in this embodiment has a certain bandwidth (43.13 kHz)
  • the power supply has good anti-interference ability, and can output the reference voltage well.
  • the circuit exceeds a certain bandwidth (such as exceeding 43.13 kHz)
  • the power supply is resistant.
  • the interference capability is poor, and therefore, the optimal use environment of the circuit in the above embodiment is limited to the bandwidth of 43.13 kHz. It can be clearly seen from the above simulations in FIG. 8 to FIG.
  • the low-temperature drift reference voltage circuit in the above embodiment realizes the reference voltage and temperature dependence of the output. Low effect, and in a certain use environment, it has strong anti-interference ability, can meet the needs of high precision applications.
  • the low temperature drift reference voltage circuit in the above embodiment directly uses two first voltage units and a second voltage unit having the same positive temperature coefficient or the same negative temperature coefficient, and is calculated so that K value, then design a calculated K value of the K times the amplification unit, and K times the amplification unit into the circuit, so that the output reference voltage and temperature dependence is extremely low, or even irrelevant, to achieve the circuit in the pole
  • the low-voltage under normal operating temperature has different output voltage reference voltages, which can meet the high-precision application requirements, and the circuit structure design is simple, the required device types are few, greatly reducing the design difficulty and Risk, very high practicality and versatility in the field of integrated circuit circuits.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Nonlinear Science (AREA)
  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)

Abstract

一种低温漂基准电压电路，包括第一电压单元，第二电压单元和K倍放大单元；第一电压单元，用于产生第一电压，其第一端接地；K倍放大单元，用于将第一电压放大K倍，其第一端与第一电压单元的第二端连接，第二端与第二电压单元的第一端连接，其中，K为大于零的常数；第二电压单元，用于产生第二电压，其第一端接入电流源电路，第二端与第一电压单元的第三端连接后作为基准电压（V REF）的输出端。低温漂基准电压电路使输出的基准电压（V REF）与温度相关性极低，且其电路结构设计简单，所需的器件类型极少，极大地减小了设计难度和风险，具有非常高的实用性和通用性。

Description

低温漂基准电压电路
相关申请
本申请要求2017年2月16日申请的，申请号为201710083188.4，名称为“低温漂基准电压电路”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及半导体集成电路领域，特别是涉及一种低温漂基准电压电路。
背景技术
随着科技的发展和生活水平的提高，便携式设备已经是生活中的必需品之一。而混合集成电路设计作为便携式装置的大脑，在得到广泛应用的同时，也面临着更加复杂多变的要求和挑战。混合集成电路的基石—基准电压性能的好坏，直接影响到终端便携式设备的性能体验。基准电压的温度特性，直接决定终端设备的使用温度范围，而基准电路的最低工作电压则限制了终端设备的另一重要性能—续航能力。
传统的带隙基准电压的设计思想是分别产生正、负温度系数的电压，然后通过运算得到零温度系数的基准电压。负温度系数的电压产生较为方便，但是正温度系数基准电压则不容易得到。传统的实现方式中可利用两个工作在不相等电流密度下的三极管的基极-发射极电压的差值来实现。但是其包含的运算放大器的电路设计很难在低电压，如：2V以下的电压条件下正常工作。且为了减少匹配误差，通常选择较大尺寸和较多数量的三极管，这样制作成的集成电路版图较大且花费成本也较高。
传统技术中使用耗尽管结构来实现电路在极低电压下的正常工作，但是由于其温度系数无法保证，输出的基准电压随温度变化波动也较大，温度对基准电压的输出影响较大，很难满足高精度的应用需求。
申请内容
基于此，有必要针对传统使用耗尽管来实现电路在极低电压下正常工作时，温度对输出的基准电压影响较大的问题，提供一种低温漂基准电压电路，能够在极低电压下正常工作的同时，还能够使得输出的基准电压与温度相关性极低。
为达到申请目的，提供一种低温漂基准电压电路，所述电路包括第一电压单元，第二电压单元和K倍放大单元；
所述第一电压单元，用于产生第一电压，其第一端接地；
所述K倍放大单元，用于将所述第一电压放大K倍，其第一端与所述第一电压单元的第二端连接，第二端与所述第二电压单元的第一端连接，其中，K为大于零的常数；
所述第二电压单元，用于产生第二电压，其第一端接入电流源电路，第二端与所述第一电压单元的第三端连接后作为基准电压的输出端。
在其中一个实施例中，所述第一电压单元包括NMOS管MN，所述第二电压单元包括PMOS管MP，所述K倍放大单元包括电阻R1和电阻R2，其中：
所述NMOS管MN的源极与所述电阻R2的第一端连接后接地，所述NMOS管MN的栅极与所述电阻R2的第二端连接后与所述电阻R1的第一端连接，所述NMOS管MN的漏极与所述PMOS管MP的漏极及栅极连接后作为所述基准电压的输出端；
所述PMOS管MP的源极与所述电阻R1的第二端连接后接入所述电流源电路。
在其中一个实施例中，所述第一电压单元包括NPN型三极管QN，所述第二电压单元包括PNP型三极管QP，所述K倍放大单元包括电阻R1和电阻R2，其中：
所述NPN型三极管QN的发射极与所述电阻R2的第一端连接后接地，所述NPN型三极管QN的基极与所述电阻R2的第二端连接后与所述电阻R1的第一端连接，所述NPN型三极管QN的集电极与所述PNP型三极管QP的集电极及基极连接后作为所述基准电压的输出端；
所述PNP型三极管QP的发射极与所述电阻R1的第二端连接后接入所述电流源电路。
在其中一个实施例中，所述电流源电路包括电流镜电路。
在其中一个实施例中，所述电流镜电路包括PMOS管MP1，PMOS管MP2，PMOS管MP3，NMOS管MN1，NMOS管MN2和电阻Rs，其中：
所述PMOS管MP1，所述PMOS管MP2和所述PMOS管MP3的源极接入同一电源，所述PMOS管MP2和所述PMOS管MP3的栅极均与所述PMOS管MP1的栅极连接，且所述PMOS管MP3的栅极与所述PMOS管MP2的漏极连接；
所述PMOS管MP1的漏极与所述NMOS管MN1的漏极和栅极连接，所述NMOS管MN1的源极接地；
所述PMOS管MP2的漏极与所述NMOS管MN2的漏极连接，所述NMOS管MN2的栅极与所述NMOS管MN1的栅极连接，且所述NMOS管MN2的源极与所述电阻Rs连接后接地；
所述PMOS管MP3的漏极与所述第二电压单元的第一端连接。
本申请还提供一种低温漂基准电压电路，所述***包括第一电压单元，第二电压单元和K倍放大单元；
所述第一电压单元，用于产生第一电压，其第一端接地；
所述K倍放大单元，用于将所述第一电压放大K倍，其第一端与所述第一电压单元的第二端连接，第二端与所述第一电压单元的第三端连接后接入电流源电路，其中，K为大于零的常数；
所述第二电压单元，用于产生第二电压，其第一端与所述第一电压单元的第三端连接后接入所述电流源电路，第二端作为基准电压的输出端。
在其中一个实施例中，所述第一电压单元包括PMOS管MP和MOS管M1，所述第二电压单元包括NMOS管MN和MOS管M2，所述K倍放大单元包括电阻R1和电阻R2，其中：
所述PMOS管MP的栅极与所述电阻R1的第一端和所述电阻R2的第一端连接，所述PMOS管MP的源极与所述电阻R1的第二端连接后接入电流源电路，所述PMOS管MP的漏极与所述MOS管M1的栅极和漏极连接，所述MOS管M1的源极接地，所述电阻R2的第二端接地；
所述NMOS管MN的栅极和漏极接入所述电流源电路，所述NMOS管MN的源极作为所述基准电压的输出端，并与所述MOS管M2的漏极连接，所述MOS管M2的栅极与所述MOS管M1的栅极和漏极连接，所述MOS管M2的源极接地。
在其中一个实施例中，所述第一电压单元包括PNP型三极管QP和三极管Q1，第二电压单元包括NPN型三极管QN和三极管Q2，所述K倍放大单元包括电阻R1和电阻R2，其中：
所述PNP型三极管QP的基极与所述电阻R1的第一端和所述电阻R2的第一端连接，所述PNP型三极管QP的发射极与所述电阻R1的第二端连接后接入电流源电路，所述PNP型三极管QP的集电极与所述三极管Q1的基极和集电极连接，所述三极管Q1的发射极接地，所述电阻R2的第二端接地；
所述NPN型三极管QN的基极和集电极接入所述电流源电路，所述NPN型三极管QN的发射极作为所述基准电压的输出端，并与所述三极管Q2的集电极连接，所述三极管Q2的基极与所述三极管Q1的基极和集电极连接，所述三极管Q2的发射极接地。
在其中一个实施例中，所述电流源电路包括电流镜电路。
在其中一个实施例中，所述电流镜电路包括PMOS管MP1，PMOS管MP2，PMOS管MP3，NMOS管MN1，NMOS管MN2和电阻Rs，其中：
所述PMOS管MP1，所述PMOS管MP2和所述PMOS管MP3的源极接入同一电源，所述PMOS管MP2和所述PMOS管MP3的栅极均与所述PMOS管MP1的栅极连接，且所述PMOS管MP3的栅极与所述PMOS管MP2的漏极连接；
所述PMOS管MP1的漏极与所述NMOS管MN1的漏极和栅极连接，所述NMOS管MN1的源极接地；
所述PMOS管MP2的漏极与所述NMOS管MN2的漏极连接，所述NMOS管MN2的栅 极与所述NMOS管MN1的栅极连接，且所述NMOS管MN2的源极与所述电阻Rs连接后接地；
所述PMOS管MP3的漏极与所述第二电压单元的第一端连接。
本申请的有益效果包括：
上述低温漂基准电压电路，直接利用两个具有同为正温度系数或者同为负温度系数的第一电压单元和第二电压单元，计算得到使得
Figure PCTCN2017106875-appb-000001
的K值，然后设计一个计算得到的K值大小的K倍放大单元，并将K倍放大单元接入电路中，从而使输出的基准电压与温度相关性极低，甚至无关，实现电路在极低电压下正常工作时温度不同输出的基准电压也无差异的效果，能够满足高精度的应用需求，且其电路结构设计简单，所需的器件类型极少，极大地减小了设计难度和风险，在集成电路电路领域具有非常高的实用性和通用性。
附图说明
图1为一个实施例中的低温漂基准电压电路的电路示意图；
图2为图1所示低温漂基准电压电路的一具体实施例的电路示意图；
图3为图1所示低温漂基准电压电路的另一具体实施例的电路示意图；
图4为图1所示低温漂基准电压电路的又一具体实施例的电路示意图；
图5为一个实施例中包括电流源电路的低温漂基准电压电路的电路示意图；
图6为另一个实施例中的低温漂基准电压电路的电路示意图；
图7为图6所示低温漂基准电压电路的一具体实施例的电路示意图；
图8为一个实施例中的低温漂基准电压电路的直流电压分析图；
图9为一个实施例中的低温漂基准电压电路的温度分析图；
图10为一个实施例中的低温漂基准电压电路的电源抑制比分析图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例对本申请低温漂基准电压电路进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
在一个实施例中，如图1所示，提供了一种低温漂基准电压电路，该电路包括第一电压单元，第二电压单元和K倍放大单元。第一电压单元，用于产生第一电压，其第一端接地；K倍放大单元，用于将第一电压放大K倍，其第一端与第一电压单元的第二端连接，第二端与第二电压单元的第一端连接，其中，K为大于零的常数；第二电压单元，用于产生第二电压，其第一端接入电流源电路，第二端与第一电压单元的第三端连接后作为基准电压的输出 端。
本实施例中的低温漂基准电压电路中的第一电压单元工作时产生第一电压V1，第二电压单元工作时产生第二电压V2，而电路中A点的电压VA由K倍放大单元和第一电压单元共同决定：VA＝K*V1，而输出的基准电压VREF＝K*V1-V2，为了使输出的基准电压VREF与温度无关，需要使得
Figure PCTCN2017106875-appb-000002
即使得
Figure PCTCN2017106875-appb-000003
而通常使用的第一、第二电压单元，如：MOS管、三极管的电压的温度系数是随着温度的升高而下降的，即通常使用的第一、第二电压单元是具有相同方向的温度系数的，即
Figure PCTCN2017106875-appb-000004
Figure PCTCN2017106875-appb-000005
为了保证
Figure PCTCN2017106875-appb-000006
能够成立，K的值需要是大于零的常数才可能成立(如果K的值为负，则等式两边则不可能相等)，即根据
Figure PCTCN2017106875-appb-000007
的大小计算得到使式子
Figure PCTCN2017106875-appb-000008
成立的K值，然后根据K值的大小设计一个K倍放大单元，从而使得输出的基准电压VREF与温度无关。
本实施例中的低温漂基准电压电路，直接利用两个具有同为正温度系数或者同为负温度系数的第一电压单元和第二电压单元，计算得到使得
Figure PCTCN2017106875-appb-000009
的K值，然后设计一个计算得到的K值大小的K倍放大单元，接入第一电压单元的第二端和第二电压单元的第一端之间，从而使输出的基准电压与温度相关性极低，甚至无关，即实现输出的基准电压即使在不同温度下也无差异的效果，能够满足高精度的应用需求，且其电路结构设计简单，所需的器件类型极少，极大地减小了设计难度和风险，在集成电路电路领域具有非常高的实用性和通用性。
其中，第一电压单元和第二电压单元可分别为MOS管或三极管。
在一个实施例中，参见图2，第一电压单元包括NMOS管MN，第二电压单元包括PMOS管MP，K倍放大单元包括电阻R1和电阻R2。其中：NMOS管MN的源极与电阻R2的第一端连接后接地，NMOS管MN的栅极与电阻R2的第二端连接后与电阻R1的第一端连接，NMOS管MN的漏极与PMOS管MP的漏极及栅极连接后作为基准电压的输出端。PMOS管MP的源极与电阻R1的第二端连接后接入电流源电路。
该实施例为实现图1所示的电路图的具体电路结构，其为较优的一种实施例。在该电路中其主要包括PMOS管MP(对应第二电压单元)，NMOS管MN(对应第一电压单元)和比例电阻R1和R2(对应K倍放大单元)。当电源启动时，电流源电路产生电流I，电流I首先流经比例电阻R1和R2，当电流I、电阻R2以及NMOS管MN的开启阈值Vthn满足I*R2＝Vgsn>Vthn时，其中Vgsn为NMOS管MN栅极的电压，NMOS管MN导通，此时PMOS管MP的栅极电压被拉低，当PMOS管MP的栅源电压|Vgsp|>|Vthp|时，PMOS管导通，此时PMOS管MP对电流I进行分流，减小流经比例电阻R1、R2的电流。当流经比例电阻R1、R2的电流偏小时，由I*R2＝Vgsn>Vthn可知，NMOS管MN的栅极电压Vgsn会减小，其通过PMOS管MP对电流I进行 分流亦会减小，从而增大流经比例电阻R1、R2的电流，这样反复最终使得整个电路趋于稳定，当电路最终稳定时，基准电压VREF由下式确定：VREF＝(1+R1/R2)Vgsn-︱Vgsp︱，其中，Vgsp是PMOS管MP的栅源电压。
而对于NMOS管MN和PMOS管MP有：Vgsn＝Vdsatn+Vthn，︱Vgsp︱＝︱Vdsatp︱+︱Vthp︱，其中，Vdsatn为NMOS管的电压的变化值，Vdsatp为PMOS管的电压的变化值。由上述VREF＝(1+R1/R2)Vgsn-︱Vgsp︱和Vgsn＝Vdsatn+Vthn，︱Vgsp︱＝︱Vdsatp︱+︱Vthp︱式子可知，当电流I恒定，电阻R1、R2取值足够大时，基准电压VREF与电源电压无关。且当电流I恒定时，NMOS管MN和PMOS管MP的宽长比足够大时，电压变化值Vdsatn和Vdsatp对NMOS管MN和PMOS管MP的影响很小(类似水管，当水管宽长比足够大时，水流流量的变化值对水管影响很小)，Vgsn、︱Vgsp︱与电流I的相关性很小，主要由Vthn和︱Vthp︱决定，而Vthn和︱Vthp︱是由NMOS管MN和PMOS管MP生产时的工艺决定的。对于绝大部分工艺，Vgsn和︱Vgsp︱的温度系数Tgsn和Tgsp均为负数，且满足︱Tgsn︱<︱Tgsp︱，故，当R1与R2比值设置合适，满足(1+R1/R2)︱Tgsn︱＝︱Tgsp︱，则，基准电压VREF表现与温度无关。
该实施例中的低温漂基准电压电路，利用两个同样具有负温度系数的电压进行运算，得到零温度系数电压。电源电压仅需高于(1+R1/R2)Vgsn≈Vthn+Vthp，即可产生基准电压，且该实施例中的电路仅需PMOS管MP、NMOS管MN以及电阻R1、R2四个器件即可实现，结构极其简单，容易实现，集成电路中版图占用尺寸小，具有很高的工业应用价值。
在一个实施例中，参见图3，第一电压单元包括NPN型三极管QN，第二电压单元包括PNP型三极管QP，K倍放大单元包括电阻R1和电阻R2。其中：NPN型三极管QN的发射极与电阻R2的第一端连接后接地，NPN型三极管QN的基极与电阻R2的第二端连接后与电阻R1的第一端连接，NPN型三极管QN的集电极与PNP型三极管QP的集电极及基极连接后作为基准电压的输出端。PNP型三极管QP的发射极与电阻R1的第二端连接后接入电流源电路。
该实施例为实现图1所示的电路图的具体电路结构，其使用三极管替代前述实施例中的MOS管，可以起到节约电路器件成本的效果。由于其与前述实施例中的原理相似，此处不再赘述。
在一个实施例中，参见图4，低温漂基准电压电路可以是三极管和MOS管的混合使用来实现输出的基准电压与温度无关。
在一个实施例中，参见图5，电流源电路包括电流镜电路。具体地，电流镜电路包括PMOS管MP1，PMOS管MP2，PMOS管MP3，NMOS管MN1，NMOS管MN2和电阻Rs。其中：PMOS管MP1，PMOS管MP2和PMOS管MP3的源极接入同一电源，PMOS管MP2和 所述PMOS管MP3的栅极均与PMOS管MP1的栅极连接，且PMOS管MP3的栅极与PMOS管MP2的漏极连接。PMOS管MP1的漏极与NMOS管MN1的漏极和栅极连接，NMOS管MN1的源极接地。PMOS管MP2的漏极与NMOS管MN2的漏极连接，NMOS管MN2的栅极与NMOS管MN1的栅极连接，且NMOS管MN2的源极与电阻Rs连接后接地。PMOS管MP3的漏极与第二电压单元的第一端连接。
上述实施例中产生电流I的一具体电路结构，电流镜电路能够产生稳定的与电源无关的电流I。其主要包括PMOS管MP1、MP2和NMOS管MN1、MN2以及电阻Rs，其中PMOS管MP1、MP2具有相同的几何尺寸，而NMOS管MN1、MN2的几何尺寸比例为1：k。
由NMOS管MN1、MN2和电阻Rs可以写出：Vgs1＝Vgs2+I*Rs，其中，I是流经NMOS管MN1和MN2的电流。Vgs1和Vgs2分别是NMOS管MN1和MN2的栅极电压。由上述公式结合饱和区NMOS管漏极电流与栅极电压的计算公式，得出I＝2/(un Cox(W/L)N)*1/(Rs^2)*(1-1/√k)^2，其中，W/L为NMOS管的宽长比，Un为NMOS管电子的迁移速率，Cox为NMOS管单位面积栅氧化层电容，由该公式中不难看出，电流I与电源电压无关(但仍是温度和工艺的函数)，其大小由电阻Rs的阻值以及NMOS管MN2、MN1的尺寸比例系数k来决定。
图5电路中的PMOS管MP、MP3、NMOS管MN以及比例电阻R1、R2主要用于产生基准电压VREF。其中PMOS管MP3与PMOS管MP1、MP2尺寸相同，并共同构成电流镜结构，PMOS管MP3输出的电流大小与PMOS管MP1、MP2的电流I相等。
基于同一申请构思，还提供一种低温漂基准电压电路，如图6所示，该电路包括第一电压单元，第二电压单元和K倍放大单元。第一电压单元，用于产生第一电压，其第一端接地。K倍放大单元，用于将第一电压放大K倍，其第一端与第一电压单元的第二端连接，第二端与第一电压单元的第三端连接后接入电流源电路，其中，K为大于零的常数。第二电压单元，用于产生第二电压，其第一端与第一电压单元的第三端连接后接入电流源电路，第二端作为基准电压的输出端。
本实施例中的低温漂基准电压电路的工作原理与前述实施例中的低温漂基准电压电路相似，第一电压单元工作时产生第一电压V1，第二电压单元工作时产生第二电压V2，而电路中A点的电压VA由K倍放大单元和第一电压单元共同决定：VA＝K*V1，而输出的基准电压VREF＝K*V1-V2，为了使输出的基准电压VREF与温度无关，需要使得
Figure PCTCN2017106875-appb-000010
Figure PCTCN2017106875-appb-000011
即使得
Figure PCTCN2017106875-appb-000012
而通常使用的第一、第二电压单元，如：MOS管、三极管的电压的温度系数是随着温度的升高而下降的，即通常使用的第一、第二电压单元是具有相同方向的温度系数的，即
Figure PCTCN2017106875-appb-000013
为了保证
Figure PCTCN2017106875-appb-000014
Figure PCTCN2017106875-appb-000015
能够成立，K的值需要是大于零的常数才可能成立。在设计本实施例中的低温漂基准电压电路时，需要根据
Figure PCTCN2017106875-appb-000016
的大小计算得到使式子
Figure PCTCN2017106875-appb-000017
Figure PCTCN2017106875-appb-000018
成立的K值，然后根据K值的大小设计一个K倍放大单元，从而使得输出的基准电压VREF与温度无关。
本实施例中的低温漂基准电压电路，直接利用两个具有同为正温度系数或者同为负温度系数的第一电压单元和第二电压单元，计算得到使得
Figure PCTCN2017106875-appb-000019
的K值，然后设计一个计算得到的K值大小的K倍放大单元，并将K倍放大单元接入到电路中，从而使输出的基准电压与温度相关性极低，甚至无关，即实现输出的基准电压即使在不同温度下也无大差异的效果，能够满足高精度的应用需求，且其电路结构设计简单，所需的器件类型极少，极大地减小了设计难度和风险，在集成电路电路领域具有非常高的实用性和通用性。
在一个实施例中，参见图7，第一电压单元包括PMOS管MP和MOS管M1，第二电压单元包括NMOS管MN和MOS管M2，K倍放大单元包括电阻R1和电阻R2。其中：PMOS管MP的栅极与电阻R1的第一端和电阻R2的第一端连接，PMOS管MP的源极与电阻R1的第二端连接后接入电流源电路，PMOS管MP的漏极与MOS管M1的栅极和漏极连接，MOS管M1的源极接地，电阻R2的第二端接地。NMOS管MN的栅极和漏极接入电流源电路，NMOS管MN的源极作为基准电压的输出端，并与MOS管M2的漏极连接，MOS管M2的栅极与MOS管M1的栅极和漏极连接，MOS管M2的源极接地。
该实施例为实现图6所示的电路图的具体电路结构，其为一种优选的实施方式。在该电路中主要包括PMOS管MP和MOS管M1(对应第一电压单元)，NMOS管MN和MOS管M2(对应第二电压单元)和比例电阻R1和R2(对应K倍放大单元)。当电源启动时，电流源电路产生电流I，电流首先流经比例电阻R1和R2，当电流I流经电阻R1时，由于存在电阻R1的压降，会使得PMOS管MP的栅极电压小于源极电压，当PMOS管MP的栅极电压Vgsp＝IR1＜Vthp，其中，Vthp为PMOS管MP的电压开启阈值，PMOS管MP导通，POMS管MP导通后，MOS管M1和MOS管M2(MOS管M1和M2优选为NMOS管)的栅极电压被拉高，此时MOS管M1和M2导通，MOS管M2导通后，使得NMOS管MN源极电压被拉低，而其栅极电压为A点电压，当NMOS管MN的栅源电压Vgsn>Vthn时，NMOS管MN也导通，此时PMOS管MP和NMOS管MN对电流I进行分流，减小流经比例电阻R1、R2的电流。当流经比例电阻R1、R2的电流偏小时，电阻R1带来的压降将减小，此时PMOS管MP栅极的电压与源极电压接近，由Vgsp＝VA-I*R1，PMOS管MP的栅极电压将增大，其通过PMOS管MP和NMOS管MN对电流I进行分流亦会减小，从而增大流经比例电阻R1、R2的电流，这样反复最终使得整个电路趋于稳定，当电路最终稳定时，基准电压VREF由下式确定：VREF＝(1+R1/R2)Vgsp-︱Vgsn︱。
而对于NMOS管MN和PMOS管MP有：Vgsn＝Vdsatn+Vthn，︱Vgsp︱＝︱Vdsatp︱+︱Vthp︱，其中，Vdsatn为NMOS管的电压的变化值，Vdsatp为PMOS管的电压的变化值。由上述VREF＝(1+R1/R2)Vgsp-︱Vgsn︱和Vgsn＝Vdsatn+Vthn，︱Vgsp︱＝︱Vdsatp︱+︱Vthp ︱式子可知，当电流I恒定，电阻R1、R2取值足够大时，基准电压VREF与电源电压无关。且当电流I恒定时，NMOS管MN和PMOS管MP的宽长比足够大时，电压变化值Vdsatn.和Vdsatp对NMOS管MN和PMOS管MP的影响很小，Vgsn、︱Vgsp︱与电流I的相关性很小，主要由Vthn和︱Vthp︱决定，而Vthn和︱Vthp︱是由NMOS管MN和PMOS管MP生产时的工艺决定的。对于绝大部分工艺，Vgsn和︱Vgsp︱的温度系数Tgsn和Tgsp均为负数，且满足︱Tgsn︱>︱Tgsp︱，故，当R1与R2比值设置合适，满足(1+R1/R2)︱Tgsp︱＝︱Tgsn︱，则，基准电压VREF表现与温度无关。
该实施例中的低温漂基准电压电路，利用两个同样具有负温度系数的电压进行运算，得到零温度系数电压。电源电压仅需高于(1+R1/R2)Vgsp≈Vthn+Vthp，即可产生基准电压，且该实施例中的电路仅需PMOS管MP、NMOS管MN、MOS管M1、MOS管M2以及电阻R1、R2四个器件即可实现，结构极其简单，容易实现，集成电路中版图占用尺寸小，具有很高的工业应用价值。
在一个实施例中，第一电压单元包括PNP型三极管QP和三极管Q1，第二电压单元包括NPN型三极管QN和三极管Q2，K倍放大单元包括电阻R1和电阻R2。其中：PNP型三极管QP的基极与电阻R1的第一端和电阻R2的第一端连接，PNP型三极管QP的发射极与电阻R1的第二端连接后接入电流源电路，PNP型三极管QP的集电极与三极管Q1的基极和集电极连接，三极管Q1的发射极接地，电阻R2的第二端接地。NPN型三极管QN的基极和集电极接入电流源电路，NPN型三极管QN发射极作为基准电压的输出端，并与三极管Q2的集电极连接，三极管Q2的基极与三极管Q1的基极和集电极连接，三极管Q2的发射极接地。
该实施例为实现图6所示的电路图的具体电路结构，其使用三极管替代前述实施例中的MOS管，可以起到节约电路器件成本的效果。由于其与前述实施例中的原理相似，此处不再赘述。
在一个实施例中，电流源电路包括电流镜电路。具体地，电流镜电路包括PMOS管MP1，PMOS管MP2，PMOS管MP3，NMOS管MN1，NMOS管MN2和电阻Rs。其中：PMOS管MP1，PMOS管MP2和PMOS管MP3的源极接入同一电源，PMOS管MP2和PMOS管MP3的栅极均与PMOS管MP1的栅极连接，且PMOS管MP3的栅极与PMOS管MP2的漏极连接。PMOS管MP1的漏极与NMOS管MN1的漏极和栅极连接，NMOS管MN1的源极接地。PMOS管MP2的漏极与NMOS管MN2的漏极连接，NMOS管MN2的栅极与NMOS管MN1的栅极连接，且NMOS管MN2的源极与电阻Rs连接后接地。PMOS管MP3的漏极与第二电压单元的第一端连接。
该实施例为产生稳定的与电源无关的电流I的具体电路结构，其产生电流I的原理已在前 述实施例中详细描述过，此处不再赘述。
为了进一步说明上述实施例中低温漂基准电压电路，以下结合对上述低温漂基准电压电路的相关参数进行仿真的仿真结果进行说明：图8为一个实施例中的低温漂基准电压电路的直流电压分析图，图中显示基准电压在电源电压从1V～6V的变化情况。图中最上面的方框中线条仿真的是电源电压变化情况，从图中可以看出，模拟的电源电压变化与实际的电源电压保持一致，电源电压的变化值为4.4V，即电源电压从1.607V变化为6V。图中中间的方框中线条仿真的是基准电压随着电源电压的变化情况，其中M5点表示电源电压为1.595V时对应的基准电压为679.1mV，M5点之前表示电路在建立过程中，此时电路处于不稳定的状态；M6点表示电源电压在4.724V时对应的基准电压为702.6mV；M3点表示电源电压变化4.4V时基准电压的变化值为37.91mV。图中下面的方框中线条仿真的是基准电流随着电源电压的变化情况，其中M9点表示电源电压在1.598V对应的基准电流为1.696μA，M10点表示电源电压为5V时对应的基准电流为2.019μA，M6点表示的是电源电压变化4.396V时对应的基准电流变化565.6nA。从该图中可知看出，在电源电压为1.595V时基准电压就能够正常工作，即基准电压能够在极低电源电压下工作，且基准电压的工作电压可以低至1.595V。
图9为一个实施例中的低温漂基准电压电路的温度分析图，其显示了基准电压和温度的变化关系，其中，M0点表示的是在正温度系数时，温度变化95.2℃时对应的基准电压变化13.75mV，从该图中可知看出，温度变化很大时，基准电压只变化了一点，即温度对基准电压的数据影响很小，输出的基准电压的与温度的相关性极低。图10为一个实施例中的低温漂基准电压电路的电源抑制比分析图，该图中显示在频率低于43.13kHz时，电源的噪声信号可以缩小到1％(-41.97dB)，由此，本实施例中的电路在一定的带宽下(43.13kHz)时，电源的抗干扰能力很好，能够较好地输出基准电压，当电路超出一定带宽时(如超出43.13kHz)时，电源的抗干扰能力较差，因此，上述实施例中的电路的最优使用环境限定在43.13kHz的带宽以下。由上述仿真图8至图10中可以明确地看出，当温度变化很大时，基准电压只变化了一点，即上述实施例中低温漂基准电压电路实现了输出的基准电压与温度相关性极低的效果，并且在一定的使用环境下，其具有很强的抗干扰能力，能够满足高精度的应用需求。
上述实施例中的低温漂基准电压电路，直接利用两个具有同为正温度系数或者同为负温度系数的第一电压单元和第二电压单元，计算得到使得
Figure PCTCN2017106875-appb-000020
的K值，然后设计一个计算得到的K值大小的K倍放大单元，并将K倍放大单元接入电路中，从而使输出的基准电压与温度相关性极低，甚至无关，实现电路在极低电压下正常工作时温度不同输出的基准电压也无大差异的效果，能够满足高精度的应用需求，且其电路结构设计简单，所需的器件类型极少，极大地减小了设计难度和风险，在集成电路电路领域具有非常高的实用性和通用性。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种低温漂基准电压电路，其特征在于，所述低温漂基准电压电路包括第一电压单元，第二电压单元和K倍放大单元；
    所述第一电压单元，用于产生第一电压，其第一端接地；
    所述K倍放大单元，用于将所述第一电压放大K倍，其第一端与所述第一电压单元的第二端连接，第二端与所述第二电压单元的第一端连接，其中，K为大于零的常数；
    所述第二电压单元，用于产生第二电压，其第一端接入电流源电路，第二端与所述第一电压单元的第三端连接后作为基准电压的输出端。
  2. 根据权利要求1所述的低温漂基准电压电路，其特征在于，所述第一电压单元包括NMOS管MN，所述第二电压单元包括PMOS管MP，所述K倍放大单元包括电阻R1和电阻R2，其中：
    所述NMOS管MN的源极与所述电阻R2的第一端连接后接地，所述NMOS管MN的栅极与所述电阻R2的第二端连接后与所述电阻R1的第一端连接，所述NMOS管MN的漏极与所述PMOS管MP的漏极及栅极连接后作为所述基准电压的输出端；
    所述PMOS管MP的源极与所述电阻R1的第二端连接后接入所述电流源电路。
  3. 根据权利要求1所述的低温漂基准电压电路，其特征在于，所述第一电压单元包括NPN型三极管QN，所述第二电压单元包括PNP型三极管QP，所述K倍放大单元包括电阻R1和电阻R2，其中：
    所述NPN型三极管QN的发射极与所述电阻R2的第一端连接后接地，所述NPN型三极管QN的基极与所述电阻R2的第二端连接后与所述电阻R1的第一端连接，所述NPN型三极管QN的集电极与所述PNP型三极管QP的集电极及基极连接后作为所述基准电压的输出端；
    所述PNP型三极管QP的发射极与所述电阻R1的第二端连接后接入所述电流源电路。
  4. 根据权利要求1至3任一项所述的低温漂基准电压电路，其特征在于，所述电流源电路包括电流镜电路。
  5. 根据权利要求4所述的低温漂基准电压电路，其特征在于，所述电流镜电路包括PMOS管MP1，PMOS管MP2，PMOS管MP3，NMOS管MN1，NMOS管MN2和电阻Rs，其中：
    所述PMOS管MP1，所述PMOS管MP2和所述PMOS管MP3的源极接入同一电源，所述PMOS管MP2和所述PMOS管MP3的栅极均与所述PMOS管MP1的栅极连接，且所述PMOS管MP3的栅极与所述PMOS管MP2的漏极连接；
    所述PMOS管MP1的漏极与所述NMOS管MN1的漏极和栅极连接，所述NMOS管MN1 的源极接地；
    所述PMOS管MP2的漏极与所述NMOS管MN2的漏极连接，所述NMOS管MN2的栅极与所述NMOS管MN1的栅极连接，且所述NMOS管MN2的源极与所述电阻Rs连接后接地；
    所述PMOS管MP3的漏极与所述第二电压单元的第一端连接。
  6. 一种低温漂基准电压电路，其特征在于，所述低温漂基准电压电路包括第一电压单元，第二电压单元和K倍放大单元；
    所述第一电压单元，用于产生第一电压，其第一端接地；
    所述K倍放大单元，用于将所述第一电压放大K倍，其第一端与所述第一电压单元的第二端连接，第二端与所述第一电压单元的第三端连接后接入电流源电路，其中，K为大于零的常数；
    所述第二电压单元，用于产生第二电压，其第一端与所述第一电压单元的第三端连接后接入所述电流源电路，第二端作为基准电压的输出端。
  7. 根据权利要求6所述的低温漂基准电压电路，其特征在于，所述第一电压单元包括PMOS管MP和MOS管M1，所述第二电压单元包括NMOS管MN和MOS管M2，所述K倍放大单元包括电阻R1和电阻R2，其中：
    所述PMOS管MP的栅极与所述电阻R1的第一端和所述电阻R2的第一端连接，所述PMOS管MP的源极与所述电阻R1的第二端连接后接入电流源电路，所述PMOS管MP的漏极与所述MOS管M1的栅极和漏极连接，所述MOS管M1的源极接地，所述电阻R2的第二端接地；
    所述NMOS管MN的栅极和漏极接入所述电流源电路，所述NMOS管MN的源极作为所述基准电压的输出端，并与所述MOS管M2的漏极连接，所述MOS管M2的栅极与所述MOS管M1的栅极和漏极连接，所述MOS管M2的源极接地。
  8. 根据权利要求6所述的低温漂基准电压电路，其特征在于，所述第一电压单元包括PNP型三极管QP和三极管Q1，第二电压单元包括NPN型三极管QN和三极管Q2，所述K倍放大单元包括电阻R1和电阻R2，其中：
    所述PNP型三极管QP的基极与所述电阻R1的第一端和所述电阻R2的第一端连接，所述PNP型三极管QP的发射极与所述电阻R1的第二端连接后接入电流源电路，所述PNP型三极管QP的集电极与所述三极管Q1的基极和集电极连接，所述三极管Q1的发射极接地，所述电阻R2的第二端接地；
    所述NPN型三极管QN的基极和集电极接入所述电流源电路，所述NPN型三极管QN的发射极作为所述基准电压的输出端，并与所述三极管Q2的集电极连接，所述三极管Q2的 基极与所述三极管Q1的基极和集电极连接，所述三极管Q2的发射极接地。
  9. 根据权利要求6至8任一项所述的低温漂基准电压电路，其特征在于，所述电流源电路包括电流镜电路。
  10. 根据权利要求9所述的低温漂基准电压电路，其特征在于，所述电流镜电路包括PMOS管MP1，PMOS管MP2，PMOS管MP3，NMOS管MN1，NMOS管MN2和电阻Rs，其中：
    所述PMOS管MP1，所述PMOS管MP2和所述PMOS管MP3的源极接入同一电源，所述PMOS管MP2和所述PMOS管MP3的栅极均与所述PMOS管MP1的栅极连接，且所述PMOS管MP3的栅极与所述PMOS管MP2的漏极连接；
    所述PMOS管MP1的漏极与所述NMOS管MN1的漏极和栅极连接，所述NMOS管MN1的源极接地；
    所述PMOS管MP2的漏极与所述NMOS管MN2的漏极连接，所述NMOS管MN2的栅极与所述NMOS管MN1的栅极连接，且所述NMOS管MN2的源极与所述电阻Rs连接后接地；
    所述PMOS管MP3的漏极与所述第二电压单元的第一端连接。
PCT/CN2017/106875 2017-02-16 2017-10-19 低温漂基准电压电路 WO2018149166A1 (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US16/486,800 US10831227B2 (en) 2017-02-16 2017-10-19 Reference voltage circuit with low temperature drift
ES17896753T ES2959784T3 (es) 2017-02-16 2017-10-19 Circuito de tensión de referencia con baja deriva de temperatura
PL17896753.5T PL3584667T3 (pl) 2017-02-16 2017-10-19 Obwód napięcia odniesienia o niskim dryfie temperaturowym
FIEP17896753.5T FI3584667T3 (fi) 2017-02-16 2017-10-19 Pienen lämpötilaryöminnän vertailujännitepiiri
EP17896753.5A EP3584667B1 (en) 2017-02-16 2017-10-19 Low temperature drift reference voltage circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710083188.4A CN106774594B (zh) 2017-02-16 2017-02-16 低温漂基准电压电路
CN201710083188.4 2017-02-16

Publications (1)

Publication Number Publication Date
WO2018149166A1 true WO2018149166A1 (zh) 2018-08-23

Family

ID=58958641

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/106875 WO2018149166A1 (zh) 2017-02-16 2017-10-19 低温漂基准电压电路

Country Status (8)

Country Link
US (1) US10831227B2 (zh)
EP (1) EP3584667B1 (zh)
CN (1) CN106774594B (zh)
ES (1) ES2959784T3 (zh)
FI (1) FI3584667T3 (zh)
PL (1) PL3584667T3 (zh)
PT (1) PT3584667T (zh)
WO (1) WO2018149166A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106774594B (zh) 2017-02-16 2018-02-16 珠海格力电器股份有限公司 低温漂基准电压电路
CN114690842A (zh) * 2020-12-29 2022-07-01 圣邦微电子（北京）股份有限公司 一种用于偏置双极型晶体管的电流源电路
CN112817362B (zh) * 2020-12-31 2022-05-24 广东大普通信技术股份有限公司 一种低温度系数参考电流及电压产生电路
CN115220517B (zh) * 2021-04-19 2024-01-16 中国科学院微电子研究所 基于pmos温度补偿特性基准电压产生电路及设计方法和装置
CN115220518B (zh) * 2021-04-19 2024-03-12 中国科学院微电子研究所 基于nmos温度补偿特性基准电压产生电路及设计方法和装置
CN114546019B (zh) * 2021-08-24 2022-12-23 南京航空航天大学 一种温度系数可调的基准电压源
CN115877908B (zh) * 2023-03-02 2023-04-28 盈力半导体(上海)有限公司 一种带隙电压基准电路及其二阶非线性校正电路和芯片
CN116559522B (zh) * 2023-07-11 2023-09-15 苏州锴威特半导体股份有限公司 一种低温漂的低压检测电路

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102279611A (zh) * 2011-05-11 2011-12-14 电子科技大学 一种可变曲率补偿的带隙电压基准源
CN103246310A (zh) * 2013-05-07 2013-08-14 上海华力微电子有限公司 Cmos带隙基准源电路
CN104793689A (zh) * 2015-04-10 2015-07-22 无锡中星微电子有限公司 基准电压源电路
EP2977849A1 (en) * 2014-07-24 2016-01-27 Dialog Semiconductor GmbH High-voltage to low-voltage low dropout regulator with self contained voltage reference
CN205405320U (zh) * 2016-03-02 2016-07-27 上海南麟电子股份有限公司 一种带阻抗调节的耗尽管基准电路
CN105892548A (zh) * 2014-05-07 2016-08-24 北京同方微电子有限公司 一种具有温度补偿功能的基准电压产生电路
CN106774594A (zh) * 2017-02-16 2017-05-31 珠海格力电器股份有限公司 低温漂基准电压电路
CN206479868U (zh) * 2017-02-16 2017-09-08 珠海格力电器股份有限公司 低温漂基准电压电路

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6441680B1 (en) * 2001-03-29 2002-08-27 The Hong Kong University Of Science And Technology CMOS voltage reference
JP2008015925A (ja) * 2006-07-07 2008-01-24 Matsushita Electric Ind Co Ltd 基準電圧発生回路
US7586357B2 (en) * 2007-01-12 2009-09-08 Texas Instruments Incorporated Systems for providing a constant resistance
TWI351590B (en) * 2007-12-05 2011-11-01 Ind Tech Res Inst Voltage generate apparatus
TW200928648A (en) * 2007-12-20 2009-07-01 Airoha Tech Corp Voltage reference circuit
TW201003356A (en) * 2008-07-10 2010-01-16 Mobien Corp Resistor device and circuit using the same
JP2010219486A (ja) * 2009-03-19 2010-09-30 Renesas Electronics Corp 中間電位発生回路
CN101598954B (zh) 2009-05-09 2012-01-18 南京微盟电子有限公司 一种增强型mos管基准电压源电路
CN102253684B (zh) * 2010-06-30 2013-06-26 中国科学院电子学研究所 一种采用电流相减技术的带隙基准电路
KR20120051442A (ko) 2010-11-12 2012-05-22 삼성전기주식회사 선택적 온도 계수를 가지는 전류원 회로
TWI459173B (zh) * 2012-01-31 2014-11-01 Fsp Technology Inc 參考電壓產生電路及參考電壓產生方法
JP6215652B2 (ja) * 2013-10-28 2017-10-18 エスアイアイ・セミコンダクタ株式会社 基準電圧発生装置
CN104977970A (zh) 2015-07-08 2015-10-14 北京兆易创新科技股份有限公司 一种无运放高电源抑制比带隙基准源电路
CN204808102U (zh) 2015-07-08 2015-11-25 北京兆易创新科技股份有限公司 一种无运放高电源抑制比带隙基准源电路

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102279611A (zh) * 2011-05-11 2011-12-14 电子科技大学 一种可变曲率补偿的带隙电压基准源
CN103246310A (zh) * 2013-05-07 2013-08-14 上海华力微电子有限公司 Cmos带隙基准源电路
CN105892548A (zh) * 2014-05-07 2016-08-24 北京同方微电子有限公司 一种具有温度补偿功能的基准电压产生电路
EP2977849A1 (en) * 2014-07-24 2016-01-27 Dialog Semiconductor GmbH High-voltage to low-voltage low dropout regulator with self contained voltage reference
CN104793689A (zh) * 2015-04-10 2015-07-22 无锡中星微电子有限公司 基准电压源电路
CN205405320U (zh) * 2016-03-02 2016-07-27 上海南麟电子股份有限公司 一种带阻抗调节的耗尽管基准电路
CN106774594A (zh) * 2017-02-16 2017-05-31 珠海格力电器股份有限公司 低温漂基准电压电路
CN206479868U (zh) * 2017-02-16 2017-09-08 珠海格力电器股份有限公司 低温漂基准电压电路

Also Published As

Publication number Publication date
PL3584667T3 (pl) 2024-02-05
ES2959784T3 (es) 2024-02-28
CN106774594B (zh) 2018-02-16
EP3584667A1 (en) 2019-12-25
EP3584667B1 (en) 2023-08-30
EP3584667A4 (en) 2020-08-19
CN106774594A (zh) 2017-05-31
US20190361476A1 (en) 2019-11-28
US10831227B2 (en) 2020-11-10
PT3584667T (pt) 2023-10-24
FI3584667T3 (fi) 2023-10-18

Similar Documents

Publication Publication Date Title
WO2018149166A1 (zh) 低温漂基准电压电路
CN105320205B (zh) 一种具有低失调电压高psrr的带隙基准源
CN109491440B (zh) 一种电压参考电路
CN108007594B (zh) 一种温度检测电路和方法
US9483069B2 (en) Circuit for generating bias current
WO2019104467A1 (zh) 稳压器以及电源
KR20160038665A (ko) 밴드갭 회로 및 관련 방법
CN111176358B (zh) 一种低功耗低压差线性稳压器
CN108874008B (zh) 一种具有双反馈的ldo电路
JP2015061294A (ja) カスコード増幅器
TWI692923B (zh) 電壓基準源電路及低功耗電源系統
US20160274616A1 (en) Bandgap voltage generation
CN102495661A (zh) 一种基于两种阈值电压mos器件的带隙基准电路
CN111506146A (zh) 一种恒流源电路和电源
US20090184752A1 (en) Bias circuit
CN105320198A (zh) 一种低功耗高psrr带隙基准源
TWI716323B (zh) 電壓產生器
CN206479868U (zh) 低温漂基准电压电路
CN107783586B (zh) 一种无双极晶体管的电压基准源电路
KR20190029244A (ko) 밴드 갭 기준 전압 생성 회로 및 밴드 갭 기준 전압 생성 시스템
CN110445482B (zh) 一种低功耗高摆率的比较器
CN114690842A (zh) 一种用于偏置双极型晶体管的电流源电路
KR100915151B1 (ko) 노이즈에 강한 기준 전압 발생 회로
CN207281633U (zh) 一种电流基准电路
CN103901936A (zh) 基于native晶体管的高电源抑制带隙基准源

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17896753

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2017896753

Country of ref document: EP

Effective date: 20190916