CN108400139A - 阵列基板及其制作方法以及显示装置 - Google Patents
阵列基板及其制作方法以及显示装置 Download PDFInfo
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- CN108400139A CN108400139A CN201710068945.0A CN201710068945A CN108400139A CN 108400139 A CN108400139 A CN 108400139A CN 201710068945 A CN201710068945 A CN 201710068945A CN 108400139 A CN108400139 A CN 108400139A
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- Prior art keywords
- drain electrode
- insulating layer
- electrode
- active layer
- source electrode
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- 238000002360 preparation method Methods 0.000 title abstract description 8
- 238000002161 passivation Methods 0.000 claims description 32
- 238000004519 manufacturing process Methods 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 4
- 230000000873 masking effect Effects 0.000 claims description 3
- 239000010409 thin film Substances 0.000 description 16
- 230000015572 biosynthetic process Effects 0.000 description 5
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- 239000000463 material Substances 0.000 description 5
- 230000005611 electricity Effects 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 210000002858 crystal cell Anatomy 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- 239000011521 glass Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
Classifications
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Nonlinear Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Mathematical Physics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
一种阵列基板及其制作方法以及显示装置。该阵列基板包括:衬底基板、设置在衬底基板上的第一有源层、设置在第一有源层和衬底基板上的第一绝缘层、设置在第一绝缘层远离第一有源层的一侧的栅极、设置在栅极和第一绝缘层上的第二绝缘层、设置在第二绝缘层远离栅极的一侧的第二有源层、分别与第一有源层部分接触设置第一漏极和第一源极、分别与第二有源层部分接触设置的第二漏极和第二源极以及像素电极。第一源极和第二源极电性相连,第一漏极和第二漏极电性相连,像素电极与第一漏极和第二漏极至少之一电性相连。该阵列基板可提高响应速度以及充电效率,并且可同时避免增加开口率。
Description
技术领域
本发明的实施例涉及一种阵列基板及其制作方法以及显示装置。
背景技术
随着显示装置市场的不断发展,薄膜晶体管液晶显示装置(TFT-LCD)因其响应速度快、集成度高、功耗小、轻薄等优点已成为主流的显示装置。薄膜晶体管液晶显示装置(TFT-LCD)通常包括具有薄膜晶体管(Thin Film Transistor,TFT)阵列的阵列基板以及与之对盒设置的对置基板形成的液晶盒以及填充在液晶盒中的液晶分子层。
目前,随着薄膜晶体管液晶显示装置(TFT-LCD)的分辨率不断提高,尺寸不断增大,这就要求薄膜晶体管液晶显示装置(TFT-LCD)必须具有更快的响应速度和更高的充电效率。
发明内容
本发明至少一个实施例提供一种阵列基板及其制作方法以及显示装置,可解决通常的阵列基板响应速度较慢、充电效率较低等问题,并且可同时避免增加开口率。
本发明至少一个实施例提供一种一种阵列基板,其包括:衬底基板;第一有源层,设置在所述衬底基板上;第一绝缘层,设置在所述第一有源层和所述衬底基板上;栅极,设置在所述第一绝缘层远离所述第一有源层的一侧;第二绝缘层,设置在所述栅极和所述第一绝缘层上;第二有源层,设置在所述第二绝缘层远离所述栅极的一侧;第一漏极和第一源极,分别与所述第一有源层部分接触设置;第二漏极和第二源极,分别与所述第二有源层部分接触设置;以及像素电极,所述第一漏极和所述第二漏极电性相连,所述第一源极和所述第二源极电性相连,所述像素电极与所述第一漏极和所述第二漏极至少之一电性相连。
例如,在本发明一实施例提供的阵列基板中,所述栅极在所述衬底基板上的正投影落入所述第一有源层和所述第二有源层在所述衬底基板的正投影之中。
例如,本发明一实施例提供的阵列基板还包括:第一过孔,设置在所述第一绝缘层和所述第二绝缘层中并部分暴露所述第一漏极,所述第二漏极通过所述第一过孔与所述第一漏极相连。
例如,本发明一实施例提供的阵列基板还包括:钝化层,设置在所述第二漏极和所述第二源极远离所述第二有源层的一侧,所述像素电极设置在所述第二漏极与所述钝化层之间并与所述第二漏极部分接触。
例如,本发明一实施例提供的阵列基板还包括:第二过孔,设置在所述第一绝缘层和所述第二绝缘层中并部分暴露所述第一源极,所述第二源极通过所述第二过孔与所述第一源极相连。
例如,本发明一实施例提供的阵列基板还包括:钝化层,设置在所述第二漏极和所述第二源极远离所述第二有源层的一侧;第三过孔,设置在所述第一绝缘层、所述第二绝缘层、第二漏极以及所述钝化层中并部分暴露所述第一漏极;以及第一导电结构,设置在所述第三过孔中以将所述第一漏极和第二漏极电性相连。
例如,本发明一实施例提供的阵列基板还包括:第四过孔,设置在所述第一绝缘层、所述第二绝缘层、所述第二源极以及所述钝化层中并部分暴露所述第一源极;以及第二导电结构,设置在所述第四过孔中以将所述第一源极和所述第二源极电性相连。
例如,本发明一实施例提供的阵列基板中,所述像素电极设置在所述第二漏极与所述钝化层之间并与所述第二漏极部分接触。
例如,本发明一实施例提供的阵列基板还包括:第五过孔,设置在所述钝化层中并部分暴露所述像素电极与所述第二漏极相接触的部分,所述第一导电结构还设置在所述第五过孔中。
例如,本发明一实施例提供的阵列基板中,所述像素电极包括所述第一导电结构。
本发明至少一个实施例提供一种显示装置,其包括上述任一项所述的阵列基板。
本发明至少一个实施例提供一种显示装置,其包括:在衬底基板上形成第一有源层;在所述衬底基板上形成第一漏极和第一源极并分别与所述第一有源层部分接触设置;在所述第一有源层、所述第一源极以及所述第一漏极远离所述衬底基板的一侧形成第一绝缘层;在所述第一绝缘层远离所述第一有源层的一侧形成栅极;在所述栅极远离所述第一绝缘层的一侧形成第二绝缘层;在所述第二绝缘层远离所述栅极的一侧形成第二有源层;在所述第二绝缘层远离所述栅极的一侧形成第二漏极和第二源极并分别与所述第二有源层部分接触设置;以及形成像素电极,所述第一源极和所述第二源极电性相连,所述第一漏极和所述第二漏极电性相连,所述像素电极与所述第一漏极和所述第二漏极至少之一电性相连。
例如,在本发明一实施例提供的阵列基板的制作方法中,在所述第二绝缘层远离所述栅极的一侧形成第二有源层后,包括:刻蚀所述第一绝缘层和所述第二绝缘层以形成部分暴露所述第一源极的第一过孔和部分暴露所述第一漏极的第二过孔,所述第二源极通过所述第一过孔与所述第一源极相连,所述第二漏极通过所述第二过孔与所述第一漏极相连。
例如,在本发明一实施例提供的阵列基板的制作方法中,在所述第二绝缘层远离所述栅极的一侧形成所述第二有源层包括:在所述第二绝缘层远离所述栅极的一侧形成第二半导体层;以及图案化所述第二半导体层以形成所述第二有源层,所述图案化所述第二半导体层以形成所述第二有源层与所述刻蚀所述第一绝缘层和所述第二绝缘层以形成所述第一过孔和所述第二过孔通过一次掩膜工艺形成。
本发明实施例提供的阵列基板及其制作方法以及显示装置至少具有以下有益效果之一:
(1)可提高阵列基板的响应速度以及充电效率。
(2)不增加薄膜晶体管开关所占的面积并且不降低开口率。
(3)结构简单,节省工艺步骤,节约成本。
附图说明
为了更清楚地说明本公开实施例的技术方案,下面将对实施例的附图作简单地介绍,显而易见地,下面描述中的附图仅仅涉及本公开的一些实施例,而非对本公开的限制。
图1为一种阵列基板的平面示意图;
图2为本发明一实施例提供的一种阵列基板的剖视示意图;
图3为本发明一实施例提供的一种阵列基板的平面示意图;
图4a为本发明一实施例提供的另一种阵列基板的剖视示意图;
图4b为本发明一实施例提供的另一种阵列基板的剖视示意图;
图5为本发明一实施例提供的一种阵列基板的制作方法的流程示意图;
图6a-图6h为本发明一实施例提供一种阵列基板的制作方法的分步示意图;
图7为本发明一实施例提供的另一种阵列基板的制作方法的分步示意图;
图8a-图8c本发明一实施例提供一种阵列基板的制作方法的分步示意图;以及
图9a-图9c本发明一实施例提供一种阵列基板的制作方法的分步示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚,下面将结合本公开实施例的附图,对本公开实施例的技术方案进行清楚、完整地描述。显然,所描述的实施例是本公开的一部分实施例,而不是全部的实施例。基于所描述的本公开的实施例,本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例,都属于本公开保护的范围。
除非另外定义,本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同,而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接,而是可以包括电性的连接,不管是直接的还是间接的。
为了使薄膜晶体管液晶显示装置(TFT-LCD)具有更快的响应速度和更高的充电效率,双薄膜晶体管(Dual-TFT)结构被广泛使用。如图1所示,双薄膜晶体管(Dual-TFT)结构包括栅线1、与栅线1电性相连的栅极2、数据线3、与数据线3电性相连的源极4、漏极5以及与漏极5电性相连的像素电极6。源极4包括第一源极41和第二源极42,漏极5包括第一漏极51和第二漏极52,第一源极41和第一漏极51相对设置,第二源极42和第二漏极52相对设置,第一源极41、第二源极42、第一漏极51以及第二漏极52共用栅极2。这种双薄膜晶体管结构虽然提高了响应速度以及充电效率,但是增加了薄膜晶体管开关所占的面积并且减小了开口率。
本发明实施例提供一种阵列基板及其制作方法以及显示装置。该阵列基板包括衬底基板、设置在衬底基板上的第一有源层、设置在第一有源层和衬底基板上的第一绝缘层、设置在第一绝缘层远离第一有源层的一侧的栅极、设置在栅极和第一绝缘层上的第二绝缘层、设置在第二绝缘层远离栅极的一侧的第二有源层、分别与第一有源层部分接触设置第一漏极和第一源极、分别与第二有源层部分接触设置的第二漏极和第二源极以及像素电极。第一源极和第二源极电性相连,第一漏极和第二漏极电性相连,像素电极与第一漏极和第二漏极至少之一电性相连。由此,该阵列基板可在提高响应速度以及充电效率的同时,不增加薄膜晶体管开关所占的面积并不降低开口率。
下面结合附图对本发明实施例提供的阵列基板及其制作方法以及显示装置进行说明。
实施例一
本实施例提供一种阵列基板。图2示出了一种阵列基板的剖视示意图,如图2所示,该阵列基板包括衬底基板101、设置在衬底基板101上的第一有源层102、设置在第一有源层102和衬底基板101上的第一绝缘层103、设置在第一绝缘层103远离第一有源层103一侧的栅极104、设置在栅极104和第一绝缘层103上的第二绝缘层105、设置在第二绝缘层105远离栅极104的一侧的第二有源层106、分别与第一有源层102部分接触设置的第一漏极1071和第一源极1072、分别与第二有源层106部分接触设置的第二漏极1081和第二源极1082以及像素电极109。第一源极1072和第二源极1082电性相连,第一漏极1071和第二漏极1081电性相连,像素电极109与第一漏极1071和第二漏极1081至少之一电性相连。第一有源层102与第一源极1072相接触的区域可为源极区域,第一有源层102与第一漏极1071相接触的区域可为漏极区域,第一有源层102的源极区域和漏极区域之间为沟道区域;第二有源层106与第二源极1082相接触的区域可为源极区域,第二有源层106与第二漏极1081相接触的区域可为漏极区域,第二有源层106的源极区域和漏极区域之间为沟道区域。
在本实施例提供的阵列基板中,第一源极和第二源极电性相连,第一漏极和第二漏极电性相连,像素电极通过第一漏极和第二漏极至少之一电性相连电信号可同时连接第一漏极和第二漏极,并且栅极可同时控制第一有源层和第二有源层的沟道区域。由此,该阵列基板可提高响应速度以及充电效率。例如,电信号可从第一源极进入,分流到第二源极后通过第一有源层和第二有源层的沟道区传输到第一漏极和第二漏极,从而利用单个栅极控制双沟道,因此不会产生延迟。另外,由于第二有源层、第二漏极以及第二源极等设置在第一有源层、第一漏极和第一源极上,从而不增加薄膜晶体管开关所占的面积并且不降低开口率。例如,图3为该阵列基板的俯视示意图,如图3所示,第二有源层、第二漏极以及第二源极在衬底基板上的正投影可与第一有源层、第一漏极和第一源极在衬底基板上的正投影重叠,从而不增加薄膜晶体管开关所占的面积并且不降低开口率。
例如,在本实施例一示例提供的阵列基板中,如图2所示,栅极104在衬底基板101上的正投影落入第一有源层102和第二有源层106在衬底基板101的正投影之中。也就是说,栅极104与第一有源层102的沟道区域以及第二有源层106的沟道区域对应设置。由此,可保证栅极可同时控制第一有源层和第二有源层的沟道区域。
例如,在本实施例一示例提供的阵列基板中,如图2所示,该阵列基板还包括设置在第一绝缘层103和第二绝缘层105中并部分暴露第一漏极1071的第一过孔121,第二漏极1081通过第一过孔121与第一漏极1071电性相连。由此,可通过第一过孔将第一漏极和第二漏极电性相连。
例如,在本实施例一示例提供的阵列基板中,如图2所示,该阵列基板还包括设置在第一绝缘层103和第二绝缘层105中并部分暴露第一源极1072的第二过孔122,第二源极1082通过第二过孔122与第一漏极1071电性相连。由此,可通过第二过孔将第一源极和第二源极电性相连。
例如,在本实施例一示例提供的阵列基板中,如图2所示,该阵列基板还包括设置在第二漏极1081和第二源极1082远离第二有源层106的一侧的钝化层110,像素电极109设置在第二漏极1081与钝化层110之间并与第二漏极1081部分接触。例如,如图2所示,像素电极109可搭接在第二漏极1081上。由此,该阵列基板不用通过过孔将像素电极和第二漏极相连,从而可简化该阵列基板的结构,提高可靠性。当然,本发明实施例包括但不限于此,像素电极也可设置在钝化层上并通过过孔与第二漏极电性相连。
例如,在本实施例一示例提供的阵列基板中,如图2所示,该阵列基板还包括公共电极线111,与栅极104同层设置。当然,公共电极线还可设置在其他层,本发明实施例在此不作限制。
例如,在本实施例一示例提供的阵列基板中,如图2所示,该阵列基板还包括公共电极112,设置在钝化层110上并通过过孔113与公共电极线111电性相连。
实施例二
在实施例一的基础上,本实施例提供一种阵列基板。图4a示出了另一种阵列基板的剖视示意图,如图4a所示,该阵列基板还包括钝化层110,钝化层110设置在第二漏极1081和第二源极1082远离第二有源层106的一侧,与实施例一提供的阵列基板不同的是,该阵列基板还包括设置在第一绝缘层103、第二绝缘层105、第二漏极1081以及钝化层110中并部分暴露第一漏极1071的第三过孔123以及设置在第三过孔123以将第一漏极1071和第二漏极1081电性相连的第一导电结构114。由此,通过第一导电结构114和第三过孔123将第一漏极1071和第二漏极1081电性相连。
例如,在本实施例一示例提供的阵列基板中,如图4a所示,该阵列基板还包括设置在第一绝缘层103、第二绝缘层105、第二源极1082以及钝化层110中并部分暴露第一源极1072的第四过孔124以及设置在第四过孔124中将第一源极1072和第二源极1082电性相连的第二导电结构115。由此,通过第二导电结构115和第四过孔124将第一源极1072和第二源极1082电性相连。
例如,如图4a所示,该阵列基板包括公共电极线111和公共电极112,公共电极112通过过孔113与公共电极线111电性相连。此时,第三过孔123和/或第四过孔124可与过孔113可通过一次掩膜工艺形成,从而可节省工艺,节约成本。
例如,在本实施例一示例提供的阵列基板中,如图4a所示,像素电极109设置在第二漏极1081和钝化层110之间并与第二漏极1081部分接触,从而与第二漏极1081电性相连。例如,如图4a所示,像素电极109可搭接在第二漏极1081上。由此,该阵列基板不用通过过孔将像素电极和第二漏极相连,从而可简化该阵列基板的结构,提高可靠性。当然,本发明实施例包括但不限于此,像素电极也可设置在钝化层上并通过过孔与第二漏极电性相连。
例如,在本实施例一示例提供的阵列基板中,如图4a所示,该阵列基板还包括设置在钝化层110中并部分暴露像素电极109与第二漏极1081相接触的部分的第五过孔125,第一导电结构114还设置在第五过孔125中。由此,可进一步提高像素电极与第二漏极电连接的可靠性。
例如,在本实施例一示例提供的阵列基板中,如图4a所示,像素电极109包括第一导电结构114,也就是说,第一导电结构114可为像素电极109的一部分。例如,如图4b所示,当本实施例提供的阵列基板采用TN结构时,即,阵列基板上只设置像素电极时,像素电极包括第一导电结构既可增加像素电极和第一漏极以及第二漏极电连接的稳定性和可靠性,还可增加该阵列基板的开口率。
实施例三
本实施例提供一种显示装置,其包括上述实施例一和二中任一项所描述的阵列基板。因此,该显示装置具有与上述实施例一和二中任一项所描述的阵列基板的有益效果相对应的有益效果,具体可参见实施例一和二中的相关描述,本实施例在此不再赘述。另外,由于该显示装置具有较快的响应速度和充电效率,可适用于尺寸较大的显示装置,例如电视机、舞台银幕等。
实施例四
本实施例提供一种阵列基板的制作方法,如图5所示,该阵列基板的制作方法包括以下步骤S401-S407。
步骤S401:如图6a所示,在衬底基板101上形成第一有源层102。
例如,衬底基板可选用玻璃基板、石英基板、塑料基板等;第一有源层的材料可采用氧化物半导体、非晶硅、多晶硅等;当然,本发明实施例包括但不限于此。
步骤S402:如图6b所示,在衬底基板101上形成第一漏极1071和第一源极1072并分别与第一有源层102部分接触设置。
例如,如图6b所示,第一漏极1071和第一源极1072分别搭接在第一有源层102的两侧,即,第一有源层102的源极区域和漏极区域。另外,如图6b所示,第一漏极1071和第一源极1072设置在第一有源层102远离衬底基板101的一侧,当然,第一漏极1071和第一源极1072也可设置在第一有源层102靠近衬底基板的一侧,本发明实施例在此不作限制。
步骤S403:如图6c所示,在第一有源层102、第一源极1072以及第一漏极1071远离衬底基板101的一侧形成第一绝缘层103。
例如,第一绝缘层的材料可采用有机绝缘材料或无机绝缘材料,本发明实施例在此不作限制。
步骤S404:如图6d所示,在第一绝缘层103远离第一有源层102的一侧形成栅极104。
例如,栅极的材料可包括选自铝,铝合金,铜,铜合金,钼,以及钼铝合金中的一种或多种。
步骤S405:如图6e所示,在栅极104远离第一绝缘层103的一侧形成第二绝缘层105。
例如,第二绝缘层的材料可采用有机绝缘材料或无机绝缘材料,本发明实施例在此不作限制。
步骤S406:如图6f所示,在第二绝缘层105远离栅极104的一侧形成第二有源层106。
例如,第二有源层的材料可采用氧化物半导体、非晶硅、多晶硅等;当然,本发明实施例包括但不限于此。
步骤S407:如图6g所示,在第二绝缘层105远离栅极104的一侧形成第二漏极1081和第二源极1082并分别与第二有源层106部分接触设置。
例如,如图6g所示,第二漏极1081和第二源极1082可通过过孔分别与第一漏极1071和第一源极1072电性相连。
步骤S408:如图6h所示,形成像素电极,像素电极与第一漏极和第二漏极至少之一电性相连。
在本实施例提供的阵列基板的制作方法中,第一源极和第二源极电性相连,第一漏极和第二漏极电性相连,像素电极通过第一漏极和第二漏极至少之一电性相连电信号可同时连接第一漏极和第二漏极,并且栅极可同时控制第一有源层和第二有源层的沟道区域。由此,该阵列基板可提高响应速度以及充电效率。例如,电信号可从第一源极进入,分流到第二源极后通过第一有源层和第二有源层的沟道区传输到第一漏极和第二漏极,从而利用单个栅极控制双沟道,因此不会产生延迟。另外,由于第二有源层、第二漏极以及第二源极等设置在第一有源层、第一漏极和第一源极上,从而不增加薄膜晶体管开关所占的面积并且不降低开口率。另外,第二有源层、第二漏极以及第二源极在衬底基板上的正投影可与第一有源层、第一漏极和第一源极在衬底基板上的正投影重叠,从而不增加薄膜晶体管开关所占的面积并且不降低开口率。
例如,在本实施例一示例提供的阵列基板的制作方法中,在步骤S406之后,即在第二绝缘层远离栅极的一侧形成第二有源层之后,如图7所示,刻蚀第一绝缘层103和第二绝缘层105以形成部分暴露所述第一源极1072的第一过孔121和部分暴露第一漏极1071的第二过孔122。第二源极1082通过第一过孔121与第一源极1072相连,第二漏极1081通过第二过孔122与第一漏极1071相连。
例如,在本实施例一示例提供的阵列基板的制作方法中,步骤S406,即,在第二绝缘层远离栅极的一侧形成第二有源层包括:在第二绝缘层远离栅极的一侧形成第二半导体层;以及图案化第二半导体层以形成第二有源层,所述图案化第二半导体层以形成第二有源层与刻蚀所述第一绝缘层和第二绝缘层以形成第一过孔和第二过孔可通过一次掩膜工艺形成,例如,使用半色调掩膜首先刻蚀第一过孔和第二过孔,然后进行灰化工艺,最后形成第二有源层。由此,可节省工艺步骤,并降低制作成本。
例如,在本实施例一示例提供的制作方法中,在步骤S408之后,即,在形成像素电极109之后,如图8a所示,该制作方法还包括:在形成后的基板上形成钝化层110。
例如,在本实施例一示例提供的制作方法中,如图8b所示,该阵列基板的制作方法还包括形成公共电极线111,例如,公共电极线111可与栅极104同层形成。当然,公共电极线还可形成在其他层,本发明实施例在此不作限制。该阵列基板还包括在钝化层110和第二绝缘层105中刻蚀过孔113。
例如,在本实施例一示例提供的制作方法中,如图8c所示,该阵列基板的制作方法还包括在钝化层110上形成公共电极112,公共电极112通过过孔113与公共电极线111电性相连。
例如,在本实施例一示例提供的制作方法中,在步骤S408之后,即,在形成像素电极之后,如图9a所示,在形成后的基板上形成钝化层110,钝化层110设置在第二漏极1081和第二源极1082远离第二有源层106的一侧。
例如,在本实施例一示例提供的制作方法中,在形成钝化层110后,如图9b所示,在第一绝缘层103、第二绝缘层105、第二漏极1081以及钝化层110中形成部分暴露第一漏极1071的第三过孔123以及部分暴露第一源极1072的第四过孔124。如图9c所示,在第三过孔123形成将第一漏极1071和第二漏极1081电性相连的第一导电结构114;在第四过孔124中形成将第一源极1072和第二源极1082电性相连的第二导电结构115。由此,通过第一导电结构114和第三过孔123将第一漏极1071和第二漏极1081电性相连。需要说明的是,上述的第一导电结构114和第二导电结构115可为同一导电层经一次图案化工艺图案化而成,通过第二导电结构115和第四过孔124将第一源极1072和第二源极1082电性相连,当然,本发明实施例包括但不限于此。
例如,在本实施例一示例提供的阵列基板的制作方法中,如图9b所示,该阵列基板的制作方法还包括在钝化层110中形成部分暴露像素电极109与第二漏极1081相接触的部分的第五过孔125。由此,如图9c所示,可通过将第一导电结构114还设置在第五过孔125中以将像素电极109与第二漏极1081电连接,从而可进一步提高像素电极与第二漏极电连接的可靠性。例如,上述形成第五过孔的步骤与形成第三过孔、第四过孔的步骤可经同一掩膜工艺完成。
有以下几点需要说明:
(1)本发明实施例附图中,只涉及到与本发明实施例涉及到的结构,其他结构可参考通常设计。
(2)为了清晰起见,在用于描述本发明的实施例的附图中,层或微结构的厚度和尺寸被放大。可以理解,当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时,该元件可以“直接”位于另一元件“上”或“下”,或者可以存在中间元件。
(3)在不冲突的情况下,本发明同一实施例及不同实施例中的特征可以相互组合。
以上所述,仅为本公开的具体实施方式,但本公开的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本公开揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本公开的保护范围之内。因此,本公开的保护范围应以所述权利要求的保护范围为准。
Claims (14)
1.一种阵列基板,包括:
衬底基板;
第一有源层,设置在所述衬底基板上;
第一绝缘层,设置在所述第一有源层和所述衬底基板上;
栅极,设置在所述第一绝缘层远离所述第一有源层的一侧;
第二绝缘层,设置在所述栅极和所述第一绝缘层上;
第二有源层,设置在所述第二绝缘层远离所述栅极的一侧;
第一漏极和第一源极,分别与所述第一有源层部分接触设置;
第二漏极和第二源极,分别与所述第二有源层部分接触设置;以及
像素电极,
其中,所述第一漏极和所述第二漏极电性相连,所述第一源极和所述第二源极电性相连,所述像素电极与所述第一漏极和所述第二漏极至少之一电性相连。
2.根据权利要求1所述的阵列基板,其中,所述栅极在所述衬底基板上的正投影落入所述第一有源层和所述第二有源层在所述衬底基板的正投影之中。
3.根据权利要求1或2所述的阵列基板,还包括:
第一过孔,设置在所述第一绝缘层和所述第二绝缘层中并部分暴露所述第一漏极,所述第二漏极通过所述第一过孔与所述第一漏极相连。
4.根据权利要求3所述的阵列基板,还包括:
钝化层,设置在所述第二漏极和所述第二源极远离所述第二有源层的一侧,
其中,所述像素电极设置在所述第二漏极与所述钝化层之间并与所述第二漏极部分接触。
5.根据权利要求3所述的阵列基板,还包括:
第二过孔,设置在所述第一绝缘层和所述第二绝缘层中并部分暴露所述第一源极,所述第二源极通过所述第二过孔与所述第一源极相连。
6.根据权利要求1或2所述的阵列基板,还包括:
钝化层,设置在所述第二漏极和所述第二源极远离所述第二有源层的一侧;
第三过孔,设置在所述第一绝缘层、所述第二绝缘层、第二漏极以及所述钝化层中并部分暴露所述第一漏极;以及
第一导电结构,设置在所述第三过孔中以将所述第一漏极和第二漏极电性相连。
7.根据权利要求6所述的阵列基板,还包括:
第四过孔,设置在所述第一绝缘层、所述第二绝缘层、所述第二源极以及所述钝化层中并部分暴露所述第一源极;以及
第二导电结构,设置在所述第四过孔中以将所述第一源极和所述第二源极电性相连。
8.根据权利要求6所述的阵列基板,其中,所述像素电极设置在所述第二漏极与所述钝化层之间并与所述第二漏极部分接触。
9.根据权利要求6所述的阵列基板,还包括:
第五过孔,设置在所述钝化层中并部分暴露所述像素电极与所述第二漏极相接触的部分,所述第一导电结构还设置在所述第五过孔中。
10.根据权利要求6所述的阵列基板,其中,所述像素电极包括所述第一导电结构。
11.一种显示装置,包括权利要求1-10中任一项所述的阵列基板。
12.一种阵列基板的制作方法,包括:
在衬底基板上形成第一有源层;
在所述衬底基板上形成第一漏极和第一源极并分别与所述第一有源层部分接触设置;
在所述第一有源层、所述第一源极以及所述第一漏极远离所述衬底基板的一侧形成第一绝缘层;
在所述第一绝缘层远离所述第一有源层的一侧形成栅极;
在所述栅极远离所述第一绝缘层的一侧形成第二绝缘层;
在所述第二绝缘层远离所述栅极的一侧形成第二有源层;
在所述第二绝缘层远离所述栅极的一侧形成第二漏极和第二源极并分别与所述第二有源层部分接触设置;以及
形成像素电极,
其中,所述第一源极和所述第二源极电性相连,所述第一漏极和所述第二漏极电性相连,所述像素电极与所述第一漏极和所述第二漏极至少之一电性相连。
13.根据权利要求12所述的阵列基板的制作方法,在所述第二绝缘层远离所述栅极的一侧形成第二有源层后,包括:
刻蚀所述第一绝缘层和所述第二绝缘层以形成部分暴露所述第一源极的第一过孔和部分暴露所述第一漏极的第二过孔,
其中,所述第二源极通过所述第一过孔与所述第一源极相连,所述第二漏极通过所述第二过孔与所述第一漏极相连。
14.根据权利要求13所述的阵列基板的制作方法,其中,在所述第二绝缘层远离所述栅极的一侧形成所述第二有源层包括:
在所述第二绝缘层远离所述栅极的一侧形成第二半导体层;以及
图案化所述第二半导体层以形成所述第二有源层,
其中,所述图案化所述第二半导体层以形成所述第二有源层与所述刻蚀所述第一绝缘层和所述第二绝缘层以形成所述第一过孔和所述第二过孔通过一次掩膜工艺形成。
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US20180374874A1 (en) | 2018-12-27 |
WO2018145465A1 (zh) | 2018-08-16 |
CN108400139B (zh) | 2020-12-01 |
EP3588562A1 (en) | 2020-01-01 |
EP3588562A4 (en) | 2020-09-23 |
US10651205B2 (en) | 2020-05-12 |
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