WO2018129967A1 - 低压差线性稳压器 - Google Patents

低压差线性稳压器 Download PDF

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Publication number
WO2018129967A1
WO2018129967A1 PCT/CN2017/106283 CN2017106283W WO2018129967A1 WO 2018129967 A1 WO2018129967 A1 WO 2018129967A1 CN 2017106283 W CN2017106283 W CN 2017106283W WO 2018129967 A1 WO2018129967 A1 WO 2018129967A1
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Prior art keywords
transistor
control
gate
drain
control signal
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PCT/CN2017/106283
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English (en)
French (fr)
Inventor
詹陈长
暨永雄
蔡桂港
赵双星
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南方科技大学
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Priority to US16/320,129 priority Critical patent/US11082047B2/en
Publication of WO2018129967A1 publication Critical patent/WO2018129967A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L5/00—Automatic control of voltage, current, or power
    • H03L5/02—Automatic control of voltage, current, or power of power
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

Definitions

  • This embodiment relates to analog integrated circuit technology, for example, to a low dropout linear regulator.
  • SoC System-on-Chip
  • the low dropout linear regulator is a general-purpose power converter with low noise, low cost, and fast response. It is widely used in system-on-chip power management applications.
  • the control loop of the low dropout linear regulator can produce the desired output voltage by adjusting the effective resistance of its power transistor.
  • an off-chip capacitor in the range of a few microfarads ⁇ F is typically used to filter out noise and provide a primary pole for the stability of the low dropout linear regulator at different load currents.
  • the present disclosure provides a low dropout linear regulator to achieve wide bandwidth and fast response without compromising loop stability or increasing quiescent current consumption.
  • the present disclosure provides a low dropout linear regulator comprising:
  • a source of the power transistor is disposed in connection with a power source, a gate of the power transistor is coupled to an output of the error amplifier, and a drain of the power transistor is coupled to an output of the low dropout linear regulator ;
  • a first end of the dynamic Miller compensation network is coupled to an output of the error amplifier, and a second end of the dynamic Miller compensation network is coupled to an output of the low dropout linear regulator, the controller
  • the first end of the controller is connected to the gate of the power transistor, and the second end of the controller is connected to the third end of the Miller compensation network;
  • the dynamic Miller compensation network includes a first RC branch and at least one second RC branch, and the first RC branch is connected in parallel with the at least one second RC branch, the a resistive branch includes a first resistor and a first capacitor connected in series, and the second resistive branch includes a second resistor and a second capacitor connected in series;
  • the controller is configured to: detect a current of an output end of the low dropout linear regulator, and generate a control signal according to the current to control each second RC branch of the dynamic Miller compensation network Connected and disconnected.
  • the first feedback resistor and the second feedback resistor are connected, the first end of the first feedback resistor is connected to the first end of the second feedback resistor, and is connected to the forward input end of the error amplifier, A second end of the first feedback resistor is coupled to an output of the low dropout linear regulator, and a second end of the second feedback resistor is coupled to ground.
  • the method further includes at least one gain amplifier, wherein the at least one gain amplifier has a one-to-one correspondence with the at least one second RC branch;
  • the second resistor in each of the second RC branches is connected in parallel with a corresponding one of the gain amplifiers.
  • the gain of the at least one gain amplifier is 1.
  • a secondary amplifier is further connected in series with the error amplifier, the secondary amplifier is connected in series with the power transistor, and the first end of the secondary amplifier and the output of the error amplifier The terminal is connected, and the second end of the secondary amplifier is connected to the gate of the power transistor.
  • the secondary amplifier is a voltage buffer.
  • the method further includes a zero point generator, the zero point generator includes a third resistor and a zero point generator switch, and the third resistor and the zero point generator switch are respectively connected in parallel with the first resistor and the first capacitor In series, the control signal of the zero generator switch is inverted with any one of the control signals in the dynamic Miller compensation network.
  • the voltage buffer includes: a first insulated gate transistor, a second insulated gate transistor, a third insulated gate transistor, a fourth insulated gate transistor, a fifth insulated gate transistor, and a sixth insulated gate a transistor and a seventh insulated gate transistor, wherein
  • a gate of the seventh insulated gate transistor is connected to a gate of the sixth insulated gate transistor, a source of the seventh insulated gate transistor and a source of the second insulated gate transistor, respectively Said a source of the first insulated gate transistor and a drain of the sixth insulated gate transistor are connected, and a drain of the seventh insulated gate transistor is respectively connected to an output end of the voltage buffer and the second insulation a gate of the gate transistor is connected; a source of the sixth insulated gate transistor is respectively connected to a source and a power source of the fifth insulated gate transistor;
  • a gate of the fifth insulated gate transistor is connected to a drain of the fifth insulated gate transistor and grounded;
  • a gate of the first insulated gate transistor is connected to an output end of the error amplifier, a drain of the first insulated gate transistor and a drain of the third insulated gate transistor and the third The gates of the insulated gate transistors are connected;
  • a drain of the second insulated gate transistor is respectively connected to a drain of the fourth insulated gate transistor and an output end of the voltage buffer;
  • a source of the third insulated gate transistor and a source of the fourth insulated gate transistor are connected to be grounded, a gate of the third insulated gate transistor and a gate of the fourth insulated gate transistor Connected.
  • a source of the sixth insulated gate transistor and a source of the second insulated gate transistor are disposed to receive a first bias current generated by the controller, where the first bias current The current value is in a predetermined proportional relationship with the current value at the output of the low dropout linear regulator.
  • the controller includes: a first control transistor, a second control transistor, a third control transistor, a fourth control transistor, a fifth control transistor, a sixth control transistor, a seventh control transistor, and an eighth control transistor;
  • a source of the first control transistor, a source of the seventh control transistor, and the eighth control transistor are disposed to be connected to the power source, a gate of the first control transistor and a gate of the power transistor a pole connection, a source of the second control transistor is connected to a drain of the power transistor, a drain of the first control transistor is connected to a source of the third control transistor, and a second control transistor is a gate is connected to a gate of the third control transistor, a gate of the second control transistor is connected to a drain of the second control transistor, a drain of the second control transistor is opposite to the fourth control a drain of the transistor, a drain of the third control transistor being coupled to a drain of the fifth control transistor, a gate of the fourth control transistor, a gate of the fifth control transistor, and the a gate of the sixth control transistor is connected to each other, a source of the fourth control transistor, a source of the fifth control transistor, and a source of the sixth control transistor are grounded, the fifth control crystal a gate of the tube is connected to
  • the controller further includes: a plurality of control signal generating circuits and at least one third control signal transistor;
  • the control signal generating circuit includes: a first control signal transistor, a second control signal transistor, a first semiconductor element, and a second semiconductor element;
  • a drain of the first control signal transistor and a source of the second control signal transistor are disposed to be connected to the power source, and a gate of the first control signal transistor is connected to a gate of the sixth control transistor ,
  • a drain of the second control signal transistor is connected to a drain of the first control signal transistor, and a drain of the second control signal transistor is connected to an input end of the first semiconductor component, the second control a gate of the signal transistor is connected to an output end of the first semiconductor element,
  • An output end of the first semiconductor element is connected to an input end of the second semiconductor element, and an output end of the second semiconductor element is arranged to output the control signal;
  • Any two adjacent control signal generating circuits are a first control signal generating circuit and a second control signal generating circuit;
  • An output end of the second semiconductor element in the first control signal generating circuit is connected to a gate of the third control signal transistor, and a source of the third control signal transistor is disposed to be connected to the power source, A drain of the third control signal transistor is coupled to a drain of the second control signal transistor of the second control signal generating circuit.
  • the controller further includes: a fourth control signal transistor, a fifth control signal transistor, a third semiconductor component, and a fourth semiconductor component;
  • a drain of the fourth control signal transistor and a source of the fifth control signal transistor are disposed to be connected to the power source
  • a gate of the fourth control signal transistor is connected to a gate of the sixth control transistor
  • a drain of the fifth control signal transistor is connected to a drain of the fourth control signal transistor, and a drain of the fifth control signal transistor is connected to an input end of the third semiconductor component, the fifth control a gate of the signal transistor is connected to an output end of the third semiconductor component,
  • An output of the third semiconductor component is coupled to an input of the fourth semiconductor component, and an output of the fourth semiconductor component is configured to output the control signal.
  • the low-dropout linear regulator detects the low-dropout linear regulator through the controller
  • the current at the output terminal generates a dynamic Miller supplemental network control signal according to the current to control the on and off of the second RC branch in the dynamic Miller compensation network, and the external load through the low dropout linear regulator Changing the number of accesses of the second capacitor in the dynamic Miller compensation network, so that the low-dropout linear regulator uses a larger compensation capacitor when the load current is low to achieve good stability, and is used when the load current is high. Small compensation capacitors for fast response and wide bandwidth.
  • FIG. 1 is a circuit diagram of a low dropout linear regulator without an off-chip capacitor provided by the related art.
  • FIG. 2 is a circuit diagram of another low dropout linear regulator without an off-chip capacitor provided by the related art.
  • FIG 3 is a circuit diagram of a low dropout linear regulator provided in the first embodiment.
  • FIG. 4 is a circuit diagram of an operational transconductance amplifier in a low dropout linear regulator provided in the first embodiment.
  • FIG. 5 is a circuit diagram of a controller in the low dropout linear regulator provided in the first embodiment.
  • FIG. 6 is a circuit diagram of a low dropout linear regulator provided in the second embodiment.
  • FIG. 7 is a circuit diagram of a low dropout linear regulator provided in the third embodiment.
  • FIG. 8A is a circuit diagram of a voltage buffer in a low dropout linear regulator provided in the third embodiment.
  • FIG. 8B is a circuit diagram of a controller provided in Embodiment 3.
  • FIG. 8C is a circuit diagram of still another controller provided in Embodiment 3.
  • FIG. 8D is a circuit diagram of still another controller provided in Embodiment 3.
  • Embodiment 9 is a circuit diagram of a low dropout linear regulator provided in Embodiment 4.
  • FIG. 1 is a circuit diagram of a low-dropout linear regulator without an off-chip capacitor provided by the related art.
  • 2 is a circuit diagram of another low dropout linear regulator without an off-chip capacitor provided by the related art.
  • the circuit includes: an operational transconductance amplifier (OTA), a power transistor M P1 , a bandgap reference, a resistor r1, a resistor r2, a resistor r3, and a capacitor C.
  • OTA operational transconductance amplifier
  • the bandgap reference generates a DC reference voltage for one input of the OTA; the resistor r1 and resistor r2 sample the output voltage (V OUT ) and feed back to the other input of the OTA to regulate the output voltage.
  • Capacitor C and resistor r3 form a compensation network, where capacitor C is the Miller capacitance that helps produce the main pole.
  • the power transistor M P1 In order to achieve a large load current and a small differential voltage, the power transistor M P1 usually has a large width/length (W/L) ratio and thus has a large parasitic capacitance.
  • a second stage amplifier can be added between the OTA and the power transistor M P1 as shown in FIG. The second stage amplifier can have a gain to increase the total loop gain and thus improve the regulation accuracy of the regulator. Among them, the second stage amplifier can also be a voltage buffer to achieve faster adjustment speed by increasing the driving capability of the OTA.
  • FIG. 3 is a circuit diagram of a low dropout linear regulator according to the embodiment.
  • the low-dropout linear regulator comprising: an error amplifier 10 and the power transistors M P, further comprising: a dynamic Miller compensation network 20 and controller 30; M P source of the power transistor and the source is set to the power supply V In the IN connection, the power transistor M P gate is connected to the output terminal of the error amplifier 10, and the power transistor M P drain is connected to the output terminal V OUT of the low dropout linear regulator; a compensation network 20 is coupled between an output of the error amplifier 10 and an output V OUT of the low dropout linear regulator, a first end of the dynamic Miller compensation network 20 and the error amplifier 10 The output terminal is connected, the second end of the dynamic Miller compensation network 20 is connected to the output terminal V OUT of the low dropout linear regulator, and the first end of the controller 30 and the gate of the power transistor M P a pole connection, the second end of the controller 30 is coupled to the third end of the Miller compensation network 20; wherein the dynamic Miller compensation network 20 includes
  • the controller 30 is configured to: detect a current of the output terminal V OUT of the low dropout linear regulator, and generate a current according to the current
  • the dynamic Miller compensation network 20 control signals are used to control the communication and disconnection of each of the second RC branches 22 in the dynamic Miller compensation network 20.
  • the low-dropout linear regulator further includes a feedback resistor 40
  • the feedback resistor 40 includes a first feedback resistor R 1 and a second feedback resistor R 2, wherein the first feedback resistor R 1 and a second feedback The resistor R 2 is connected in series to form a feedback resistor 40.
  • the first end of the first feedback resistor R 1 is connected to the first end of the second feedback resistor R 2 and is connected to the forward input terminal of the error amplifier 10, and the first feedback resistor R 1
  • the second end is connected to the output terminal V OUT of the low dropout linear regulator, and the second end of the second feedback resistor R 2 is grounded.
  • the error amplifier 10 is an operational transconductance amplifier OTA.
  • the OTA includes a forward input terminal, an inverting input terminal, and an output terminal.
  • the inverting input of the error amplifier 10 is input with a reference voltage.
  • the reference voltage is a bandgap reference voltage, wherein the bandgap reference voltage is a reference voltage of the voltage regulator.
  • the dynamic Miller compensation network 20 includes a first RC branch 21 and at least one second RC branch 22.
  • the dynamic Miller compensation network 20 includes N second RC branches 22, wherein, N For an integer not less than 1, the second resistor in each second RC branch is represented by R C1 , . . .
  • the controller 30 compensates the control signal of the dynamic Miller compensation network 20 according to the current of the output terminal V OUT of the low-dropout linear regulator.
  • the control signal is N, and each control signal respectively controls a second resistance.
  • the switches of the fulcrum 22 are connected and disconnected, and the switches corresponding to the control signals of each control signal are respectively denoted by S 1 , . . . , S N .
  • the controller 30 When the current (load current) at the output of the low dropout linear regulator changes, the controller 30 generates N control signals S 11 , . . .
  • CN in the dynamic Miller compensation network 20 are connected to achieve better stability of the low dropout linear regulator; when the output of the low dropout linear regulator is V OUT When the load current is at a large value, the control signal generated by the controller 30 controls all of the switches S 1 , . . . , S N to be turned on to compensate all of the second capacitors C 1 , . . . , CN in the dynamic Miller compensation network 20 . Cut off to achieve a better phase margin and better transient response speed for the low dropout linear regulator.
  • the operational transconductance amplifier OTA can be a current mirror amplifier.
  • 4 is a circuit diagram of an operational transconductance amplifier in the low dropout linear regulator provided in the embodiment.
  • the OTA includes a pair of input terminals composed of first transistors M 1 -M 2 and three currents composed of second transistors M 3 -M 4 , M 5 -M 6 , M 7 -M 8 a mirror, a bias network composed of a bias current I B1 and third transistors M 9 -M 10 , a fourth transistor M 11 , a gate of the fourth transistor M 11 may be separately applied with a voltage V DB , and a fourth transistor M 11 can provide dynamic bias current for OAT.
  • the sources of the second transistors M 3 -M 6 are connected to the input power source V IN ; the sources of the second transistors M 7 -M 8 , the sources of the third transistors M 9 -M 10 and the sources of the fourth transistor M 11 are connected and ground; a first transistor M 1 -M 2 of the source electrode, and a drain of the fourth transistor connected to the drain of the third transistor M 11 M 10; a drain of the drain of the first transistor M 1 and M 3 of the second transistor
  • the drain of the first transistor M 2 is connected to the drain of the second transistor M 5 ; the drain of the second transistor M 4 is connected to the drain of the second transistor M 7 ; the drain of the second transistor M 6
  • the drain of the second transistor M 8 is connected, and the connection point is the output terminal V 0 of the OTA; the bias current I B1 is the current between the input power source V IN and the drain of the third transistor M 9 .
  • the response speed of the current transient at the output of the low dropout linear regulator can be increased.
  • the current mirror amplifier provides a wide output voltage swing that helps increase the wide load range of low dropout linear regulators.
  • FIG. 5 is a circuit diagram of a controller in a low dropout linear regulator according to the embodiment.
  • the power transistor M P also is a circuit diagram of the controller shown.
  • the controller includes a current detecting module and a control signal generating module, wherein the current detecting module is composed of a fifth transistor M SEN and sixth transistors M 31 - M 34 , and the sixth transistors M 31 - M 34 constitute an amplifier such that the fifth transistor M
  • the drain voltage of SEN is the same as the drain voltage of the power transistor for accurate current sensing.
  • the detection ratio that is, the size ratio of the fifth transistor M SEN and the power transistor M P is set to 1:M, usually M is an integer far greater than 1, for example, M is 100 or 1000, etc. .
  • the detected load current is mirrored by the seventh transistor M 35 -M 37 to provide an adaptive bias current in M 37 .
  • the detected load current is also mirrored by the eighth transistors M 38 and M 41 to help generate a control signal for the dynamic Miller compensation network in the low dropout linear regulator. For illustrative purposes, only the generation of the two control signals S 11 and S 22 that control switches S 1 and S 2 are shown.
  • the first fixed bias current I B3 and the second fixed bias current I B7 have predetermined current values.
  • the control signals S 11 and S 22 are both at a high level, and the second capacitors C 1 and C 2 are connected to the dynamic Miller compensation network to form a low voltage. Compensation for the stability of the differential linear regulator.
  • the ninth transistors M 39 and M 42 are turned on to allow the currents I B4 and I B7 to pass, and the tenth transistor M 40 is turned off to block the current I B5 .
  • the control signal S 11 It is pulled low to remove the second capacitor C 1 from the dynamic Miller compensation network. Therefore, the total number of second capacitors in the dynamic Miller compensation network is reduced, and the bandwidth of the low dropout linear regulator is improved. In this case, the control signal S 11 is at a low level, so the transistor tenth transistor M 40 is turned on to allow the current I B5 to pass.
  • the eleventh transistor M 41 When the load current is gradually increased to exceed the second specific predefined value I L2 such that the current of the eleventh transistor M 41 is higher than the sum of the total currents of the currents I B5 , I B6 and I B7 , the eleventh transistor M 41 The drain voltage drops, and thus the control signal S 22 is pulled low, thereby removing the second capacitor C 2 from the dynamic Miller compensation network. Therefore, the number of total second capacitors in the dynamic Miller compensation network is gradually reduced, and the bandwidth of the low dropout linear regulator is improved.
  • a similar method can be used to generate more control signals as needed. Since the load current may actually vary, hysteresis is introduced by the currents I B4 and I B7 to avoid oscillations in the control signal generation.
  • the control signal S 11 is switched from a high level to a low level.
  • the ninth transistor M 39 is turned off, and the current I B4 is blocked, and only when the load current is greatly lowered, so that the current of the eighth transistor M 38 is lower than the current I B3 , the drain of the eighth transistor M 38 rises.
  • the control signal S 11 is pulled up to a high level, otherwise the control signal S 11 will remain at a low level, and in addition, a small change in the load current will not cause S 11 to be erroneously triggered.
  • the low-dropout linear regulator detects the current at the output end of the low-dropout linear regulator through a controller, and generates a dynamic Miller supplemental network control signal according to the current to control the dynamic Miller compensation network.
  • the on-off of the second resistive-capacitor branch dynamically changes the number of accesses of the second capacitor in the dynamic Miller compensation network through the external load of the low-dropout linear regulator, so that the low-dropout linear regulator is compared at the load current
  • FIG. 6 is a circuit diagram of a low dropout linear regulator according to an embodiment of the present invention. This embodiment adds at least one gain amplifier 23 to the above embodiment.
  • the low dropout linear regulator further includes at least one gain amplifier 23, wherein the at least one gain amplifier 23 is in one-to-one correspondence with at least one second RC branch 22 of the dynamic Miller compensation network 20;
  • the second resistors R C1 , . . . , R CN in a second resistive branch 22 are respectively connected in parallel with a corresponding one of the gain amplifiers 23.
  • the gain of the at least one gain amplifier 23 is 1.
  • the number of gain amplifiers 23 is N, and each of the gain amplifiers 23 controls the on/off of the switches S 1b , ..., S Nb by the opposite signals of the control signals S 11 - S NN generated by the controller 30,
  • Each of the gain amplifiers 23 is switched between the output terminal V EA of the error amplifier 20 and a corresponding terminal of the second capacitor C 1 , . . . , C N (ie, V EA1 , . . . , V EAN ).
  • C N is connected to the dynamic Miller compensation network 20, usually occurs when the load current is small and a large compensation capacitor is required, and the corresponding gain amplifier 23 is turned off, so that the gain amplifier The output of 23 is in a high impedance state and does not affect the terminals V EA1 ,...,V EAN , while saving power consumption when the load current is small.
  • any one of the second capacitors C 1 , . . . , C N is removed from the dynamic Miller compensation network 20, usually occurs when a large load current requires a small compensation capacitor, and the corresponding gain amplifier 23 is turned on, so that the terminal V EA1 ,...,V EAN will follow the output V EA change. Since no current flows through the second capacitance C 1 , . . .
  • the voltages V EA1 , . . . , V EAN should be equal to the voltage V EA . Therefore, the steady state V EA1 , ..., V EAN voltage is always at the desired level.
  • the terminals V EA1 , . . . , V EAN will not pass the switches S 1 , . . . , S N and the second resistor R C1 ,...,R CN causes a large voltage peak at the output V EA , making the transient response smoother. Because when the current efficiency of the second capacitor C 1, ..., C N dynamic load Miller compensation network 20 is disconnected from the current, so the corresponding gain of the amplifier 23 is turned on extra current consumption without impairing the regulator.
  • the low dropout linear regulator provided in this embodiment increases the transient response speed of the low dropout linear regulator by adding at least one gain amplifier.
  • FIG. 7 is a circuit diagram of a low dropout linear regulator according to the embodiment. This embodiment adds a secondary amplifier 50 to the above embodiment.
  • low-dropout linear regulator further comprises a secondary amplifier 50, a secondary amplifier 50 are connected in series between the output terminal and the gate of the power transistor M P of the error amplifier 10, i.e., secondary the error amplifier 50 and amplifier 10 in series, secondary amplifier 50 in series with the power transistor P M, a first end connected to secondary amplifier 50 to the output of the error amplifier 10, a second end 50 of the secondary amplifier and the power transistor M The gate of P is connected.
  • the secondary amplifier 50 is a voltage buffer BUF.
  • FIG. 8A is a circuit diagram of a voltage buffer in a low dropout linear regulator according to the embodiment.
  • the voltage buffer includes: a first insulated gate transistor M 21 , a second insulated gate transistor M 22 , a third insulated gate transistor M 23 , and a fourth insulated gate transistor M 24 , a fifth insulated gate transistor M 25 , a sixth insulated gate transistor M 26 , and a seventh insulated gate transistor M 27 , wherein a gate of the seventh insulated gate transistor M 27 and the sixth insulated gate transistor a gate of M 26 is connected, a source of the seventh insulated gate transistor M 27 and a source of the second insulated gate transistor M 22 , a source of the first insulated gate transistor M 21 , and a drain of the sixth insulated gate transistor M 26 is connected, and a drain of the seventh insulated gate transistor M 27 is respectively connected to an output end of the voltage buffer and the second insulated gate transistor M 22 a gate connected; source of said sixth insulating gate type transistor M
  • a first bias current I AB is input between a source of the sixth insulated gate transistor M 26 and a source of the second insulated gate transistor M 22 , the first bias current
  • the current value of I AB is the preset current value.
  • the current value of the first bias current I AB varies with a current value of the output of the low-dropout linear regulator according to a preset ratio, and the current value of the first bias current I AB is linear with the low-voltage difference
  • the current value at the output of the regulator is a preset proportional relationship.
  • the first bias current I AB can be provided by the seventh transistor M 37 in FIG.
  • the first insulated gate type transistor M 21 and the second insulated gate type transistor M 22 constitute an input end of the voltage buffer; the third insulated gate type transistor M 23 and the fourth insulated gate type transistor M 24 form a voltage The active load of the buffer; the second bias current I B2 between the drain of the fifth insulated gate transistor M 25 , the sixth insulated gate transistor M 26 and the fifth insulated gate transistor M 25 and the ground Set up the network.
  • the voltage V EA at the output of the error amplifier 10 is close to the power supply voltage, and the voltage V BS in the voltage buffer is at a high level.
  • the seventh insulated gate transistor M 27 is turned on, and the current of the sixth insulated gate type transistor M 26 can be turned on by the seventh insulated gate type transistor M 27 to charge the output terminal voltage V GP of the voltage buffer, so that the power transistor M P is weakly inverted or sub- Work in the threshold area.
  • the voltage V EA at the output of the error amplifier 10 is small, and the voltage V BS in the voltage buffer is also small.
  • the seventh insulated gate transistor M 27 Closed, and because the first insulated gate transistor M 21 and the second insulated gate transistor M 22 form the input end of the voltage buffer, the lower limit of the output swing of the voltage buffer can be very small, and the low dropout can be linearly stabilized.
  • the power transistor M P in the voltage regulator is better turned on, thereby facilitating the low dropout voltage regulator to achieve a larger load current capability.
  • the voltage buffer can be applied not only to the low-dropout linear regulator provided in this embodiment, but also to a general low-dropout linear regulator including an off-chip capacitor or an off-chip capacitor. .
  • the controller includes: a first control transistor 81, a second control transistor 82, a third control transistor 83, a fourth control transistor 84, and a fifth control transistor. 85, a sixth control transistor 86, a seventh control transistor 87 and an eighth control transistor 88;
  • the first control transistor 81, the source of the seventh control transistor 87, and the source of the eighth control transistor 88 are disposed to be connected to the power source V IN , and the gate of the first control transistor 81 is a gate of the power transistor M P is connected, a source of the second control transistor 82 is connected to a drain of the power transistor M P , a drain of the first control transistor 81 and the third control transistor The source of the second control transistor 82 is connected to the gate of the third control transistor 83, the gate of the second control transistor 82 and the drain of the second control transistor 82.
  • a drain of the second control transistor 82 is connected to a drain of the fourth control transistor 82, and a drain of the third control transistor 83 is connected to a drain of the fifth control transistor 85.
  • a gate of the fourth control transistor 84, a gate of the fifth control transistor 85, and a gate of the sixth control transistor 86 are connected to each other, a source of the fourth control transistor 84, and a fifth control a source of the transistor 85 and the sixth control
  • the source of the transistor 86 is grounded, the gate of the fifth control transistor 85 is connected to the drain of the fifth control transistor 85, and the drain of the sixth control transistor 86 and the drain of the seventh control transistor 87 a gate connection, a gate of the seventh control transistor 87 is connected to a drain of the seventh control transistor 87, and a gate of the seventh control transistor 87 is connected to a gate of the eighth control transistor 88.
  • the drain of the eighth transistor 88 is arranged to output a first bias current I AB .
  • the current value of the first bias current I AB is in a preset proportional relationship with the current value of the output terminal of the low dropout linear regulator.
  • the controller when the controller outputs the multiple control signals, referring to FIG. 8C, the controller further includes: a plurality of control signal generating circuits and at least one third control signal transistor 91. ; the control signal generating circuit, comprising: a first control signal to transistor 89, transistor 90 of the second control signal, a first semiconductor element and the second semiconductor element D 1 D 2; drain of the first transistor 89 and a control signal a source of the second control signal transistor 90 is disposed to be connected to the power source V IN , a gate of the first control signal transistor 89 is connected to a gate of the sixth control transistor 86, and the second control the drain of transistor 90 to the signal a first control signal connected to the drain of transistor 89, the drain of the second transistor 90 and the control signal input of the first semiconductor element D 1 is connected to the second control transistor 90 and the gate signal of the first semiconductor element D 1 is connected to an output terminal, the output terminal of the first semiconductor element D 1 is connected to an input terminal of the second semiconductor
  • I B3 -I B7 is the current value.
  • the transistor parameter of the first control signal transistor 89 in the first control signal generating circuit K1 may be different from the transistor parameter of the first control signal transistor 89 in the second control signal generating circuit K2; the first control signal generating circuit K1
  • the transistor parameter of the second control signal transistor 90 may also be different from the transistor parameter of the second control signal transistor 90 of the second control signal generating circuit K2.
  • the controller when the controller outputs only one control signal, referring to FIG. 8D, the controller further includes: a fourth control signal transistor 92, a fifth control signal transistor 93, and a a third semiconductor element D 3 and a fourth semiconductor element D 4 ; a drain of the fourth control signal transistor 92 and a source of the fifth control signal transistor 83 are disposed to be connected to the power source V IN , the fourth A gate of the control signal transistor 92 is connected to a gate of the sixth control transistor 86, and a drain of the fifth control signal transistor 93 is connected to a drain of the fourth control signal transistor 92, the fifth control the drain of transistor 93 and the signal input terminal of the third semiconductor element D 3 is connected to the gate of the fifth transistor 93 and the control signal output terminal of the third semiconductor element D 3 is connected to the third semiconductor output of element D 3 and the input terminal of the fourth semiconductor element D 4 is connected to the output terminal of the fourth semiconductor element D 4 is arranged to output the control signal S 11.
  • the low dropout linear regulator provided in this embodiment uses a low power wide swing voltage buffer, On the basis of ensuring the adjustment accuracy of the low-dropout linear regulator, the response speed of the low-dropout linear regulator is improved, making the low-dropout linear regulator more suitable for power supply management in the system.
  • FIG. 9 is a circuit diagram of a low dropout linear regulator according to the embodiment. This embodiment adds a zero point generator 24 to the above embodiment.
  • low-dropout linear regulator further comprises a zero generator 24, the zero generator 24 includes a third resistor R 0 and the zero generator switch S 1b, a third resistor R 0 and the zero generator
  • the switches S 1b are connected in parallel with the first resistor R C0 and the first capacitor C 0 , respectively, and the control signal of the zero generator switch S 1b is inverted with any one of the control signals of the dynamic Miller compensation network.
  • control signal of the zero point generator switch S 1b is the opposite signal of the control signal of the control switch S 1 in the dynamic Miller compensation network, that is, when the zero point generator switch S 1b is turned off, the switch S 1 is turned on. When the zero generator switch S 1b is open, the switch S 1 is turned off.
  • the third resistor R 0 is connected in parallel with the zero point generator switch S 1b and is connected in series between the first resistor R C0 and the first capacitor C 0 .
  • the resistance value of the third resistor R 0 is much larger than the resistance value of the first resistor R C0 .
  • the zero point generator switch S 1b and the third resistor R 0 form a zero point generator 24, which is a Left Half Plane (LHP) zero point generator, so that the low dropout linear regulator is under load or Get better phase margins without load.
  • LHP Left Half Plane
  • the switch S 1, ..., S N is closed, while the first opened S 1b, a third resistor R 0 Miller dynamic compensation network access. Since the resistance value of the third resistor R 0 is much larger than the first resistor R C0 , the right half plane (RHP) zero point introduced in the dynamic Miller compensation network can be alleviated, eliminated, and even an LHP zero point is generated. A better phase margin can be obtained.
  • the low-dropout linear regulator provided in this embodiment increases the resistance of the dynamic Miller compensation network with a large resistance value at a light load or no load by adding a zero-point generator, and has a large resistance value at a heavy load.
  • the smaller value of the resistor allows the low dropout linear regulator to achieve better phase margin. It can help eliminate the right half-plane zero introduced by dynamic Miller compensation, creating an appropriate left half-plane zero without disrupting Miller frequency compensation and pole separation.
  • the low dropout linear regulator detects the current at the output of the low dropout linear regulator through a controller, and generates a dynamic Miller supplemental network control signal according to the current to control the second in the dynamic Miller compensation network.
  • the on-off of the RC branch dynamically changes the number of accesses of the second capacitor in the dynamic Miller compensation network through the external load of the low-dropout linear regulator, so that the low-dropout linear regulator has a low load current Use a larger compensation capacitor for good stability and a smaller compensation capacitor for higher response and wide bandwidth when the load current is high.

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Abstract

一种低压差线性稳压器，包括误差放大器（10）、功率晶体管（M P）、动态密勒补偿网络（20）和控制器（30）；其中，所述功率晶体管（M P）的源极设置为与电源（V IN）连接，所述功率晶体管（M P）的栅极与所述误差放大器（10）的输出端连接，所述功率晶体管（M P）的漏极与所述低压差线性稳压器的输出端连接；所述低压差线性稳压器通过控制器检测低压差线性稳压器的输出端的电流，并根据该电流生成动态密勒补充网络的控制信号，以控制动态密勒补偿网络中的第二阻容支路（22）的通断，通过低压差线性稳压器外接负载的情况，动态改变动态密勒补偿网络中第二电容（C 1）的接入个数，使得低压差线性稳压器在负载电流较低时使用较大的补偿电容以实现良好的稳定性，在负载电流较高时使用较小的补偿电容以实现快速响应和宽带宽。

Description

低压差线性稳压器 技术领域
本实施例涉及模拟集成电路技术，例如涉及一种低压差线性稳压器。
背景技术
移动电话、笔记本电脑和音乐播放器等高级消费电子设备由电池供电以获得便携性。为了使每个电子设备的功能更强大，采用了越来越复杂的且高度集成的片上***(System-on-Chip，SoC)设计。对于这些片上***，通过采用多个类型的功率转换器来实现能够快速响应、高效且低成本的电源管理以获得竞争优势是至关重要的。低压差线性稳压器是一种通用的功率转换器，具有低噪声、低成本和快速响应等优点，广泛应用于片上***电源管理应用。
通过使用负反馈机制，低压差线性稳压器的控制回路通过调整其功率管的有效电阻，可以产生所需的输出电压。在典型的低压差线性稳压器中，通常使用在几微法拉μF范围内的片外电容器来滤除噪声并且给低压差线性稳压器在不同的负载电流下的稳定性提供主极点。然而，随着低压差线性稳压器的数量的持续增加，去除片外电容以降低成本并提高片上***开发的集成度变得非常重要。
对于相关技术中这种全集成的低压差线性稳压器，在大负载范围内同时实现宽带宽，快速响应和良好稳定性仍是待解决的问题。
发明内容
本公开提供一种低压差线性稳压器，以实现宽带宽和快速响应，而不损害环路稳定性或增加静态电流消耗。
第一方面，本公开提供了一种低压差线性稳压器，包括：
误差放大器、功率晶体管、动态密勒补偿网络和控制器；
所述功率晶体管的源极设置为与电源连接，所述功率晶体管的栅极与所述误差放大器的输出端连接，所述功率晶体管的漏极与所述低压差线性稳压器的输出端连接；
所述动态密勒补偿网络的第一端与所述误差放大器的输出端连接，所述动态密勒补偿网络的第二端与所述低压差线性稳压器的输出端连接，所述控制器 的第一端与所述功率晶体管的栅极连接，所述控制器的第二端与所述密勒补偿网络的第三端连接；
其中，所述动态密勒补偿网络包含第一阻容支路和至少一个第二阻容支路，所述第一阻容支路与所述至少一个第二阻容支路并联，所述第一阻容支路包含串联的第一电阻和第一电容，所述第二阻容支路包含串联的第二电阻和第二电容；
所述控制器设置为：检测所述低压差线性稳压器的输出端的电流，并根据所述电流生成控制信号，以控制所述动态密勒补偿网络中的每个第二阻容支路的连通和断开。
可选的，还包括第一反馈电阻和第二反馈电阻，第一反馈电阻的第一端和第二反馈电阻的第一端相连，并与所述误差放大器的正向输入端相连，所述第一反馈电阻的第二端与所述低压差线性稳压器的输出端相连，所述第二反馈电阻的第二端设置为接地。
可选的，还包括至少一个增益放大器，所述至少一个增益放大器与所述至少一个第二阻容支路一一对应；
其中，每一个所述第二阻容支路中的第二电阻与对应的一个所述增益放大器并联。
可选的，所述至少一个增益放大器的增益为1。
可选的，还包括次级放大器，所述次级放大器与所述误差放大器串联，所述次级放大器与所述功率晶体管串联，所述次级放大器的第一端与所述误差放大器的输出端连接，所述次级放大器的第二端与所述功率晶体管的栅极连接。
可选的，所述次级放大器为电压缓冲器。
可选的，还包括零点发生器，所述零点发生器包括第三电阻和零点发生器开关，所述第三电阻和所述零点发生器开关并联后分别与所述第一电阻和第一电容串联，所述零点发生器开关的控制信号与所述动态密勒补偿网络中的任意一个控制信号反相。
可选的，所述电压缓冲器包括：第一绝缘栅型晶体管、第二绝缘栅型晶体管、第三绝缘栅型晶体管、第四绝缘栅型晶体管、第五绝缘栅型晶体管、第六绝缘栅型晶体管和第七绝缘栅型晶体管，其中，
所述第七绝缘栅型晶体管的栅极与所述第六绝缘栅型晶体管的栅极相连，所述第七绝缘栅型晶体管的源极分别与所述第二绝缘栅型晶体管的源极、所述 第一绝缘栅型晶体管的源极以及所述第六绝缘栅型晶体管的漏极相连，所述第七绝缘栅型晶体管的漏极分别与所述电压缓冲器的输出端及所述第二绝缘栅型晶体管的栅极相连；所述第六绝缘栅型晶体管的源极分别与所述第五绝缘栅型晶体管的源极及电源相连；
所述第五绝缘栅型晶体管的栅极与所述第五绝缘栅型晶体管的漏极连接后接地；
所述第一绝缘栅型晶体管的栅极与所述误差放大器的输出端相连，所述第一绝缘栅型晶体管的漏极分别与所述第三绝缘栅型晶体管的漏极及所述第三绝缘栅型晶体管的栅极相连；
所述第二绝缘栅型晶体管的漏极分别与所述第四绝缘栅型晶体管的漏极及所述电压缓冲器的输出端相连；
所述第三绝缘栅型晶体管的源极和所述第四绝缘栅型晶体管的源极连接后接地，所述第三绝缘栅型晶体管的栅极和所述第四绝缘栅型晶体管的栅极相连。
可选的，所述第六绝缘栅型晶体管的源极与所述第二绝缘栅型晶体管的源极设置为接收所述控制器产生的第一偏置电流，所述第一偏置电流的电流值与所述低压差线性稳压器的输出端的电流值成预设比例关系。
可选的，所述控制器包括：第一控制晶体管、第二控制晶体管、第三控制晶体管、第四控制晶体管、第五控制晶体管、第六控制晶体管、第七控制晶体管和第八控制晶体管；
所述第一控制晶体管、所述第七控制晶体管的源极以及所述第八控制晶体管的源极设置为与所述电源连接，所述第一控制晶体管的栅极与所述功率晶体管的栅极连接，所述第二控制晶体管的源极与所述功率晶体管的漏极连接，所述第一控制晶体管的漏极与所述第三控制晶体管的源极连接，所述第二控制晶体管的栅极与所述第三控制晶体管的栅极连接，所述第二控制晶体管的栅极与所述第二控制晶体管的漏极连接，所述第二控制晶体管的漏极与所述第四控制晶体管的漏极连接，所述第三控制晶体管的漏极与所述第五控制晶体管的漏极连接，所述第四控制晶体管的栅极、所述第五控制晶体管的栅极、以及所述第六控制晶体管的栅极相互连接，所述第四控制晶体管的源极、所述第五控制晶体管的源极以及所述第六控制晶体管的源极接地，所述第五控制晶体管的栅极与所述第五控制晶体管的漏极连接，所述第六控制晶体管的漏极与所述第七控制晶体管的漏极连接，所述第七控制晶体管的栅极与所述第七控制晶体管的漏 极连接，所述第七控制晶体管的栅极与所述第八控制晶体管的栅极连接，所述第八晶体管的漏极设置为输出所述第一偏置电流。
可选的，所述控制器还包括：多个控制信号生成电路和至少一个第三控制信号晶体管；
所述控制信号生成电路包括：第一控制信号晶体管、第二控制信号晶体管、第一半导体元件和第二半导体元件；
所述第一控制信号晶体管的漏极和所述第二控制信号晶体管的源极设置为与所述电源连接，所述第一控制信号晶体管的栅极与所述第六控制晶体管的栅极连接，
所述第二控制信号晶体管的漏极与所述第一控制信号晶体管的漏极连接，所述第二控制信号晶体管的漏极与所述第一半导体元件的输入端连接，所述第二控制信号晶体管的栅极与所述第一半导体元件的输出端连接，
所述第一半导体元件的输出端与所述第二半导体元件的输入端连接，所述第二半导体元件的输出端设置为输出所述控制信号；
任意相邻两个所述控制信号生成电路为第一控制信号生成电路和第二控制信号生成电路；
所述第一控制信号生成电路中的第二半导体元件的输出端与所述第三控制信号晶体管的栅极连接，所述第三控制信号晶体管的源极设置为与所述电源连接，所述第三控制信号晶体管的漏极与所述第二控制信号生成电路中的所述第二控制信号晶体管的漏极连接。
可选的，所述控制器还包括：第四控制信号晶体管、第五控制信号晶体管、第三半导体元件和第四半导体元件；
所述第四控制信号晶体管的漏极和所述第五控制信号晶体管的源极设置为与所述电源连接，
所述第四控制信号晶体管的栅极与所述第六控制晶体管的栅极连接，
所述第五控制信号晶体管的漏极与所述第四控制信号晶体管的漏极连接，所述第五控制信号晶体管的漏极与所述第三半导体元件的输入端连接，所述第五控制信号晶体管的栅极与所述第三半导体元件的输出端连接，
所述第三半导体元件的输出端与所述第四半导体元件的输入端连接，所述第四半导体元件的输出端设置为输出所述控制信号。
本实施例提供的低压差线性稳压器，通过控制器检测低压差线性稳压器的 输出端的电流，并根据该电流生成动态密勒补充网络的控制信号，以控制动态密勒补偿网络中的第二阻容支路的通断，通过低压差线性稳压器外接负载的情况，动态改变动态密勒补偿网络中第二电容的接入个数，使得低压差线性稳压器在负载电流较低时使用较大的补偿电容以实现良好的稳定性，在负载电流较高时使用较小的补偿电容以实现快速响应和宽带宽。
附图说明
图1为相关技术提供的一种无片外电容的低压差线性稳压器的电路图。
图2为相关技术提供的另一种无片外电容的低压差线性稳压器的电路图。
图3为实施例一提供的一种低压差线性稳压器的电路图。
图4为实施例一提供的低压差线性稳压器中的运算跨导放大器的电路图。
图5为实施例一提供的低压差线性稳压器中的控制器的电路图。
图6为实施例二提供的一种低压差线性稳压器的电路图。
图7为实施例三提供的一种低压差线性稳压器的电路图。
图8A为实施例三提供的低压差线性稳压器中的电压缓冲器的电路图。
图8B为实施例三提供的一种控制器的电路图。
图8C为实施例三提供的又一种控制器的电路图。
图8D为实施例三提供的又一种控制器的电路图。
图9为实施例四提供的一种低压差线性稳压器的电路图。
具体实施方式
相关技术中提供了一种无片外电容的低压差线性稳压器，图1为相关技术提供的一种无片外电容的低压差线性稳压器的电路图。图2为相关技术提供的另一种无片外电容的低压差线性稳压器的电路图。如图1所示，该电路包括：运算跨导放大器(Operational Transconductance Amplifier，OTA)、功率晶体管MP1、带隙基准、电阻r1、电阻r2、电阻r3和电容C。带隙基准为OTA的一个输入端产生直流参考电压；电阻r1和电阻r2对输出电压(VOUT)进行采样并反馈到OTA的另一输入端以调节输出电压。电容C和电阻r3组成补偿网络，其中电容C是帮助产生主极点的密勒电容。为了实现大的负载电流和小的压差 电压，功率晶体管MP1通常具有较大的宽度/长度(W/L)比值，因此具有较大的寄生电容。可以在OTA和功率晶体管MP1之间增加第二级放大器，如图2所示。第二级放大器可以具有增益可以提高总环路增益，并因此提高稳压器的调节精度。其中，第二级放大器也可以是电压缓冲器，以通过提高OTA的驱动能力来获得更快的调节速度。
实施例一
图3为本实施例提供的一种低压差线性稳压器的电路图。参见图3，该低压差线性稳压器包括：误差放大器10和功率晶体管MP，还包括：动态密勒补偿网络20和控制器30；所述功率晶体管MP的源极设置为与电源VIN连接，所述功率晶体管MP栅极与所述误差放大器10的输出端连接，所述功率晶体管MP漏极与所述低压差线性稳压器的输出端VOUT连接；所述动态密勒补偿网络20连接在所述误差放大器10的输出端与所述低压差线性稳压器的输出端VOUT之间，所述动态密勒补偿网络20的第一端与所述误差放大器10的输出端连接，所述动态密勒补偿网络20的第二端与所述低压差线性稳压器的输出端VOUT连接，所述控制器30的第一端与所述功率晶体管MP的栅极连接，所述控制器30的第二端与和所述密勒补偿网络20的第三端连接；其中，所述动态密勒补偿网络20包含第一阻容支路21和至少一个第二阻容支路22，所述第一阻容支路21与所述至少一个第二阻容支路22并联，所述第一阻容支路21包含串联的第一电阻RC0和第一电容C0，所述第二阻容支路包含串联的第二电阻RC1，…，RCN和第二电容C1，…，CN；所述控制器30设置为：检测所述低压差线性稳压器的输出端VOUT的电流，并根据所述电流生成所述动态密勒补偿网络20的控制信号，以控制所述动态密勒补偿网络20中的每个第二阻容支路22的连通和断开。
可选的，所述低压差线性稳压器还包括反馈电阻40，所述反馈电阻40包括第一反馈电阻R1和第二反馈电阻R2，其中，第一反馈电阻R1和第二反馈电阻R2串联构成反馈电阻40，第一反馈电阻R1的第一端和第二反馈电阻R2的第一端相连，并与误差放大器10的正向输入端相连，第一反馈电阻R1的第二端与低压差线性稳压器的输出端VOUT相连，第二反馈电阻R2的第二端接地。
在本实施例中，可选的，误差放大器10为运算跨导放大器OTA，OTA包括 一个正向输入端、一个反向输入端和一个输出端。误差放大器10的反向输入端输入有基准电压，可选的，所述基准电压为带隙基准电压，其中，带隙基准电压为稳压器的参考电压。动态密勒补偿网络20包含第一阻容支路21和至少一个第二阻容支路22，示例性的，动态密勒补偿网络20中包含N个第二阻容支路22，其中，N为不小于1的整数，每个第二阻容支路中的第二电阻分别用RC1，…，RCN表示，第二电容分别用C1，…，CN表示。相应的，控制器30根据低压差线性稳压器的输出端VOUT的电流生成的动态密勒补偿网络20的控制信号，上述控制信号为N个，每个控制信号分别对应控制一个第二阻容支路22中一个开关的连通与断开，每个控制信号对应控制的开关分别用S1，…，SN表示。当低压差线性稳压器的输出端的电流(负载电流)变化时，控制器30产生N个控制信号S11，…，SNN，分别对应控制开关S1，…，SN的通断，使得第二阻容支路22中的第二电容C1，…，CN保持在动态密勒补偿网络20中或从动态密勒补偿网络20去除，以达到具有所需的相位和增益裕度的期望带宽。示例性的，当低压差线性稳压器的输出端VOUT的负载电流处于较小时，控制器30产生的控制信号S11，…，SNN控制所有开关S1，…，SN闭合，以将动态密勒补偿网络20中所有的第二电容C1，…，CN接入，以使低压差线性稳压器达到较佳的稳定性；当低压差线性稳压器的输出端VOUT的负载电流处于较大值时，控制器30产生的控制信号控制所有开关S1，…，SN全部打开，以将动态密勒补偿网络20中所有的第二电容C1，…，CN切断，以使低压差线性稳压器获得较佳的相位裕度和较佳的瞬态响应速度。
在本实施例中，运算跨导放大器OTA可以是一个电流镜式放大器。图4是本实施例提供的低压差线性稳压器中的运算跨导放大器的电路图。如图4所示，OTA包括一对由第一晶体管M1-M2组成的输入端，三个由第二晶体管M3-M4，M5-M6，M7-M8组成的电流镜，一个由偏置电流IB1和第三晶体管M9-M10组成的偏置网络，第四晶体管M11，第四晶体管M11的栅极可以被单独施加电压VDB，且第四晶体管M11可以为OAT提供动态偏置电流。第二晶体管M3-M6的源极接输入电源VIN；第二晶体管M7-M8的源极、第三晶体管M9-M10的源极及第四晶体管M11的源极相连并接地；第一晶体管M1-M2的源极、第三晶体管M10的漏极及第四晶体管M11的漏极相连；第一晶体管M1的漏极和第二晶体管M3的漏极相连；第一晶体管M2的漏极和 第二晶体管M5的漏极相连；第二晶体管M4的漏极和第二晶体管M7的漏极相连；第二晶体管M6的漏极和第二晶体管M8的漏极相连，且该连接点为OTA的输出端V0；偏置电流IB1为输入电源VIN和第三晶体管M9的漏极之间的电流。通过瞬时地增加或减少OTA中的偏置电流IB1，可以提高低压差线性稳压器输出端的电流瞬变时的响应速度。该电流镜式放大器可以提供宽输出电压摆幅，有利于提高低压差线性稳压器的宽负载范围。
图5为本实施例提供的低压差线性稳压器中的控制器的电路图。为了便于讨论，功率晶体管MP也在该控制器的电路图中示出。上述控制器包括电流检测模块和控制信号生成模块，其中电流检测模块由第五晶体管MSEN和第六晶体管M31-M34组成，第六晶体管M31-M34构成放大器，使得第五晶体管MSEN的漏极电压与功率晶体管的漏极电压相同，以实现精确的电流检测。为了节省电流检测模块的功耗，将检测比也即第五晶体管MSEN与功率晶体管MP的大小比设置为1∶M，通常M为远远大于1的整数，例如M为100或1000等。检测到的负载电流通过第七晶体管M35-M37镜像以在M37中提供自适应偏置电流。检测到的负载电流也通过第八晶体管M38和M41被镜像，以帮助产生用于低压差线性稳压器中的动态密勒补偿网络的控制信号。为了示范说明，仅示出了控制开关S1和S2的两个控制信号S11和S22的生成。第一固定偏置电流IB3和第二固定偏置电流IB7具有预定的电流值。假设低压差线性稳压器具有非常小的初始负载电流，控制信号S11和S22都处于高电平，第二电容C1和C2被接入动态密勒补偿网络中，以形成对低压差线性稳压器的稳定性的补偿。在这种情况下，第九晶体管M39和M42导通以允许电流IB4和IB7通过，而第十晶体管M40截止以阻断电流IB5。当负载电流超过第一个预定值IL1，使得第八晶体管M38的电流高于电流IB3和IB4的电流之和时，第八晶体管M38的漏极电压下降，因此控制信号S11被下拉至低电平，从而使第二电容C1从动态密勒补偿网络中去除。因此，动态密勒补偿网络中的总的第二电容的个数减小，低压差线性稳压器的带宽得到改善。在这种情况下，控制信号S11处于低电平，因此晶体管第十晶体管M40导通以允许电流IB5通过。当负载电流逐渐增加以超过第二个特定预定义值IL2，使得第十一晶体管M41的电流高于电流IB5，IB6和IB7的总电流之和时，第十一晶体管M41的漏极电压下降，并且因此控制信号 S22被下拉到低电平，从而使第二电容C2从动态密勒补偿网络中去除。因此，动态密勒补偿网络中的总的第二电容的个数逐渐减小，使低压差线性稳压器的带宽得到改善。根据需要可以用类似的方法生成更多的控制信号。由于实际上负载电流可能有变化，因此通过电流IB4和IB7引入滞后以避免控制信号产生中的振荡。示例性的，当负载电流增加到超过IL1，使得第八晶体管M38的电流高于IB3和IB4之和时，则控制信号S11从高电平切换到低电平。此时，第九晶体管M39被关闭，并且电流IB4被阻塞，只有当负载电流大幅降低，使得第八晶体管M38的电流低于电流IB3，则第八晶体管M38的漏极上升，控制信号S11被上拉至高电平，否则控制信号S11将保持在低电平，另外，负载电流的小变化不会导致S11被错误触发。类似地，当负载电流超过IL2，使得第十一晶体管M41的电流高于IB5、IB6和IB7之和时，则控制信号S22从高电平切换到低电平，电流IB7被第九晶体管M42阻挡。只有当负载电流大幅降低时，第十一晶体管M41低于IB5和IB6之和，以再次使控制信号S22回到高电平。
本实施例提供的低压差线性稳压器，通过控制器检测低压差线性稳压器的输出端的电流，并根据该电流生成动态密勒补充网络的控制信号，以控制动态密勒补偿网络中的第二阻容支路的通断，通过低压差线性稳压器外接负载的情况，动态改变动态密勒补偿网络中第二电容的接入个数，使得低压差线性稳压器在负载电流较低时使用较大的补偿电容以实现良好的稳定性，在负载电流较高时使用较小的补偿电容以实现快速响应和宽带宽。
实施例二
图6为本实施例提供的一种低压差线性稳压器的电路图。本实施例在上述实施例的基础上，增加了至少一个增益放大器23。
可选的，低压差线性稳压器还包括至少一个增益放大器23，所述至少一个增益放大器23与所述动态密勒补偿网络20中的至少一个第二阻容支路22一一对应；每一个第二阻容支路22中的第二电阻RC1，…，RCN分别与对应的一个增益放大器23并联。可选的，所述至少一个增益放大器23的增益为1。
如图6所示，增益放大器23的个数为N个，每个增益放大器23由控制器 30产生的控制信号S11-SNN的相反信号控制开关S1b，…，SNb的通断，以切换每个增益放大器23分别接入在误差放大器20输出端VEA与相应的第二电容C1，…，CN的一个端子(即VEA1，…，VEAN)之间。当第二电容C1，…，CN中的任意一个电容接入动态密勒补偿网络20时，通常在负载电流较小需要大补偿电容时发生，相应的增益放大器23被关闭，使得增益放大器23的输出处于高阻抗状态并且不影响端子VEA1，…，VEAN，同时节省了负载电流较小时的功耗。当第二电容C1，…，CN中的任意一个从动态密勒补偿网络20去除时，通常在负载电流较大需要小补偿电容时发生，相应的增益放大器23将被接通，使得端子VEA1，…，VEAN将跟随输出端VEA变化。由于在稳态中没有电流流过第二电容C1，…，CN，所以电压VEA1，…，VEAN应该等于电压VEA。因此，稳态VEA1，…，VEAN电压总是处于所需的电平。当具有较大负载电流并且第二电容需要被接入或切出动态密勒补偿网络20时，端子VEA1，…，VEAN将不会通过开关S1，…，SN和第二电阻RC1，…，RCN在输出端VEA引起大的电压峰值，使得瞬态响应变得更平滑。由于当第二电容C1，…，CN从动态密勒补偿网络20断开时负载电流大，所以相应的导通的增益放大器23消耗的额外电流不会损害稳压器的电流效率。
本实施例提供的低压差线性稳压器，通过增加至少一个增益放大器，提高了低压差线性稳压器的瞬态响应速度。
实施例三
图7为本实施例提供的一种低压差线性稳压器的电路图。本实施例在上述实施例的基础上，增加了次级放大器50。
可选的，低压差线性稳压器还包括次级放大器50，所述次级放大器50串联在所述误差放大器10的输出端与所述功率晶体管MP的栅极之间，也即次级放大器50与所述误差放大器10串联，次级放大器50与功率晶体管MP串联，次级放大器50的第一端与误差放大器10的输出端连接，次级放大器50的第二端与功率晶体管MP的栅极连接。可选的，所述次级放大器50为电压缓冲器BUF。
图8A为本实施例提供的低压差线性稳压器中的电压缓冲器的电路图。如图8A所示，所述电压缓冲器包括：第一绝缘栅型晶体管M21、第二绝缘栅型晶体管 M22、第三绝缘栅型晶体管M23、第四绝缘栅型晶体管M24、第五绝缘栅型晶体管M25、第六绝缘栅型晶体管M26和第七绝缘栅型晶体管M27，其中，所述第七绝缘栅型晶体管M27的栅极与所述第六绝缘栅型晶体管M26的栅极相连，所述第七绝缘栅型晶体管M27的源极分别与所述第二绝缘栅型晶体管M22的源极、所述第一绝缘栅型晶体管M21的源极以及所述第六绝缘栅型晶体管M26的漏极相连，所述第七绝缘栅型晶体管M27的漏极分别与所述电压缓冲器的输出端及所述第二绝缘栅型晶体管M22的栅极相连；所述第六绝缘栅型晶体管M26的源极分别与所述第五绝缘栅型晶体管M25的源极及电源相连；所述第五绝缘栅型晶体管M25的栅极与所述第五绝缘栅型晶体管M25的漏极连接后接地；所述第一绝缘栅型晶体管M21的栅极与所述误差放大器的输出端相连，所述第一绝缘栅型晶体管M21的漏极分别与所述第三绝缘栅型晶体管M23的漏极及所述第三绝缘栅型晶体管M23的栅极相连；所述第二绝缘栅型晶体管M22的漏极分别与所述第四绝缘栅型晶体管M24的漏极及所述电压缓冲器的输出端相连；所述第三绝缘栅型晶体管M23的源极和所述第四绝缘栅型晶体管M24的源极连接后接地，所述第三绝缘栅型晶体管M23的栅极和所述第四绝缘栅型晶体管M24的栅极相连。可选的，向所述第六绝缘栅型晶体管M26的源极与所述第二绝缘栅型晶体管M22的源极之间输入第一偏置电流IAB，所述第一偏置电流IAB的电流值为预设电流值。示例性的，所述第一偏置电流IAB的电流值按预设比例随所述低压差线性稳压器的输出端的电流值变化，第一偏置电流IAB的电流值与低压差线性稳压器的输出端的电流值为预设比例关系。第一偏置电流IAB可以由图5中第七晶体管M37提供。
在本实施例中，第一绝缘栅型晶体管M21和第二绝缘栅型晶体管M22组成电压缓冲器的输入端；第三绝缘栅型晶体管M23和第四绝缘栅型晶体管M24组成电压缓冲器的有源负载；第五绝缘栅型晶体管M25、第六绝缘栅型晶体管M26和第五绝缘栅型晶体管M25的漏极与地之间的第二偏置电流IB2组偏置网络。当低压差线性稳压器的输出端的电流较小时，误差放大器10的输出端的电压VEA接近电源电压，电压缓冲器中的电压VBS为高电平，此时，第七绝缘栅型晶体管M27导通，第六绝缘栅型晶体管M26的电流可以通过第七绝缘栅型晶体管M27导通，对电压缓冲器的输出端电压VGP充电，使得功率晶体管MP在弱反转或亚阈值区域中工作。当低压 差线性稳压器的输出端的电流较大时，误差放大器10的输出端的电压VEA较小，电压缓冲器中的电压VBS也较小，此时，第七绝缘栅型晶体管M27被关闭，又由于第一绝缘栅型晶体管M21和第二绝缘栅型晶体管M22组成电压缓冲器的输入端，使得电压缓冲器的输出摆幅的下限可以非常小，可以使低压差线性稳压器中的功率晶体管MP更好接通，从而利于该低压差稳压器实现具有较大的负载电流能力。需要说明的是，电压缓冲器不仅可以适用于本实施例提供的低压差线性稳压器中，而且也可以适用于一般的包括片外电容或不包括片外电容的低压差线性稳压器中。
可选的，在上述实施例的基础上，参考图8B，所述控制器包括：第一控制晶体管81、第二控制晶体管82、第三控制晶体管83、第四控制晶体管84、第五控制晶体管85、第六控制晶体管86、第七控制晶体管87和第八控制晶体管88；
所述第一控制晶体管81、所述第七控制晶体管87的源极以及所述第八控制晶体管88的源极设置为与所述电源VIN连接，所述第一控制晶体管81的栅极与所述功率晶体管MP的栅极连接，所述第二控制晶体管82的源极与所述功率晶体管MP的漏极连接，所述第一控制晶体管81的漏极与所述第三控制晶体管83的源极连接，所述第二控制晶体管82的栅极与所述第三控制晶体管83的栅极连接，所述第二控制晶体管82的栅极与所述第二控制晶体管82的漏极连接，所述第二控制晶体管82的漏极与所述第四控制晶体管82的漏极连接，所述第三控制晶体管83的漏极与所述第五控制晶体管85的漏极连接，所述第四控制晶体管84的栅极、所述第五控制晶体管85的栅极、以及所述第六控制晶体管86的栅极相互连接，所述第四控制晶体管84的源极、所述第五控制晶体管85的源极以及所述第六控制晶体管86的源极接地，所述第五控制晶体管85的栅极与所述第五控制晶体管85的漏极连接，所述第六控制晶体管86的漏极与所述第七控制晶体管87的漏极连接，所述第七控制晶体管87的栅极与所述第七控制晶体管87的漏极连接，所述第七控制晶体管87的栅极与所述第八控制晶体管88的栅极连接，所述第八晶体管88的漏极设置为输出第一偏置电流IAB。
其中，所述第一偏置电流IAB的电流值与所述低压差线性稳压器的输出端的电流值成预设比例关系。
可选的，在上述实施例的基础上，当所述控制器输出多路控制信号时，参考图8C，所述控制器还包括：多个控制信号生成电路和至少一个第三控制信号 晶体管91；所述控制信号生成电路，包括：第一控制信号晶体管89、第二控制信号晶体管90、第一半导体元件D1和第二半导体元件D2；所述第一控制信号晶体管89的漏极和所述第二控制信号晶体管90的源极设置为与所述电源VIN连接，所述第一控制信号晶体管89的栅极与所述第六控制晶体管86的栅极连接，所述第二控制信号晶体管90的漏极与所述第一控制信号晶体管89的漏极连接，所述第二控制信号晶体管90的漏极与所述第一半导体元件D1的输入端连接，所述第二控制信号晶体管90的栅极与所述第一半导体元件D1的输出端连接，所述第一半导体元件D1的输出端与所述第二半导体元件D2的输入端连接，所述第二半导体元件D2的输出端设置为输出所述控制信号(图中示意性的画出两个控制信号S11、S22)；任意相邻两个所述控制信号生成电路为第一控制信号生成电路K1和第二控制信号生成电路K2；所述第一控制信号生成电路K1中的第二半导体元件D2的输出端与所述第三控制信号晶体管91的栅极连接，所述第三控制信号晶体管91的源极设置为与所述电源VIN连接，所述第三控制信号晶体管91的漏极与所述第二控制信号生成电路K2中的所述第二控制信号晶体管90的漏极连接。其中，IB3-IB7为电流值。其中，第一控制信号生成电路K1中的第一控制信号晶体管89的晶体管参数可以与第二控制信号生成电路K2中的第一控制信号晶体管89的晶体管参数不相同；第一控制信号生成电路K1中的第二控制信号晶体管90的晶体管参数也可以与第二控制信号生成电路K2中的第二控制信号晶体管90的晶体管参数不相同。
可选的，在上述实施例的基础上，当所述控制器只输出一路控制信号时，参考图8D，所述控制器还包括：第四控制信号晶体管92、第五控制信号晶体管93、第三半导体元件D3和第四半导体元件D4；所述第四控制信号晶体管92的漏极和所述第五控制信号晶体管83的源极设置为与所述电源VIN连接，所述第四控制信号晶体管92的栅极与所述第六控制晶体管86的栅极连接，所述第五控制信号晶体管93的漏极与所述第四控制信号晶体管92的漏极连接，所述第五控制信号晶体管93的漏极与所述第三半导体元件D3的输入端连接，所述第五控制信号晶体管93的栅极与所述第三半导体元件D3的输出端连接，所述第三半导体元件D3的输出端与所述第四半导体元件D4的输入端连接，所述第四半导体元件D4的输出端设置为输出所述控制信号S11。
本实施例提供的低压差线性稳压器，通过使用低功率宽摆幅的电压缓冲器， 在保证低压差线性稳压器调节精度的基础上，提高了低压差线性稳压器的响应速度，使得低压差线性稳压器更加适合在片上***电源管理中应用。
实施例四
图9为本实施例提供的一种低压差线性稳压器的电路图。本实施例在上述实施例的基础上，增加了零点发生器24。
可选的，低压差线性稳压器还包括零点发生器24，所述零点发生器24包括第三电阻R0和零点发生器开关S1b，所述第三电阻R0和所述零点发生器开关S1b并联后分别与所述第一电阻RC0和第一电容C0串联，所述零点发生器开关S1b的控制信号与动态密勒补偿网络的任意一个控制信号反相。
示例性的，零点发生器开关S1b的控制信号为动态密勒补偿网络中控制开关S1的控制信号的相反信号，也即是，当零点发生器开关S1b关闭时，开关S1打开，当零点发生器开关S1b打开时，开关S1关闭。第三电阻R0与零点发生器开关S1b并联后串联在第一电阻RC0和第一电容C0之间。其中，第三电阻R0的电阻值远远大于第一电阻RC0的电阻值。零点发生器开关S1b与第三电阻R0构成零点发生器24，该零点发生器24为左半平面(Left Half Plane，LHP)零点发生器，使得低压差线性稳压器在负载较小或者无负载时获得更好的相位裕度。当低压差线性稳压器的输出端的电流小于阈值时，开关S1，…，SN闭合，同时第一S1b打开，第三电阻R0接入动态密勒补偿网络。由于第三电阻R0的电阻值远大于第一电阻RC0，使得动态密勒补偿网络中引入的右半平面(Right Half Plane，RHP)零点可以得到减轻，消除，甚至产生一个LHP零点，这样可以获得更好的相位裕度。当低压差线性稳压器的输出端的电流增加时，不再需要动态密勒补偿网络中的电阻阻值较大来获得合适的相位裕度。而且，如果电阻阻值太大会使动态密勒补偿网络断开，这样会破坏动态密勒频率补偿的效果，极点分离效应也会消失。因此，当低压差线性稳压器输出端的电流增加到某个预定的值时，零点发生器开关S1b闭合，第一电阻R0从动态密勒补偿网络中断开。
本实施例提供的低压差线性稳压器，通过增加零点发生器，在轻负载或无负载时，使动态密勒补偿网络中的电阻具有较大的电阻值，而在重负载时具有 较小的电阻值，使得低压差线性稳压器获得更好的相位裕度。可以有助于消除由动态密勒补偿引入的右半平面零点，创造一个适当的左半平面零点而不破坏密勒频率补偿和极点分离效果。
工业实用性
本公开提供的低压差线性稳压器通过控制器检测低压差线性稳压器的输出端的电流，并根据该电流生成动态密勒补充网络的控制信号，以控制动态密勒补偿网络中的第二阻容支路的通断，通过低压差线性稳压器外接负载的情况，动态改变动态密勒补偿网络中第二电容的接入个数，使得低压差线性稳压器在负载电流较低时使用较大的补偿电容以实现良好的稳定性，在负载电流较高时使用较小的补偿电容以实现快速响应和宽带宽。

Claims (12)

  1. 一种低压差线性稳压器，包括：误差放大器、功率晶体管、动态密勒补偿网络和控制器；
    所述功率晶体管的源极设置为与电源连接，所述功率晶体管的栅极与所述误差放大器的输出端连接，所述功率晶体管的漏极与所述低压差线性稳压器的输出端连接；
    所述动态密勒补偿网络的第一端与所述误差放大器的输出端连接，所述动态密勒补偿网络的第二端与所述低压差线性稳压器的输出端连接，所述控制器的第一端与所述功率晶体管的栅极连接，所述控制器的第二端与所述密勒补偿网络的第三端连接；
    其中，所述动态密勒补偿网络包含第一阻容支路和至少一个第二阻容支路，所述第一阻容支路与所述至少一个第二阻容支路并联，所述第一阻容支路包含串联的第一电阻和第一电容，所述第二阻容支路包含串联的第二电阻和第二电容；
    所述控制器设置为：检测所述低压差线性稳压器的输出端的电流，并根据所述电流生成控制信号，以控制所述动态密勒补偿网络中的每个第二阻容支路的连通和断开。
  2. 根据权利要求1所述的低压差线性稳压器，还包括第一反馈电阻和第二反馈电阻，第一反馈电阻的第一端和第二反馈电阻的第一端相连，并与所述误差放大器的正向输入端相连，所述第一反馈电阻的第二端与所述低压差线性稳压器的输出端相连，所述第二反馈电阻的第二端设置为接地。
  3. 根据权利要求2所述的低压差线性稳压器，还包括至少一个增益放大器，所述至少一个增益放大器与所述至少一个第二阻容支路一一对应；
    其中，每一个所述第二阻容支路中的第二电阻与对应的一个所述增益放大器并联。
  4. 根据权利要求3所述的低压差线性稳压器，所述至少一个增益放大器的增益为1。
  5. 根据权利要求3所述的低压差线性稳压器，还包括次级放大器，所述次级放大器与所述误差放大器串联，所述次级放大器与所述功率晶体管串联，所述次级放大器的第一端与所述误差放大器的输出端连接，所述次级放大器的第二端与所述功率晶体管的栅极连接。
  6. 根据权利要求5所述的低压差线性稳压器，所述次级放大器为电压缓冲 器。
  7. 根据权利要求2-6任一项所述的低压差线性稳压器，还包括零点发生器，所述零点发生器包括第三电阻和零点发生器开关，所述第三电阻和所述零点发生器开关并联后分别与所述第一电阻和第一电容串联，所述零点发生器开关的控制信号与所述动态密勒补偿网络中的任意一个控制信号反相。
  8. 根据权利要求6所述的低压差线性稳压器，所述电压缓冲器包括：第一绝缘栅型晶体管、第二绝缘栅型晶体管、第三绝缘栅型晶体管、第四绝缘栅型晶体管、第五绝缘栅型晶体管、第六绝缘栅型晶体管和第七绝缘栅型晶体管，其中，
    所述第七绝缘栅型晶体管的栅极与所述第六绝缘栅型晶体管的栅极相连，所述第七绝缘栅型晶体管的源极分别与所述第二绝缘栅型晶体管的源极、所述第一绝缘栅型晶体管的源极以及所述第六绝缘栅型晶体管的漏极相连，所述第七绝缘栅型晶体管的漏极分别与所述电压缓冲器的输出端及所述第二绝缘栅型晶体管的栅极相连；所述第六绝缘栅型晶体管的源极分别与所述第五绝缘栅型晶体管的源极及电源相连；
    所述第五绝缘栅型晶体管的栅极与所述第五绝缘栅型晶体管的漏极连接后接地；
    所述第一绝缘栅型晶体管的栅极与所述误差放大器的输出端相连，所述第一绝缘栅型晶体管的漏极分别与所述第三绝缘栅型晶体管的漏极及所述第三绝缘栅型晶体管的栅极相连；
    所述第二绝缘栅型晶体管的漏极分别与所述第四绝缘栅型晶体管的漏极及所述电压缓冲器的输出端相连；
    所述第三绝缘栅型晶体管的源极和所述第四绝缘栅型晶体管的源极连接后接地，所述第三绝缘栅型晶体管的栅极和所述第四绝缘栅型晶体管的栅极相连。
  9. 根据权利要求8所述的低压差线性稳压器，所述第六绝缘栅型晶体管的源极与所述第二绝缘栅型晶体管的源极设置为接收所述控制器产生的第一偏置电流，所述第一偏置电流的电流值与所述低压差线性稳压器的输出端的电流值成预设比例关系。
  10. 根据权利要求9所述的低压差线性稳压器，所述控制器包括：第一控制晶体管、第二控制晶体管、第三控制晶体管、第四控制晶体管、第五控制晶体管、第六控制晶体管、第七控制晶体管和第八控制晶体管；
    所述第一控制晶体管、所述第七控制晶体管的源极以及所述第八控制晶体管的源极设置为与所述电源连接，所述第一控制晶体管的栅极与所述功率晶体管的栅极连接，所述第二控制晶体管的源极与所述功率晶体管的漏极连接，所述第一控制晶体管的漏极与所述第三控制晶体管的源极连接，所述第二控制晶体管的栅极与所述第三控制晶体管的栅极连接，所述第二控制晶体管的栅极与所述第二控制晶体管的漏极连接，所述第二控制晶体管的漏极与所述第四控制晶体管的漏极连接，所述第三控制晶体管的漏极与所述第五控制晶体管的漏极连接，所述第四控制晶体管的栅极、所述第五控制晶体管的栅极、以及所述第六控制晶体管的栅极相互连接，所述第四控制晶体管的源极、所述第五控制晶体管的源极以及所述第六控制晶体管的源极接地，所述第五控制晶体管的栅极与所述第五控制晶体管的漏极连接，所述第六控制晶体管的漏极与所述第七控制晶体管的漏极连接，所述第七控制晶体管的栅极与所述第七控制晶体管的漏极连接，所述第七控制晶体管的栅极与所述第八控制晶体管的栅极连接，所述第八晶体管的漏极设置为输出所述第一偏置电流。
  11. 根据权利要求10所述的低压差线性稳压器，所述控制器还包括：多个控制信号生成电路和至少一个第三控制信号晶体管；
    所述控制信号生成电路包括：第一控制信号晶体管、第二控制信号晶体管、第一半导体元件和第二半导体元件；
    所述第一控制信号晶体管的漏极和所述第二控制信号晶体管的源极设置为与所述电源连接，所述第一控制信号晶体管的栅极与所述第六控制晶体管的栅极连接，
    所述第二控制信号晶体管的漏极与所述第一控制信号晶体管的漏极连接，所述第二控制信号晶体管的漏极与所述第一半导体元件的输入端连接，所述第二控制信号晶体管的栅极与所述第一半导体元件的输出端连接，
    所述第一半导体元件的输出端与所述第二半导体元件的输入端连接，所述第二半导体元件的输出端设置为输出所述控制信号；
    任意相邻两个所述控制信号生成电路为第一控制信号生成电路和第二控制信号生成电路；
    所述第一控制信号生成电路中的第二半导体元件的输出端与所述第三控制信号晶体管的栅极连接，所述第三控制信号晶体管的源极设置为与所述电源连接，所述第三控制信号晶体管的漏极与所述第二控制信号生成电路中的所述第 二控制信号晶体管的漏极连接。
  12. 根据权利要求10所述的低压差线性稳压器，所述控制器还包括：第四控制信号晶体管、第五控制信号晶体管、第三半导体元件和第四半导体元件；
    所述第四控制信号晶体管的漏极和所述第五控制信号晶体管的源极设置为与所述电源连接，
    所述第四控制信号晶体管的栅极与所述第六控制晶体管的栅极连接，
    所述第五控制信号晶体管的漏极与所述第四控制信号晶体管的漏极连接，所述第五控制信号晶体管的漏极与所述第三半导体元件的输入端连接，所述第五控制信号晶体管的栅极与所述第三半导体元件的输出端连接，
    所述第三半导体元件的输出端与所述第四半导体元件的输入端连接，所述第四半导体元件的输出端设置为输出所述控制信号。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220187863A1 (en) * 2020-12-15 2022-06-16 Texas Instruments Incorporated Mitigation of transient effects for wide load ranges
CN115469703A (zh) * 2022-10-27 2022-12-13 北京智芯微电子科技有限公司 线性稳压电路、工作方法及电子设备
CN117055671A (zh) * 2023-07-26 2023-11-14 无锡前诺德半导体有限公司 低压差稳压器

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106774578B (zh) * 2017-01-10 2018-02-27 南方科技大学 低压差线性稳压器
CN108491020B (zh) * 2018-06-08 2024-06-07 长江存储科技有限责任公司 低压差稳压器和快闪存储器
US11112812B2 (en) 2018-06-19 2021-09-07 Stmicroelectronics Sa Low-dropout voltage regulation device having compensation circuit to compensate for voltage overshoots and undershoots when changing between activity mode and standby mode
CN108919874B (zh) * 2018-08-30 2023-07-11 北京神经元网络技术有限公司 一种低压差线性稳压器
TWI683200B (zh) * 2018-12-21 2020-01-21 新唐科技股份有限公司 動態偏壓控制系統
CN109375696B (zh) * 2018-12-25 2020-07-21 美芯晟科技（北京）有限公司 一种线性低压差恒流源电路及共源极放大器
CN113014216B (zh) * 2019-12-19 2022-08-16 圣邦微电子（北京）股份有限公司 一种运算放大器
US11397444B2 (en) * 2020-11-19 2022-07-26 Apple Inc. Voltage regulator dropout detection
CN112527041B (zh) * 2020-12-25 2022-04-08 北京集创北方科技股份有限公司 一种低压差线性稳压器电路
US11936373B2 (en) * 2021-06-24 2024-03-19 Cirrus Logic Inc. Pre-conditioning a node of a circuit
CN113568466B (zh) * 2021-09-26 2021-12-10 芯灵通(天津)科技有限公司 一种低压差线性稳压器ldo上电电路
CN114023278B (zh) * 2021-10-28 2022-12-27 深圳市爱协生科技有限公司 一种无外挂电容的驱动Buffer电路及缓冲器
CN113922761B (zh) * 2021-12-14 2022-03-25 深圳市时代速信科技有限公司 一种二级放大电路与电子设备
US11789478B2 (en) * 2022-02-22 2023-10-17 Credo Technology Group Limited Voltage regulator with supply noise cancellation
CN115079760B (zh) * 2022-04-18 2023-07-14 深圳市中科蓝讯科技股份有限公司 一种低压差线性稳压器和芯片
CN114740934B (zh) * 2022-04-29 2024-04-05 北京时代民芯科技有限公司 一种大驱动均衡式ldo电路
CN114578892B (zh) * 2022-05-05 2022-07-29 深圳芯能半导体技术有限公司 一种线性稳压电路
TWI831244B (zh) * 2022-06-15 2024-02-01 瑞昱半導體股份有限公司 低壓差穩壓器及其運作方法
US20230409062A1 (en) * 2022-06-20 2023-12-21 Key Asic Inc. Low dropout regulator
CN117970990A (zh) * 2024-03-29 2024-05-03 华南师范大学 多环路全集成式低压降线性稳压器

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080174289A1 (en) * 2006-11-13 2008-07-24 Decicon, Inc. (A California Corporation) Fast low dropout voltage regulator circuit
CN101369161A (zh) * 2008-10-14 2009-02-18 复旦大学 一种无需片外补偿电容的低压差线性稳压器
CN102707754A (zh) * 2012-05-30 2012-10-03 昆山锐芯微电子有限公司 低压差线性稳压电路
CN104407662A (zh) * 2014-11-21 2015-03-11 电子科技大学 一种轻载瞬态增强电路及集成该电路的低压差线性稳压器
CN105005351A (zh) * 2015-07-23 2015-10-28 中山大学 一种共源共栅全集成低漏失线性稳压器电路
CN106774578A (zh) * 2017-01-10 2017-05-31 南方科技大学 低压差线性稳压器

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6373233B2 (en) * 2000-07-17 2002-04-16 Philips Electronics No. America Corp. Low-dropout voltage regulator with improved stability for all capacitive loads
US6977490B1 (en) * 2002-12-23 2005-12-20 Marvell International Ltd. Compensation for low drop out voltage regulator
US7091710B2 (en) * 2004-05-03 2006-08-15 System General Corp. Low dropout voltage regulator providing adaptive compensation
TWI371671B (en) * 2008-03-19 2012-09-01 Raydium Semiconductor Corp Power management circuit and method of frequency compensation thereof
JP5594980B2 (ja) * 2009-04-03 2014-09-24 ピーエスフォー ルクスコ エスエイアールエル 非反転増幅回路及び半導体集積回路と非反転増幅回路の位相補償方法
TWI413881B (zh) * 2010-08-10 2013-11-01 Novatek Microelectronics Corp 線性穩壓器及其電流感測電路
US8169203B1 (en) * 2010-11-19 2012-05-01 Nxp B.V. Low dropout regulator
KR101857084B1 (ko) * 2011-06-30 2018-05-11 삼성전자주식회사 전원공급모듈, 이를 포함한 전자장치 및 그 전원공급방법
CN102707757B (zh) * 2012-06-05 2014-07-16 电子科技大学 一种动态电荷放电电路以及集成该电路的ldo
US9170590B2 (en) * 2012-10-31 2015-10-27 Qualcomm Incorporated Method and apparatus for load adaptive LDO bias and compensation
US8981745B2 (en) * 2012-11-18 2015-03-17 Qualcomm Incorporated Method and apparatus for bypass mode low dropout (LDO) regulator
US9122292B2 (en) * 2012-12-07 2015-09-01 Sandisk Technologies Inc. LDO/HDO architecture using supplementary current source to improve effective system bandwidth
US9459642B2 (en) * 2013-07-15 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Low dropout regulator and related method
KR102204678B1 (ko) * 2014-12-11 2021-01-20 삼성전자주식회사 인버터 증폭기 기반의 이중 루프 레귤레이터 및 그에 따른 전압 레귤레이팅 방법
CN106055012A (zh) * 2016-07-15 2016-10-26 上海璜域光电科技有限公司 一种提高电源抑制比的高速ldo电路

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080174289A1 (en) * 2006-11-13 2008-07-24 Decicon, Inc. (A California Corporation) Fast low dropout voltage regulator circuit
CN101369161A (zh) * 2008-10-14 2009-02-18 复旦大学 一种无需片外补偿电容的低压差线性稳压器
CN102707754A (zh) * 2012-05-30 2012-10-03 昆山锐芯微电子有限公司 低压差线性稳压电路
CN104407662A (zh) * 2014-11-21 2015-03-11 电子科技大学 一种轻载瞬态增强电路及集成该电路的低压差线性稳压器
CN105005351A (zh) * 2015-07-23 2015-10-28 中山大学 一种共源共栅全集成低漏失线性稳压器电路
CN106774578A (zh) * 2017-01-10 2017-05-31 南方科技大学 低压差线性稳压器

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220187863A1 (en) * 2020-12-15 2022-06-16 Texas Instruments Incorporated Mitigation of transient effects for wide load ranges
US11630472B2 (en) * 2020-12-15 2023-04-18 Texas Instruments Incorporated Mitigation of transient effects for wide load ranges
US11880216B2 (en) 2020-12-15 2024-01-23 Texas Instruments Incorporated Circuit and method for mitigating transient effects in a voltage regulator
CN115469703A (zh) * 2022-10-27 2022-12-13 北京智芯微电子科技有限公司 线性稳压电路、工作方法及电子设备
CN115469703B (zh) * 2022-10-27 2024-05-03 北京智芯微电子科技有限公司 线性稳压电路、工作方法及电子设备
CN117055671A (zh) * 2023-07-26 2023-11-14 无锡前诺德半导体有限公司 低压差稳压器
CN117055671B (zh) * 2023-07-26 2024-03-15 无锡前诺德半导体有限公司 低压差稳压器

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