WO2018120087A1 - 阵列基板及阵列基板制造方法 - Google Patents

阵列基板及阵列基板制造方法 Download PDF

Info

Publication number
WO2018120087A1
WO2018120087A1 PCT/CN2016/113657 CN2016113657W WO2018120087A1 WO 2018120087 A1 WO2018120087 A1 WO 2018120087A1 CN 2016113657 W CN2016113657 W CN 2016113657W WO 2018120087 A1 WO2018120087 A1 WO 2018120087A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
array substrate
protective layer
source
drain
Prior art date
Application number
PCT/CN2016/113657
Other languages
English (en)
French (fr)
Inventor
叶江波
Original Assignee
深圳市柔宇科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to PCT/CN2016/113657 priority Critical patent/WO2018120087A1/zh
Priority to CN201680042773.3A priority patent/CN107996002A/zh
Publication of WO2018120087A1 publication Critical patent/WO2018120087A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to the field of display panel manufacturing technology, and in particular, to an array substrate and an array substrate manufacturing method.
  • the display panel When the light of the display panel is emitted through the backlight panel, not all light can pass through the display panel, such as a signal trace for the panel driver chip, and a TFT (Thin Film Transistor) itself.
  • the conventional pixel electrode and the source are connected in a surface contact manner for conducting current, and the source and the drain are made of an opaque metal material, so when the backlight is illuminated from the back, the pixel electrode and the source are The connection area is reduced in light transmittance due to the opaque metal occlusion affecting the aperture ratio.
  • the present application provides an array substrate, which reduces the light shielding area and increases the aperture ratio.
  • the array substrate of the present application includes a substrate, a TFT switch formed on the substrate, a protective layer covering the substrate and the TFT switch, and a pixel electrode formed on the protective layer, and the TFT switch includes a gate insulation a layer, a channel region on the gate insulating layer, and a source and a drain connected to the channel region, wherein the pixel electrode is connected to the source or the drain through a via, the via Located on one side of the channel region and the via extends through the protective layer and the source or drain.
  • the present application provides a method for fabricating an array substrate, the method comprising:
  • the TFT switch includes a source and a drain
  • the protective layer and the source or the drain are dry etched by using the photoresist layer as a mask to form a via hole penetrating the protective layer and the source or the drain in the first opening region;
  • the photoresist layer is removed, and a pixel electrode layer connected to the source or drain through a via is formed on the protective layer.
  • the method for fabricating an array substrate provided by the present application further includes: forming a peripheral bridge structure on the substrate, and the peripheral bridge structure comprises a double-layer metal stack structure peripheral bridge metal wire;
  • the photoresist layer is removed.
  • the array substrate described in the present application forms a via hole penetrating a source or a drain of a metal material on a side of the TFT switch to connect the pixel electrode to the source or the drain, thereby ensuring current transmission while making the via position transparent.
  • the light zone in turn, increases the aperture ratio of the entire array substrate.
  • 1 is a schematic structural view of an array substrate of the present application.
  • FIG. 2 is a flow chart of a method of manufacturing an array substrate of the present application.
  • FIG. 3 is a flow chart of a method for peripheral bridge structure in the method of fabricating an array substrate of the present application.
  • FIGS. 4 is a flow chart of a specific embodiment of the method for fabricating the array substrate described in FIGS. 2 and 3.
  • FIG. 5 to FIG. 7 are schematic structural views of processes corresponding to the respective steps of the array substrate illustrated in FIG. 4.
  • the array substrate of the embodiment of the present application may be used for, but not limited to, an OLED display or a liquid crystal display, and the display may be flexible or non-flexible, which is not specifically limited in the embodiment of the present application.
  • an array substrate includes a substrate 10 and is formed on the substrate 10 .
  • the TFT switch 12 includes a gate insulating layer 121 and is located at the gate insulating layer 121.
  • the pixel electrode 14 and the source electrode 123 are connected through a via 15 , the via 15 is located at one side of the channel region 122 and the via 15 extends through the protective layer 13 And the source 123.
  • a via hole may be disposed on the drain for connecting the drain and the pixel electrode.
  • the array substrate is a TFT array substrate or an LTPS-TFT (Low Temperature Poly Si Thin Film Transistor) array substrate.
  • the TFT array substrate is connected to the source electrode and the pixel electrode through via holes as an example.
  • the TFT switch 12 further includes a gate 120 covered by the gate insulating layer 121, a semiconductor layer 124 corresponding to the gate 120 on the gate insulating layer 121, the source 123 and the drain A pole 125 connecting the two sides of the semiconductor layer 124 constitutes the channel region 122.
  • the semiconductor layer 124 is made of an amorphous silicon material.
  • the array substrate is an LTPS-TFT array substrate, and the semiconductor layer is made of a polysilicon material.
  • the protective layer 13 at the via location is stacked with the source 123 and the gate insulating layer 121.
  • the via 15 penetrates the insulating layer and exposes the gate insulating layer. Floor.
  • the pixel electrode 14 covers the inner surface of the hole of the via hole 15, that is, the via hole 15 penetrates the protective layer 13 and the source electrode 123, and the inner surface of the hole is the source 123.
  • the pixel electrode 14 is connected to the cross-sectional side surface of the source electrode 123 in the cross section and the cross-sectional side surface of the insulating layer.
  • the via 15 is formed by an etching process. Specifically, after the protective layer 13 is formed, the protective layer 13 and the source 123 are dry etched by a dry etching machine, and the same dry etching is performed in two steps. The protective layer 13 and the source 123 are respectively etched to form a via 15 exposing the gate insulating layer.
  • the array substrate of the present application forms a via hole on the side of the TFT switch to connect the pixel electrode and the source to ensure current transmission, and the via hole penetrates the source 123 of the metal material, so that the position of the via hole 15 is transparent.
  • the area increases the aperture ratio of the entire array substrate. According to the conventional design of the prior art, the area where the pixel electrode is connected to the source is 15%, and then the transparent via is provided here. The increase of the aperture ratio of the array substrate is about 15%, which greatly improves the display of the display screen.
  • the present application provides a method for fabricating an array substrate, the method comprising:
  • Step S1 providing a substrate formed with a TFT switch; wherein the TFT switch includes a source and a drain;
  • Step S2 forming a protective layer covering the substrate and the TFT switch
  • Step S3 forming a photoresist layer having a first opening region on the protective layer, and the first opening region is projected on one side of the source or the drain; in this embodiment, the first opening region is projected onto the substrate Describe one side of the source.
  • Step S4 using a photoresist layer as a mask to dry-etch the protective layer and the source (which may also be a drain, depending on the specific arrangement of the array substrate), to form the protective layer and the source through the first opening region or Via of the drain;
  • a photoresist layer as a mask to dry-etch the protective layer and the source (which may also be a drain, depending on the specific arrangement of the array substrate), to form the protective layer and the source through the first opening region or Via of the drain;
  • step S5 the photoresist layer is removed, and a pixel electrode layer connected to the source through a via is formed on the protective layer.
  • a peripheral bridge structure including a peripheral bridge metal wire is further formed on the substrate.
  • the peripheral bridging structure includes a double-layer metal stack structure peripheral bridging metal line.
  • the method for forming the peripheral bridge structure includes:
  • Step S101 forming a peripheral bridge structure including a peripheral bridge metal line on the substrate;
  • Step S102 forming an insulating layer and a protective layer covering the substrate and the peripheral bridge structure
  • Step S103 forming a photoresist layer having a second opening region on the protective layer, and the second opening region is projected onto the peripheral bridge metal line;
  • Step S104 dry etching the protective layer and the insulating layer with the photoresist layer as a mask to form a gap penetrating the protective layer and the insulating layer in the second opening region;
  • Step S105 removing the photoresist layer.
  • peripheral bridge metal line is formed in the same process as the gate, and the notch and the via are formed in the same process, which will be described below by way of specific embodiments.
  • Step S11 providing a substrate 10 formed with a TFT switch and a peripheral bridge structure; wherein the TFT switch includes a gate electrode 120, a gate insulating layer 121, a channel region, a source electrode 123, and a drain electrode 125.
  • the peripheral bridging structure includes a peripheral bridging metal line layer 150 and an insulating layer covering the peripheral bridging metal line layer 150.
  • the gate electrode 120 and the peripheral bridge metal line 150 are formed in the same process of the same layer, and the gate insulating layer 121 and the insulating layer are in the same layer.
  • step S12 a protective layer 13 of a peripheral bridge metal line 150 covering the peripheral bridge structure of the substrate and the TFT switch is formed.
  • step S13 a photoresist layer 20 having a first opening region 21 and a second opening region 22 is formed on the protective layer 13, and the first opening region 21 is projected onto the source. 123 is away from the side of the drain 125; the second opening region 22 is projected onto the peripheral bridge metal line 150.
  • step S14 dry etching is performed with the photoresist layer 20 as a mask to form a via 15 penetrating the protective layer 13 and the source 123 opposite to the first opening region 21,
  • the second opening region 22 forms a notch 152 exposing the peripheral bridging metal line 150.
  • the protective layer is etched by using the photoresist layer 20 as a mask.
  • the via of this embodiment is opened on the source.
  • dry etching is performed separately by two different gases.
  • it can also be formed by a gas etching.
  • the dry etching is performed by using the two different gases respectively: the same dry etching step is performed on the protective layer by using a first etching gas to form a first hole and a first notch, and the first hole and the first notch respectively correspond to the a first opening region and a second opening region; then converting into a second etching gas to continue etching on the source to form a second hole, since the insulating layer covering the peripheral bridge metal line 150 is on the same layer as the source 123 a second notch is formed on the insulating layer, and the first hole and the second hole communicate with each other to form the via hole, and the first notch and the second notch form the notch.
  • the first etching gas is a mixture of carbon tetrafluoride (CF4) and oxygen.
  • the second etching gas is a mixture of sulfur hexafluoride
  • the preset byproduct concentration range value is further included;
  • the by-product concentration value generated by the etching is detected by the carbon tetrafluoride when the via and the notch are etched; when the by-product concentration value generated by the etching is within the preset by-product concentration range value, the etching is stopped.
  • the by-product concentration value generated by the etching includes a by-product concentration value generated by the etching source and a by-product concentration value generated when the peripheral bridges the metal line.
  • a concentration of by-products generated by etching having a first concentration range is generated, and when the source is etched and not broken, the first concentration range is increased.
  • the two concentration ranges until the source is broken down to a second concentration range to a predetermined byproduct concentration value is generated.
  • the etching is stopped to avoid excessive etching of the peripheral bridge metal line 150.
  • the gate and peripheral bridge metal lines 150 are a two-layer metal stack structure, wherein a top metal etch rate of the gate is less than a bottom metal, and in fact, the gate 120 and the peripheral bridge metal line 150 are through metal molybdenum and A two-layer aluminum layer is formed in which the metal molybdenum is located on the surface layer of aluminum, and the non-metal is faster than the metal due to etching.
  • the top portion of the peripheral bridge metal line 150 has begun to have a loss of by-product concentration, and the effect of setting the two layers is to slow down.
  • the peripheral bridge wire is etched, and the by-product concentration range value is detected in order to stop the etching in time to prevent the peripheral bridge wire 150 from being broken down.
  • step S15 the photoresist layer 20 is removed, and a pixel electrode layer 14 is formed on the protective layer 13, and the pixel electrode 14 is connected to the source electrode 123 through a via 15.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板，包括基板（10）、形成于所述基板（10）上的TFT开关（12）、覆盖所述基板（10）及TFT开关（12）的保护层（13）及形成于所述保护层（13）的像素电极（14），所述TFT开关（12）包括栅极绝缘层（121）、位于所述栅极绝缘层（121）上的沟道区（122）及连接所述沟道区（122）的源极（123）和漏极（125），所述像素电极（14）与所述源极（123）或漏极（125）通过一过孔（15）连接，所述过孔（15）位于所述沟道区（122）的一侧并且所述过孔（15）贯穿所述保护层（13）及所述源极（123）或漏极（125）；以及一种阵列基板制造方法。

Description

阵列基板及阵列基板制造方法 技术领域
本发明涉及显示面板制造技术领域，尤其涉及一种阵列基板、阵列基板制造方法。
背景技术
显示面板的光线经由背光板发射出来时，并不是所有的光线都能穿过显示面板，比如面板驱动芯片用的信号走线，以及TFT(Thin Film Transistor，薄膜晶体管)本身等。传统的像素电极与源极连接采用的是面接触的方式进行电流的传导，因源极和漏极采用的是不透光金属材料制成，故当背光从后面照射时，像素电极与源极连接区域因不透光金属遮挡影响开口率而造成光穿透率的降低。
发明内容
基于上述问题，本申请提供一种阵列基板，减小遮光区提高开口率。
本申请所述的阵列基板，包括基板、形成于所述基板上的TFT开关、覆盖所述基板及TFT开关的保护层及形成于所述保护层的像素电极，所述TFT开关包括栅极绝缘层、位于所述栅极绝缘层上的沟道区及连接所述沟道区的源极和漏极，所述像素电极与所述源极或漏极通过一过孔连接，所述过孔位于所述沟道区的一侧并且所述过孔贯穿所述保护层及所述源极或漏极。
本申请提供一种阵列基板制造方法，所述方法包括：
提供形成有TFT开关的基板；其中，TFT开关包括源极和漏极；
形成覆盖所述基板及TFT开关的保护层；
在保护层上形成一具有第一开口区域的光阻层，且第一开口区域正投影于所述源极或漏极的一侧；
以光阻层为掩膜板进行干蚀刻所述保护层及源极或漏极，以在第一开口区域形成贯穿所述保护层及源极或漏极的过孔；
去除所述光阻层，并在所述保护层上形成通过过孔与所述源极或漏极连接的像素电极层。
本申请提供的阵列基板制造方法，还包括：在所述基板上形成***桥接结构，***桥接结构包括双层金属堆叠结构***桥接金属线；
形成覆盖所述基板及***桥接结构的绝缘层及保护层；
在保护层上形成一具有第二开口区域的光阻层，且第二开口区域正投影于所述***桥接金属线；
以光阻层为掩膜板进行干蚀刻所述保护层及绝缘层，以在第二开口区域形成贯穿所述保护层及绝缘层的缺口；
去除所述光阻层。
本申请所述的阵列基板在TFT开关一侧形成贯穿了金属材质的源极或漏极的过孔来连接像素电极与源极或漏极，保证电流传输的同时，以使过孔位置为透光区，进而增加了整个阵列基板的开口率。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请的阵列基板的结构示意图。
图2是本申请的阵列基板制造方法流程图。
图3是本申请的阵列基板制造方法中***桥接结构方法流程图。
图4是图2与图3所述的阵列基板制造方法的具体实施方式流程图。
图5-图7是图4所述的阵列基板的对应各个步骤工艺的结构示意图。
具体实施方式
下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行清楚、完整地描述。
本申请实施例涉及的阵列基板可以用于但不限于OLED显示屏或者液晶显示屏中，且显示屏可以是柔性的也可以是非柔性的，本申请实施例对此不作具体限定。
请参阅图1，本申请所述的阵列基板，包括基板10、形成于所述基板10 上的TFT开关12、覆盖所述基板及TFT开关的保护层13及形成于所述保护层13的像素电极14，所述TFT开关12包括栅极绝缘层121、位于所述栅极绝缘层121上的沟道区122及连接所述沟道区的源极123及漏极125。本实施例中，所述像素电极14与所述源极123通过一过孔15连接，所述过孔15位于所述沟道区122的一侧并且所述过孔15贯穿所述保护层13及所述源极123。可以理解的是，根据阵列基板的性能选择及设计需求，也可以是漏极上设置过孔用来连接漏极与像素电极。
所述阵列基板为TFT阵列基板或者LTPS-TFT(Low Temperature Poly Si Thin Film Transistor，低温多晶硅薄膜晶体管)阵列基板。本实施例中，以TFT阵列基板通过过孔连接源极与像素电极为例进行说明。
所述TFT开关12还包括被所述栅极绝缘层121覆盖的栅极120、位于栅极绝缘层121上的与所述栅极120对应的半导体层124，所述源极123与所述漏极125连接所述半导体层124两侧构成所述沟道区122。本实施例中，所述半导体层124为非晶硅材料制成。在其他实施例中，阵列基板为LTPS-TFT阵列基板，所述半导体层为多晶硅材料制成。
进一步的需要说明的，位于所述过孔位置的所述保护层13与所述源极123、栅极绝缘层121层叠设置，所述过孔15贯穿所述绝缘层并露出所述栅极绝缘层。
优选的，所述像素电极14覆盖所述过孔15的孔内侧表面，也就是说，所述过孔15贯穿了所述保护层13及源极123，那么孔的内侧表面就是源极123的截面及绝缘层的截面侧面，所述像素电极14通过与源极123的截面侧面连接。
进一步的，所述过孔15通过一道蚀刻工艺形成，具体的，在形成所述保护层13之后，通过干蚀机对保护层13及源极123进行干蚀刻，同一道干蚀刻分两步来分别蚀刻所述保护层13及源极123，进而形成露出所述栅极绝缘层的过孔15。
本申请所述的阵列基板在TFT开关一侧形成过孔，来连接像素电极与源极，保证电流传输的同时，过孔贯穿了金属材质的源极123，以使过孔15位置为透光区，进而增加了整个阵列基板的开口率。根据现有技术的常规设计，该像素电极与源极连接的区域占用面积为15％，那么此处设置透光的过孔，那 么增加了阵列基板开口率大概为15％，这对显示屏的显示有大幅度的提高。
请参阅图2，本申请提供一种阵列基板制造方法，所述方法包括：
步骤S1，提供形成有TFT开关的基板；其中，TFT开关包括源极和漏极；
步骤S2，形成覆盖所述基板及TFT开关的保护层；
步骤S3，在保护层上形成一具有第一开口区域的光阻层，且第一开口区域正投影于所述源极或漏极的一侧；本实施例中第一开口区域正投影于所述源极的一侧。
步骤S4，以光阻层为掩膜板干蚀刻保护层及源极(也可以是漏极，根据阵列基板具体设置而定)，以在第一开口区域形成贯穿所述保护层及源极或者漏极的过孔；
步骤S5，去除所述光阻层，并在所述保护层上形成通过过孔与所述源极连接的像素电极层。
本实施例中，所述基板上还形成有包括有***桥接金属线的***桥接结构。***桥接结构包括双层金属堆叠结构***桥接金属线。
请参照图3，所述***桥接结构的形成方法包括：
步骤S101，在所述基板上还形成包括有***桥接金属线的***桥接结构；
步骤S102，形成覆盖所述基板及***桥接结构的绝缘层及保护层；
步骤S103，在保护层上形成一具有第二开口区域的光阻层，且第二开口区域正投影于所述***桥接金属线；
步骤S104，以光阻层为掩膜板进行干蚀刻所述保护层及绝缘层，以在第二开口区域形成贯穿所述保护层及绝缘层的缺口；
步骤S105，去除所述光阻层。
实际上，所述***桥接金属线与所述栅极同一制程形成，所述缺口与过孔是同一制程形成，下面以具体实施例进行说明，
请参照图4，以源极上设置过孔为例进行说明。步骤S11，提供形成有TFT开关及***桥接结构的基板10；其中，TFT开关包括栅极120、栅极绝缘层121、沟道区及源极123及漏极125。所述***桥接结构包括***桥接金属线层150及覆盖***桥接金属线层150的绝缘层。所述栅极120和***桥接金属线150为同一层的同一道制程形成，栅极绝缘层121与绝缘层为同一层。
如图5，步骤S12，形成覆盖所述基板及TFT开关的***桥接结构的***桥接金属线150的保护层13。
一并参阅图5与图6，步骤S13，在保护层13上形成一具有第一开口区域21及第二开口区域22的光阻层20，且第一开口区域21正投影于所述源极123远离漏极125的一侧；第二开口区域22正投影于所述***桥接金属线150。
一并参阅图6与图7，步骤S14，以光阻层20为掩膜板干蚀刻，以形成贯穿所述保护层13及源极123的与第一开口区域21相对的过孔15，在第二开口区域22形成露出***桥接金属线150的缺口152，本步骤是以光阻层20为掩膜板对保护层蚀刻。本实施例的过孔是开在所述源极上的。
本步骤中，干蚀刻是通过两种不同气体分别进行。当然在其他实施例中，也可以通过一种气体蚀刻形成。具体的，所述使用两种不同气体分别干蚀刻包括：同一干蚀刻步骤使用第一蚀刻气体在所述保护层上蚀刻形成第一孔及第一缺口，第一孔及第一缺口分别对应所述第一开口区域及第二开口区域；然后转换成第二蚀刻气体在所述源极上继续蚀刻形成第二孔，由于覆盖***桥接金属线150的绝缘层与所述源极123在同一层，所述绝缘层上形成第二缺口，第一孔与第二孔连通形成所述过孔，第一缺口与第二缺口形成所述缺口。所述第一蚀刻气体为四氟化碳(CF4)与氧气的混合体。所述第二蚀刻气体为六氟化硫与氧气的混合体。
所以在以光阻层20为掩膜板干蚀刻的实际蚀刻过程中还包括，预设副产物浓度范围值；
在蚀刻所述过孔及缺口时通过四氟化碳检测蚀刻生成的副产物浓度值；当蚀刻生成的副产物浓度值在所述预设的副产物浓度范围值内时，停止蚀刻。
其中，所述蚀刻生成的副产物浓度值包括蚀刻源极生成的副产物浓度值以及***桥接金属线时生成的副产物浓度值。
具体的，所述保护层及绝缘层被蚀刻时，会产生具有第一浓度范围的蚀刻生成的副产物浓度，在所述源极被蚀刻且未击穿的时候，第一浓度范围上升是第二浓度范围，直到所述源极被击穿第二浓度范围下降到所述的预设的副产物浓度值。
当蚀刻生成的副产物浓度值在所述预设的副产物浓度范围值内时，停止蚀刻，避免过多的蚀刻所述***桥接金属线150。
所述栅极及***桥接金属线150为双层金属堆叠结构，其中所述栅极的顶层金属刻蚀速率小于底层金属，实际上所述栅极120及***桥接金属线150是通过金属钼和铝两层层叠设置形成，其中金属钼位于铝的表层，由于刻蚀的时候非金属的速度要快于金属。在刻蚀源极123形成过孔的过程中时候，在源极123还未被完全击穿时，***桥接金属线150的顶层部分已经开始有损耗产生副产物浓度，设置两层的作用就是减缓***桥接金属线的刻蚀，而检测副产物浓度范围值及是为了能及时停止蚀刻，防止***桥接金属线150被击穿。
复参阅图1，步骤S15，去除所述光阻层20，并在所述保护层13上形成像素电极层14，所述像素电极成14通过过孔15与所述源极123连接。
以上所述是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本申请的保护范围。

Claims (15)

  1. 一种阵列基板，其特征在于，包括基板、形成于所述基板上的TFT开关、覆盖所述基板及TFT开关的保护层及形成于所述保护层的像素电极，所述TFT开关包括栅极绝缘层、位于所述栅极绝缘层上的沟道区及连接所述沟道区的源极和漏极，所述像素电极与所述源极或漏极通过一过孔连接，所述过孔位于所述沟道区的一侧并且所述过孔贯穿所述保护层及所述源极或漏极。
  2. 如权利要求1所述的阵列基板，其特征在于，所述像素电极覆盖所述过孔的孔内侧表面。
  3. 如权利要求1所述的阵列基板，其特征在于，所述TFT开关还包括被所述栅极绝缘层覆盖的栅极、位于栅极绝缘层上的与所述栅极对应的半导体层，所述源极及漏极连接所述半导体层两侧构成所述沟道区。
  4. 如权利要求3所述的阵列基板，其特征在于，所述半导体层为多晶硅材料、非晶硅材料、金属氧化物中的一种制成。
  5. 如权利要求1所述的阵列基板，其特征在于，所述保护层通过所述过孔覆盖所述栅极绝缘层。
  6. 如权利要求1所述的阵列基板，其特征在于，所述像素电极、保护层和栅极绝缘层为透明材料制成。
  7. 如权利要求1所述的阵列基板，其特征在于，所述阵列基板还包括形成于所述基板上的***桥接结构，所述***桥接结构包括***桥接金属线，所述栅极绝缘层和所述保护层覆盖所述***桥接金属线。
  8. 如权利要求7所述的阵列基板，其特征在于，所述***桥接金属线为双层金属堆叠结构，其中所述***桥接金属线的顶层金属刻蚀速率小于底层金属。
  9. 如权利要求8所述的阵列基板，其特征在于，所述栅极为双层金属堆叠结构，所述栅极和***桥接金属线通过同一道制程形成。
  10. 一种阵列基板制造方法，其特征在于，所述方法包括：
    提供形成有TFT开关的基板，其中，TFT开关包括源极和漏极；
    形成覆盖所述基板及TFT开关的保护层；
    在保护层上形成一具有第一开口区域的光阻层，且第一开口区域正投影于所述源极或漏极的一侧；
    以光阻层为掩膜板进行干蚀刻所述保护层及源极或漏极，以在第一开口区域形成贯穿所述保护层及源极或漏极的过孔；
    去除所述光阻层，并在所述保护层上形成通过过孔与所述源极或漏极连接的像素电极层。
  11. 如权利要求10所述的阵列基板制造方法，其特征在于，还包括：
    在所述基板上形成***桥接结构，***桥接结构包括双层金属堆叠结构***桥接金属线；
    形成覆盖所述基板及***桥接结构的绝缘层及保护层；
    在保护层上形成一具有第二开口区域的光阻层，且第二开口区域正投影于所述***桥接金属线；
    以光阻层为掩膜板进行干蚀刻所述保护层及绝缘层，以在第二开口区域形成贯穿所述保护层及绝缘层的缺口；
    去除所述光阻层。
  12. 如权利要求11所述的阵列基板制造方法，其特征在于，所述***桥接金属线与所述TFT开关的的栅极在同一制程形成；
    设有所述第二开口区域的光阻层与设有第一开口区域的光阻层为同一光阻层，并且所述第二开口区域与所述第一开口区域为同一制程形成；
    所述缺口与所述过孔在同一制程形成。
  13. 如权利要求12所述的阵列基板制造方法，其特征在于，所述以光阻层为掩膜板进行干蚀刻包括：使用第一蚀刻气体在所述保护层上蚀刻形成第一孔及第一缺口，然后转换成第二蚀刻气体在所述源极上继续蚀刻形成第二孔，在栅极绝缘层上形成第二缺口，第一孔与第二孔连通形成所述过孔，第一缺口与第二缺口形成所述缺口。
  14. 如权利要求13所述的阵列基板制造方法，其特征在于，所述***桥接金属线为双层金属堆叠结构，其中所述***桥接金属线的顶层金属刻蚀速率小于底层金属；所述栅极为双层金属堆叠结构，其中所述栅极的顶层金属刻蚀速率小于底层金属，栅极和***桥接金属线为同一道制程形成。
  15. 如权利要求14所述的阵列基板制造方法，其特征在于，所述方法还包括，预设副产物浓度范围值；
    在蚀刻所述过孔及缺口时检测蚀刻生成的副产物浓度值；当蚀刻生成的副 产物浓度值在所述预设副产物浓度范围值内时，停止蚀刻。
PCT/CN2016/113657 2016-12-30 2016-12-30 阵列基板及阵列基板制造方法 WO2018120087A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2016/113657 WO2018120087A1 (zh) 2016-12-30 2016-12-30 阵列基板及阵列基板制造方法
CN201680042773.3A CN107996002A (zh) 2016-12-30 2016-12-30 阵列基板及阵列基板制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/113657 WO2018120087A1 (zh) 2016-12-30 2016-12-30 阵列基板及阵列基板制造方法

Publications (1)

Publication Number Publication Date
WO2018120087A1 true WO2018120087A1 (zh) 2018-07-05

Family

ID=62028857

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/113657 WO2018120087A1 (zh) 2016-12-30 2016-12-30 阵列基板及阵列基板制造方法

Country Status (2)

Country Link
CN (1) CN107996002A (zh)
WO (1) WO2018120087A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109616496B (zh) * 2018-11-15 2020-08-11 武汉华星光电半导体显示技术有限公司 Oled触控显示屏的制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003152188A (ja) * 2001-11-14 2003-05-23 Casio Comput Co Ltd 薄膜トランジスタパネル
US20060054889A1 (en) * 2004-09-16 2006-03-16 Jang-Soo Kim Thin film transistor array panel
CN101276840A (zh) * 2007-03-26 2008-10-01 株式会社半导体能源研究所 半导体装置及其制造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101121620B1 (ko) * 2004-06-05 2012-02-28 엘지디스플레이 주식회사 표시 소자용 박막 트랜지스터 기판 및 그 제조 방법
KR101107682B1 (ko) * 2004-12-31 2012-01-25 엘지디스플레이 주식회사 표시 소자용 박막 트랜지스터 기판 및 그 제조 방법
KR20070081016A (ko) * 2006-02-09 2007-08-14 삼성전자주식회사 박막 트랜지스터 표시판 및 그 제조 방법
CN101556415B (zh) * 2008-04-10 2011-05-11 北京京东方光电科技有限公司 像素结构及其制备方法
JP5923326B2 (ja) * 2012-02-08 2016-05-24 株式会社ジャパンディスプレイ 回路基板およびその製造方法、ならびに電気光学装置
CN103824862B (zh) * 2012-11-16 2016-12-07 群康科技(深圳)有限公司 薄膜晶体管基板与显示器
CN104733384B (zh) * 2013-08-22 2018-03-23 合肥京东方光电科技有限公司 显示基板及其制造方法、显示装置
CN103456740B (zh) * 2013-08-22 2016-02-24 京东方科技集团股份有限公司 像素单元及其制造方法、阵列基板和显示装置
KR102284754B1 (ko) * 2014-10-27 2021-08-03 삼성디스플레이 주식회사 박막 트랜지스터 어레이 기판, 및 이를 포함하는 유기 발광 표시 장치
CN104600030B (zh) * 2015-02-02 2017-08-29 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN106033765B (zh) * 2015-03-17 2019-06-11 上海和辉光电有限公司 有机发光二极管触控显示面板
CN104966719A (zh) * 2015-06-29 2015-10-07 武汉华星光电技术有限公司 显示面板、薄膜晶体管阵列基板及其制作方法
CN105070684B (zh) * 2015-07-17 2018-01-05 京东方科技集团股份有限公司 阵列基板的制备方法、阵列基板及显示装置
CN105652541B (zh) * 2016-01-20 2018-11-23 深圳市华星光电技术有限公司 阵列基板的制作方法及液晶显示面板

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003152188A (ja) * 2001-11-14 2003-05-23 Casio Comput Co Ltd 薄膜トランジスタパネル
US20060054889A1 (en) * 2004-09-16 2006-03-16 Jang-Soo Kim Thin film transistor array panel
CN101276840A (zh) * 2007-03-26 2008-10-01 株式会社半导体能源研究所 半导体装置及其制造方法

Also Published As

Publication number Publication date
CN107996002A (zh) 2018-05-04

Similar Documents

Publication Publication Date Title
JP4885968B2 (ja) アクティブマトリクス基板およびそれを備えた液晶表示装置
WO2017054384A1 (zh) 一种阵列基板及其制作方法、显示面板
US9904132B2 (en) Liquid crystal display panel, array substrate and manufacturing method for the same
US6555409B2 (en) Method for fabricating a thin film transistor array substrate for liquid crystal display
TWI653747B (zh) 陣列基板及其製造方法
US10879339B2 (en) Display panel having pad disposed on bottom surface of substrate and manufacturing method thereof
JP6526215B2 (ja) 半導体装置およびその製造方法
US20160197191A1 (en) Array Substrate, Method for Fabricating the Same and Display Device
US20240049539A1 (en) Display substrate, method for fabricating the same, and display panel
US9761615B2 (en) Array substrate, manufacturing method thereof and display device
US9837449B2 (en) Display device with contact between an electrode of a thin film transistor and a pixel electrode
US20210408062A1 (en) Tft array substrate and manufacturing method thereof
US9425270B2 (en) Array substrate structure and contact structure
US8557621B2 (en) Method for manufacturing thin film transistor array panel
US8912552B2 (en) Display substrate and method of manufacturing the same
US9653608B2 (en) Array substrate and manufacturing method thereof, display device and thin film transistor
WO2018120087A1 (zh) 阵列基板及阵列基板制造方法
TW201322340A (zh) 畫素結構及其製作方法
WO2018058522A1 (zh) 薄膜晶体管制造方法及阵列基板
WO2021248609A1 (zh) 一种阵列基板及其制备方法以及显示面板
WO2017024755A1 (zh) 阵列基板及其制造方法、显示面板和显示装置
US20150372024A1 (en) Array substrate, manufacturing method thereof and display device
KR20120094575A (ko) 표시 기판 및 이의 제조 방법
TWI460515B (zh) 一種邊緣電場型液晶顯示器陣列基板及其製造方法
WO2018000967A1 (zh) 阵列基板及其制备方法、显示器件

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16925173

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 24/10/2019)

122 Ep: pct application non-entry in european phase

Ref document number: 16925173

Country of ref document: EP

Kind code of ref document: A1