WO2021248609A1 - 一种阵列基板及其制备方法以及显示面板 - Google Patents

一种阵列基板及其制备方法以及显示面板 Download PDF

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Publication number
WO2021248609A1
WO2021248609A1 PCT/CN2020/101098 CN2020101098W WO2021248609A1 WO 2021248609 A1 WO2021248609 A1 WO 2021248609A1 CN 2020101098 W CN2020101098 W CN 2020101098W WO 2021248609 A1 WO2021248609 A1 WO 2021248609A1
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Prior art keywords
layer
metal contact
gate
array substrate
drain
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PCT/CN2020/101098
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English (en)
French (fr)
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张鹏
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/963,369 priority Critical patent/US11894386B2/en
Publication of WO2021248609A1 publication Critical patent/WO2021248609A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78639—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a drain or source connected to a bulk conducting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the present application relates to the field of display technology, and in particular to an array substrate, a preparation method thereof, and a display panel.
  • TFT Thin Film Transistor
  • a-Si Amorphous Silicon
  • IGZO Indium Gallium Zinc Oxide, indium gallium zinc oxide
  • Using IGZO as the channel material in the TFT device can improve the resolution of the display panel.
  • top grid (Top Gate) structure of oxide semiconductor TFT devices usually after the gate layer and gate insulating layer are etched, helium plasma is used to conduct conductorization of the IGZO area not covered by the gate layer to ensure the source and drain Good ohmic contact between layer and semiconductor layer. Afterwards, the source and drain layers are fabricated to form TFT devices.
  • a long-term thermal annealing process will increase the resistance of the IGZO conductorized area, and affect the conductorization effect, thereby deteriorating the electrical properties of the TFT device or even failing.
  • the present application provides an array substrate, a preparation method thereof, and a display panel, so as to alleviate the technical problem of the large resistance of the IGZO conductive area in the existing TFT device.
  • An embodiment of the present application provides an array substrate, which includes an active layer, a metal contact layer, a gate insulating layer, a gate layer, a source and drain layer, and a pixel electrode that are sequentially laminated and prepared on a substrate.
  • the active layer is disposed on the substrate and includes a channel region.
  • the metal contact layer is disposed on the active layer and includes a conductor area and an insulating area, the insulating area corresponds to the channel area, and the conductor area is disposed on both sides of the insulating area.
  • the gate insulating layer is disposed above the metal contact layer.
  • the gate layer is disposed above the gate insulating layer, the gate layer includes a gate, and the gate is located relatively above the channel region.
  • the source and drain layer is disposed above the conductor region, and the source and drain layer includes a source electrode and a drain electrode.
  • the pixel electrode is disposed above the source and drain layer, and is connected to the source electrode or the drain electrode. Wherein, the source electrode and the drain electrode are respectively connected to the conductor area.
  • the array substrate further includes a light-shielding layer, and the light-shielding layer is disposed on the substrate and located below the active layer.
  • the width of the active layer is smaller than the width of the light shielding layer.
  • the material of the active layer includes one of indium gallium zinc oxide, indium zinc tin oxide, and indium gallium zinc tin oxide.
  • the material of the light shielding layer includes one or an alloy of aluminum, copper, molybdenum, and titanium.
  • the material of the metal contact layer includes one or an alloy of aluminum, copper, molybdenum, and others.
  • the thickness of the metal contact layer ranges from 50 angstroms to 200 angstroms.
  • the pattern size of the gate insulating layer is the same as the pattern size of the gate.
  • the array substrate further includes an interlayer insulating layer disposed between the gate electrode layer and the source drain layer, and an interlayer insulating layer disposed between the source drain layer and the source drain layer.
  • the embodiment of the present application provides a method for preparing an array substrate, which includes the following steps: step S10, a substrate is provided, an active layer and a metal contact layer are sequentially prepared on the substrate, and a photomask is used for the active layer.
  • the layer and the metal contact layer are subjected to a yellowing process, and a part of the metal contact layer is oxidized, so that the metal contact layer forms a conductor region and an insulating region to define a channel region of the active layer.
  • Step S20 preparing a gate insulating layer on the metal contact layer, preparing a gate layer on the gate insulating layer, and performing a yellowing process on the gate layer and the gate insulating layer to form a gate .
  • Step S30 preparing an interlayer insulating layer on the gate layer, preparing a source and drain layer on the interlayer insulating layer, and performing a yellowing process on the source and drain layer to form a source electrode and a drain electrode.
  • the source electrode and the drain electrode are respectively connected to the conductor region.
  • preparing the active layer and the metal contact layer includes the following steps: preparing a light-shielding layer on the substrate, and on the light-shielding layer A buffer layer is prepared, and the active layer is prepared on the buffer layer.
  • a metal film is deposited on the active layer as a metal contact layer, a photoresist is coated on the metal contact layer, and the photoresist is exposed and developed using a halftone mask photomask to form a photoresist pattern.
  • the photoresist pattern as a shield, the metal contact layer and the active layer are etched to remove the metal contact layer and the active layer that are not shielded by the photoresist pattern.
  • Ashing is performed on the photoresist pattern, so that the two sides of the photoresist pattern are thinned, and the middle part is removed to expose a part of the metal contact layer.
  • the thinned photoresist pattern as a shield, the exposed metal contact layer is oxidized to form an insulating region. The thinned photoresist pattern is peeled off.
  • the width of the active layer is smaller than the width of the light shielding layer.
  • the material of the metal contact layer includes one or an alloy of aluminum, copper, molybdenum, and titanium.
  • the thickness of the metal contact layer ranges from 50 angstroms to 200 angstroms.
  • the thickness of the two side portions of the photoresist pattern is greater than the thickness of the middle portion.
  • step S20 the gate electrode is formed by a photoresist stripping process.
  • the method further includes the following steps: step S40, sequentially preparing a passivation layer and a planarization layer on the source and drain layers and the interlayer insulating layer, and A pixel electrode is prepared on the planarization layer, and the pixel electrode is connected to the source electrode or the drain electrode.
  • An embodiment of the present application provides a display panel, which includes an array substrate including an active layer, a metal contact layer, a gate insulating layer, a gate layer, a source and drain layer, which are sequentially laminated and prepared on a substrate. And pixel electrodes.
  • the active layer is disposed on the substrate and includes a channel region.
  • the metal contact layer is disposed on the active layer and includes a conductor area and an insulating area, the insulating area corresponds to the channel area, and the conductor area is disposed on both sides of the insulating area.
  • the gate insulating layer is disposed above the metal contact layer.
  • the gate layer is disposed above the gate insulating layer, the gate layer includes a gate, and the gate is located relatively above the channel region.
  • the source and drain layer is disposed above the conductor region, and the source and drain layer includes a source electrode and a drain electrode.
  • the pixel electrode is disposed above the source and drain layer, and is connected to the source electrode or the drain electrode. Wherein, the source electrode and the drain electrode are respectively connected to the conductor area.
  • the array substrate further includes a light-shielding layer, and the light-shielding layer is disposed on the substrate and located below the active layer.
  • the width of the active layer is smaller than the width of the light shielding layer.
  • a metal contact layer is prepared on the active layer, and the conductor area of the metal contact layer has better conductivity and stability, and serves as the subsequent source, drain, and active electrode.
  • the layer-connected bridge solves the problem of the large resistance of the IGZO conductorization area in the existing TFT device, thereby effectively avoiding the deterioration of the performance of the TFT device due to the weakening or failure of the conductorization.
  • the active layer and the metal contact layer are deposited at the same time, which can better protect the channel region of the active layer.
  • the insulating region formed after the metal contact layer corresponding to the channel region is oxidized can be used as a part of the gate insulating layer, which can better protect the active layer and make the performance of the TFT device more stable.
  • FIG. 1 is a schematic side view of a film structure of an array substrate provided by an embodiment of the application.
  • FIG. 2 is a schematic flowchart of a method for manufacturing an array substrate provided by an embodiment of the application.
  • 3 to 9 are schematic side views of the film structure produced in each step of the method for manufacturing the array substrate provided by the embodiments of the application.
  • FIG. 10 is a schematic side view of the first display panel provided by an embodiment of the application.
  • FIG. 11 is a schematic side view of a second type of display panel provided by an embodiment of the application.
  • an array substrate 100 is provided, as shown in FIG. 1, which includes an active layer 40, a metal contact layer 50, a gate insulating layer 11, and a gate layer which are sequentially laminated and prepared on a substrate 10. 60.
  • the active layer 40 is disposed on the substrate 10 and includes a channel region 41.
  • the metal contact layer 50 is disposed on the active layer 40, and includes a conductor region 52 and an insulating region 51.
  • the insulating region 51 corresponds to the channel region 41, and the conductor region 52 is disposed on the insulating region. 51 on both sides.
  • the gate insulating layer 11 is disposed above the metal contact layer 50.
  • the gate layer 60 is disposed above the gate insulating layer 11, and the gate layer 60 includes a gate 61, and the gate 61 is located relatively above the channel region 41.
  • the source-drain layer 70 is disposed above the conductor region 52, and the source-drain layer 70 includes a source 72 and a drain 71.
  • the pixel electrode 80 is disposed above the source and drain layer 70 and is connected to the source 72 or the drain 71. As shown in FIG. 1, the pixel electrode 80 is connected to the source 72. Wherein, the source 72 and the drain 71 are connected to the conductor region 52 respectively.
  • the substrate 10 includes a flexible substrate such as a glass substrate or polyimide.
  • the array substrate 100 further includes a light-shielding layer 20, and the light-shielding layer 20 is disposed on the substrate 10 and located below the active layer 40.
  • a buffer layer 30 is further provided between the active layer 40 and the light shielding layer 20.
  • the material of the light-shielding layer 20 includes metals such as aluminum, copper, molybdenum, titanium, or alloys thereof, or other light-shielding materials.
  • the width of the active layer 40 is smaller than the width of the light shielding layer 20.
  • the material of the active layer 40 includes one of metal oxide semiconductors such as indium gallium zinc oxide, indium zinc tin oxide, and indium gallium zinc tin oxide.
  • the metal contact layer 50 and the active layer 40 use the same photomask to perform the yellow light etching process.
  • the metal contact layer 50 and the active layer 40 are formed to have the same pattern size.
  • the middle part of the metal contact layer 50 after the yellow light etching process is oxidized, so that the metal contact layer 50 forms a conductor region 52 and an insulating region 51 to define the channel region 41 of the active layer 40 The aspect ratio.
  • the portions on both sides that have not been oxidized are used as the conductor regions 52 of the metal contact layer 50 to be connected to the source 72 and the drain 71 of the source and drain layer 70.
  • a metal oxide insulating region 51 is formed.
  • the insulating region 51 can be used as a part of the gate insulating layer 11 to better protect the active layer 40.
  • the gate insulating layer 11 and the gate layer 60 are subjected to a yellow light etching process through the same photomask to form a gate 61 and signal wiring (not shown).
  • the pattern size of the gate insulating layer 11 after etching is the same as that of the gate electrode 61.
  • the material of the metal contact layer 50 includes metals such as aluminum, copper, molybdenum, titanium, or their alloys.
  • the thickness of the metal contact layer 50 ranges from 50 angstroms to 200 angstroms.
  • the source 72 or the drain 71 of the source and drain layer 70 is connected to the conductor region 52 of the metal contact layer 50, and the conductor region 52 of the metal contact layer 50 is electrically conductive compared to the conductive active layer. With better performance and stability, it can effectively avoid the deterioration of TFT device performance caused by weakening or failure of conductors.
  • the materials of the gate layer 60 and the source and drain layer 70 both include metals such as aluminum, copper, molybdenum, titanium, or their alloys, or their laminated structures.
  • a plurality of insulating layers are provided between the gate layer 60, the source and drain layers 70, and the pixel electrode 80.
  • the plurality of insulating layers includes an interlayer insulating layer 12, a passivation layer 13 and a planarization layer 14.
  • the interlayer insulating layer 12 is located between the gate layer 60 and the source drain layer 70.
  • the passivation layer 13 and the planarization layer 14 are located between the source and drain layer 70 and the pixel electrode 80.
  • the interlayer insulating layer 12, the passivation layer 13, the planarization layer 14 and the buffer layer 30 are provided with via holes.
  • the source 72 and the drain 71 of the source and drain layer 70 are connected to the conductor region 52 of the metal contact layer 50 through the via hole of the interlayer insulating layer 12, and the source 72 is also connected to the conductor region 52 of the metal contact layer 50 through the interlayer insulating layer 12 and the buffer layer 30.
  • the via hole is connected to the light shielding layer 20.
  • the pixel electrode 80 is connected to the source 72 or the drain 71 through the via hole of the planarization layer 14 and the passivation layer 13.
  • the pixel electrode 80 as shown in FIG. 1 is connected to the source electrode 72.
  • a method for preparing an array substrate is provided, as shown in FIG. 2, which includes the following steps:
  • Step S10 Provide a substrate, prepare an active layer and a metal contact layer on the substrate in sequence, apply a yellow light process to the active layer and the metal contact layer by using a photomask, and perform a yellow light process on the active layer and the metal contact layer.
  • the metal contact layer is oxidized, so that the metal contact layer forms a conductor region and an insulating region to define the channel region of the active layer.
  • a light shielding layer 20 is prepared on the substrate 10
  • a buffer layer 30 is prepared on the light shielding layer 20
  • the active layer 40 is prepared on the buffer layer 30.
  • a metal film with a thickness of 500 angstroms to 2000 angstroms is deposited on the substrate 10, and the yellow light process is performed on the metal film to form the light shielding layer 20.
  • the metal thin film for preparing the light shielding layer 20 includes metals such as aluminum, copper, molybdenum, titanium, or their alloys.
  • an inorganic film of silicon oxide (SiOx) or silicon nitride (SiNx) with a thickness of 1000 angstroms to 5000 angstroms is deposited on the light shielding layer 20 and the substrate 10 as the buffer layer 30.
  • a layer of metal oxide semiconductor film with a thickness of 100 to 1000 angstroms is deposited on the buffer layer 30 as the active layer 40, and then a layer of metal with a thickness of 50 angstroms to 200 angstroms is deposited on the metal oxide semiconductor material
  • the thin film serves as the metal contact layer 50.
  • the metal film of the metal contact layer 50 includes metals such as aluminum, copper, molybdenum, titanium, or their alloys.
  • a layer of photoresist is coated on the metal contact layer 50, and a halftone mask photomask is used to expose and develop the photoresist to form a photoresist pattern 200.
  • the thickness of the two side portions of the photoresist pattern 200 is greater than the thickness of the middle portion.
  • the metal contact layer 50 and the active layer 40 are etched to remove the metal contact layer and the active layer that are not shielded by the photoresist pattern. Floor.
  • the photoresist pattern 200 is ashed using an ashing gas such as oxygen, so that the two sides of the photoresist pattern are thinned, and the middle part is removed to expose a part of the metal contact layer 50, as shown in FIG. 4 .
  • an ashing gas such as oxygen
  • the exposed metal contact layer 50 is oxidized, so that the metal contact layer 50 forms a conductor area 52 and an insulating area 51 to define an active layer 40 of the channel region 41.
  • a metal oxide insulating region 51 is formed.
  • the insulating region 51 can be used as a part of the subsequent gate insulating layer, and can better protect the active layer 40.
  • the portions on both sides that have not been oxidized are used as the conductor regions 52 of the metal contact layer 50.
  • the thinned photoresist pattern 201 is peeled off to form a structure as shown in FIG. 5.
  • Step S20 Prepare a gate insulating layer 11 on the metal contact layer 50, prepare a gate layer 60 on the gate insulating layer 11, and perform yellowing on the gate layer 60 and the gate insulating layer 11.
  • the light process forms the gate 61 as shown in FIG. 6.
  • an inorganic thin film such as silicon oxide (SiOx) or silicon nitride (SiNx) with a thickness of 1000 angstroms to 3000 angstroms is deposited on the metal contact layer and the buffer layer as the gate insulating layer.
  • a metal film with a thickness of 2000 angstroms to 8000 angstroms is deposited on the gate insulating layer as the gate layer.
  • the metal film of the gate layer includes metals such as aluminum, copper, molybdenum, titanium, or their alloys or their laminated structure.
  • a yellow light etching process is performed on the gate layer 60 to form a gate 61.
  • the gate insulating layer 11 is etched so that all the gate insulating layer 11 that is not blocked by the metal pattern of the gate 61 is etched away.
  • a photoresist lift-off process can also be used to reduce the number of etchings.
  • Step S30 preparing an interlayer insulating layer on the gate layer, preparing a source and drain layer on the interlayer insulating layer, and performing a yellowing process on the source and drain layer to form a source electrode and a drain electrode.
  • the source electrode and the drain electrode are respectively connected to the conductor region.
  • an inorganic film of silicon oxide (SiOx) or silicon nitride (SiNx) with a thickness of 2000 angstroms to 10000 angstroms is deposited on the gate layer 60 and the buffer layer 30 as the interlayer insulation.
  • Layer 12 an inorganic film of silicon oxide (SiOx) or silicon nitride (SiNx) with a thickness of 2000 angstroms to 10000 angstroms is deposited on the gate layer 60 and the buffer layer 30 as the interlayer insulation.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • a yellowing process is performed on the interlayer insulating layer 12 to form a plurality of via holes.
  • One type of via 121 penetrates the interlayer insulating layer 12 to the metal contact layer 50 to expose the conductor area 52 of the metal contact layer 50.
  • Another type of via hole 121' penetrates the interlayer insulating layer 12 and the buffer layer 30 to the light shielding layer 20, so as to expose a part of the light shielding layer 20.
  • a metal film with a thickness of 2000 angstroms to 8000 angstroms is deposited on the interlayer insulating layer 12 as the source and drain layer 70.
  • the metal film of the source and drain layer 70 includes metals such as aluminum, copper, molybdenum, titanium, or alloys thereof, or a laminated structure thereof.
  • a yellow light etching process is performed on the source and drain layer 70 to form a source 72, a drain 71 and signal traces (not shown).
  • the source 72 and the drain 71 are respectively connected to the conductor region 52 of the metal contact layer 50 and the light shielding layer 20 through the via holes of the corresponding interlayer insulating layer 12.
  • the source electrode 72 is connected to the conductor region 52 and the light shielding layer 20 at the same time.
  • the drain 71 is connected to the conductor region 52.
  • step S40 a passivation layer and a planarization layer are sequentially prepared on the source and drain layers and the interlayer insulating layer, and a pixel electrode is prepared on the planarization layer.
  • a layer of silicon oxide (SiOx), silicon nitride (SiNx) or silicon oxynitride (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOx) with a thickness of 1000 angstroms to 5000 angstroms is deposited on the source and drain layers 70 and the interlayer insulating layer 12
  • Inorganic thin films such as SiNOx are used as the passivation layer 13.
  • a planarization layer 14 is deposited on the passivation layer 13.
  • the planarization layer 14 is subjected to a yellow photo-etching process to form a via 121".
  • the via 121" penetrates the planarization layer 14 and the passivation layer 13 to expose the source 72 or the drain 71, as shown in FIG. ⁇ 72 ⁇ Out of the source 72.
  • a pixel electrode 80 is prepared on the planarization layer 14, and the pixel electrode 80 is connected to the source 72 or the drain 71 through the via hole to form the array substrate 100 as shown in FIG. 1, In FIG. 1, the pixel electrode 80 is connected to the source electrode 72.
  • a display panel which includes the array substrate of one of the above-mentioned embodiments.
  • the display panel is a liquid crystal display panel.
  • the liquid crystal display panel 1000 shown in FIG. A liquid crystal molecule 400.
  • the display panel is an OLED display panel.
  • the OLED display panel 1001 shown in FIG. 11 includes an array substrate 100, a light-emitting function layer 500 disposed on the array substrate 100, and an encapsulation layer 600 disposed on the light-emitting function layer 500.
  • the present application provides an array substrate, a preparation method thereof, and a display panel.
  • the array substrate includes an active layer, a metal contact layer, a gate insulating layer, a gate layer, a source and drain layer, and pixels which are sequentially stacked on a substrate. electrode.
  • the insulating region of the metal contact layer corresponds to the channel region of the active layer, and the conductor region of the metal contact layer is located on both sides of the insulating region.
  • the source and drain of the source-drain layer are respectively connected to the conductor area.
  • the metal contact layer is prepared on the active layer, and the conductivity and stability of the conductor area of the metal contact layer are better.
  • the active layer and the metal contact layer are deposited at the same time, which can better protect the channel region of the active layer.
  • the insulating region formed after the metal contact layer corresponding to the channel region is oxidized can be used as a part of the gate insulating layer, which can better protect the active layer and make the performance of the TFT device more stable.

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Abstract

本申请提供一种阵列基板及其制备方法以及显示面板。阵列基板包括依次层叠设置在衬底上的有源层、金属接触层、栅极绝缘层、栅极层、源漏极层、像素电极。金属接触层的绝缘区对应于有源层的沟道区，金属接触层的导体区位于绝缘区的两旁。源漏极层的源极和漏极分别与导体区连接。以缓解现有TFT器件中IGZO导体化区电阻较大的问题。

Description

一种阵列基板及其制备方法以及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制备方法以及显示面板。
 背景技术
随着显示技术的发展，显示屏逐渐往大尺寸高分辨率的方向发展。而传统的TFT（Thin Film Transistor，薄膜晶体管）器件一般采用a-Si（Amorphous Silicon，非晶硅）作为有源层。a-Si器件由于发展已久，器件特性稳定，但是a-Si迁移率低下，在高分辨率及高刷新频率下，就逐渐失去了原有的优势。而IGZO（Indium Gallium Zinc Oxide，铟镓锌氧化物）作为氧化物半导体材料中的一种，相比较于a-Si，有着比a-Si更大的迁移率。使用IGZO作为TFT器件中的沟道材料，可以提高显示面板的分辨率。而对于顶栅（Top gate）结构的氧化物半导体TFT器件，通常在对栅极层和栅极绝缘层进行刻蚀后，采用氦气等离子体对未被栅极层覆盖的IGZO区域进行导体化，以保证源漏极层与半导体层间良好的欧姆接触。之后再进行源漏极层的制作，形成TFT器件。但是经历长时间的热退火制程会增加IGZO被导体化区域的电阻，影响导体化的效果，从而使TFT器件的电性恶化甚至失效。
因此，现有TFT器件中IGZO导体化区电阻较大的问题需要解决。
 技术问题
本申请提供一种阵列基板及其制备方法以及显示面板，以缓解现有TFT器件中IGZO导体化区电阻较大的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种阵列基板，其包括在衬底上依次层叠制备的有源层、金属接触层、栅极绝缘层、栅极层、源漏极层、及像素电极。所述有源层设置于所述衬底上，包括沟道区。所述金属接触层设置于所述有源层上，包括导体区和绝缘区，所述绝缘区对应于所述沟道区，所述导体区设置于所述绝缘区两旁。所述栅极绝缘层设置于所述金属接触层上方。所述栅极层设置于所述栅极绝缘层上方，所述栅极层包括栅极，所述栅极位于所述沟道区的相对上方。所述源漏极层设置于所述导体区上方，所述源漏极层包括源极和漏极。所述像素电极设置于所述源漏极层上方，且与所述源极或所述漏极连接。其中，所述源极和所述漏极分别与所述导体区连接。
在本申请实施例提供的阵列基板中，所述阵列基板还包括遮光层，所述遮光层设置于所述衬底上，且位于所述有源层的下方。
在本申请实施例提供的阵列基板中，所述有源层的宽度小于所述遮光层的宽度。
在本申请实施例提供的阵列基板中，所述有源层的材料包括铟镓锌氧化物、铟锌锡氧化物、铟镓锌锡氧化物中的一种。
在本申请实施例提供的阵列基板中，所述遮光层的材料包括铝、铜、钼、钛中的一种或者几种的合金。
在本申请实施例提供的阵列基板中，所述金属接触层的材料包括铝、铜、钼、中的一种或者几种的合金。
在本申请实施例提供的阵列基板中，所述金属接触层的厚度范围为50埃至200埃。
在本申请实施例提供的阵列基板中，所述栅极绝缘层的图案大小与所述栅极的图案大小相同。
在本申请实施例提供的阵列基板中，所述阵列基板还包括设置于所述栅极层和所述源漏极层之间的层间绝缘层，以及设置于所述源漏极层和所述像素电极之间的钝化层及平坦化层。
本申请实施例提供一种阵列基板制备方法，其包括以下步骤：步骤S10、提供一衬底，依次在所述衬底上制备有源层及金属接触层，使用一道光罩对所述有源层和所述金属接触层进行黄光工艺，并对部分所述金属接触层进行氧化处理，使所述金属接触层形成导体区和绝缘区，以定义出所述有源层的沟道区。步骤S20、在所述金属接触层上制备栅极绝缘层，在所述栅极绝缘层上制备栅极层，对所述栅极层和所述栅极绝缘层进行黄光工艺，形成栅极。步骤S30、在所述栅极层上制备层间绝缘层，在所述层间绝缘层上制备源漏极层，对所述源漏极层进行黄光工艺形成源极和漏极，所述源极和所述漏极分别连接到所述导体区。
在本申请实施例提供的阵列基板制备方法中，在步骤S10中，制备所述有源层和所述金属接触层包括以下步骤：在所述衬底上制备遮光层，在所述遮光层上制备缓冲层，在所述缓冲层上制备所述有源层。在所述有源层上沉积一层金属薄膜作为金属接触层，在所述金属接触层上涂布光阻，使用半色调掩膜光罩对所述光阻进行曝光显影形成光阻图案。以所述光阻图案为遮挡，对所述金属接触层和所述有源层进行蚀刻，去除未被所述光阻图案遮挡的所述金属接触层和所述有源层。对所述光阻图案进行灰化，使所述光阻图案两侧部分减薄，中间部分去除，以裸露出部分所述金属接触层。以减薄的光阻图案为遮挡，对裸露出的所述金属接触层进行氧化处理，形成绝缘区。剥离掉所述减薄的光阻图案。
在本申请实施例提供的阵列基板制备方法中，所述有源层的宽度小于所述遮光层的宽度。
在本申请实施例提供的阵列基板制备方法中，所述金属接触层的材料包括铝、铜、钼、钛中的一种或者几种的合金。
在本申请实施例提供的阵列基板制备方法中，所述金属接触层的厚度范围为50埃至200埃。
在本申请实施例提供的阵列基板制备方法中，所述光阻图案两侧部分的厚度大于中间部分的厚度。
在本申请实施例提供的阵列基板制备方法中，在步骤S20中，采用光阻剥离工艺形成所述栅极。
在本申请实施例提供的阵列基板制备方法中，还包括以下步骤：步骤S40、在所述源漏极层以及所述层间绝缘层上依次制备钝化层和平坦化层，并在所述平坦化层上制备像素电极，所述像素电极与所述源极或所述漏极连接。
本申请实施例提供一种显示面板，其包括阵列基板，所述阵列基板包括在衬底上依次层叠制备的有源层、金属接触层、栅极绝缘层、栅极层、源漏极层、及像素电极。所述有源层设置于所述衬底上，包括沟道区。所述金属接触层设置于所述有源层上，包括导体区和绝缘区，所述绝缘区对应于所述沟道区，所述导体区设置于所述绝缘区两旁。所述栅极绝缘层设置于所述金属接触层上方。所述栅极层设置于所述栅极绝缘层上方，所述栅极层包括栅极，所述栅极位于所述沟道区的相对上方。所述源漏极层设置于所述导体区上方，所述源漏极层包括源极和漏极。所述像素电极设置于所述源漏极层上方，且与所述源极或所述漏极连接。其中，所述源极和所述漏极分别与所述导体区连接。
在本申请实施例提供的显示面板中，所述阵列基板还包括遮光层，所述遮光层设置于所述衬底上，且位于所述有源层的下方。
在本申请实施例提供的显示面板中，所述有源层的宽度小于所述遮光层的宽度。
 有益效果
本申请提供的阵列基板及其制备方法以及显示面板中，在有源层上制备金属接触层，金属接触层的导体区的导电性和稳定性更好，作为后续源极、漏极与有源层连接的桥梁，解决了现有TFT器件中IGZO导体化区电阻较大的问题，进而有效的避免因导体化弱化或失效造成的TFT器件性能恶化。同时有源层和金属接触层同时沉积，可以更好的保护有源层的沟道区。而且对应沟道区的金属接触层经氧化处理后形成的绝缘区可以作为栅极绝缘层的一部分，可以更好的保护有源层，使TFT器件性能更稳定。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的阵列基板的膜层结构侧视示意图。
图2为本申请实施例提供的阵列基板制备方法的流程示意图。
图3至图9为本申请实施例提供的阵列基板制备方法中各步骤制得的膜层结构侧视示意图。
图10为本申请实施例提供的第一种显示面板的侧视示意图。
图11为本申请实施例提供的第二种显示面板的侧视示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
在一种实施例中，提供一种阵列基板100，如图1所示，其包括在衬底10上依次层叠制备的有源层40、金属接触层50、栅极绝缘层11、栅极层60、源漏极层70、及像素电极80。所述有源层40设置于所述衬底10上，包括沟道区41。所述金属接触层50设置于所述有源层40上，包括导体区52和绝缘区51，所述绝缘区51对应于所述沟道区41，所述导体区52设置于所述绝缘区51的两旁。所述栅极绝缘层11设置于所述金属接触层50上方。所述栅极层60设置于所述栅极绝缘层11上方，所述栅极层60包括栅极61，所述栅极61位于所述沟道区41的相对上方。所述源漏极层70设置于所述导体区52上方，所述源漏极层70包括源极72和漏极71。所述像素电极80设置于所述源漏极层70上方，且与所述源极72或所述漏极71连接，如图1示出的像素电极80与源极72连接。其中，所述源极72和所述漏极71分别与所述导体区52连接。
具体的，所述衬底10包括玻璃基板或聚酰亚胺等柔性基板。
具体的，所述阵列基板100还包括遮光层20，所述遮光层20设置于所述衬底10上，且位于所述有源层40的下方。当然的，所述有源层40和所述遮光层20之间还设置有缓冲层30。
进一步的，所述遮光层20的材料包括铝、铜、钼、钛等金属或者其合金或者其他遮光材料。
进一步的，所述有源层40的宽度小于所述遮光层20的宽度。
进一步的，所述有源层40的材料包括铟镓锌氧化物、铟锌锡氧化物、铟镓锌锡氧化物等金属氧化物半导体中的一种。
进一步的，所述金属接触层50和所述有源层40使用同一道光罩进行黄光蚀刻工艺。使形成的所述金属接触层50和所述有源层40的图案大小相同。
进一步的，对经过黄光蚀刻工艺后的金属接触层50的中间部分进行氧化处理，使所述金属接触层50形成导体区52和绝缘区51，以定义出有源层40的沟道区41的宽长比。未进行氧化处理的两侧部分作为所述金属接触层50的导体区52，用于与所述源漏极层70的源极72和漏极71连接。
进一步的，金属接触层50的中间部分经过氧化处理后，形成金属氧化物绝缘区51。该绝缘区51可以作为栅极绝缘层11的一部分，能够更好的保护有源层40。
进一步的，栅极绝缘层11和所述栅极层60经同一道光罩进行黄光蚀刻工艺，形成栅极61及信号走线（图未示）。其中经过蚀刻后的栅极绝缘层11的图案大小和栅极61相同。
进一步的，所述金属接触层50的材料包括铝、铜、钼、钛等金属或者其合金。
进一步的，所述金属接触层50的厚度范围为50埃至200埃。
进一步的，所述源漏极层70的源极72或漏极71与所述金属接触层50的导体区52连接，金属接触层50的导体区52相较于导体化的有源层，导电性和稳定性更好，可以有效的避免因导体化弱化或失效造成的TFT器件性能恶化。
进一步的，所述栅极层60和所述源漏极层70的材料均包括铝、铜、钼、钛等金属或者其合金或者其叠层结构。
进一步的，所述栅极层60、所述源漏极层70以及所述像素电极80之间设置有多个绝缘层。多个绝缘层包括层间绝缘层12、钝化层13及平坦化层14。其中层间绝缘层12位于所述栅极层60和所述源漏极层70之间。钝化层13和平坦化层14位于源漏极层70和像素电极80之间。
进一步的，层间绝缘层12、钝化层13、平坦化层14及缓冲层30上设置有过孔。所述源漏极层70的源极72和漏极71通过层间绝缘层12的过孔连接金属接触层50的导体区52，且源极72还通过层间绝缘层12和缓冲层30的过孔连接遮光层20。像素电极80通过平坦化层14和钝化层13的过孔连接源极72或漏极71。如图1示出的像素电极80与源极72连接。
在一种实施例中，提供一种阵列基板的制备方法，如图2所示，其包括以下步骤：
步骤S10、提供一衬底，依次在所述衬底上制备有源层及金属接触层，使用一道光罩对所述有源层和所述金属接触层进行黄光工艺，并对部分所述金属接触层进行氧化处理，使所述金属接触层形成导体区和绝缘区，以定义出所述有源层的沟道区。
具体的，如图3所示，在所述衬底10上制备遮光层20，在所述遮光层20上制备缓冲层30，在所述缓冲层30上制备所述有源层40。
具体的，在所述衬底10上沉积一层厚度为500埃至2000埃的金属薄膜，并对金属薄膜进行黄光工艺，形成遮光层20。制备遮光层20的金属薄膜包括铝、铜、钼、钛等金属或者其合金。
进一步的，在遮光层20及所述衬底10上沉积一层厚度为1000埃至5000埃的氧化硅（SiOx）或氮化硅（SiNx）等无机物薄膜作为缓冲层30。
进一步的，在缓冲层30上沉积一层厚度为100埃至1000埃的金属氧化物半导体薄膜作为有源层40，接着在金属氧化物半导体材料上沉积一层厚度为50埃至200埃的金属薄膜作为金属接触层50。金属接触层50的金属薄膜包括铝、铜、钼、钛等金属或者其合金。
进一步的，在金属接触层50上涂布一层光阻，使用一道半色调掩膜光罩对光阻进行曝光显影，形成光阻图案200。光阻图案200两侧部分的厚度大于中间部分的厚度。
进一步的，以所述光阻图案200为遮挡，对所述金属接触层50和所述有源层40进行蚀刻，去除未被所述光阻图案遮挡的所述金属接触层和所述有源层。
进一步的，使用氧气等灰化气体对所述光阻图案200进行灰化，使所述光阻图案两侧部分减薄，中间部分去除，以裸露出部分金属接触层50，如图4所示。
进一步的，以减薄的光阻图案201为遮挡，对裸露出的所述金属接触层50进行氧化处理，使所述金属接触层50形成导体区52和绝缘区51，以定义出有源层40的沟道区41。
具体的，金属接触层50的中间部分经过氧化处理后，形成金属氧化物绝缘区51。该绝缘区51可以作为后续栅极绝缘层的一部分，能够更好的保护有源层40。
进一步的，未进行氧化处理的两侧部分作为所述金属接触层50的导体区52。
进一步的，剥离掉所述减薄的光阻图案201，形成如图5所示的结构。
步骤S20、在所述金属接触层50上制备栅极绝缘层11，在所述栅极绝缘层11上制备栅极层60，对所述栅极层60和所述栅极绝缘层11进行黄光工艺，形成栅极61，如图6所示。
具体的，在金属接触层及缓冲层上沉积一层厚度为1000埃至3000埃的氧化硅（SiOx）或氮化硅（SiNx）等无机物薄膜作为栅极绝缘层。
进一步的，在栅极绝缘层上沉积一层厚度为2000埃至8000埃的金属薄膜作为栅极层。栅极层的金属薄膜包括铝、铜、钼、钛等金属或者其合金或者其叠层结构。
进一步的，对栅极层60进行黄光蚀刻工艺，形成栅极61。
进一步的，以栅极61的金属图案为自对准，蚀刻栅极绝缘层11，使未被栅极61的金属图案遮挡的栅极绝缘层11全部蚀刻掉。
当然的，在形成栅极61和栅极绝缘层11时，也可以采用光阻剥离（lift-off）工艺以减少蚀刻次数。
步骤S30、在所述栅极层上制备层间绝缘层，在所述层间绝缘层上制备源漏极层，对所述源漏极层进行黄光工艺形成源极和漏极，所述源极和所述漏极分别连接到所述导体区。
具体的，如图7所示，在栅极层60及缓冲层30上沉积一层厚度为2000埃至10000埃的氧化硅（SiOx）或氮化硅（SiNx）等无机物薄膜作为层间绝缘层12。
进一步的，对层间绝缘层12进行黄光工艺，形成多个过孔。其中一种过孔121贯穿层间绝缘层12至金属接触层50，以裸露出金属接触层50的导体区52。另外一种过孔121’贯穿层间绝缘层12和缓冲层30至遮光层20，以裸露出部分遮光层20。
进一步的，如图8所示，在层间绝缘层12上沉积一层厚度为2000埃至8000埃的金属薄膜作为源漏极层70。源漏极层70的金属薄膜包括铝、铜、钼、钛等金属或者其合金或者其叠层结构。
进一步的，对源漏极层70进行黄光蚀刻工艺，形成源极72、漏极71及信号走线（图未示）。源极72、漏极71分别通过对应的层间绝缘层12的过孔连接金属接触层50的导体区52和遮光层20。
具体的，如图8所示，源极72同时连接导体区52和遮光层20。漏极71连接导体区52。
步骤S40、在所述源漏极层以及所述层间绝缘层上依次制备钝化层和平坦化层，在所述平坦化层上制备像素电极。
具体的，如图9所示，在源漏极层70及层间绝缘层12上沉积一层厚度为1000埃至5000埃的氧化硅（SiOx）、氮化硅（SiNx）或氮氧化硅（SiNOx）等无机物薄膜作为钝化层13。
进一步的，在钝化层13上沉积一层平坦化层14。对平坦化层14进行黄光蚀刻工艺形成过孔121”。过孔121”贯穿平坦化层14和钝化层13，以裸露出源极72或漏极71，如图9示出的以裸露出源极72。
进一步的，在所述平坦化层14上制备像素电极80，所述像素电极80通过所述过孔连接所述源极72或所述漏极71，形成如图1所示的阵列基板100，在图1中，像素电极80与源极72连接。
在一种实施例中，提供一种显示面板，其包括上述实施例其中之一的阵列基板。
具体的，显示面板为液晶显示面板，如图10所示的液晶显示面板1000包括阵列基板100、与阵列基板100相对设置的彩膜基板300以及位于阵列基板100和彩膜基板300之间的多个液晶分子400。
具体的，显示面板为OLED显示面板，如图11所示的OLED显示面板1001包括阵列基板100、设置于阵列基板100上的发光功能层500及设置于发光功能层500上的封装层600。
根据上述实施例可知：
本申请提供一种阵列基板及其制备方法以及显示面板，阵列基板包括依次层叠设置在衬底上的有源层、金属接触层、栅极绝缘层、栅极层、源漏极层、及像素电极。金属接触层的绝缘区对应于有源层的沟道区，金属接触层的导体区位于绝缘区的两旁。源漏极层的源极和漏极分别与导体区连接。在有源层上制备金属接触层，金属接触层的导体区的导电性和稳定性更好，作为后续源极、漏极与有源层连接的桥梁，解决了现有TFT器件中IGZO导体化区电阻较大的问题，进而有效的避免因导体化弱化或失效造成的TFT器件性能恶化。同时有源层和金属接触层同时沉积，可以更好的保护有源层的沟道区。而且对应沟道区的金属接触层经氧化处理后形成的绝缘区可以作为栅极绝缘层的一部分，可以更好的保护有源层，使TFT器件性能更稳定。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板，其包括：
    衬底；
    有源层，设置于所述衬底上，包括沟道区；
    金属接触层，设置于所述有源层上，包括导体区和绝缘区，所述绝缘区对应于所述沟道区，所述导体区设置于所述绝缘区两旁；
    栅极绝缘层，设置于所述金属接触层上方；
    栅极层，设置于所述栅极绝缘层上方，所述栅极层包括栅极，所述栅极位于所述沟道区的相对上方；
    源漏极层，设置于所述导体区上方，所述源漏极层包括源极和漏极；以及
    像素电极，设置于所述源漏极层上方，且与所述源极或所述漏极连接；
    其中，所述源极和所述漏极分别与所述导体区连接。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括遮光层，所述遮光层设置于所述衬底上，且位于所述有源层的下方。
  3. 根据权利要求2所述的阵列基板，其中，所述有源层的宽度小于所述遮光层的宽度。
  4. 根据权利要求3所述的阵列基板，其中，所述有源层的材料包括铟镓锌氧化物、铟锌锡氧化物、铟镓锌锡氧化物中的一种。
  5. 根据权利要求3所述的阵列基板，其中，所述遮光层的材料包括铝、铜、钼、钛中的一种或者几种的合金。
  6. 根据权利要求1所述的阵列基板，其中，所述金属接触层的材料包括铝、铜、钼、钛中的一种或者几种的合金。
  7. 根据权利要求6所述的阵列基板，其中，所述金属接触层的厚度范围为50埃至200埃。
  8. 根据权利要求1所述的阵列基板，其中，所述栅极绝缘层的图案大小与所述栅极的图案大小相同。
  9. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括设置于所述栅极层和所述源漏极层之间的层间绝缘层，以及设置于所述源漏极层和所述像素电极之间的钝化层及平坦化层。
  10. 一种阵列基板的制备方法，其包括以下步骤：
    步骤S10、提供一衬底，依次在所述衬底上制备有源层及金属接触层，使用一道光罩对所述有源层和所述金属接触层进行黄光工艺，并对部分所述金属接触层进行氧化处理，使所述金属接触层形成导体区和绝缘区，以定义出所述有源层的沟道区；
    步骤S20、在所述金属接触层上制备栅极绝缘层，在所述栅极绝缘层上制备栅极层，对所述栅极层和所述栅极绝缘层进行黄光工艺，形成栅极；以及
    步骤S30、在所述栅极层上制备层间绝缘层，在所述层间绝缘层上制备源漏极层，对所述源漏极层进行黄光工艺形成源极和漏极，所述源极和所述漏极分别连接到所述导体区。
  11. 根据权利要求10所述的阵列基板制备方法，其中，在步骤S10中，制备所述有源层和所述金属接触层包括以下步骤：
    在所述衬底上制备遮光层，在所述遮光层上制备缓冲层，在所述缓冲层上制备所述有源层；
    在所述有源层上沉积一层金属薄膜作为金属接触层，在所述金属接触层上涂布光阻，使用半色调掩膜光罩对所述光阻进行曝光显影形成光阻图案；
    以所述光阻图案为遮挡，对所述金属接触层和所述有源层进行蚀刻，去除未被所述光阻图案遮挡的所述金属接触层和所述有源层；
    对所述光阻图案进行灰化，使所述光阻图案两侧部分减薄，中间部分去除，以裸露出部分所述金属接触层；
    以减薄的光阻图案为遮挡，对裸露出的所述金属接触层进行氧化处理，形成绝缘区；以及
    剥离掉所述减薄的光阻图案。
  12. 根据权利要求11所述的阵列基板制备方法，其中，所述有源层的宽度小于所述遮光层的宽度。
  13. 根据权利要求11所述的阵列基板制备方法，其中，所述金属接触层的材料包括铝、铜、钼、钛中的一种或者几种的合金。
  14. 根据权利要求13所述的阵列基板制备方法，其中，所述金属接触层的厚度范围为50埃至200埃。
  15. 根据权利要求11所述的阵列基板制备方法，其中，所述光阻图案两侧部分的厚度大于中间部分的厚度。
  16. 根据权利要求10所述的阵列基板制备方法，其中，在步骤S20中，采用光阻剥离工艺形成所述栅极。
  17. 根据权利要求10所述的阵列基板制备方法，其还包括以下步骤：
    步骤S40、在所述源漏极层以及所述层间绝缘层上依次制备钝化层和平坦化层，并在所述平坦化层上制备像素电极，所述像素电极与所述源极或所述漏极连接。
  18. 一种显示面板，其包括阵列基板，所述阵列基板包括：
    衬底；
    有源层，设置于所述衬底上，包括沟道区；
    金属接触层，设置于所述有源层上，包括导体区和绝缘区，所述绝缘区对应于所述沟道区，所述导体区设置于所述绝缘区两旁；
    栅极绝缘层，设置于所述金属接触层上方；
    栅极层，设置于所述栅极绝缘层上方，所述栅极层包括栅极，所述栅极位于所述沟道区的相对上方；
    源漏极层，设置于所述导体区上方，所述源漏极层包括源极和漏极；以及
    像素电极，设置于所述源漏极层上方，且与所述源极或所述漏极连接；
    其中，所述源极和所述漏极分别与所述导体区连接。
  19. 根据权利要求18所述的显示面板，其中，所述阵列基板还包括遮光层，所述遮光层设置于所述衬底上，且位于所述有源层的下方。
  20. 根据权利要求19所述的显示面板，其中，所述有源层的宽度小于所述遮光层的宽度。
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