WO2018113625A1 - 时间数字转换器和时间测量方法 - Google Patents

时间数字转换器和时间测量方法 Download PDF

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WO2018113625A1
WO2018113625A1 PCT/CN2017/116915 CN2017116915W WO2018113625A1 WO 2018113625 A1 WO2018113625 A1 WO 2018113625A1 CN 2017116915 W CN2017116915 W CN 2017116915W WO 2018113625 A1 WO2018113625 A1 WO 2018113625A1
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signal
clock
sampling
time
clock signals
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PCT/CN2017/116915
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English (en)
French (fr)
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隋腾杰
龚政
谢思维
赵指向
黄秋
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武汉中派科技有限责任公司
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Publication of WO2018113625A1 publication Critical patent/WO2018113625A1/zh

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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/005—Time-to-digital converters [TDC]

Definitions

  • the present invention relates to the field of circuits, and in particular to a time to digital converter and a time measuring method.
  • Time-to-Digital Converters technology is widely used in time-frequency measurement, satellite navigation, radar positioning, laser ranging, medical, nuclear physics and particle physics detection.
  • the time resolution of TDC largely influences the advancement of these fields.
  • PET medical full-body positron emission imaging
  • TOF time-of-flight
  • TOF-PET time-of-flight-based PET
  • the image signal-to-noise ratio can be increased by 2.1 times, and the image signal-to-noise ratio of TOF-PET with a time resolution of 100 ps can be increased by 5.2 times.
  • the coarse time measurement is to count the input signal to be measured by using the counting clock, and calculate the high level duration of the input signal to be tested according to the counting result. There is an error between the high level duration obtained by the above coarse time measurement method and the actual high level duration, the error value and the edge of the input signal to be tested (this article mainly uses the rising edge as an example for explanation) and the count clock.
  • the time difference between the edges is related. The time difference can be measured by a fine time measurement method.
  • the most commonly used fine time measurement method is based on the time interpolation method of the internal add-on chain of FPGA (Field Programmable Gate Array, FPGA).
  • the principle of the time interpolation method is to use the addition carry chain to perform multiple delays on the input signal to be tested, and use the counting clock to latch all the delayed signals, and according to the latched "1111...1110000...00" sequence, 1-
  • the position of the 0 boundary calculates the time difference between the rising edge of the input signal to be tested and the rising edge of the counting clock. In order to correctly determine the position of the 1-0 junction, it is necessary to keep the phase of the delayed signal in order.
  • the rising edge of the delayed signal output by the nth adder in the addition carry chain should be delayed by a period of time from the rising edge of the delayed signal output by the n-1th adder.
  • the delay signals received by the latch unit need to maintain the above ordered phase relationship, which may need to be controlled by additional hardware resources. If the phase relationship of the delay signal is disturbed, the accuracy of the time measurement will be affected.
  • due to the addition of some BIN wide (100ps or so) addition carry chain inside the FPGA the time resolution of the time interpolation is limited. At present, most of the methods of Wave Union are used to eliminate the influence of these large BIN widths, but the FPGA consumes a lot of internal resources, and the "bubble" phenomenon caused by the metastability of the register is difficult to solve.
  • a time to digital converter includes: an unordered signal generating unit configured to generate a plurality of disordered clock signals; and a sampling unit connected to the out-of-order signal generating unit for receiving the plurality of unordered clock signals and the input signals to be tested And using the input signal to be tested to sample a plurality of unordered clock signals, and output corresponding actual sampling results;
  • the decoding unit is connected to the sampling unit, and is configured to receive the actual sampling result, and according to the actual sampling result and the plurality of Timing related timing information of the sequenced clock signal determines a time difference between a particular edge of the input signal to be tested and a particular edge of the selected one of the plurality of disordered clock signals to obtain a fine time result of the input signal to be tested
  • a coarse time counting unit connected to the unordered signal generating unit for receiving the selected clock signal and the input signal to be tested, and
  • the sampling unit is further configured to receive a calibration signal, sample the plurality of disordered clock signals by using the calibration signal, and output a corresponding calibration sampling result;
  • the time-to-digital converter further includes: a sequencing unit, and a sampling unit
  • the decoding unit is connected to receive the calibration sampling result, determine timing of the plurality of unordered clock signals according to the calibration sampling result, and output timing information related to timing of the plurality of unordered clock signals to the decoding unit.
  • the time to digital converter further includes a clock management unit for generating a calibration signal.
  • the time-to-digital converter further includes: a selector connected to the clock management unit and the sampling unit, configured to receive the input signal to be tested and the calibration signal output by the clock management unit, and select the input signal to be tested and the calibration signal. One input to the sampling unit.
  • the out-of-order signal generating unit includes: a clock management unit configured to generate at least one initial clock signal by using a phase locked loop; and a delay unit connected to the clock management unit for delaying the at least one initial clock signal To convert at least one initial clock signal into a plurality of unordered clock signals.
  • the delay unit includes at least one of the following: at least one adder set, a plurality of logic gates, and a plurality of delay lines.
  • the at least one adder set is for receiving at least one initial clock signal in a one-to-one correspondence, wherein each adder set is used to form an additive carry chain, and the received initial clock signal is used as a corresponding addition carry chain
  • the least significant input signal, and selecting a predetermined number of output signals from the output signals output by the corresponding addition carry chain, is output to the sampling unit as at least a portion of the plurality of unordered clock signals.
  • the delay unit further includes: a specific number of lookup table units connected in one-to-one correspondence with a specific number of adder sets in the at least one adder set; wherein the at least one adder set is via a specific number of lookup tables
  • the unit outputs a specific number of out-of-order clock signals of the plurality of disordered clock signals to the sampling unit, and outputs the remaining unordered clock signals directly to the sampling unit.
  • each of the plurality of logic gates is configured to receive one of the at least one initial clock signal and delay the received initial clock signal, wherein at least a portion of the plurality of logic gates The delay times of the logic gate circuits are different from each other, wherein a predetermined number of logic gate circuits of the plurality of logic gate circuits are connected to the sampling unit, and the predetermined number of logic gate circuits are used to treat the predetermined number of delayed clock signals as multiple An unordered clock signal is output to the sampling unit.
  • the number of at least one initial clock signal is greater than one, and the plurality of delay lines are used to transmit at least one initial clock signal from the clock management unit to the sampling unit in a one-to-one correspondence, wherein at least one of the plurality of delay lines The delay times of some delay lines are different from each other.
  • the number of at least one initial clock signal is greater than one, the period of at least one initial clock signal is the same, and the phase of at least one initial clock signal is evenly distributed over a range of 0 to 180°.
  • the out-of-order signal generating unit includes: a clock management unit configured to generate a plurality of disordered clock signals using the phase locked loop.
  • the sampling unit includes: a plurality of registers for receiving a plurality of out-of-order clock signals in a one-to-one correspondence, and latching the plurality of unordered clock signals by using the input signal to be tested as a latch enable signal Multiple unordered clock signals are sampled.
  • the time to digital converter further includes an output unit coupled to the decoding unit and the coarse time counting unit for outputting the coarse time result and the fine time result.
  • a time measuring method includes: generating a plurality of out-of-order clock signals; sampling a plurality of disordered clock signals by using the input signals to be tested to obtain actual sampling results; The result and timing information associated with the timing of the plurality of out-of-order clock signals determine a time difference between a first particular edge of the input signal to be tested and a first particular edge of the selected one of the plurality of out-of-order clock signals, Obtaining a fine time result of the input signal to be tested; and counting the input signal to be tested with the selected clock signal as a count clock to obtain a coarse time result of the input signal to be tested.
  • the time measuring method further comprises: sampling the plurality of unordered clock signals by using the calibration signal to obtain the calibration sampling result; and determining the timing of the plurality of unordered clock signals according to the calibration sampling result. To obtain timing information related to the timing of multiple unordered clock signals.
  • the calibration signal includes a first sampling signal having a sampling period equal to an integer multiple of a period of the plurality of disordered clock signals and a predetermined time interval, and a second period in which the sampling period is independent of a period of the plurality of disordered clock signals a sampling signal
  • the calibration sampling result includes a first sampling result obtained by sampling the plurality of disordered clock signals by using the first sampling signal, and a second obtained by sampling the plurality of disordered clock signals by using the second sampling signal
  • the sampling result, determining the timing of the plurality of unordered clock signals according to the calibration sampling result includes: selecting one of the plurality of unordered clock signals as the reference signal; and estimating the second of the reference signals according to the value of the reference signal in the first sampling result
  • the occurrence position of the specific edge determining that the most recent sampling position after the occurrence position of the second specific edge is the cycle start position, and determining the period starting from the cycle start position and having a duration equal to the period of the plurality of disordered clock
  • determining the timing of the clock signal includes: for any of the plurality of unordered clock signals, the clock signal according to the second sampling result The ratio of occurrence of each combination of the clock signal to be sequenced and the reference signal determines the time taken by each combination of the clock signal and the reference signal to be sequenced in the reference period; if the clock signal to be sequenced and the reference signal
  • the combined value includes four different combined values and each combination takes a time in the reference period for more than a predetermined time interval, and then according to the clock signal to be sequenced in the first sampling result and the reference signal at the beginning of the cycle
  • the value of the combination, the combination of the clock signal to be sequenced and the reference signal in the second sampling result determine the timing of the clock signal to be sequenced; If
  • the combination of the clock signal and the reference signal to be sequenced determines the timing of the clock signal to be sequenced, wherein the combined value of the first auxiliary signal and the reference signal includes four different combinations, and each combination takes The time occupied by the reference period is greater than the predetermined time interval and the value of the first auxiliary signal in the first sampling result is at the beginning of the cycle The level appearing before a certain edge is consistent; if the combined value of the clock signal to be sequenced and the reference signal includes three different combined values, wherein the specific order of the clock signal to be sequenced in the three different combined values The value appears only once, the second auxiliary signal is selected from the sequenced clock signals, and the timing of the clock signal to be sequenced is determined according to the combined value of the second auxiliary signal and the clock signal to be
  • the calibration signal includes a first sampling signal having a sampling period equal to an integer multiple of a period of the plurality of disordered clock signals and a predetermined time interval, and a second period in which the sampling period is independent of a period of the plurality of disordered clock signals a sampling signal
  • the calibration sampling result includes a first sampling result obtained by sampling the plurality of disordered clock signals by using the first sampling signal, and a second obtained by sampling the plurality of disordered clock signals by using the second sampling signal
  • the sampling result, determining the timing of the plurality of unordered clock signals according to the calibration sampling result includes: selecting one of the plurality of unordered clock signals as the reference signal; repeating the following sequencing operation until determining the timing of the plurality of unordered clock signals Up to: estimating the occurrence position of the second specific edge of the reference signal according to the value of the reference signal in the first sampling result, determining that the latest sampling position after the occurrence position of the second specific edge is the cycle start position, and determining from the cycle The time
  • the combination of the clock signal and the reference signal determines the timing of the clock signal to be sequenced, wherein the preset condition includes a combination of the clock signal to be sequenced and the reference signal, including four different combinations of values and each combination is taken
  • the time occupied by the value in the reference period is greater than the preset time period, and the preset time period is related to the predetermined time interval; one of the plurality of out-of-order clock signals is selected as the new reference signal;
  • the uniform cycle start position corrects the timing of multiple unordered clock signals.
  • the time-to-digital converter and the time measuring method since the out-of-order clock signal is used to perform fine time measurement of the input signal to be tested, the existence of a large BIN width can be avoided, so that the time-to-digital converter can have Very high time resolution. In addition, the time-to-digital converter requires less hardware resources and lower production costs.
  • FIG. 1 shows a schematic block diagram of a time to digital converter in accordance with one embodiment of the present invention
  • FIG. 2 shows a schematic block diagram of a time to digital converter in accordance with another embodiment of the present invention
  • FIG. 3 shows a schematic block diagram of a time to digital converter in accordance with another embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of a delay unit and a sampling unit according to an embodiment of the present invention.
  • FIG. 5 illustrates an exemplary timing diagram of a plurality of out-of-order clock signals in accordance with one embodiment of the present invention
  • FIG. 6 is a schematic diagram showing sampling results obtained by sampling a plurality of unordered clock signals using a first sampling signal, according to an embodiment of the present invention
  • Figure 7 shows the waveform distribution of two kinds of clock signals having different values at the start position of the cycle
  • FIG. 8 is a schematic diagram showing a clock signal to be sequenced with a generally evenly distributed distribution according to an embodiment of the present invention
  • FIG. 9 is a schematic diagram showing a clock signal to be sequenced with a distribution of a particular distribution according to an embodiment of the present invention.
  • 10a and 10b respectively show schematic diagrams of two special distributions of clock signals to be sequenced according to an embodiment of the invention
  • FIG. 11 is a schematic diagram showing a clock signal to be sequenced in a distributed manner in a distributed manner according to an embodiment of the present invention
  • FIG. 12 illustrates a Gaussian distribution result obtained by testing time measurement accuracy of a time-to-digital converter according to an embodiment of the present invention
  • FIG. 13 shows a schematic flow chart of a time measuring method according to an embodiment of the present invention.
  • the present invention proposes a time-to-digital converter and a time measuring method for measuring fine time information of an input signal to be tested by an unordered clock signal.
  • the time-to-digital converter and the time measuring method according to the embodiment of the present invention it is possible to achieve finer time measurement than the prior art without ensuring the phase order of the clock signal.
  • the input signal to be tested described herein can be any electrical signal that requires measurement of its time information.
  • the input signal to be tested may be an electrical signal output by a readout circuit of the PET system.
  • the front-end photon detector of the PET system detects a gamma photon, it can output a pulse signal, which is commonly referred to as HIT.
  • the input signal to be tested may be the pulse signal.
  • FIG. 1 shows a schematic block diagram of a time to digital converter 100 in accordance with one embodiment of the present invention.
  • the time-to-digital converter 100 includes an out-of-order signal generating unit 110, a sampling unit 120, a decoding unit 130, and a coarse time counting unit 140.
  • the out-of-order signal generating unit 110 is configured to generate a plurality of out-of-order clock signals.
  • the plurality of clock signals generated by the out-of-order signal generating unit 110 have the same period, but the phases and duty ratios are not completely the same.
  • the plurality of clock signals are unordered, and their rising or falling edges (or high-level regions or low-level regions) are not distributed in an orderly and regular manner, but are scattered and irregularly Distributed throughout the clock cycle (ie, the period of the unordered clock signal).
  • the sampling unit 120 is connected to the out-of-order signal generating unit 110, and configured to receive a plurality of unordered clock signals and an input signal to be tested, and sample the plurality of unordered clock signals by using the input signal to be tested, and output corresponding actual samples. result.
  • a plurality of unordered clock signals can be latched using the input signal to be tested as a latch enable signal.
  • an edge eg, a rising edge
  • a plurality of unordered clock signals are latched.
  • the specific edge and the plurality of edges of the input signal to be tested can be calculated according to the sampling result obtained by sampling the plurality of unordered clock signals by using the input signal to be tested.
  • the time difference between the specific edges of the disordered clock signal that is, the fine time information of the input signal to be tested can be obtained.
  • the decoding unit 130 is connected to the sampling unit 120 for receiving an actual sampling result, and determining a specific edge of the input signal to be tested and a plurality of unordered according to the actual sampling result and timing information related to the timing of the plurality of disordered clock signals. The time difference between specific edges of the selected clock signal in the clock signal to obtain a fine time result of the input signal to be tested.
  • the time to digital converter 100 can also include separate memory cells in which timing information associated with the timing of the plurality of out-of-order clock signals can be stored.
  • the decoding unit 130 may internally include a storage unit, and timing information related to timing of the plurality of out-of-order clock signals may be stored in the storage unit of the decoding unit 130.
  • timing information associated with the timing of a plurality of out-of-order clock signals may also be stored in a sequencing unit as described below. After the sequencing unit determines the timing of the plurality of unordered clock signals, a sequencing lookup table can be established, and timing information associated with the timing of the plurality of out-of-order clock signals is stored in the sequencing lookup table.
  • the selected clock signal may be any one of a plurality of unordered clock signals, which may be arbitrarily selected, which is not limited in the present invention.
  • a clock signal can be arbitrarily selected from a plurality of disordered clock signals as a clock signal for coarse time counting, and the decoding unit 130 can determine only the time difference between a specific edge of the input signal to be tested and a specific edge of the selected clock signal. .
  • the decoding unit 130 can also determine the time difference between a particular edge of the input signal to be tested and a particular edge of all out-of-order clock signals.
  • the above specific edge may be a rising edge or a falling edge, which is not limited by the present invention.
  • the coarse time counting unit 140 is connected to the out-of-order signal generating unit 110 for receiving the selected clock signal and the input signal to be tested, and counting the input signal to be measured with the selected clock signal as a counting clock to obtain an input signal to be tested. The rough time results.
  • the coarse time counting unit 140 operates in the same manner as the coarse time counting mode in the conventional art.
  • the coarse time counting unit 140 may count the input signals to be measured using the direct counting method.
  • the coarse time result is a preliminary measurement result of the high level duration of the input signal to be measured obtained by calculation such as the direct counting method.
  • the fine time measurement is mainly to measure the above error. Therefore, the time information of the input signal to be tested may include both a coarse time result and a fine time result.
  • the obtained coarse time result and fine time result may be transmitted to a processing unit in the time-to-digital converter for further processing, or may be output to an external device for further processing by the external device.
  • the coarse time measurement uses the count clock to count the input signals to be measured, and the fine time measurement uses the same count clock to latch a plurality of delay signals of the input signal to determine the input signal to be tested.
  • the time difference between the edge and the edge of the count clock eg, the rising edge of the input signal to be tested and the rising edge of the count clock.
  • the fine time measurement is to sample a plurality of unordered clock signals by using the input signal to be tested to determine an edge of the input signal to be tested and an edge of the selected clock signal (for example, an increase of the input signal to be tested) The time difference between the edge and the rising edge of the selected clock signal.
  • the coarse time measurement uses the selected clock signal to count the input signals to be measured. It can be seen that the time measurement manner of the time-to-digital converter 100 is different from the time measurement method in the prior art, especially the fine time measurement is very different.
  • the clock signal used for the fine time measurement of the input signal to be tested is an unordered clock signal, its rising edge or falling edge (or a high level region or a low level)
  • the regions can be distributed arbitrarily and decently throughout the clock cycle, so that the presence of a large BIN width can be avoided, enabling the time-to-digital converter to have a high temporal resolution.
  • the layout of the circuit, the response speed of the device, etc. all have an effect on the delay of the signal, so keeping the signal out of order is easier to achieve than keeping the signal in order. Since it is not necessary to maintain the phase order of the clock signal, the above-mentioned time-to-digital converter requires less hardware resources and low production cost.
  • the time to digital converter may further comprise an output unit.
  • FIG. 2 shows a schematic block diagram of a time to digital converter 200 in accordance with another embodiment of the present invention. It should be understood that the time-to-digital converter 200 shown in FIG. 2 is merely an example and not a limitation, and the present invention is not limited to the circuit configuration shown in FIG. 2.
  • the structure and working principle of 140 are the same and will not be described again.
  • the time to digital converter 200 may also include an output unit 250.
  • the output unit 250 is coupled to the decoding unit 230 and the coarse time counting unit 240 for outputting the coarse time result and the fine time result.
  • the output unit 250 may include a First Input First Output (FIFO) unit and a Universal Asynchronous Receiver/Transmitter (UART) unit.
  • FIFO First Input First Output
  • UART Universal Asynchronous Receiver/Transmitter
  • the output unit 250 may output the coarse time result together with the fine time result to an external device, such as a mobile terminal, a personal computer or a server, etc., to facilitate external device to further process the received time information.
  • an external device such as a mobile terminal, a personal computer or a server, etc.
  • the time to digital converter may further comprise a sequencing unit.
  • the time to digital converter 200 can also include a sequencing unit 260.
  • the sampling unit 120 can also be configured to receive a calibration signal, sample a plurality of disordered clock signals with the calibration signal, and output a corresponding calibration sampling result.
  • the sequencing unit 260 is connected to the sampling unit 220 and the decoding unit 230, for receiving the calibration sampling result, determining the timing of the plurality of unordered clock signals according to the calibration sampling result, and correlating with the timing of the plurality of disordered clock signals. The timing information is output to the decoding unit 230.
  • timing unit 260 can be used to determine the timing of a plurality of out-of-order clock signals (which may be referred to as sequencing) when time-to-digital converter 200 is first operational. Each time the time information of the input signal to be tested is measured, the stored timing information related to the timing of the plurality of out-of-order clock signals can be used. In another example, the sequencing unit 260 can be used to determine the timing of the plurality of out-of-order clock signals each time the time information of the input signal to be tested is measured.
  • the process of determining the timing of a plurality of out-of-order clock signals using the sequencing unit 260 can be considered a calibration process.
  • sampling unit 220 samples a plurality of unordered clock signals using the calibration signal.
  • the sequencing unit 260 receives the sampling result of the sampling unit 220 and determines the timing of the plurality of disordered clock signals based on the sampling result.
  • the sampling unit 220 samples a plurality of disordered clock signals by using the input signal to be tested.
  • the decoding unit 230 receives the sampling result of the sampling unit 220, and determines the position of the edge of the input signal to be tested according to the sampling result and the determined timing of the plurality of disordered clock signals, and thereby can determine the input signal to be tested.
  • “Sequencing” is to determine the exact position of the high-level and low-level regions of a plurality of unordered clock signals in one clock cycle, or to determine the rising and falling edges of multiple unordered clock signals in one clock. The exact location in the cycle.
  • the sequencing unit 260 can establish a Look-Up-Table (LUT) for use in the decoding process.
  • Table 1 below exemplarily shows one form of a sequenced lookup table.
  • the sequencing lookup table can record the high level range and the low level range of n unordered clock signals.
  • the high-level range and the low-level range of the n unordered clock signals are calculated starting from a certain preset time as the starting point of the time axis.
  • the preset time may be a high-level starting time of one of the n out-of-order clock signals.
  • I n-1 , I n respectively , and the input to be tested is
  • the midpoint value of I may be taken as the final result of the position of the edge (rising edge or falling edge) of the input signal to be tested.
  • the specific edge of the obtained input signal to be tested is calculated by the above method ( The position of the rising or falling edge in the clock cycle is the fine time result of the input signal to be tested. If the selected clock signal for the coarse time measurement is not its high level start time as the clock signal at the beginning of the time axis of the sequencing lookup table, then the edge of the selected clock signal can be determined in the clock cycle according to the sequencing lookup table. The position, in combination with the calculated edge of the input signal to be tested in the clock cycle, can also determine the time difference between the specific edge of the input signal to be tested and the specific edge of the selected clock signal, thereby obtaining the input signal to be tested. Fine time results.
  • the out-of-order signal generating unit 110 may include a clock management unit and a delay unit.
  • FIG. 3 shows a schematic block diagram of a time to digital converter 300 in accordance with another embodiment of the present invention.
  • the structure and working principle of the sequence unit 260 are the same, and will not be described again.
  • the out-of-order signal generating unit of the time-to-digital converter 300 shown in FIG. 3 includes a clock management unit 312 and a delay unit 314.
  • the clock management unit 312 is configured to generate at least one initial clock signal using a phase locked loop.
  • the delay unit 314 is coupled to the clock management unit 312 for delaying the at least one initial clock signal to convert the at least one initial clock signal into a plurality of unordered clock signals.
  • the clock management unit 312 can be implemented by using a clock management module (Digi Clock Manager, DCM) inside the FPGA.
  • the clock management unit 312 internally includes a Phase Locked Loop (PLL), and the phase locked loop can generate clock signals having various periods (or frequencies) and phases as needed.
  • PLL Phase Locked Loop
  • Delay unit 314 can be any suitable device capable of delaying the clock signal.
  • delay unit 314 may delay the initial clock signal within delay unit 314 by means of buffer delay, logic gate delay, or line delay.
  • the delay unit 314 may further include an adder that delays the initial clock signal by an addition carry chain composed of the adder.
  • the delay unit 314 can perform different amounts of delay on different initial clock signals to try to make the rising edge or the falling edge (or the high level region) of the delayed clock signal as much as possible. Or low level regions) are distributed throughout the entire clock cycle.
  • the phase of the clock signal output by the delay unit 314 does not need to guarantee a certain order, so the hardware and software design requirements of the delay unit 314 are relatively low.
  • Each initial clock signal can be delayed to generate any number of unordered clock signals, which is not limited by the present invention.
  • the delay unit 314 can be used to generate the desired unordered clock signal more conveniently.
  • delay unit 314 can include at least one of the following: at least one adder set, a plurality of logic gates, and a plurality of delay lines.
  • the initial clock signal may be delayed using an adder, logic gate or delay line or the like.
  • At least one adder set is for receiving at least one initial clock signal in a one-to-one correspondence, wherein each adder set is used to form an additive carry chain, and the received initial clock signal is used as a corresponding addition
  • the lowest bit input signal of the carry chain and a predetermined number of output signals selected from the output signals output by the corresponding addition carry chain are output to the sampling unit as at least a portion of the plurality of unordered clock signals.
  • FIG. 4 is a block diagram showing the structure of a delay unit and a sampling unit according to an embodiment of the present invention.
  • the initial clock signal generated by the clock management unit 312 is four paths, that is, clk1, clk2, clk3, clk4.
  • the unordered clock signal output by the delay unit 314 is 96 channels.
  • delay unit 314 includes four adder sets. Each adder set includes 40 adders to form a 40-bit add-in carry chain.
  • the sampling unit 320 includes 96 registers.
  • the structure of the delay unit and the sampling unit shown in FIG. 4 is merely an example and not a limitation.
  • the number of adder sets in the delay unit 314, the number of adders in each adder set, the number of clock signals output to the sampling unit 320, and the number of corresponding registers in the sampling unit 320 are all Anyly set is not limited to the example shown in FIG.
  • the delay unit 314 and the sampling unit 320 can implement a new time interpolation method. As shown in FIG. 4, the delay unit 314 can generate 96 channels of the same-period square wave signal, which can divide the clock period used for counting in the coarse time counting unit 340 into 96*2 copies. In the sampling unit 320, 96 registers are enabled by the input signal to be tested or the calibration signal to latch the square wave signal.
  • clk1, clk2, clk3, and clk4 are the initial clock signals generated by the PLL with four frequencies of 1 GHz and phases of 0°, 45°, 90°, and 135°, respectively, which are input with four 40-bit inputs.
  • Addition in the carry chain as an input to the least significant adder.
  • the following takes clk1 as an example for explanation.
  • clk1 When clk1 is low level 0, the outputs Sum0 to Sum39 of the corresponding addition carry chain are all 1; when clk1 jumps to high level 1, the outputs Sum0 to Sum39 will become 0 in order. Therefore, Sum0 to Sum39 are square wave signals having a frequency of 1 GHz.
  • the 24 signals can be selected from Sum0 to Sum39 and introduced into the sampling unit 320, and latched (ie, sampled) by the register in the sampling unit 320.
  • the latch enable signal is a calibration signal.
  • the latch enable signal is the input signal to be tested. Perform the same operation on clk2, clk3, and clk4 to obtain 96-bit clock signals of the same period and different phases and their sampling results.
  • the delay unit 314 may further include: a specific number of lookup table units connected in one-to-one correspondence with a specific number of adder sets in the at least one adder set; wherein the at least one adder set is via a specific one
  • the number of lookup table cells outputs a specific number of out-of-order clock signals of the plurality of out-of-order clock signals to the sampling unit 320, and outputs the remaining unordered clock signals directly to the sampling unit 320.
  • the Quartus Prime compiler can be used for automatic place and route. Place and route can cause differences in the transmission path of the clock signal.
  • some clock signals can be input to the registers via a lookup table (LUT) unit.
  • the LUT unit can further cause a delay in the clock signal. After different paths and different LUT units, the delay of the clock signal is also different.
  • some of the clock signals are buffered by the LUT unit, and some are directly connected to the registers. The delay caused by the LUT unit, plus the difference in path delay, can widen the phase difference between the various clock signals.
  • each of the plurality of logic gate circuits is configured to receive one of the at least one initial clock signal and delay the received initial clock signal, wherein the plurality of logic gate circuits The delay times of at least some of the logic gate circuits are different from each other, wherein a predetermined number of logic gate circuits of the plurality of logic gate circuits are connected to the sampling unit 320, and a predetermined number of logic gate circuits are used for a predetermined number of delayed clocks The signal is output to the sampling unit as a plurality of unordered clock signals.
  • a logic gate circuit can be used in place of the adder in the at least one adder set described above.
  • the logic gate has a delay function that acts like an adder.
  • the clock management unit 312 can generate a plurality of initial clock signals having different phases and input them to different logic gate circuits, respectively.
  • clock management unit 312 can also generate an initial clock signal and input it to a different logic gate.
  • the predetermined number of logic gates connected to sampling unit 320 may be part or all of a plurality of logic gate circuits.
  • the number of the at least one initial clock signal is greater than 1, and the plurality of delay lines are used to transmit the at least one initial clock signal from the clock management unit 312 to the sampling unit 320 in a one-to-one correspondence, wherein the plurality of delays The delay times of at least some of the delay lines in the line are different from each other.
  • the initial clock signal can be delayed by simply using a plurality of delay lines having different delay times to obtain a plurality of unordered clock signals.
  • the lengths of at least some of the delay lines may be different from each other such that their delay times are different from each other.
  • the number of at least one initial clock signal is greater than 1, the period of at least one initial clock signal is the same, and the phase of at least one initial clock signal is evenly distributed in the range of 0 to 180°.
  • the initial clock signal has four paths, namely clk1, clk2, clk3, and clk4.
  • the phases of clk1, clk2, clk3, and clk4 are 0°, 45°, 90°, and 135°, respectively, and the phases of the four initial clock signals are evenly distributed in the range of 0 to 180°.
  • the phase spacing of two adjacent initial clock signals arranged in sequence may be equal to or substantially equal to 180°/n, n being the number of initial clock signals, such that the phase of the initial clock signal is as uniform as possible Ground distribution.
  • the out-of-order signal generating unit 110 may include a clock management unit for generating a plurality of disordered clock signals by using a phase locked loop.
  • multiple unordered clock signals can be generated directly using the PLL in the FPGA.
  • the PLL can generate clock signals of various periods and phases as needed, so that a plurality of signals having the same period and different phases can be directly generated by the PLL as a desired unordered clock signal.
  • the time to digital converter 100 may further comprise: a clock management unit for generating a calibration signal.
  • the calibration signal may include a sampling signal having a sampling period related to a period of the plurality of disordered clock signals and a sampling signal having a sampling period completely independent of a period of the plurality of disordered clock signals. That is to say, the calibration signal can also be a clock signal with a certain period, so it can be generated by the clock management unit.
  • the clock management unit for generating the calibration signal may be the same unit as the clock management unit 312 described above for generating the initial clock signal.
  • the time to digital converter also includes a selector.
  • the time to digital converter 300 can also include a selector 370.
  • the selector 370 is connected to the clock management unit 312 and the sampling unit 320 for receiving the input signal to be tested and the calibration signal output by the clock management unit 312, and selecting one of the input signal to be tested and the calibration signal to be input to the sampling unit 320.
  • the selector 370 controls which signal is input to the sampling unit 320 for sampling by the control signal.
  • the coarse time counting unit 340 is connected to the selector 370 in FIG. 3, the input signal to be tested is input to the coarse time counting unit 340 via the selector 370, but it can be understood that the input signal to be tested can also be directly input to the coarse time counting unit. 340.
  • the sampling unit 120 may include a plurality of registers for receiving a plurality of out-of-order clock signals in a one-to-one correspondence, by using the input signal to be tested as a latch enable signal A plurality of unordered clock signals are latched to sample a plurality of unordered clock signals.
  • the input signal to be tested is used as a latch enable signal to latch a plurality of unordered clock signals, and in the calibration process, the calibration signal needs to be used as a latch.
  • the signal can latch a plurality of unordered clock signals.
  • sequencing process of the above-described sequencing unit 260 (or 360) will be described below with reference to FIGS. 5 through 11.
  • an example of the 96-way out-of-order clock signal shown in FIG. 4 is used.
  • FIG. 5 illustrates an exemplary timing diagram of a plurality of out-of-order clock signals in accordance with one embodiment of the present invention.
  • line segments 510 and 520 represent the start and end positions of one clock cycle T, respectively, and line segment 530 represents a certain sampling position.
  • Figure 5 shows a timing diagram of a 96-channel out-of-order clock signal.
  • the calibration signal may include a first sampling signal having a sampling period equal to an integer multiple of a period of the plurality of disordered clock signals and a predetermined time interval, and the sampling period is independent of a period of the plurality of disordered clock signals
  • the second sampling signal, the calibration sampling result may include a first sampling result obtained by sampling the plurality of unordered clock signals by using the first sampling signal, and sampling the plurality of disordered clock signals by using the second sampling signal.
  • the sequencing unit 260 may determine the timing of the plurality of disordered clock signals by selecting one of the plurality of disordered clock signals as the reference signal; according to the first sampling result
  • the value of the reference signal estimates the occurrence position of the specific edge of the reference signal, determines that the most recent sampling position after the occurrence position of the specific edge is the cycle start position, and determines that the duration starting from the cycle start position is equal to a plurality of The period of the period of the sequenced clock signal is the reference period; each value of the reference signal in the second sampling result is counted
  • a ratio is generated to determine a high level and/or a low level of the reference signal in the reference period; according to the value of the reference signal at the beginning of the period and the high level of the reference signal according to the first sampling result
  • the time occupied by the low level in the reference period determines the timing of the reference signal; for each of the plurality of unordered clock signals except the reference signal, the clock signal and the reference signal in the second sampling result are counted
  • the time to digital converter 100 may perform the following steps: selecting a reference signal, sampling with a first sampled signal, sampling with a second sampled signal, and sequencing by signal.
  • selecting a reference signal selecting a reference signal
  • sampling with a first sampled signal sampling with a second sampled signal
  • sequencing by signal The specific description is as follows:
  • the sequencing unit 260 may select from among the plurality of out-of-order clock signals corresponding to the lowest bit output signal in the addition carry chain.
  • the clock signal is used as a reference signal.
  • the high level start position of the reference signal can be determined based on the first sampling result, which will be described below.
  • the reference signal preferably selects a clock signal having a duty cycle close to 50%.
  • multiple unordered clock signals can be sampled with a 49M clock.
  • the 49M clock is a 49MHz clock with a clock period of 10 6 /49ps.
  • the 49M clock can be counted and sampled every 490027 clock cycles.
  • the time interval between the two samples ie, the sampling period
  • the out-of-order signal generating unit 110 uses a 1 GHz clock to generate a plurality of out-of-order clock signals
  • the period of the plurality of unordered clock signals is 1000 ps.
  • the sampling period of 10 6 ⁇ 490027 / 49 ps is the sum of 10000551 times and 20.4 ps of the period 1000 ps of the disordered clock signal.
  • 20.4 ps is the predetermined time interval described herein. Therefore, assuming that the first sample is located at the 10th ps of the first cycle of the clock signal X, the second sample will be located at the 30.4 ps of the 10000552th cycle of the clock signal X, and the third sample will be located at the clock signal. X at the 50.8ps of the 2001103 cycle, and so on.
  • every 49 consecutive sampled results can represent the sampling results obtained by sampling within the same full 1000 ps period, so the time interval between two samples can be considered as 20.4 ps.
  • a large number of samples (for example, more than 1000 times) can be sampled, and the high-level starting position of the reference signal in a certain period is estimated based on the sampling result. Approximating the most recent sampling position after the high-level start position as the cycle start position, and selecting 49 sampling results calculated from the start position of the cycle as one cycle of the unordered clock signal using the first sampling signal The sampling result obtained by sampling inside.
  • a period of time having a duration equal to a period of a plurality of disordered clock signals starting from a period starting position may be used as a reference period.
  • FIG. 6 shows a schematic diagram of sampling results obtained by sampling a plurality of unordered clock signals using a first sampling signal, in accordance with one embodiment of the present invention.
  • the two longer line segments represent the actual cycle start position and the actual cycle end position of the reference cycle, respectively, and the shorter line segments represent the sampling positions.
  • the sampling position with the sampling number of 1 as shown in FIG. 6 can be approximated as the period starting position of the reference period, which is the purpose of sampling with sampling signals having a fixed time interval.
  • the sampling position with sample number 1 is very close to the actual cycle start position
  • the sampling position with sample number 49 is very close to the actual cycle end position. Since it is an approximate result, it will cause a certain error, which will be discussed below.
  • the value of the plurality of unordered clock signals at the start of the cycle can be determined. It should be noted that in FIGS. 6 to 11, the identified cycle start position is the actual cycle start position.
  • FIG. Fig. 7 shows the waveform distribution of two kinds of clock signals having different values at the start position of the cycle. It can be understood that if a clock signal takes a low value at the beginning of the cycle, its waveform distribution should be similar to the upper waveform shown in FIG. 7, that is, the middle portion of the clock signal is high in one reference period. Level area with low level on both sides. Similarly, if a clock signal is at a high level at the beginning of the cycle, its waveform distribution should be similar to the lower waveform shown in Figure 7, ie, in a reference cycle, the middle portion of the clock signal is low. Flat area with high level on both sides.
  • statistical sampling can be used, that is, a large amount of sampling is performed using a clock that is completely independent of the period (or frequency) of a plurality of disordered clock signals. As long as the number of samples is sufficient, the sampled signal can be uniformly distributed over one cycle of the unordered clock signal. To achieve statistical sampling, a large number (eg, 5000) of samples can be taken with the second sampled signal.
  • multiple unordered clock signals can be sampled using a 9.992038M clock (with a frequency of 9.992038 MHz). Similar to the 49M clock, when statistical sampling is performed using the 9.992038M clock, the clock cycle can also be counted and sampled after several clock cycles.
  • the number of sampling results, denoted as F11, the combination of the reference signal and the 10th signal, the value "11" in the reference period can be expressed as follows:
  • N is the number of all sampling results in the second sampling result
  • T is the period of the plurality of unordered clock signals.
  • the reference signal is first sequenced. As described above, when determining the cycle start position, it is necessary to determine the high-level start position of the reference signal.
  • the low-level starting position of the reference signal can also be regarded as the starting position of the cycle.
  • the high-level starting position is taken as an example for description.
  • the values at two adjacent sampling positions representing the reference signal transitioning from a low level to a high level may be found from the first sampling result, the two values being '0' and '1, respectively. '. It can be determined that the high level starting position of the reference signal is between the two sampling positions. Subsequently, the found sampling position whose value is '1' can be regarded as the cycle start position.
  • the start position of the cycle can also be regarded as the position of the rising edge of the reference signal in the reference period.
  • the occurrence ratio of each value of the reference signal in the second sampling result can be counted to determine the time occupied by the high level of the reference signal in the reference period. It is known that the value of the reference signal at the start position of the cycle is '1' and the high level of the reference signal occupies the time in the reference period, and the position of the falling edge of the reference signal in the reference period can be determined very easily. When the positions of the rising edge and the falling edge of the reference signal are determined, the sequencing of the reference signal is completed.
  • the sequencing unit 260 implements, for each clock signal other than the reference signal, among the plurality of disordered clock signals, at least according to the clock signal and the first sampling result.
  • the combined value of the number determines the timing of the clock signal to be sequenced; if the combined value of the clock signal to be sequenced and the reference signal includes four different combined values and the value of the included reference signal is at the second specific edge
  • the first auxiliary signal is selected from the sequenced clock signals according to any one of the two combined values of the level that occurs after the reference period is less than or equal to the predetermined time interval, according to the first auxiliary
  • the combination of the signal, the clock signal to be sequenced and the reference signal determines the waveform distribution of the clock signal to be sequenced, and according to the waveform distribution of the clock signal to be sequenced, the clock signal to
  • the value of the first auxiliary signal at the start position of the cycle coincides with the level appearing before the second specific edge; if the combined value of the clock signal to be sequenced and the reference signal includes three different combinations, wherein The specific value of the clock signal to be sequenced appears only once in three different combined values, then the second auxiliary signal is selected from the sequenced clock signals, and the second auxiliary signal and the pending one are determined according to the second sampling result.
  • the combined value of the sequenced clock signals determines the timing of the clock signal to be sequenced, wherein the combined value of the second auxiliary signal and the reference signal includes four different combined values and the second auxiliary signal and the clock signal to be sequenced
  • the specific value of the clock signal to be sequenced in the combined value appears twice.
  • the uniform distribution means that the rising edge and the falling edge of the clock signal to be sequenced are respectively distributed in the high level period and the low level period of the reference signal. That is to say, the combination of the clock signal and the reference signal whose distribution is uniformly distributed includes four different combinations of values: "11", “10", “01”, and "00". Uniform distribution can be divided into two cases: ordinary uniform distribution and special distribution.
  • the normal uniform distribution means that the four combined values of the clock signals to be sequenced take longer than the predetermined time interval in the reference period, and the predetermined time interval is 20.4 ps in the example described above.
  • the combined value of the clock signal to be sequenced and the reference signal described herein may include the value of the clock signal to be sequenced after the value of the previous reference signal and the value of the reference signal before the clock to be sequenced.
  • the signal value is in the latter two cases. That is to say, when describing the combined value of the clock signal, the order of the values of the respective clock signals is not limited herein, except as specifically noted in the examples.
  • Figure 8 shows a schematic diagram of a clock signal to be sequenced with a generally evenly distributed distribution, in accordance with one embodiment of the present invention.
  • the values of the plurality of disordered clock signals at the cycle start position can be determined.
  • the clock signal to be sequenced has a value of '0' at the start position of the cycle.
  • the ratio of occurrence of various combinations of the clock signal to be sequenced and the reference signal in the second sampling result may be calculated, that is, the calculation combination values are “11”, “10”, “00”, “01”.
  • the proportion of occurrence of the situation According to the occurrence ratio of each combination value, the time occupied by the combination value in the reference period can be determined, that is, the four time intervals of the sequence numbers 1, 2, 3, and 4 in FIG. 8 can be referred to the formula (2). .
  • the approximate waveform distribution of the clock signal to be sequenced and the reference signal can be determined, combining "11", “10", “00”
  • the four combinations of "01” take the time occupied by the reference period, and the position of the rising edge and the falling edge of the clock signal to be sequenced in the reference period can be easily obtained, and the corresponding sequencing lookup table is completed.
  • the clock signal to be sequenced has a value of '0' at the actual cycle start position, but its value at the sample position of sample number 1 is '1'. Therefore, approximating the sampling position with the sampling number of 1 as the starting position of the cycle may cause an initial value judgment of the clock signal to be sequenced to be incorrect, thereby causing an error in the entire waveform distribution of the clock signal to be sequenced.
  • the combination of the reference signal and the clock signal to be sequenced takes a value of "11" or "10" (the value of the reference signal is before, and the value of the clock signal to be sequenced is later) is smaller than In the case of equal to a predetermined time interval (for example, 20.4 ps), the above waveform distribution determination error may occur. Therefore, this situation can be referred to as a special distribution case.
  • the combined value of the clock signal to be sequenced and the reference signal includes four different combined values and the value of the included reference signal and the power appearing after a specific edge (as shown by the rising edge of Figure 9)
  • the two combinations of the flat (high level shown in FIG. 9) values (such as the combined values "11” and "10” shown in FIG. 9) occupy less time in the reference period. Or equal to the predetermined time interval, it is determined that the waveform distribution of the clock signal to be sequenced belongs to a special distribution.
  • FIGS 10a and 10b respectively show schematic diagrams of two special distributions of clock signals to be sequenced in accordance with an embodiment of the present invention.
  • the combination of the reference signal and the clock signal to be sequenced takes a value of "10" (the value of the reference signal is first, and the value of the clock signal to be sequenced is later) is less than the predetermined time.
  • the interval for example, 20.4 ps
  • only the waveform distribution of Fig. 10a may cause a waveform distribution judgment error due to an approximation error.
  • a first auxiliary signal can be introduced, as shown in Figures 10a and 10b.
  • the first auxiliary signal has the following characteristics: self-sequence has been completed; the combination of the reference signal and the first auxiliary signal takes the values of "11", “10", “01”, and "00" in the reference period. Both are greater than a predetermined time interval (eg, 20.4 ps); the value of the first auxiliary signal at the beginning of the cycle (the sampling result at the sampling position of sample number 1 as shown in FIG. 6) is at a specific edge (as shown in FIG. The level appearing before the rising edge shown in Figure 9 (the low level shown in Figure 9) is identical.
  • Fig. 10a After the first auxiliary signal is added, for the combined value of the reference signal, the clock signal to be sequenced, and the first auxiliary signal, Fig. 10a will appear "100", and Fig. 10b will have "101". This makes it possible to distinguish between two special distributions. If the waveform distribution of the clock signal to be sequenced belongs to the case shown in FIG. 10a, the value of the clock signal to be sequenced at the beginning of the cycle can be re-determined, for example, the correction of '1' is originally '0'. .
  • the combination of the clock signal to be sequenced and the reference signal in the second sampling result determines the timing of the clock signal to be sequenced. If the waveform distribution of the clock signal to be sequenced belongs to the case shown in Fig. 10b, the timing of the clock signal to be sequenced can be determined in the same manner as the ordinary uniform distribution.
  • FIG. 11 shows a schematic diagram of a clock signal to be sequenced whose distribution is a centrally distributed distribution, in accordance with one embodiment of the present invention.
  • the combination of the reference signal and the clock signal to be sequenced includes only three different combinations of values: "10", “11", "00” (the value of the reference signal is first, The value of the clock signal to be sequenced is later. In these three combined values, the value '1' of the clock signal to be sequenced appears only once.
  • the combination value "10" of the reference signal and the clock signal to be sequenced is divided into two.
  • the separated time intervals of the two segments cannot be found without the aid of the auxiliary signal. Therefore, it is possible to introduce a second auxiliary signal having the following characteristics: belonging to a uniform distribution and having completed the sequencing itself; capable of dividing the combined value of the reference signal and the clock signal to be sequenced by "11" into two segments, that is, in FIG. T1 and t2 are shown.
  • the combination of the signals takes the value "11" into two segments.
  • the combination of the second auxiliary signal and the clock signal to be sequenced includes "10" and "11" (the value of the clock signal to be sequenced is first, and the second auxiliary signal is taken. The value is after).
  • the values of "01" and "11" are taken according to the combination of the second auxiliary signal and the clock signal to be sequenced (the value of the auxiliary signal is in the front, and the value of the clock signal to be sequenced is after) in the reference period.
  • the rising edge and falling edge positions of the clock signal to be sequenced are: t0-t1 and t0+t2, respectively. This completes the sequencing of the clock signal to be sequenced.
  • the calibration signal may include a first sampling signal having a sampling period equal to an integer multiple of a period of the plurality of disordered clock signals and a predetermined time interval, and a sampling period independent of a period of the plurality of disordered clock signals a second sampling signal
  • the calibration sampling result includes a first sampling result obtained by sampling a plurality of disordered clock signals by using the first sampling signal, and a sampling obtained by sampling the plurality of disordered clock signals by using the second sampling signal
  • the sequencing unit 260 may determine the timing of the plurality of unordered clock signals by selecting one of the plurality of unordered clock signals as the reference signal; repeating the following sequencing operations until determining more
  • the timing of the unordered clock signal is: estimating the occurrence position of the second specific edge of the reference signal according to the value of the reference signal in the first sampling result, determining that the most recent sampling position after the occurrence position of the second specific edge is a period a starting position, and determining
  • the preset time period is related to the predetermined time interval; selecting one of the sequenced clock signals in the plurality of unordered clock signals as the new a reference signal; and correcting the timing of the plurality of unordered clock signals based on a uniform cycle start position.
  • the sequencing process can consist of the following steps:
  • the timing of the clock signal to be sequenced may be determined according to the first sampling result and the second sampling result.
  • the manner of determining the timing of the clock signal to be sequenced in this step is similar to the above-mentioned sequencing process for the clock signal of the to-be-ordered sequence whose distribution is normally uniformly distributed, and details are not described herein again.
  • the preset time period is related to the predetermined time interval, which can be set as needed. For example, assuming that the predetermined time interval is 20.4 ps, the preset time period may be about twice the predetermined time interval, for example, 45 ps.
  • the sequencing method in the second example is simpler and easier to implement than the sequencing method in the first example.
  • the time to digital converter can be implemented in any suitable hardware, software, and/or firmware in accordance with embodiments of the present invention.
  • a time to digital converter can be implemented using PFGA.
  • the time measurement accuracy of the built time to digital converter can be tested in the following manner. For example, you can set up a two-channel time-to-digital converter that uses the same input signal to be tested for sampling. Since the path delay of the input signal to be tested to the two time-to-digital converters is different, the time values obtained by the sampling results of the two time-to-digital converters after decoding should have a fixed difference. In the actual test, the difference exhibits a Gaussian distribution, and the full width at half maximum (FWHM) of the Gaussian distribution is the time resolution of the time-to-digital converter.
  • Figure 12 illustrates Gaussian distribution results obtained by testing time measurement accuracy of a time to digital converter in accordance with one embodiment of the present invention.
  • the FWHM value (i.e., the time measurement accuracy) is about 61.5 ps. This result also has a certain gap with the theoretical time measurement accuracy of the time-to-digital converter according to the embodiment of the present invention, so there is still room for further improvement.
  • the value of the 96-order unordered clock signal at the beginning of the cycle of one clock cycle is approximated.
  • statistical sampling is performed using the 9.992038M clock, and the time interval occupied by any combination of the 96 unordered clock signals in one clock cycle is obtained.
  • the clock signals are divided into three categories one by one, and the corresponding sequencing lookup table is completed.
  • the input signal to be tested is input to the coarse time counting unit to obtain a coarse time result.
  • the input signal to be tested is input to the sampling unit, and 96 unordered clock signals are latched.
  • the latched result is decoded to obtain a fine time result.
  • the fine time result is combined with the coarse time result and output to the external device through the output unit.
  • time-to-digital converters Compared to current time-to-digital converters based on technologies such as "Wave union", time-to-digital converters according to embodiments of the present invention have the following advantages:
  • the out-of-order signal generating unit generates 96 unordered clock signals
  • the clock period used is 1000 ps.
  • more than 95% of the BIN width is below 20ps, and the maximum BIN width is only about 30ps, so the time digitizer has a high time resolution.
  • the time resolution of the time-to-digital converter can be flexibly adjusted. For example, if a higher time resolution is required, the number of clock signals generated by the out-of-order signal generating unit can be increased; conversely, the number of generated clock signals can be reduced. As you can see, the way to adjust the time resolution is very convenient and simple.
  • the FPGA consumes less internal resources and can implement hundreds of channels inside an FPGA chip.
  • sequencing units and decoding units that consume more resources and are relatively complex in design can be executed in the NIOS II soft core embedded in the FPGA.
  • the resources required to complete a single-channel TDC are on average around 10 Logic Array Blocks (LABs). If the time-to-digital converter described above is implemented in an FPGA with thousands of available LABs internally, a TDC of more than one hundred channels can be achieved.
  • the time measurement accuracy of the time-to-digital converter according to an embodiment of the present invention is not low. From the above test link, the current time measurement accuracy has reached about 60ps, and there is a large room for improvement.
  • FIG. 13 shows a schematic flow chart of a time measurement method 1300 in accordance with one embodiment of the present invention. As shown in FIG. 13, the time measurement method 1300 includes the following steps.
  • step S1310 a plurality of out-of-order clock signals are generated.
  • step S1320 a plurality of unordered clock signals are sampled using the input signal to be tested to obtain an actual sampling result.
  • step S1330 determining, according to the actual sampling result and the timing information related to the timing of the plurality of disordered clock signals, the first specific edge of the input signal to be tested and the first of the selected ones of the plurality of disordered clock signals The time difference between specific edges to obtain a fine time result of the input signal to be tested.
  • step S1340 the input signal to be measured is counted with the selected clock signal as a count clock to obtain a coarse time result of the input signal to be tested.
  • the time measuring method 1300 may further include: sampling a plurality of disordered clock signals with a calibration signal to obtain a calibration sampling result; and determining a plurality of disordered according to the calibration sampling result. Timing of the clock signal to obtain timing information related to the timing of the plurality of unordered clock signals.
  • the calibration signal includes a first sampling signal having a sampling period equal to an integer multiple of a period of the plurality of disordered clock signals and a predetermined time interval, and the sampling period is independent of a period of the plurality of disordered clock signals a second sampling signal
  • the calibration sampling result includes a first sampling result obtained by sampling a plurality of disordered clock signals by using the first sampling signal, and sampling the plurality of disordered clock signals by using the second sampling signal.
  • the second sampling result, determining the timing of the plurality of unordered clock signals according to the calibration sampling result includes: selecting one of the plurality of unordered clock signals as the reference signal; and estimating the reference signal according to the value of the reference signal in the first sampling result
  • the occurrence position of the second specific edge determines that the most recent sampling position after the occurrence position of the second specific edge is the cycle start position, and determines that the duration is equal to the plurality of disordered clock signals starting from the cycle start position
  • the period of the period is the reference period; the proportion of occurrence of each value of the reference signal in the second sampling result is counted, Determining the time of the high level and/or low level of the reference signal in the reference period; according to the value of the reference signal at the beginning of the period and the high level and/or the low level of the reference signal according to the first sampling result Determining the timing of the reference signal in the time occupied by the reference period; for each of the plurality of unordered clock signals except the reference signal, counting each combination of the
  • determining the timing of the clock signal includes: for any one of the plurality of unordered clock signals, according to the second The ratio of the occurrence of each combination of the clock signal to be sequenced and the reference signal in the sampling result determines the time taken by each combination of the clock signal and the reference signal to be sequenced in the reference period; if the clock signal to be sequenced is The combined value of the reference signal includes four different combined values, and each combination takes a time in the reference period for more than a predetermined time interval, and then the clock signal to be sequenced and the reference signal in the first sampling result are in a period The value at the start position, the combined value of the clock signal to be sequenced in the second sampling result, and the reference signal determine the clock signal to be
  • the calibration signal includes a first sampling signal having a sampling period equal to an integer multiple of a period of the plurality of disordered clock signals and a predetermined time interval, and the sampling period is independent of a period of the plurality of disordered clock signals a second sampling signal
  • the calibration sampling result includes a first sampling result obtained by sampling a plurality of disordered clock signals by using the first sampling signal, and sampling the plurality of disordered clock signals by using the second sampling signal.
  • the second sampling result, determining the timing of the plurality of unordered clock signals according to the calibration sampling result comprises: selecting one of the plurality of unordered clock signals as the reference signal; repeatedly performing the following sequencing operation until determining the plurality of unordered clock signals Up to the timing: estimating the occurrence position of the second specific edge of the reference signal according to the value of the reference signal in the first sampling result, determining that the latest sampling position after the occurrence position of the second specific edge is the cycle start position, and determining The period in which the period starting position is the starting point and the duration is equal to the period of the plurality of unordered clock signals is For a clock signal to be sequenced that satisfies a preset condition among a plurality of disordered clock signals, the ratio of occurrence of each combination of the clock signal to be sequenced and the reference signal in the second sampling result is determined to be determined.
  • Each combination of the clock signal and the reference signal takes the time occupied by the reference period, and according to the value of the clock signal to be sequenced in the first sampling result and the reference signal at the beginning of the cycle, the second sampling result
  • the combination of the clock signal to be sequenced and the reference signal determines the timing of the clock signal to be sequenced, wherein the preset condition includes a combination of the clock signal to be sequenced and the reference signal, including four different combinations of values and each The combined value takes longer than the preset time period in the reference period, and the preset time period is related to the predetermined time interval; one of the sequenced clock signals in the plurality of unordered clock signals is selected as the new reference signal And correcting the timing of multiple unordered clock signals based on a uniform cycle start position.
  • first specific edge and “second specific edge” described herein are only used for the purpose of distinguishing two edges, and the “first specific edge” and the “second specific edge” may be the same type of edge (for example) Both rising edges or falling edges) can also be different types of edges (for example, one is a rising edge and one is a falling edge).
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another device, or some features can be ignored or not executed.

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Abstract

一种时间数字转换器和时间测量方法。时间数字转换器（100）包括：无序信号生成单元（110），用于生成多个无序的时钟信号（S1310）；采样单元（120），用于接收多个无序的时钟信号和待测输入信号，利用待测输入信号对多个无序的时钟信号进行采样，并输出对应的实际采样结果（S1320）；解码单元（130），用于接收实际采样结果，并根据实际采样结果和与多个无序的时钟信号的时序相关的时序信息确定待测输入信号的特定边沿与多个无序的时钟信号中的选定时钟信号的特定边沿之间的时间差，以获得待测输入信号的细时间结果（S1330）；以及粗时间计数单元（140），用于接收选定时钟信号和待测输入信号，并以选定时钟信号作为计数时钟来对待测输入信号进行计数，以获得待测输入信号的粗时间结果（S1340）。该时间数字转换器的时间分辨率高。

Description

时间数字转换器和时间测量方法 技术领域
本发明涉及电路领域，具体地，涉及一种时间数字转换器和时间测量方法。
背景技术
高精度的时间数字转换器(Time-to-Digital Converters，TDC)技术广泛应用于时频测量、卫星导航、雷达定位、激光测距、医疗、核物理和粒子物理探测等领域。TDC的时间分辨率很大程度上影响着这些领域的先进程度。以医用全身正电子发射成像技术(PET)***为例，相比于传统无TDC的PET，时间分辨率为600ps的基于飞行时间(Time of flight，TOF)技术的PET(简称为TOF-PET)的图像信噪比可提高2.1倍，时间分辨率为100ps的TOF-PET的图像信噪比可提高5.2倍。
目前在TDC中广泛使用粗时间测量与细时间测量相结合的方法。粗时间测量是利用计数时钟对待测输入信号进行计数，根据计数结果计算待测输入信号的高电平持续时间。通过上述粗时间测量方法测量获得的高电平持续时间与实际的高电平持续时间之间存在误差，误差值与待测输入信号的边沿(本文主要以上升沿为例进行说明)和计数时钟的边沿之间的时间差相关。所述时间差可以通过细时间测量方法来测量。
目前最常用的细时间测量方法是基于FPGA(Field Programmable Gate Array，FPGA)内部加法进位链的时间内插法。时间内插法的原理为利用加法进位链对待测输入信号进行多次延时，利用计数时钟对所有延时信号进行锁存，并根据锁存得到的“1111…1110000…00”序列中1-0交界的位置计算待测输入信号的上升沿与计数时钟的上升沿之间的时间差。为了正确确定1-0交界的位置，需要保持延时信号的相位有序。例如，加法进位链中第n个加法器输出的延时信号的上升沿应当比第n-1个加法器输出的延时信号的上升沿滞后一段时间。锁存单元所接收到的各延时信号需要保持上述有序的相位关系，这可能需要依靠额外的硬件资源来控制。如果延时 信号的相位关系被打乱，则时间测量的精度会受到影响。此外，由于FPGA内部存在一些BIN宽较大(100ps左右)的加法进位链，因此限制了时间内插法的时间分辨率。目前大多采用定制波(Wave Union)的方法来消除这些较大BIN宽的影响，但消耗的FPGA内部资源较多，且由于寄存器亚稳态现象而产生的“气泡”现象难以解决。
因此，需要提供一种改进的时间测量技术，以至少部分地解决现有技术中存在的上述问题。
发明内容
为了至少部分地解决现有技术中存在的问题，根据本发明的一个方面，提供一种时间数字转换器。该时间数字转换器包括：无序信号生成单元，用于生成多个无序的时钟信号；采样单元，与无序信号生成单元连接，用于接收多个无序的时钟信号和待测输入信号，利用待测输入信号对多个无序的时钟信号进行采样，并输出对应的实际采样结果；解码单元，与采样单元连接，用于接收实际采样结果，并根据实际采样结果和与多个无序的时钟信号的时序相关的时序信息确定待测输入信号的特定边沿与多个无序的时钟信号中的选定时钟信号的特定边沿之间的时间差，以获得待测输入信号的细时间结果；以及粗时间计数单元，与无序信号生成单元连接，用于接收选定时钟信号和待测输入信号，并以选定时钟信号作为计数时钟来对待测输入信号进行计数，以获得待测输入信号的粗时间结果。
示例性地，采样单元还用于接收校准信号，利用校准信号对多个无序的时钟信号进行采样，并输出对应的校准采样结果；时间数字转换器还包括：定序单元，与采样单元和解码单元连接，用于接收校准采样结果，根据校准采样结果确定多个无序的时钟信号的时序，并将与多个无序的时钟信号的时序相关的时序信息输出到解码单元。
示例性地，时间数字转换器还包括：时钟管理单元，用于生成校准信号。
示例性地，时间数字转换器还包括：选择器，与时钟管理单元和采样单元连接，用于接收待测输入信号和时钟管理单元输出的校准信号，并选择将待测输入信号和校准信号之一输入到采样单元。
示例性地，无序信号生成单元包括：时钟管理单元，用于利用锁相环 生成至少一个初始时钟信号；以及延时单元，与时钟管理单元连接，用于对至少一个初始时钟信号进行延时，以将至少一个初始时钟信号转换为多个无序的时钟信号。
示例性地，延时单元包括以下项中的至少一项：至少一个加法器集合、多个逻辑门电路和多条延时线。
示例性地，至少一个加法器集合用于一一对应地接收至少一个初始时钟信号，其中，每个加法器集合用于组成一个加法进位链，将所接收的初始时钟信号作为对应的加法进位链的最低位输入信号，并从对应的加法进位链所输出的输出信号中选择预定数目的输出信号作为多个无序的时钟信号的至少一部分输出至采样单元。
示例性地，延时单元还包括：特定数目的查找表单元，与至少一个加法器集合中的特定数目的加法器集合一一对应地连接；其中，至少一个加法器集合经由特定数目的查找表单元将多个无序的时钟信号中的特定数目的无序的时钟信号输出至采样单元，并将剩余的无序的时钟信号直接输出至采样单元。
示例性地，多个逻辑门电路中的每个逻辑门电路用于接收至少一个初始时钟信号之一，并对所接收的初始时钟信号进行延时，其中，多个逻辑门电路中的至少部分逻辑门电路的延时时间彼此不同，其中，多个逻辑门电路中的预定数目的逻辑门电路与采样单元连接，预定数目的逻辑门电路用于将预定数目的延时后的时钟信号作为多个无序的时钟信号输出至采样单元。
示例性地，至少一个初始时钟信号的数目大于1，多条延时线用于一一对应地将至少一个初始时钟信号从时钟管理单元传输到采样单元，其中，多条延时线中的至少部分延时线的延时时间彼此不同。
示例性地，至少一个初始时钟信号的数目大于1，至少一个初始时钟信号的周期相同，并且至少一个初始时钟信号的相位均匀分布在0至180°的范围内。
示例性地，无序信号生成单元包括：时钟管理单元，用于利用锁相环生成多个无序的时钟信号。
示例性地，采样单元包括：多个寄存器，用于一一对应地接收多个无序的时钟信号，通过以待测输入信号作为锁存使能信号锁存多个无序的时 钟信号来对多个无序的时钟信号进行采样。
示例性地，时间数字转换器还包括：输出单元，与解码单元和粗时间计数单元连接，用于输出粗时间结果和细时间结果。
根据本发明另一方面，提供一种时间测量方法，包括：生成多个无序的时钟信号；利用待测输入信号对多个无序的时钟信号进行采样，以获得实际采样结果；根据实际采样结果和与多个无序的时钟信号的时序相关的时序信息确定待测输入信号的第一特定边沿与多个无序的时钟信号中的选定时钟信号的第一特定边沿之间的时间差，以获得待测输入信号的细时间结果；以及以选定时钟信号作为计数时钟来对待测输入信号进行计数，以获得待测输入信号的粗时间结果。
示例性地，在根据实际采样结果和与多个无序的时钟信号的时序相关的时序信息确定待测输入信号的第一特定边沿与多个无序的时钟信号中的选定时钟信号的第一特定边沿之间的时间差之前，时间测量方法还包括：利用校准信号对多个无序的时钟信号进行采样，以获得校准采样结果；以及根据校准采样结果确定多个无序的时钟信号的时序，以获得与多个无序的时钟信号的时序相关的时序信息。
示例性地，校准信号包括采样周期等于多个无序的时钟信号的周期的整数倍与预定时间间隔之和的第一采样信号和采样周期与多个无序的时钟信号的周期无关的第二采样信号，校准采样结果包括利用第一采样信号对多个无序的时钟信号进行采样所获得的第一采样结果和利用第二采样信号对多个无序的时钟信号进行采样所获得的第二采样结果，根据校准采样结果确定多个无序的时钟信号的时序包括：选择多个无序的时钟信号之一作为基准信号；根据第一采样结果中基准信号的取值估计基准信号的第二特定边沿的出现位置，确定在第二特定边沿的出现位置后面的最近采样位置为周期起始位置，并确定以周期起始位置为起点的、持续时间等于多个无序的时钟信号的周期的时间段为参考周期；统计第二采样结果中基准信号的每种取值的出现比例，以确定基准信号的高电平和/或低电平在参考周期中所占时间；根据第一采样结果中基准信号在周期起始位置处的取值和基准信号的高电平和/或低电平在参考周期中所占时间确定基准信号的时序；对于多个无序的时钟信号中的、除基准信号以外的每个时钟信号，统计第二采样结果中该时钟信号与基准信号的每种组合取值的出现比例；以及至 少根据第一采样结果中该时钟信号与基准信号在周期起始位置处的取值和第二采样结果中该时钟信号与基准信号的每种组合取值的出现比例，确定该时钟信号的时序。
示例性地，对于多个无序的时钟信号中的、除基准信号以外的每个时钟信号，至少根据第一采样结果中该时钟信号与基准信号在周期起始位置处的取值和第二采样结果中该时钟信号与基准信号的每种组合取值的出现比例，确定该时钟信号的时序包括：对于多个无序的时钟信号中的任一待定序的时钟信号，根据第二采样结果中待定序的时钟信号与基准信号的每种组合取值的出现比例确定待定序的时钟信号与基准信号的每种组合取值在参考周期中所占时间；如果待定序的时钟信号与基准信号的组合取值包括四种不同的组合取值并且每种组合取值在参考周期中所占时间大于预定时间间隔，则根据第一采样结果中待定序的时钟信号与基准信号在周期起始位置处的取值、第二采样结果中待定序的时钟信号和基准信号的组合取值确定待定序的时钟信号的时序；如果待定序的时钟信号与基准信号的组合取值包括四种不同的组合取值并且所包含的基准信号的取值与在第二特定边沿后出现的电平一致的两种组合取值中的任一种在参考周期中所占时间小于或等于预定时间间隔，则从已定序的时钟信号中选择第一辅助信号，根据第一辅助信号、待定序的时钟信号与基准信号的组合取值确定待定序的时钟信号的波形分布情况，并根据待定序的时钟信号的波形分布情况、第一采样结果中待定序的时钟信号与基准信号在周期起始位置处的取值、第二采样结果中待定序的时钟信号和基准信号的组合取值确定待定序的时钟信号的时序，其中，第一辅助信号与基准信号的组合取值包括四种不同的组合取值、每种组合取值在参考周期中所占时间大于预定时间间隔并且第一采样结果中第一辅助信号在周期起始位置处的取值与在第二特定边沿前出现的电平一致；如果待定序的时钟信号与基准信号的组合取值包括三种不同的组合取值，其中，在三种不同的组合取值中待定序的时钟信号的特定取值仅出现一次，则从已定序的时钟信号中选择第二辅助信号，并根据第二采样结果中第二辅助信号与待定序的时钟信号的组合取值确定待定序的时钟信号的时序，其中，第二辅助信号与基准信号的组合取值包括四种不同的组合取值并且在第二辅助信号与待定序的时钟信号的组合取值中待定序的时钟信号的特定取值出现两次。
示例性地，校准信号包括采样周期等于多个无序的时钟信号的周期的整数倍与预定时间间隔之和的第一采样信号和采样周期与多个无序的时钟信号的周期无关的第二采样信号，校准采样结果包括利用第一采样信号对多个无序的时钟信号进行采样所获得的第一采样结果和利用第二采样信号对多个无序的时钟信号进行采样所获得的第二采样结果，根据校准采样结果确定多个无序的时钟信号的时序包括：选择多个无序的时钟信号之一作为基准信号；重复执行以下定序操作直至确定多个无序的时钟信号的时序为止：根据第一采样结果中基准信号的取值估计基准信号的第二特定边沿的出现位置，确定在第二特定边沿的出现位置后面的最近采样位置为周期起始位置，并确定以周期起始位置为起点的、持续时间等于多个无序的时钟信号的周期的时间段为参考周期；对于多个无序的时钟信号中的、满足预设条件的待定序的时钟信号，根据第二采样结果中待定序的时钟信号与基准信号的每种组合取值的出现比例确定待定序的时钟信号与基准信号的每种组合取值在参考周期中所占时间，并根据第一采样结果中待定序的时钟信号与基准信号在周期起始位置处的取值、第二采样结果中待定序的时钟信号和基准信号的组合取值确定待定序的时钟信号的时序，其中，预设条件包括待定序的时钟信号与基准信号的组合取值包括四种不同的组合取值并且每种组合取值在参考周期中所占时间大于预设时间段，预设时间段与预定时间间隔相关；选择多个无序的时钟信号中的已定序的时钟信号之一作为新的基准信号；以及基于统一的周期起始位置对多个无序的时钟信号的时序进行校正。
根据本发明实施例的时间数字转换器和时间测量方法，由于利用无序的时钟信号来进行待测输入信号的细时间测量，因此可以避免较大BIN宽的存在，使得时间数字转换器能够具有很高的时间分辨率。此外，上述时间数字转换器所需要的硬件资源少，生产成本低。
在发明内容中引入了一系列简化的概念，这些概念将在具体实施方式部分中进一步详细说明。本发明内容部分并不意味着要试图限定所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
以下结合附图，详细说明本发明的优点和特征。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施方式及其描述，用来解释本发明的原理。在附图中，
图1示出根据本发明一个实施例的时间数字转换器的示意性框图；
图2示出根据本发明另一个实施例的时间数字转换器的示意性框图；
图3示出根据本发明另一个实施例的时间数字转换器的示意性框图；
图4示出根据本发明一个实施例的延时单元与采样单元的结构示意图；
图5示出根据本发明一个实施例的多个无序的时钟信号的示例性时序图；
图6示出根据本发明一个实施例的、采用第一采样信号对多个无序的时钟信号进行采样所获得的采样结果的示意图；
图7示出两种在周期起始位置处取值不同的时钟信号的波形分布情况；
图8示出根据本发明一个实施例的分布情况为普通均匀分布的待定序的时钟信号的示意图；
图9示出根据本发明一个实施例的分布情况为特殊分布的待定序的时钟信号的示意图；
图10a和10b分别示出根据本发明实施例的待定序的时钟信号的两种特殊分布的示意图；
图11示出根据本发明一个实施例的分布情况为集中分布的待定序的时钟信号的示意图；
图12示出根据本发明一个实施例的针对时间数字转换器的时间测量精度进行测试所获得的高斯分布结果；以及
图13示出根据本发明一个实施例的时间测量方法的示意性流程图。
具体实施方式
在下文的描述中，提供了大量的细节以便能够彻底地理解本发明。然而，本领域技术人员可以了解，如下描述仅涉及本发明的较佳实施例，本发明可以无需一个或多个这样的细节而得以实施。此外，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
为了解决上述问题，本发明提出一种时间数字转换器和时间测量方法，其通过无序的时钟信号来测量待测输入信号的细时间信息。在根据本发明 实施例的时间数字转换器和时间测量方法中，无需保证时钟信号的相位有序，可以实现比现有技术更精细的时间测量。
本文所述的待测输入信号可以是任何需要测量其时间信息的电信号。例如，待测输入信号可以是PET***的读出电路所输出的电信号。当PET***的前端光子检测器检测到伽玛光子时，可以输出一个脉冲信号，该脉冲信号通常称为HIT。待测输入信号可以是所述脉冲信号。
图1示出根据本发明一个实施例的时间数字转换器100的示意性框图。如图1所示，时间数字转换器100包括无序信号生成单元110、采样单元120、解码单元130和粗时间计数单元140。
无序信号生成单元110用于生成多个无序的时钟信号。无序信号生成单元110生成的多个时钟信号周期相同，但是相位和占空比不完全相同。该多个时钟信号是无序的，它们的上升沿或下降沿(或说高电平区域或低电平区域)并未有序地、规律性地分布，而是分散地、无规律性地分布在整个时钟周期(即无序的时钟信号的周期)中。
采样单元120与无序信号生成单元110连接，用于接收多个无序的时钟信号和待测输入信号，利用待测输入信号对多个无序的时钟信号进行采样，并输出对应的实际采样结果。
示例性地，可以利用待测输入信号作为锁存使能信号来对多个无序的时钟信号进行锁存。当待测输入信号的边沿(例如上升沿)到达时，多个无序的时钟信号被锁存。在已获知多个无序的时钟信号的时序的情况下，根据利用待测输入信号对多个无序的时钟信号进行采样所获得的采样结果可以计算出待测输入信号的特定边沿与多个无序的时钟信号的特定边沿之间的时间差，即可以获得待测输入信号的细时间信息。
解码单元130与采样单元120连接，用于接收实际采样结果，并根据实际采样结果和与多个无序的时钟信号的时序相关的时序信息确定待测输入信号的特定边沿与多个无序的时钟信号中的选定时钟信号的特定边沿之间的时间差，以获得待测输入信号的细时间结果。
示例性地，时间数字转换器100还可以包括单独的存储单元，与多个无序的时钟信号的时序相关的时序信息可以存储在该存储单元中。示例性地，解码单元130内部可以包括存储单元，与多个无序的时钟信号的时序相关的时序信息可以存储在解码单元130的存储单元中。示例性地，与多 个无序的时钟信号的时序相关的时序信息还可以存储在如下文所述的定序单元中。定序单元确定多个无序的时钟信号的时序之后，可以建立定序查找表，并将与多个无序的时钟信号的时序相关的时序信息存储在定序查找表中。
所述选定时钟信号可以是多个无序的时钟信号中的任一时钟信号，其可以任意选择，本发明不对此进行限制。可以从多个无序的时钟信号中任意选择一个时钟信号作为粗时间计数所用的时钟信号，解码单元130可以仅确定待测输入信号的特定边沿与所选择的时钟信号的特定边沿之间的时间差。当然，解码单元130也可以确定待测输入信号的特定边沿与所有无序的时钟信号的特定边沿之间的时间差。上述特定边沿可以是上升沿或下降沿，本发明不对此进行限制。
粗时间计数单元140与无序信号生成单元110连接，用于接收选定时钟信号和待测输入信号，并以选定时钟信号作为计数时钟来对待测输入信号进行计数，以获得待测输入信号的粗时间结果。
粗时间计数单元140的工作方式与常规技术中的粗时间计数方式一致。示例性地，粗时间计数单元140可以采用直接计数法对待测输入信号进行计数。
由上文所述可知，粗时间结果是利用诸如直接计数法所计算获得的待测输入信号的高电平持续时间的初步测量结果。该初步测量结果与待测输入信号的实际的高电平持续时间之间存在一定误差。细时间测量主要是为了测量上述误差多大。因此，待测输入信号的时间信息可以包括粗时间结果和细时间结果两方面。所获得的粗时间结果和细时间结果可以传输到时间数字转换器中的处理单元中进行进一步处理，也可以输出到外部设备以由外部设备进行进一步处理。
在现有技术中，粗时间测量是利用计数时钟对待测输入信号进行计数，细时间测量是利用同样的计数时钟对待测输入信号的多个延时信号进行锁存，来确定待测输入信号的边沿与该计数时钟的边沿(例如待测输入信号的上升沿与该计数时钟的上升沿)之间的时间差。而根据本发明实施例，细时间测量是利用待测输入信号对多个无序的时钟信号进行采样，以确定待测输入信号的边沿与选定时钟信号的边沿(例如待测输入信号的上升沿与选定时钟信号的上升沿)之间的时间差。粗时间测量是利用选定时钟信 号对待测输入信号进行计数。可见，上述时间数字转换器100的时间测量方式与现有技术中的时间测量方式是不同的，尤其细时间测量的区别很大。
根据本发明实施例的时间数字转换器，由于用来进行待测输入信号的细时间测量的时钟信号是无序的时钟信号，其上升沿或下降沿(或说高电平区域或低电平区域)可以任意地、分散地分布在整个时钟周期中，因此可以避免较大BIN宽的存在，使得时间数字转换器能够具有很高的时间分辨率。此外，电路的布局布线、器件的响应速度等都会对信号的延时产生影响，因此保持信号无序比保持信号有序更容易实现。由于无需保持时钟信号的相位有序，因此上述时间数字转换器所需要的硬件资源少，生产成本低。
根据本发明实施例，时间数字转换器还可以包括输出单元。图2示出根据本发明另一个实施例的时间数字转换器200的示意性框图。应理解，图2所示的时间数字转换器200仅是示例而非限制，本发明并不局限于图2所示的电路结构。
图2所示的无序信号生成单元210、采样单元220、解码单元230和粗时间计数单元240与图1所示的无序信号生成单元110、采样单元120、解码单元130和粗时间计数单元140的结构和工作原理一致，不再赘述。如图2所示，时间数字转换器200还可以包括输出单元250。
输出单元250与解码单元230和粗时间计数单元240连接，用于输出粗时间结果和细时间结果。
示例性地，输出单元250可以包括先入先出(First Input First Output，FIFO)单元和通用异步收发传输器(Universal Asynchronous Receiver/Transmitter，UART)单元。
输出单元250可以将粗时间结果和细时间结果一起输出到外部设备，例如移动终端、个人计算机或服务器等，以方便外部设备对接收到的时间信息进行进一步处理。
根据本发明实施例，时间数字转换器还可以包括定序单元。继续参考图2，时间数字转换器200还可以包括定序单元260。
采样单元120还可以用于接收校准信号，利用校准信号对多个无序的时钟信号进行采样，并输出对应的校准采样结果。定序单元260与采样单元220和解码单元230连接，用于接收校准采样结果，根据校准采样结果 确定多个无序的时钟信号的时序，并将与多个无序的时钟信号的时序相关的时序信息输出到解码单元230。
为了测量待测输入信号的细时间信息，需要知道多个无序的时钟信号的时序。在一个示例中，可以在时间数字转换器200第一次工作时，使用定序单元260确定多个无序的时钟信号的时序(可以称为定序)。之后每次测量待测输入信号的时间信息时，可以使用存储好的与多个无序的时钟信号的时序相关的时序信息。在另一个示例中，可以在每次测量待测输入信号的时间信息之前，均使用定序单元260确定多个无序的时钟信号的时序。
使用定序单元260确定多个无序的时钟信号的时序的过程可以视为校准过程。在校准过程中，采样单元220利用校准信号对多个无序的时钟信号进行采样。定序单元260接收采样单元220的采样结果并根据该采样结果确定多个无序的时钟信号的时序。在实际测量过程中，采样单元220利用待测输入信号对多个无序的时钟信号进行采样。解码单元230接收采样单元220的采样结果，并根据该采样结果与已确定的多个无序的时钟信号的时序来确定待测输入信号的边沿的位置，并由此可以确定待测输入信号的特定边沿与任一无序的时钟信号的特定边沿之间的时间差。
“定序”就是确定多个无序的时钟信号的高电平区域和低电平区域在一个时钟周期中的准确位置，或者确定多个无序的时钟信号的上升沿和下降沿在一个时钟周期中的准确位置。
定序单元260可以建立定序查找表(Look-Up-Table，LUT)以便在解码过程中使用。下面的表1示例性地示出定序查找表的一种形式。如表1所示，定序查找表可以记录n个无序的时钟信号的高电平范围和低电平范围。当然，n个无序的时钟信号的高电平范围和低电平范围是以某一预设时刻为时间轴起点开始计算的。该预设时刻可以是n个无序的时钟信号中的某一时钟信号的高电平起始时刻。
表1.定序查找表结构
Figure PCTCN2017116915-appb-000001
在建立定序查找表的情况下，“解码”就是根据定序过程产生的定序查找表得出待测输入信号的上升沿和/或下降沿在一个时钟周期中的准确位置。例如，假设实际采样结果为“10100011……11000”(n位)，从最低位开始解码，第1位信号值为‘0’，假设根据定序查找表得到的时间范围为I 1＝(200，500)，同理可以得到第2位、第3位到第n位信号值所对应的时间范围，分别用I 2、I 3、……I n-1、I n表示，则待测输入信号的边沿(上升沿或下降沿)在时钟周期中的位置即为对上述各个时间范围进行交集运算所获得的结果：I＝I 1∩I 2∩I 3……∩I n-1∩I n。可选地，可以取I的中点值作为该待测输入信号的边沿(上升沿或下降沿)所在位置的最终结果。
可以理解，如果用于粗时间测量的选定时钟信号是其高电平起始时刻作为定序查找表的时间轴起点的时钟信号，则通过上述方式计算获得的待测输入信号的特定边沿(上升沿或下降沿)在时钟周期中的位置即为待测输入信号的细时间结果。如果用于粗时间测量的选定时钟信号不是其高电平起始时刻作为定序查找表的时间轴起点的时钟信号，则根据定序查找表可以确定选定时钟信号的边沿在时钟周期中的位置，结合计算获得的待测 输入信号的边沿在时钟周期中的位置同样可以确定待测输入信号的特定边沿与选定时钟信号的特定边沿之间的时间差，即可获得待测输入信号的细时间结果。
根据本发明实施例，无序信号生成单元110(或210)可以包括时钟管理单元和延时单元。图3示出根据本发明另一个实施例的时间数字转换器300的示意性框图。图3所示的采样单元320、解码单元330、粗时间计数单元340、输出单元350和定序单元360与图2所示的采样单元220、解码单元230、粗时间计数单元240、输出单元250和定序单元260的结构和工作原理一致，不再赘述。图3所示的时间数字转换器300的无序信号生成单元包括时钟管理单元312和延时单元314。
时钟管理单元312用于利用锁相环生成至少一个初始时钟信号。延时单元314与时钟管理单元312连接，用于对至少一个初始时钟信号进行延时，以将至少一个初始时钟信号转换为多个无序的时钟信号。
时钟管理单元312可以利用FPGA内部的时钟管理模块(Digit Clock Manager，DCM)实现。时钟管理单元312内部包括锁相环(Phase Locked Loop，PLL)，锁相环可以根据需要产生具有各种周期(或说频率)和相位的时钟信号。
延时单元314可以是各种合适的能够对时钟信号进行延时的装置。示例性而非限制性地，延时单元314可以通过缓冲器延时、逻辑门延时或线路延时等方式使初始时钟信号在延时单元314内部发生延时。延时单元314还可以包括加法器，通过加法器组成的加法进位链对初始时钟信号进行延时。
延时单元314在对初始时钟信号进行延时时，可以对不同的初始时钟信号进行不同量的延时，以尽量使延时后的时钟信号的上升沿或下降沿(或说高电平区域或低电平区域)分散地分布在整个时钟周期中。延时单元314所输出的时钟信号的相位无需保证一定的顺序，因此对于延时单元314的硬件及软件设计要求都比较低。
每个初始时钟信号可以延时产生任意数目的无序的时钟信号，本发明不对此进行限制。
利用延时单元314可以比较方便地生成所需的无序的时钟信号。
根据本发明实施例，延时单元314可以包括以下项中的至少一项：至 少一个加法器集合、多个逻辑门电路和多条延时线。示例性而非限制性地，可以采用加法器、逻辑门或延时线等对初始时钟信号进行延时。
根据本发明实施例，至少一个加法器集合用于一一对应地接收至少一个初始时钟信号，其中，每个加法器集合用于组成一个加法进位链，将所接收的初始时钟信号作为对应的加法进位链的最低位输入信号，并从对应的加法进位链所输出的输出信号中选择预定数目的输出信号作为多个无序的时钟信号的至少一部分输出至采样单元。
图4示出根据本发明一个实施例的延时单元与采样单元的结构示意图。在图4所示的示例中，时钟管理单元312所生成的初始时钟信号为4路，即clk1、clk2、clk3、clk4。延时单元314所输出的无序的时钟信号为96路。如图4所示，延时单元314包括4个加法器集合。每个加法器集合包括40个加法器，组成一个40位的加法进位链。采样单元320包括96个寄存器。图4所示的延时单元和采样单元的结构仅是示例而非限制。例如，延时单元314中的加法器集合的数目、每个加法器集合中的加法器的数目、输出至采样单元320的时钟信号的数目及采样单元320中的相应的寄存器的数目均是可以任意设定的，并不局限于图4所示的示例。
延时单元314与采样单元320可以实现一种新的时间内插方式。如图4所示，延时单元314可以产生96路无序同周期的方波信号，其可将粗时间计数单元340中用来计数的时钟周期分成96*2份。在采样单元320中由待测输入信号或校准信号使能96个寄存器来对方波信号进行锁存。
如图4所示，clk1、clk2、clk3和clk4为PLL产生的四个频率为1GHz，相位分别是0°、45°、90°和135°的初始时钟信号，它们分别输入四个40位的加法进位链中作为最低位加法器的一个输入。下面以clk1为例进行说明。当clk1为低电平0时，对应的加法进位链的输出Sum0～Sum39都为1；当clk1跳变为高电平1时，输出Sum0～Sum39将依次变为0。因此，Sum0～Sum39都是频率为1GHz的方波信号。可以从Sum0～Sum39中选取24路信号引入到采样单元320中，通过采样单元320中的寄存器进行锁存(即采样)。在校准阶段，锁存使能信号signal为校准信号。在实际测量阶段，锁存使能信号signal为待测输入信号。对clk2、clk3、clk4执行相同操作，即可得到96位同周期、不同相位的时钟信号及其采样结果。
根据本发明实施例，延时单元314还可以包括：特定数目的查找表单 元，与至少一个加法器集合中的特定数目的加法器集合一一对应地连接；其中，至少一个加法器集合经由特定数目的查找表单元将多个无序的时钟信号中的特定数目的无序的时钟信号输出至采样单元320，并将剩余的无序的时钟信号直接输出至采样单元320。
在FPGA中搭建时间数字转换器时，可以采用Quartus Prime编译器进行自动布局布线。布局布线会导致时钟信号的传输路线存在差异。在将加法器集合输出的时钟信号输入到采样单元320的各寄存器的过程中，可以使某些时钟信号经由查找表(LUT)单元输入寄存器。LUT单元可以进一步导致时钟信号发生延时。经过不同的路径和不同的LUT单元，时钟信号的延时情况也不同。在加法进位链输出端到寄存器的输入端之间，有些时钟信号经过了LUT单元的缓冲，有些则直接连入寄存器中。LUT单元带来的延时，加上路径延时的不同，可以拉大各路时钟信号之间的相位差异。
根据本发明实施例，多个逻辑门电路中的每个逻辑门电路用于接收至少一个初始时钟信号之一，并对所接收的初始时钟信号进行延时，其中，多个逻辑门电路中的至少部分逻辑门电路的延时时间彼此不同，其中，多个逻辑门电路中的预定数目的逻辑门电路与采样单元320连接，预定数目的逻辑门电路用于将预定数目的延时后的时钟信号作为多个无序的时钟信号输出至采样单元。
可以使用逻辑门电路取代上述至少一个加法器集合中的加法器。逻辑门电路具有延时功能，作用与加法器类似。示例性地，时钟管理单元312可以生成具有不同相位的多个初始时钟信号，并将其分别输入到不同逻辑门电路。示例性地，时钟管理单元312也可以生成一个初始时钟信号，并将其输入到不同逻辑门电路。示例性地，与采样单元320连接的预定数目的逻辑门电路可以是多个逻辑门电路中的一部分或者全部。
根据本发明实施例，至少一个初始时钟信号的数目大于1，多条延时线用于一一对应地将至少一个初始时钟信号从时钟管理单元312传输到采样单元320，其中，多条延时线中的至少部分延时线的延时时间彼此不同。
可以单纯地采用延时时间不同的多条延时线对初始时钟信号进行延时，以获得多个无序的时钟信号。例如，至少部分延时线的长度可以彼此不同，以使得其延时时间彼此不同。
根据本发明实施例，至少一个初始时钟信号的数目大于1，至少一个 初始时钟信号的周期相同，并且至少一个初始时钟信号的相位均匀分布在0至180°的范围内。
参考图4，初始时钟信号共有4路，即clk1、clk2、clk3、clk4。clk1、clk2、clk3和clk4的相位分别是0°、45°、90°和135°，这四个初始时钟信号的相位均匀地分布在0至180°的范围内。示例性而非限制地，可以使按顺序排列的两个相邻初始时钟信号的相位间隔等于或大致等于180°/n，n为初始时钟信号的数目，这样可以使初始时钟信号的相位尽量均匀地分布。通过引入存在相位差的多路初始时钟信号，可以保证最终获得的多个无序的时钟信号的边沿在一个时钟周期内分布得较为分散和均匀，不会出现BIN宽很大的情况。
根据本发明实施例，无序信号生成单元110(或210)可以包括时钟管理单元，用于利用锁相环生成多个无序的时钟信号。
示例性地，可以利用FPGA中的PLL直接生成多个无序的时钟信号。PLL可以根据需要生成各种周期、相位的时钟信号，因此可以利用PLL直接生成周期相同、相位不同的多个信号作为所需的无序的时钟信号。
可以理解，上述生成多个无序的时钟信号的方式仅是示例而非对本发明的限制，本领域技术人员通过阅读本文可以想到其他采用合适的硬件和/或软件来生成多个无序的时钟信号的方式，其均应落入本发明的保护范围。
根据本发明实施例，时间数字转换器100(200、300)还可以包括：时钟管理单元，用于生成校准信号。
示例性地，校准信号可以包括采样周期与多个无序的时钟信号的周期存在一定关系的采样信号及采样周期与多个无序的时钟信号的周期完全无关的采样信号。也就是说，校准信号也可以是具有一定周期的时钟信号，因此可以采用时钟管理单元生成。用于生成校准信号的时钟管理单元可以与上述用于生成初始时钟信号的时钟管理单元312是同一单元。
示例性地，时间数字转换器还包括选择器。返回参考图3，时间数字转换器300还可以包括选择器370。选择器370与时钟管理单元312和采样单元320连接，用于接收待测输入信号和时钟管理单元312输出的校准信号，并选择将待测输入信号和校准信号之一输入到采样单元320。选择器370由控制信号来控制将哪个信号输入到采样单元320进行采样。虽然图3中示出粗时间计数单元340与选择器370连接，待测输入信号经由选 择器370输入粗时间计数单元340，但是可以理解的是，待测输入信号也可以直接输入粗时间计数单元340。
根据本发明实施例，采样单元120(220、320)可以包括多个寄存器，多个寄存器用于一一对应地接收多个无序的时钟信号，通过以待测输入信号作为锁存使能信号锁存多个无序的时钟信号来对多个无序的时钟信号进行采样。
上文已经参考图4描述了采样单元中的寄存器的结构及工作原理，在此不再赘述。应注意，在实际测量待测输入信号的时间信息时，以待测输入信号作为锁存使能信号锁存多个无序的时钟信号，而在校准过程中，需要以校准信号作为锁存使能信号锁存多个无序的时钟信号。
下面结合图5至图11描述上述定序单元260(或360)的定序过程。在下面关于定序过程的描述中，沿用图4所示的96路无序时钟信号的示例。
图5示出根据本发明一个实施例的多个无序的时钟信号的示例性时序图。在图5中，线段510和520分别表示一个时钟周期T的起始位置和结束位置，线段530表示某一次的采样位置。图5示出的是96路无序时钟信号的时序图。当利用校准信号或待测输入信号采样时，在线段530所对应的时刻可以获得一次采样结果，如图5所示。
下面描述定序单元260的定序过程的两个示例。
第一示例
根据本发明实施例，校准信号可以包括采样周期等于多个无序的时钟信号的周期的整数倍与预定时间间隔之和的第一采样信号和采样周期与多个无序的时钟信号的周期无关的第二采样信号，校准采样结果可以包括利用第一采样信号对多个无序的时钟信号进行采样所获得的第一采样结果和利用第二采样信号对多个无序的时钟信号进行采样所获得的第二采样结果，定序单元260(或360)可以通过以下方式确定多个无序的时钟信号的时序：选择多个无序的时钟信号之一作为基准信号；根据第一采样结果中基准信号的取值估计基准信号的特定边沿的出现位置，确定在特定边沿的出现位置后面的最近采样位置为周期起始位置，并确定以周期起始位置为起点的、持续时间等于多个无序的时钟信号的周期的时间段为参考周期；统计第二采样结果中基准信号的每种取值的出现比例，以确定基准信号的高电平和/或低电平在参考周期中所占时间；根据第一采样结果中基准信号在周期起 始位置处的取值和基准信号的高电平和/或低电平在参考周期中所占时间确定基准信号的时序；对于多个无序的时钟信号中的、除基准信号以外的每个时钟信号，统计第二采样结果中该时钟信号与基准信号的每种组合取值的出现比例；以及对于多个无序的时钟信号中的、除基准信号以外的每个时钟信号，至少根据第一采样结果中该时钟信号与基准信号在周期起始位置处的取值和第二采样结果中该时钟信号与基准信号的每种组合取值的出现比例，确定该时钟信号的时序。
为了实现定序，时间数字转换器100(200、300)可以实施以下几个步骤：选择基准信号、采用第一采样信号进行采样、采用第二采样信号进行采样、逐个信号进行定序。具体描述如下：
(1)、选择基准信号
示例性而非限制性地，当采用加法器实现延时单元314时，定序单元260(或360)可以从多个无序的时钟信号中选择与加法进位链中的最低位输出信号对应的时钟信号作为基准信号。选定基准信号之后，可以以基准信号的高电平起始位置作为多个无序的时钟信号的一个完整时钟周期的起始位置，即t＝0的位置。基准信号的高电平起始位置可以根据第一采样结果确定，其将在下文中描述。为了方便后续的定序步骤，基准信号最好选取占空比接近50％的时钟信号。
(2)、采用第一采样信号进行采样
在一个示例中，可以采用49M时钟对多个无序的时钟信号进行采样。49M时钟是频率为49MHz的时钟，其时钟周期为10 6/49ps。可以对49M时钟进行计数，并在每经过490027个时钟周期时采样一次。两次采样之间的时间间隔(即采样周期)是固定值，大小为490027×10 6/49ps。
沿用上述示例，假设无序信号生成单元110(或210)采用1GHz的时钟来生成多个无序的时钟信号，则多个无序的时钟信号的周期为1000ps。第一采样信号的采样周期与多个无序的时钟信号的周期之间存在以下关系：
Figure PCTCN2017116915-appb-000002
参考式(1)可知，采用第一采样信号对多个无序的时钟信号进行采样时，采样周期10 6×490027/49ps是无序的时钟信号的周期1000ps的10000551倍与20.4ps之和，20.4ps即为本文所述的预定时间间隔。因此， 假设第1次采样位于时钟信号X的第1个周期的第10ps处，则第2次采样将位于时钟信号X的第10000552个周期的第30.4ps处，第三次采样将位于时钟信号X的第2001103个周期的第50.8ps处，依此类推。应当理解，每49次连续的采样结果可以代表在同一个完整的1000ps周期内进行采样所获得的采样结果，因此两次采样的时间间隔可以视为20.4ps。在校准过程中，可以进行大量(例如次数在1000次以上)采样，根据采样结果估计基准信号在某一周期内的高电平起始位置。将该高电平起始位置后面的最近采样位置近似为周期起始位置，并选择从该周期起始位置开始计算的49次采样结果作为利用第一采样信号在无序的时钟信号的一个周期内进行采样所获得的采样结果。此外，还可以将以周期起始位置为起点的、持续时间等于多个无序的时钟信号的周期的时间段作为参考周期。
图6示出根据本发明一个实施例的、采用第一采样信号对多个无序的时钟信号进行采样所获得的采样结果的示意图。在图6中，两个较长的线段分别表示参考周期的实际的周期起始位置和实际的周期结束位置，较短的线段表示采样位置。
可以将如图6所示的采样序号为1的采样位置近似为参考周期的周期起始位置，这是采用具有固定时间间隔的采样信号进行采样的目的所在。实际上，采样序号为1的采样位置非常接近实际的周期起始位置，采样序号为49的采样位置非常接近实际的周期结束位置。由于是近似结果，所以会导致一定误差，这将在下文讨论。确定周期起始位置之后，多个无序的时钟信号在周期起始位置处的取值即可确定。应注意，在图6至图11中，所标识出的周期起始位置为实际的周期起始位置。
可以理解的是，如果各路时钟信号在周期起始位置处的取值确定，则其在参考周期内的大致波形分布就可以确定了，如图7所示。图7示出两种在周期起始位置处取值不同的时钟信号的波形分布情况。可以理解，如果某时钟信号在周期起始位置处的取值为低电平，则其波形分布应类似于图7所示的上方波形，即在一个参考周期中，时钟信号的中间部分为高电平区域，两侧为低电平区域。同样，如果某时钟信号在周期起始位置处的取值为高电平，则其波形分布应类似于图7所示的下方波形，即在一个参考周期中，时钟信号的中间部分为低电平区域，两侧为高电平区域。
(3)、采用第二采样信号进行采样
在本步骤中，可以使用统计法采样法，即利用与多个无序的时钟信号的周期(或说频率)完全无关的时钟进行大量采样。只要采样次数足够多，采样信号可以在无序的时钟信号的一个周期内呈现均匀分布。为了实现统计采样，可以利用第二采样信号进行大量(例如5000次)采样。在一个示例中，可以采用9.992038M时钟(频率为9.992038MHz)对多个无序的时钟信号进行采样。与49M时钟类似地，使用9.992038M时钟进行统计采样时，也可以对时钟周期进行计数，在经过若干次时钟周期之后采样一次。
通过对得到的第二采样结果进行分析，可以得到96路时钟信号中两个或更多个时钟信号的任意组合取值的出现比例，进而可以获得任意组合取值在参考周期中所占时间。例如，如果期望得到基准信号与第10路信号的组合取值为“11”的时间间隔，只需要统计出第二采样结果中出现基准信号＝‘1’且第10路信号＝‘1’的采样结果的次数，记为F11，则基准信号与第10路信号的组合取值“11”在参考周期中所占时间t可以表示为下式：
Figure PCTCN2017116915-appb-000003
在式(2)中，N为第二采样结果中的所有采样结果的数目，T为多个无序的时钟信号的周期。
(4)、逐个信号进行定序
首先对基准信号进行定序。如上文所述，在确定周期起始位置时，需要确定基准信号的高电平起始位置。当然，基准信号的低电平起始位置也可以视为周期起始位置，为了描述方便，本文仅以其高电平起始位置作为示例进行描述。示例性地，可以从第一采样结果中找出代表基准信号从低电平转变为高电平的两个相邻采样位置处的取值，这两个取值分别为‘0’和‘1’。可以确定基准信号的高电平起始位置在这两个采样位置之间。随后，可以将所找出的取值为‘1’的采样位置视为周期起始位置。此外，还可以将该周期起始位置视为基准信号的上升沿在参考周期中的位置。
随后，可以统计第二采样结果中基准信号的每种取值的出现比例，以确定基准信号的高电平在参考周期中所占时间。已知基准信号在周期起始位置处的取值为‘1’以及基准信号的高电平在参考周期中所占时间，可以非常容易地确定基准信号的下降沿在参考周期中的位置。当确定基准信号的上升沿和下降沿的位置时，基准信号的定序完成。
根据本发明实施例，定序单元260(或360)通过以下方式实施对于多个无序的时钟信号中的、除基准信号以外的每个时钟信号，至少根据第一采样结果中该时钟信号与基准信号在周期起始位置处的取值和第二采样结果中该时钟信号与基准信号的每种组合取值的出现比例，确定该时钟信号的时序的步骤：对于多个无序的时钟信号中的任一待定序的时钟信号，根据第二采样结果中待定序的时钟信号与基准信号的每种组合取值的出现比例确定待定序的时钟信号与基准信号的每种组合取值在参考周期中所占时间；如果待定序的时钟信号与基准信号的组合取值包括四种不同的组合取值并且每种组合取值在参考周期中所占时间大于预定时间间隔，则根据第一采样结果中待定序的时钟信号与基准信号在周期起始位置处的取值、第二采样结果中待定序的时钟信号和基准信号的组合取值确定待定序的时钟信号的时序；如果待定序的时钟信号与基准信号的组合取值包括四种不同的组合取值并且所包含的基准信号的取值与在第二特定边沿后出现的电平一致的两种组合取值中的任一种在参考周期中所占时间小于或等于预定时间间隔，则从已定序的时钟信号中选择第一辅助信号，根据第一辅助信号、待定序的时钟信号与基准信号的组合取值确定待定序的时钟信号的波形分布情况，并根据待定序的时钟信号的波形分布情况、第一采样结果中待定序的时钟信号与基准信号在周期起始位置处的取值、第二采样结果中待定序的时钟信号和基准信号的组合取值确定待定序的时钟信号的时序，其中，第一辅助信号与基准信号的组合取值包括四种不同的组合取值、每种组合取值在参考周期中所占时间大于预定时间间隔并且第一采样结果中第一辅助信号在周期起始位置处的取值与在第二特定边沿前出现的电平一致；如果待定序的时钟信号与基准信号的组合取值包括三种不同的组合取值，其中，在三种不同的组合取值中待定序的时钟信号的特定取值仅出现一次，则从已定序的时钟信号中选择第二辅助信号，并根据第二采样结果中第二辅助信号与待定序的时钟信号的组合取值确定待定序的时钟信号的时序，其中，第二辅助信号与基准信号的组合取值包括四种不同的组合取值并且在第二辅助信号与待定序的时钟信号的组合取值中待定序的时钟信号的特定取值出现两次。
在对其他时钟信号进行定序时，可以根据它们与基准信号之间的相位关系，将它们分为三类进行定序：普通均匀分布、特殊分布和集中分布。
(a)、普通均匀分布
均匀分布是指待定序的时钟信号的上升沿和下降沿分别分布在基准信号的高电平时段和低电平时段。也就是说，分布情况为均匀分布的待定序的时钟信号与基准信号的组合取值包括四种不同的组合取值：“11”、“10”、“01”和“00”。均匀分布可以分为普通均匀分布和特殊分布两种情况。普通均匀分布是指待定序的时钟信号的四种组合取值在参考周期中所占时间均大于预定时间间隔，在上文所述的示例中该预定时间间隔为20.4ps。
应当理解，本文所述的待定序的时钟信号与基准信号的组合取值可以包括待定序的时钟信号的取值在前基准信号的取值在后以及基准信号的取值在前待定序的时钟信号取值在后这两种情况。也就是说，在描述时钟信号的组合取值时，本文并未限定各时钟信号的取值的排列顺序，在示例中特别指出的除外。
图8示出根据本发明一个实施例的分布情况为普通均匀分布的待定序的时钟信号的示意图。如上文所述，在确定周期起始位置之后，可以确定多个无序的时钟信号在周期起始位置处的取值。参考图8，待定序的时钟信号在周期起始位置处的取值为‘0’。
此外，可以计算第二采样结果中待定序的时钟信号与基准信号的各种组合取值的出现比例，即计算组合取值为“11”、“10”、“00”、“01”这四种情况的出现比例。根据每种组合取值的出现比例可以确定该组合取值在参考周期中所占时间，即图8中序号为1、2、3、4的四段时间间隔，计算方式可以参考式(2)。根据第一采样结果中待定序的时钟信号与基准信号在周期起始位置处的取值可以确定待定序的时钟信号与基准信号的大致波形分布，结合“11”、“10”、“00”、“01”这四种组合取值在参考周期中所占时间，可以很容易地求得待定序的时钟信号的上升沿与下降沿在参考周期中的位置，完成相应的定序查找表。
(b)、特殊分布
特殊分布是均匀分布中的特殊情况。由于在确定周期起始位置时，将在基准信号的特定边沿的出现位置(例如上文所述的高电平起始位置)后面的最近采样位置(如图6所示的采样序号为1的采样位置)近似为周期起始位置，并将在该最近采样位置处获得的采样结果作为各无序的时钟信号在周期起始位置处的取值，因此可能出现由于时钟信号在实际的周期起 始位置处的取值与在该最近采样位置处的取值不同而导致的误差。图9示出根据本发明一个实施例的分布情况为特殊分布的待定序的时钟信号的示意图。如图9所示，待定序的时钟信号在实际的周期起始位置处的取值为‘0’，但其在采样序号为1的采样位置处的取值为‘1’。因此，将采样序号为1的采样位置近似为周期起始位置会造成待定序的时钟信号的初始取值判断错误，进而造成待定序的时钟信号的整个波形分布判断错误。
由图9所示的波形可知，在基准信号与待定序的时钟信号的组合取值“11”或“10”(基准信号的取值在前，待定序的时钟信号的取值在后)小于或等于预定时间间隔(例如20.4ps)的情况下，可能出现上述波形分布判断错误。因此，可以将这种情况称为特殊分布情况。总之，如果待定序的时钟信号与基准信号的组合取值包括四种不同的组合取值并且所包含的基准信号的取值与在特定边沿(如图9所示的上升沿)后出现的电平(如图9所示的高电平)一致的两种组合取值(如图9所示的组合取值“11”和“10”)中的任一种在参考周期中所占时间小于或等于预定时间间隔，则确定待定序的时钟信号的波形分布属于特殊分布。
虽然上面描述了特殊分布的特点，然而满足上述特点的波形分布却不一定会导致波形分布判断错误。实际上，特殊分布可以分为两种情况。图10a和10b分别示出根据本发明实施例的待定序的时钟信号的两种特殊分布的示意图。
在图10a和图10b中，基准信号与待定序的时钟信号的组合取值“10”(基准信号的取值在前，待定序的时钟信号的取值在后)的时间间隔都小于预定时间间隔(例如20.4ps)，但是只有图10a的波形分布可能会由于近似错误而导致波形分布判断错误。
为了区分这两种情况，可以引入第一辅助信号，如图10a和图10b所示。该第一辅助信号具有以下特点：自身已经完成定序；基准信号与第一辅助信号的四种组合取值“11”、“10”、“01”和“00”在参考周期中所占时间都大于预定时间间隔(例如20.4ps)；第一辅助信号在周期起始位置处的取值(如图6所示的采样序号为1的采样位置处的采样结果)与在特定边沿(如图9所示的上升沿)前出现的电平(如图9所示的低电平)一致。
加入第一辅助信号之后，对于基准信号、待定序的时钟信号和第一辅助信号的组合取值来说，图10a会有“100”出现，而图10b有“101”出 现。由此可以完成两种特殊分布的区分。如果待定序的时钟信号的波形分布属于图10a所示的那种情况，则可以重新确定待定序的时钟信号在周期起始位置处的取值，例如原本是‘1’的修正为‘0’。随后可以根据修正后的待定序的时钟信号与在周期起始位置处的取值与基准信号在周期起始位置处的取值、第二采样结果中待定序的时钟信号和基准信号的组合取值确定待定序的时钟信号的时序。如果待定序的时钟信号的波形分布属于图10b所示的那种情况，则可以采用与普通均匀分布一样的方式确定待定序的时钟信号的时序。
(c)、集中分布
集中分布是指待定序的时钟信号的上升沿和下降沿都落在基准信号的高电平时段或都落在基准信号的低电平时段。图11示出根据本发明一个实施例的分布情况为集中分布的待定序的时钟信号的示意图。
从图11中可以看出，基准信号与待定序的时钟信号的组合取值只包括三种不同的组合取值：“10”、“11”、“00”(基准信号的取值在前，待定序的时钟信号的取值在后)。在这三个组合取值中，待定序的时钟信号的取值‘1’仅出现了一次。
从图11中可以看出，基准信号与待定序的时钟信号的组合取值“10”被分成了两份。在不借助辅助信号的情况下，这两段分开的时间间隔无法求出。因此，可以引入一个具有以下特点的第二辅助信号：属于均匀分布并且自身已经完成定序；能够将基准信号与待定序的时钟信号的组合取值“11”分成两段，即图11中所示的t1和t2。当某时钟信号与待定序的时钟信号的组合取值中待定序的时钟信号的特定取值(图11所示的示例中为‘1’)出现两次时，可以认为该时钟信号能够将基准信号的组合取值“11”分成两段。例如在图11所示的示例中，第二辅助信号与待定序的时钟信号的组合取值包括“10”和“11”(待定序的时钟信号的取值在前，第二辅助信号的取值在后)。
从图11可知，根据第二辅助信号与待定序的时钟信号的组合取值“01”和“11”(辅助信号的取值在前，待定序的时钟信号的取值在后)在参考周期中所占时间，可以确定t1和t2的大小。由于第二辅助信号已经完成定序，因此其上升沿位置是已知的，可以将其上升沿位置设为t0。待定序的时钟信号的上升沿与下降沿位置分别为：t0-t1和t0+t2。由此可以完成待定序的 时钟信号的定序。
总之，在逐个信号定序过程中，可以将多个无序的时钟信号分为三种类别进行定序。由于特殊分布和集中分布信号的定序过程中都需要均匀分布信号作为辅助信号，因此如果一个时钟信号与基准信号的组合取值包括四种不同的组合取值“10”、“11”、“01”、“00”并且这四种组合取值在参考周期中所占时间都大于预定时间间隔(例如20.4ps)，则可以最先对其进行定序，以便为特殊分布或集中分布信号提供辅助。
第二示例
示例性地，校准信号可以包括采样周期等于多个无序的时钟信号的周期的整数倍与预定时间间隔之和的第一采样信号和采样周期与多个无序的时钟信号的周期无关的第二采样信号，校准采样结果包括利用第一采样信号对多个无序的时钟信号进行采样所获得的第一采样结果和利用第二采样信号对多个无序的时钟信号进行采样所获得的第二采样结果，定序单元260(或360)可以通过以下方式确定多个无序的时钟信号的时序：选择多个无序的时钟信号之一作为基准信号；重复执行以下定序操作直至确定多个无序的时钟信号的时序为止：根据第一采样结果中基准信号的取值估计基准信号的第二特定边沿的出现位置，确定在第二特定边沿的出现位置后面的最近采样位置为周期起始位置，并确定以周期起始位置为起点的、持续时间等于多个无序的时钟信号的周期的时间段为参考周期；对于多个无序的时钟信号中的、满足预设条件的待定序的时钟信号，根据第二采样结果中待定序的时钟信号与基准信号的每种组合取值的出现比例确定待定序的时钟信号与基准信号的每种组合取值在参考周期中所占时间，并根据第一采样结果中待定序的时钟信号与基准信号在周期起始位置处的取值、第二采样结果中待定序的时钟信号和基准信号的组合取值确定待定序的时钟信号的时序，其中，预设条件包括待定序的时钟信号与基准信号的组合取值包括四种不同的组合取值并且每种组合取值在参考周期中所占时间大于预设时间段，预设时间段与预定时间间隔相关；选择多个无序的时钟信号中的已定序的时钟信号之一作为新的基准信号；以及基于统一的周期起始位置对多个无序的时钟信号的时序进行校正。
在本示例中，定序过程可以由以下几个步骤组成：
1)、选择一路时钟信号作为基准信号。
2)、根据第一采样结果中基准信号的取值确定周期起始位置，并根据第一采样结果求出各路时钟信号在周期起始位置处的取值。
3)、根据第二采样结果求出基准信号与待定序的时钟信号的四种组合取值“10”“11”“01”“00”中的每种组合取值在参考周期中所占时间，如图8所示的序号为1、2、3、4的四段时间间隔。如果这四段时间间隔都大于某一预设时间段，则根据第一采样结果及第二采样结果，就可以确定待定序的时钟信号的时序。在本步骤中确定待定序的时钟信号的时序的方式与上述针对分布情况为普通均匀分布的待定序的时钟信号的定序过程类似，此处不再赘述。预设时间段与预定时间间隔相关，其可以根据需要设定。例如，假设预定时间间隔为20.4ps，则预设时间段可以是预定时间间隔的两倍左右，例如45ps。
4)、在已经完成定序的时钟信号中选择一个时钟信号作为新的基准信号，以继续对没有完成定序的时钟信号进行定序。
5)、重复执行步骤2)、3)和4)直到所有的时钟信号都完成定序。
6)、基于统一的周期起始位置对得到的定序结果进行处理。由于在上述循环过程中，基准信号发生改变，因此每次定序所采用的周期起始位置可能是不同的，因此需要对时钟信号的时序进行统一校正。可以理解，每个时钟信号与自身定序时所使用的基准信号之间的相位关系是已确定的，其所使用的基准信号与其他的基准信号之间的相位关系也是已确定的，所以通过时钟信号之间的相位关系，经过若干次时序校正，最终可以将所有时钟信号的时序调整为以同一周期起始位置为起点。
与第一示例中的定序方法相比，第二示例中的定序方法更加简单和易于实施。
示例性地，根据本发明实施例时间数字转换器可以采用任何合适的硬件、软件和/或固件实现。例如，时间数字转换器可以采用PFGA实现。
示例性地，可以通过以下方式测试所搭建的时间数字转换器的时间测量精度。例如，可以搭建两个通道的时间数字转换器，使用同一待测输入信号进行采样。由于待测输入信号到达两个时间数字转换器的路径延时不同，因此两个时间数字转换器的采样结果在解码以后获得的时间值应该具有固定的差值。在实际测试中，该差值呈现高斯分布，该高斯分布的半高宽(full width at half maximum，FWHM)即为时间数字转换器的时间分辨 率。图12示出根据本发明一个实施例的针对时间数字转换器的时间测量精度进行测试所获得的高斯分布结果。
由图12中可以看出，FWHM值(即时间测量精度)为61.5ps左右。该结果与根据本发明实施例的时间数字转换器的理论时间测量精度还具有一定差距，因此仍然存在继续改进的空间。
下面描述根据本发明一个实施例的时间数字转换器的完整工作步骤。
(1)、***启动后，首先进行定序。
使用49M时钟进行固定时间间隔的采样，近似得到96路无序的时钟信号在一个时钟周期的周期起始位置处的取值。随后，使用9.992038M时钟进行统计法采样，得到96路无序的时钟信号的任何组合取值在一个时钟周期内所占的时间间隔。将时钟信号分为三类逐个定序，并完成相应的定序查找表。
(2)、时间数字转换器进入工作状态。
将待测输入信号输入粗时间计数单元，得到粗时间结果。将待测输入信号输入采样单元，锁存96路无序的时钟信号。对锁存结果进行解码，得到细时间结果。将细时间结果与粗时间结果组合后，通过输出单元输出至外部设备。
相比于目前的基于“Wave union”等技术的时间数字转换器，根据本发明实施例的时间数字转换器具有以下优点：
(1))、时间分辨率高，且可以灵活调整。
假设无序信号生成单元生成96路无序的时钟信号，则这些时钟信号的上升沿和下降沿可以将一个时钟周期T分为96*2＝192份，采用的时钟周期为1000ps。经测试，95％以上的BIN宽都在20ps以下，最大的BIN宽只有30ps左右，因此时间数字转换器拥有很高的时间分辨率。
此外，时间数字转换器的时间分辨率可以灵活调整。例如，如果需要更高的时间分辨率的话，可以增加无序信号生成单元所生成的时钟信号的个数；反之，减少所生成的时钟信号的个数即可。可见，调整时间分辨率的方式非常方便简捷。
(2)、当采用FPGA实现时间数字转换器时，所消耗的FPGA内部资源较少，在一个FPGA芯片内部可以实现数百个通道。
例如，可以将消耗资源较多、设计相对复杂的定序单元和解码单元放 在FPGA内嵌的NIOS II软核中执行。在这种情况下，完成单通道TDC所需要的资源平均为10个逻辑阵列块(Logic Array Block，LAB)左右。如果将上述时间数字转换器在内部具有上千个可用LAB的FPGA内实现，则可实现一百多个通道的TDC。
尽管所消耗的资源较少，但根据本发明实施例的时间数字转换器的时间测量精度并不低。由上面的测试环节可知，目前的时间测量精度已经到达60ps左右，并且有较大的提升空间。
根据本发明另一方面，提供一种时间测量方法。图13示出根据本发明一个实施例的时间测量方法1300的示意性流程图。如图13所示，时间测量方法1300包括以下步骤。
在步骤S1310，生成多个无序的时钟信号。
在步骤S1320，利用待测输入信号对多个无序的时钟信号进行采样，以获得实际采样结果。
在步骤S1330，根据实际采样结果和与多个无序的时钟信号的时序相关的时序信息确定待测输入信号的第一特定边沿与多个无序的时钟信号中的选定时钟信号的第一特定边沿之间的时间差，以获得待测输入信号的细时间结果。
在步骤S1340，以选定时钟信号作为计数时钟来对待测输入信号进行计数，以获得待测输入信号的粗时间结果。
根据本发明实施例，在步骤S1330之前，时间测量方法1300还可以包括：利用校准信号对多个无序的时钟信号进行采样，以获得校准采样结果；以及根据校准采样结果确定多个无序的时钟信号的时序，以获得与多个无序的时钟信号的时序相关的时序信息。
根据本发明实施例，校准信号包括采样周期等于多个无序的时钟信号的周期的整数倍与预定时间间隔之和的第一采样信号和采样周期与多个无序的时钟信号的周期无关的第二采样信号，校准采样结果包括利用第一采样信号对多个无序的时钟信号进行采样所获得的第一采样结果和利用第二采样信号对多个无序的时钟信号进行采样所获得的第二采样结果，根据校准采样结果确定多个无序的时钟信号的时序包括：选择多个无序的时钟信号之一作为基准信号；根据第一采样结果中基准信号的取值估计基准信号的第二特定边沿的出现位置，确定在第二特定边沿的出现位置后面的最近 采样位置为周期起始位置，并确定以周期起始位置为起点的、持续时间等于多个无序的时钟信号的周期的时间段为参考周期；统计第二采样结果中基准信号的每种取值的出现比例，以确定基准信号的高电平和/或低电平在参考周期中所占时间；根据第一采样结果中基准信号在周期起始位置处的取值和基准信号的高电平和/或低电平在参考周期中所占时间确定基准信号的时序；对于多个无序的时钟信号中的、除基准信号以外的每个时钟信号，统计第二采样结果中该时钟信号与基准信号的每种组合取值的出现比例；以及对于多个无序的时钟信号中的、除基准信号以外的每个时钟信号，至少根据第一采样结果中该时钟信号与基准信号在周期起始位置处的取值和第二采样结果中该时钟信号与基准信号的每种组合取值的出现比例，确定该时钟信号的时序。
根据本发明实施例，对于多个无序的时钟信号中的、除基准信号以外的每个时钟信号，至少根据第一采样结果中该时钟信号与基准信号在周期起始位置处的取值和第二采样结果中该时钟信号与基准信号的每种组合取值的出现比例，确定该时钟信号的时序包括：对于多个无序的时钟信号中的任一待定序的时钟信号，根据第二采样结果中待定序的时钟信号与基准信号的每种组合取值的出现比例确定待定序的时钟信号与基准信号的每种组合取值在参考周期中所占时间；如果待定序的时钟信号与基准信号的组合取值包括四种不同的组合取值并且每种组合取值在参考周期中所占时间大于预定时间间隔，则根据第一采样结果中待定序的时钟信号与基准信号在周期起始位置处的取值、第二采样结果中待定序的时钟信号和基准信号的组合取值确定待定序的时钟信号的时序；如果待定序的时钟信号与基准信号的组合取值包括四种不同的组合取值并且所包含的基准信号的取值与在第二特定边沿后出现的电平一致的两种组合取值中的任一种在参考周期中所占时间小于或等于预定时间间隔，则从已定序的时钟信号中选择第一辅助信号，根据第一辅助信号、待定序的时钟信号与基准信号的组合取值确定待定序的时钟信号的波形分布情况，并根据待定序的时钟信号的波形分布情况、第一采样结果中待定序的时钟信号与基准信号在周期起始位置处的取值、第二采样结果中待定序的时钟信号和基准信号的组合取值确定待定序的时钟信号的时序，其中，第一辅助信号与基准信号的组合取值包括四种不同的组合取值、每种组合取值在参考周期中所占时间大于预定时 间间隔并且第一采样结果中第一辅助信号在周期起始位置处的取值与在第二特定边沿前出现的电平一致；如果待定序的时钟信号与基准信号的组合取值包括三种不同的组合取值，其中，在三种不同的组合取值中待定序的时钟信号的特定取值仅出现一次，则从已定序的时钟信号中选择第二辅助信号，并根据第二采样结果中第二辅助信号与待定序的时钟信号的组合取值确定待定序的时钟信号的时序，其中，第二辅助信号与基准信号的组合取值包括四种不同的组合取值并且在第二辅助信号与待定序的时钟信号的组合取值中待定序的时钟信号的特定取值出现两次。
根据本发明实施例，校准信号包括采样周期等于多个无序的时钟信号的周期的整数倍与预定时间间隔之和的第一采样信号和采样周期与多个无序的时钟信号的周期无关的第二采样信号，校准采样结果包括利用第一采样信号对多个无序的时钟信号进行采样所获得的第一采样结果和利用第二采样信号对多个无序的时钟信号进行采样所获得的第二采样结果，根据校准采样结果确定多个无序的时钟信号的时序包括：选择多个无序的时钟信号之一作为基准信号；重复执行以下定序操作直至确定多个无序的时钟信号的时序为止：根据第一采样结果中基准信号的取值估计基准信号的第二特定边沿的出现位置，确定在第二特定边沿的出现位置后面的最近采样位置为周期起始位置，并确定以周期起始位置为起点的、持续时间等于多个无序的时钟信号的周期的时间段为参考周期；对于多个无序的时钟信号中的、满足预设条件的待定序的时钟信号，根据第二采样结果中待定序的时钟信号与基准信号的每种组合取值的出现比例确定待定序的时钟信号与基准信号的每种组合取值在参考周期中所占时间，并根据第一采样结果中待定序的时钟信号与基准信号在周期起始位置处的取值、第二采样结果中待定序的时钟信号和基准信号的组合取值确定待定序的时钟信号的时序，其中，预设条件包括待定序的时钟信号与基准信号的组合取值包括四种不同的组合取值并且每种组合取值在参考周期中所占时间大于预设时间段，预设时间段与预定时间间隔相关；选择多个无序的时钟信号中的已定序的时钟信号之一作为新的基准信号；以及基于统一的周期起始位置对多个无序的时钟信号的时序进行校正。
上文已经结合附图1至12描述了时间数字转换器中的各单元的结构、工作原理和优点，本领域技术人员根据以上关于时间数字转换器的描述以 及附图1至12，能够理解本文所公开的时间测量方法1300的实施方式及其优点等，为了简洁，本文不对此进行赘述。
应该注意的是上述实施例对本发明进行说明而不是对本发明进行限制，并且本领域技术人员在不脱离所附权利要求的范围的情况下可设计出替换实施例。在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本发明可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。例如，本文所述的“第一特定边沿”和“第二特定边沿”仅用于区分两个边沿的目的，“第一特定边沿”和“第二特定边沿”可以是相同类型的边沿(例如均为上升沿或均为下降沿)，也可以是不同类型的边沿(例如一个是上升沿，一个是下降沿)。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个设备，或一些特征可以忽略，或不执行。

Claims (19)

  1. 一种时间数字转换器，包括：
    无序信号生成单元，用于生成多个无序的时钟信号；
    采样单元，与所述无序信号生成单元连接，用于接收所述多个无序的时钟信号和待测输入信号，利用所述待测输入信号对所述多个无序的时钟信号进行采样，并输出对应的实际采样结果；
    解码单元，与所述采样单元连接，用于接收所述实际采样结果，并根据所述实际采样结果和与所述多个无序的时钟信号的时序相关的时序信息确定所述待测输入信号的特定边沿与所述多个无序的时钟信号中的选定时钟信号的特定边沿之间的时间差，以获得所述待测输入信号的细时间结果；以及
    粗时间计数单元，与所述无序信号生成单元连接，用于接收所述选定时钟信号和所述待测输入信号，并以所述选定时钟信号作为计数时钟来对所述待测输入信号进行计数，以获得所述待测输入信号的粗时间结果。
  2. 根据权利要求1所述的时间数字转换器，其特征在于，所述采样单元还用于接收校准信号，利用所述校准信号对所述多个无序的时钟信号进行采样，并输出对应的校准采样结果；
    所述时间数字转换器还包括：
    定序单元，与所述采样单元和所述解码单元连接，用于接收所述校准采样结果，根据所述校准采样结果确定所述多个无序的时钟信号的时序，并将与所述多个无序的时钟信号的时序相关的所述时序信息输出到所述解码单元。
  3. 根据权利要求2所述的时间数字转换器，其特征在于，所述时间数字转换器还包括：
    时钟管理单元，用于生成所述校准信号。
  4. 根据权利要求3所述的时间数字转换器，其特征在于，所述时间数字转换器还包括：
    选择器，与所述时钟管理单元和所述采样单元连接，用于接收所述待测输入信号和所述时钟管理单元输出的所述校准信号，并选择将所述待测输入信号和所述校准信号之一输入到所述采样单元。
  5. 根据权利要求1所述的时间数字转换器，其特征在于，所述无序信 号生成单元包括：
    时钟管理单元，用于利用锁相环生成至少一个初始时钟信号；以及
    延时单元，与所述时钟管理单元连接，用于对所述至少一个初始时钟信号进行延时，以将所述至少一个初始时钟信号转换为所述多个无序的时钟信号。
  6. 根据权利要求5所述的时间数字转换器，其特征在于，所述延时单元包括以下项中的至少一项：至少一个加法器集合、多个逻辑门电路和多条延时线。
  7. 根据权利要求6所述的时间数字转换器，其特征在于，所述至少一个加法器集合用于一一对应地接收所述至少一个初始时钟信号，其中，每个加法器集合用于组成一个加法进位链，将所接收的初始时钟信号作为对应的加法进位链的最低位输入信号，并从对应的加法进位链所输出的输出信号中选择预定数目的输出信号作为所述多个无序的时钟信号的至少一部分输出至所述采样单元。
  8. 根据权利要求7所述的时间数字转换器，其特征在于，所述延时单元还包括：
    特定数目的查找表单元，与所述至少一个加法器集合中的特定数目的加法器集合一一对应地连接；
    其中，所述至少一个加法器集合经由所述特定数目的查找表单元将所述多个无序的时钟信号中的特定数目的无序的时钟信号输出至所述采样单元，并将剩余的无序的时钟信号直接输出至所述采样单元。
  9. 根据权利要求6所述的时间数字转换器，其特征在于，所述多个逻辑门电路中的每个逻辑门电路用于接收所述至少一个初始时钟信号之一，并对所接收的初始时钟信号进行延时，其中，所述多个逻辑门电路中的至少部分逻辑门电路的延时时间彼此不同，
    其中，所述多个逻辑门电路中的预定数目的逻辑门电路与所述采样单元连接，所述预定数目的逻辑门电路用于将预定数目的延时后的时钟信号作为所述多个无序的时钟信号输出至所述采样单元。
  10. 根据权利要求6所述的时间数字转换器，其特征在于，所述至少一个初始时钟信号的数目大于1，所述多条延时线用于一一对应地将所述至少一个初始时钟信号从所述时钟管理单元传输到所述采样单元，其中， 所述多条延时线中的至少部分延时线的延时时间彼此不同。
  11. 根据权利要求5所述的时间数字转换器，其特征在于，所述至少一个初始时钟信号的数目大于1，所述至少一个初始时钟信号的周期相同，并且所述至少一个初始时钟信号的相位均匀分布在0至180°的范围内。
  12. 根据权利要求1所述的时间数字转换器，其特征在于，所述无序信号生成单元包括：
    时钟管理单元，用于利用锁相环生成所述多个无序的时钟信号。
  13. 根据权利要求1所述的时间数字转换器，其特征在于，所述采样单元包括：
    多个寄存器，用于一一对应地接收所述多个无序的时钟信号，通过以所述待测输入信号作为锁存使能信号锁存所述多个无序的时钟信号来对所述多个无序的时钟信号进行采样。
  14. 根据权利要求1所述的时间数字转换器，其特征在于，所述时间数字转换器还包括：
    输出单元，与所述解码单元和所述粗时间计数单元连接，用于输出所述粗时间结果和所述细时间结果。
  15. 一种时间测量方法，包括：
    生成多个无序的时钟信号；
    利用待测输入信号对所述多个无序的时钟信号进行采样，以获得实际采样结果；
    根据所述实际采样结果和与所述多个无序的时钟信号的时序相关的时序信息确定所述待测输入信号的第一特定边沿与所述多个无序的时钟信号中的选定时钟信号的第一特定边沿之间的时间差，以获得所述待测输入信号的细时间结果；以及
    以所述选定时钟信号作为计数时钟来对所述待测输入信号进行计数，以获得所述待测输入信号的粗时间结果。
  16. 根据权利要求15所述的时间测量方法，其特征在于，在所述根据所述实际采样结果和与所述多个无序的时钟信号的时序相关的时序信息确定所述待测输入信号的第一特定边沿与所述多个无序的时钟信号中的选定时钟信号的第一特定边沿之间的时间差之前，所述时间测量方法还包括：
    利用校准信号对所述多个无序的时钟信号进行采样，以获得校准采样 结果；以及
    根据所述校准采样结果确定所述多个无序的时钟信号的时序，以获得与所述多个无序的时钟信号的时序相关的所述时序信息。
  17. 根据权利要求16所述的时间测量方法，其特征在于，所述校准信号包括采样周期等于所述多个无序的时钟信号的周期的整数倍与预定时间间隔之和的第一采样信号和采样周期与所述多个无序的时钟信号的周期无关的第二采样信号，所述校准采样结果包括利用所述第一采样信号对所述多个无序的时钟信号进行采样所获得的第一采样结果和利用所述第二采样信号对所述多个无序的时钟信号进行采样所获得的第二采样结果，
    所述根据所述校准采样结果确定所述多个无序的时钟信号的时序包括：
    选择所述多个无序的时钟信号之一作为基准信号；
    根据所述第一采样结果中所述基准信号的取值估计所述基准信号的第二特定边沿的出现位置，确定在所述第二特定边沿的出现位置后面的最近采样位置为周期起始位置，并确定以所述周期起始位置为起点的、持续时间等于所述多个无序的时钟信号的周期的时间段为参考周期；
    统计所述第二采样结果中所述基准信号的每种取值的出现比例，以确定所述基准信号的高电平和/或低电平在所述参考周期中所占时间；
    根据所述第一采样结果中所述基准信号在所述周期起始位置处的取值和所述基准信号的高电平和/或低电平在所述参考周期中所占时间确定所述基准信号的时序；
    对于所述多个无序的时钟信号中的、除所述基准信号以外的每个时钟信号，
    统计所述第二采样结果中该时钟信号与所述基准信号的每种组合取值的出现比例；以及
    至少根据所述第一采样结果中该时钟信号与所述基准信号在所述周期起始位置处的取值和所述第二采样结果中该时钟信号与所述基准信号的每种组合取值的出现比例，确定该时钟信号的时序。
  18. 根据权利要求17所述的时间测量方法，其特征在于，所述对于所述多个无序的时钟信号中的、除所述基准信号以外的每个时钟信号，至少根据所述第一采样结果中该时钟信号与所述基准信号在所述周期起始位置处的取值和所述第二采样结果中该时钟信号与所述基准信号的每种组合 取值的出现比例，确定该时钟信号的时序包括：
    对于所述多个无序的时钟信号中的任一待定序的时钟信号，
    根据所述第二采样结果中所述待定序的时钟信号与所述基准信号的每种组合取值的出现比例确定所述待定序的时钟信号与所述基准信号的每种组合取值在所述参考周期中所占时间；
    如果所述待定序的时钟信号与所述基准信号的组合取值包括四种不同的组合取值并且每种组合取值在所述参考周期中所占时间大于所述预定时间间隔，则根据所述第一采样结果中所述待定序的时钟信号与所述基准信号在所述周期起始位置处的取值、所述第二采样结果中所述待定序的时钟信号和所述基准信号的组合取值确定所述待定序的时钟信号的时序；
    如果所述待定序的时钟信号与所述基准信号的组合取值包括四种不同的组合取值并且所包含的所述基准信号的取值与在所述第二特定边沿后出现的电平一致的两种组合取值中的任一种在所述参考周期中所占时间小于或等于所述预定时间间隔，则从已定序的时钟信号中选择第一辅助信号，根据所述第一辅助信号、所述待定序的时钟信号与所述基准信号的组合取值确定所述待定序的时钟信号的波形分布情况，并根据所述待定序的时钟信号的波形分布情况、所述第一采样结果中所述待定序的时钟信号与所述基准信号在所述周期起始位置处的取值、所述第二采样结果中所述待定序的时钟信号和所述基准信号的组合取值确定所述待定序的时钟信号的时序，其中，所述第一辅助信号与所述基准信号的组合取值包括四种不同的组合取值、每种组合取值在所述参考周期中所占时间大于所述预定时间间隔并且所述第一采样结果中所述第一辅助信号在所述周期起始位置处的取值与在所述第二特定边沿前出现的电平一致；
    如果所述待定序的时钟信号与所述基准信号的组合取值包括三种不同的组合取值，其中，在所述三种不同的组合取值中所述待定序的时钟信号的特定取值仅出现一次，则从已定序的时钟信号中选择第二辅助信号，并根据所述第二采样结果中所述第二辅助信号与所述待定序的时钟信号的组合取值确定所述待定序的时钟信号的时序，其中，所述第二辅助信号与所述基准信号的组合取值包括四种不同的组合取值并且在所述第二辅助信号与所述待定序的时钟信号的组合取值中所述待定序的时钟信号的所述特定取值出现两次。
  19. 根据权利要求16所述的时间测量方法，其特征在于，所述校准信号包括采样周期等于所述多个无序的时钟信号的周期的整数倍与预定时间间隔之和的第一采样信号和采样周期与所述多个无序的时钟信号的周期无关的第二采样信号，所述校准采样结果包括利用所述第一采样信号对所述多个无序的时钟信号进行采样所获得的第一采样结果和利用所述第二采样信号对所述多个无序的时钟信号进行采样所获得的第二采样结果，
    所述根据所述校准采样结果确定所述多个无序的时钟信号的时序包括：
    选择所述多个无序的时钟信号之一作为基准信号；
    重复执行以下定序操作直至确定所述多个无序的时钟信号的时序为止：
    根据所述第一采样结果中所述基准信号的取值估计所述基准信号的第二特定边沿的出现位置，确定在所述第二特定边沿的出现位置后面的最近采样位置为周期起始位置，并确定以所述周期起始位置为起点的、持续时间等于所述多个无序的时钟信号的周期的时间段为参考周期；
    对于所述多个无序的时钟信号中的、满足预设条件的待定序的时钟信号，根据所述第二采样结果中所述待定序的时钟信号与所述基准信号的每种组合取值的出现比例确定所述待定序的时钟信号与所述基准信号的每种组合取值在所述参考周期中所占时间，并根据所述第一采样结果中所述待定序的时钟信号与所述基准信号在所述周期起始位置处的取值、所述第二采样结果中所述待定序的时钟信号和所述基准信号的组合取值确定所述待定序的时钟信号的时序，其中，所述预设条件包括所述待定序的时钟信号与所述基准信号的组合取值包括四种不同的组合取值并且每种组合取值在所述参考周期中所占时间大于预设时间段，所述预设时间段与所述预定时间间隔相关；
    选择所述多个无序的时钟信号中的已定序的时钟信号之一作为新的基准信号；以及
    基于统一的周期起始位置对所述多个无序的时钟信号的时序进行校正。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112764342A (zh) * 2019-11-01 2021-05-07 北京一径科技有限公司 一种时间测量装置和方法
CN114675526A (zh) * 2021-09-30 2022-06-28 绍兴圆方半导体有限公司 时间数字转换器及电路

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106773613B (zh) * 2016-12-19 2019-03-22 武汉中派科技有限责任公司 时间数字转换器和时间测量方法
CN107037721B (zh) * 2017-06-16 2019-06-21 中国科学技术大学 一种自修正型时间数字转换器
CN108020716B (zh) * 2017-11-17 2021-04-13 杭州海兴电力科技股份有限公司 基于分布式时钟源对终端精确对时的方法
CN108061848B (zh) * 2017-12-06 2019-12-10 武汉万集信息技术有限公司 基于fpga的加法进位链延时的测量方法及***
CN110658715B (zh) * 2018-06-29 2021-05-04 南京理工大学 一种基于抽头动态可调进位链细时间内插延时线的tdc电路
WO2020142922A1 (zh) * 2019-01-09 2020-07-16 深圳市大疆创新科技有限公司 时间测量的校正方法及装置
WO2020142948A1 (zh) * 2019-01-09 2020-07-16 深圳市大疆创新科技有限公司 一种激光雷达设备、专用集成电路及测距装置
DE102019205731A1 (de) * 2019-04-18 2020-10-22 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Zeit-zu-Digital-Wandler-Anordnung
CN110208667A (zh) * 2019-07-10 2019-09-06 江苏利得智能监测科技有限公司 基于时间转换技术的gis设备局部放电定位方法
JP2021027496A (ja) * 2019-08-07 2021-02-22 セイコーエプソン株式会社 回路装置、物理量測定装置、電子機器及び移動体
CN114995093B (zh) * 2021-09-30 2022-10-21 绍兴圆方半导体有限公司 时间数字转换器、处理周期信号的方法和信号处理***
CN113917830B (zh) * 2021-10-13 2023-03-14 中国科学院微电子研究所 循环游标延时链电路、时间数字转换器和信号选取方法
CN114637184B (zh) * 2022-03-14 2023-12-08 浙江师范大学 一种基于相关信号处理的时间间隔快速测量方法
CN115509111B (zh) * 2022-09-26 2023-09-01 西北核技术研究所 用于延时链型时间数字转换器的采样控制电路及控制方法
CN116009376A (zh) * 2022-09-29 2023-04-25 深圳越登智能技术有限公司 进位链计时校准方法、装置、设备及存储介质

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030213913A1 (en) * 2002-01-28 2003-11-20 Cti Pet Systems, Inc. Continuous sampling and digital integration for pet scintillation
CN101866165A (zh) * 2010-06-30 2010-10-20 清华大学 基于现场可编程门阵列的回波飞行时间测量方法
CN102736511A (zh) * 2011-04-06 2012-10-17 中国科学院高能物理研究所 时间测量***及时间测量方法
CN103472712A (zh) * 2013-09-26 2013-12-25 中国科学技术大学 一种基于fpga的高精度高集成度时间数字转换器及实现方法
CN105763196A (zh) * 2016-03-10 2016-07-13 中国科学技术大学 一种延迟内插型时间数字转换器
CN106773613A (zh) * 2016-12-19 2017-05-31 武汉中派科技有限责任公司 时间数字转换器和时间测量方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4425122B2 (ja) * 2004-12-08 2010-03-03 セイコープレシジョン株式会社 競技用計時システムおよびタイム取得方法
CN100468234C (zh) * 2005-06-21 2009-03-11 中国科学技术大学 基于fpga的时间数字转换器及其转换方法
CN101326470A (zh) * 2005-12-12 2008-12-17 Nxp股份有限公司 电子计数器电路
CN102621878A (zh) * 2012-01-04 2012-08-01 西安近代化学研究所 高精度时间间隔测量装置
CN203950131U (zh) * 2014-07-22 2014-11-19 西安宏泰时频技术有限公司 一种基于fpga的高精度时间间隔测量装置
CN104614976B (zh) * 2015-02-12 2017-03-29 中国科学技术大学 一种基于fpga的时间数字变换器
CN106019923B (zh) * 2016-05-18 2018-11-13 中国科学技术大学 一种基于fpga的时间数字变换器

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030213913A1 (en) * 2002-01-28 2003-11-20 Cti Pet Systems, Inc. Continuous sampling and digital integration for pet scintillation
CN101866165A (zh) * 2010-06-30 2010-10-20 清华大学 基于现场可编程门阵列的回波飞行时间测量方法
CN102736511A (zh) * 2011-04-06 2012-10-17 中国科学院高能物理研究所 时间测量***及时间测量方法
CN103472712A (zh) * 2013-09-26 2013-12-25 中国科学技术大学 一种基于fpga的高精度高集成度时间数字转换器及实现方法
CN105763196A (zh) * 2016-03-10 2016-07-13 中国科学技术大学 一种延迟内插型时间数字转换器
CN106773613A (zh) * 2016-12-19 2017-05-31 武汉中派科技有限责任公司 时间数字转换器和时间测量方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112764342A (zh) * 2019-11-01 2021-05-07 北京一径科技有限公司 一种时间测量装置和方法
CN112764342B (zh) * 2019-11-01 2022-02-18 北京一径科技有限公司 一种时间测量装置和方法
CN114675526A (zh) * 2021-09-30 2022-06-28 绍兴圆方半导体有限公司 时间数字转换器及电路

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