WO2017177589A1 - 阵列基板、其制造方法、显示面板及显示装置 - Google Patents

阵列基板、其制造方法、显示面板及显示装置 Download PDF

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WO2017177589A1
WO2017177589A1 PCT/CN2016/095663 CN2016095663W WO2017177589A1 WO 2017177589 A1 WO2017177589 A1 WO 2017177589A1 CN 2016095663 W CN2016095663 W CN 2016095663W WO 2017177589 A1 WO2017177589 A1 WO 2017177589A1
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Prior art keywords
common electrode
array substrate
electrode line
line
substrate according
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PCT/CN2016/095663
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English (en)
French (fr)
Inventor
江鹏
杨海鹏
戴珂
尹傛俊
王章涛
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/528,799 priority Critical patent/US10317739B2/en
Publication of WO2017177589A1 publication Critical patent/WO2017177589A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background

Definitions

  • Embodiments of the present disclosure relate to the field of display, and more particularly, to an array substrate, a method of fabricating an array substrate, a display panel, and a display device.
  • the pixel electrode and the common electrode form an electric field, and the liquid crystal is deflected.
  • the angle of the liquid crystal deflection is different, and the transmittance is different to form a display of different screens.
  • the ideal state of the common electrode is a constant value.
  • the common electrode In the liquid crystal driving process, the ideal state of the common electrode is a constant value.
  • the related defects are mainly solved by the peripheral common electrode line optimization of the display panel and the circuit common electrode signal compensation.
  • the product frame is getting narrower and narrower, the space of the peripheral common electrode line is compressed, and the wiring resistance is increased, so that the circuit compensation cannot improve the related defects.
  • the metal common electrode formed by the gate line metal
  • the vertical direction is mainly connected through the pixel electrode ITO (indium tin oxide) and the via hole, and the longitudinal common electrode uniformity is poor.
  • the embodiments of the present disclosure greatly enhance the resistance uniformity of the common electrode by adding the longitudinal common electrode lines. Specifically, the following technical solutions are provided.
  • An array substrate comprising:
  • the common electrode is electrically connected to the common electrode adjacent to and adjacent to the second common electrode line and the second common electrode line.
  • the uniformity of the resistance of the common electrode is improved, and defects such as afterimage, flashing green, and crosstalk are improved.
  • the resistance uniformity of the common electrode is improved. At the same time, it will not increase manufacturing costs. Further, by directly connecting the first common electrode line and the second common electrode line to form a common electrode line network, the resistance uniformity of the common electrode can be further improved.
  • the uniformity of the common electrode resistance is improved without affecting the aperture ratio.
  • the array substrate according to any one of the above aspects, wherein at least one of the common electrode and the pixel electrode material comprises indium tin oxide.
  • a display panel comprising the array substrate according to any one of the above aspects [1] to [15].
  • a display device comprising the array substrate according to any one of the above aspects [1] to [15].
  • the above display panel and display device have the advantages of the above array substrate, that is, the uniformity of resistance of the common electrode is improved, and defects such as afterimage, flashing green, and crosstalk are improved.
  • a method of manufacturing an array substrate comprising:
  • the common electrode on both sides of the second common electrode line and adjacent thereto is electrically connected to the second common electrode line.
  • the uniformity of the resistance of the common electrode is improved, and defects such as afterimage, flashing green, and crosstalk are improved.
  • FIG. 1(a) is a schematic diagram of a bilaterally driven array substrate according to an embodiment of the present disclosure
  • FIG. 1(b) is a schematic diagram of a bilaterally driven array substrate according to another embodiment of the present disclosure
  • FIG. 1(c) is a diagram A cross-sectional view of the AA line in 1(b).
  • FIG. 2(a) is a schematic view of a bilaterally driven array substrate according to another embodiment of the present disclosure
  • FIG. 2(b) is a cross-sectional view taken along line B-B of FIG. 2(a).
  • FIG. 3(a) is a schematic view of a single-sided driving array substrate according to another embodiment of the present disclosure
  • FIG. 3(b) is a cross-sectional view taken along line C-C of FIG. 3(a).
  • 4(a) is a single-sided driving array substrate according to another embodiment of the present disclosure.
  • 4(b) is a cross-sectional view of the line of D-D in FIG. 4(a).
  • FIG. 5 is a schematic diagram of a single-sided drive array substrate in accordance with another embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a GOA drive array substrate in accordance with another embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a COF drive array substrate in accordance with another embodiment of the present disclosure.
  • Fig. 8(a) is a schematic view of an array substrate according to the prior art
  • Fig. 8(b) is a cross-sectional view taken along line E-E of Fig. 8(a).
  • FIG. 9 is a schematic diagram of a prior art GOA drive array substrate.
  • FIG. 10 is a schematic diagram of a prior art COF drive array substrate.
  • Figures 8-10 illustrate a prior art array substrate.
  • Figure 8(a) is based on the present A schematic diagram of an array substrate
  • FIG. 8(b) is a cross-sectional view taken along line EE of FIG. 8(a)
  • FIG. 9 is a prior art GOA driver (Gate Driver on Array) array substrate
  • FIG. 10 is a schematic diagram of a COF (Chip On Flex or Chip On Film) driving array substrate of the prior art.
  • COF Chip On Flex or Chip On Film
  • a lateral common electrode line is formed in parallel with the gate line 1, and in the longitudinal direction, the common electrode 9 on both sides of the gate line 1 passes through a pixel electrode material (for example, ITO) 8 and two via holes 7 connection. Since the resistivity of the pixel electrode material 8 is much larger than that of the metal, the in-plane resistance uniformity of the longitudinal common electrode is poor.
  • a pixel electrode material for example, ITO
  • Embodiments of the present disclosure greatly enhance the uniformity of resistance of the common electrode by adding longitudinal common electrode lines.
  • FIG. 1(a) is a schematic diagram of a bilaterally driven array substrate according to an embodiment of the present disclosure
  • FIG. 1(b) is a schematic diagram of a bilaterally driven array substrate according to another embodiment of the present disclosure
  • FIG. 1(c) is FIG. (b) A cross-sectional view of the AA line.
  • the array substrate of the present embodiment includes: a gate line 1 extending in a first direction; and a data line 5 extending in a second direction different from the first direction a first common electrode line 2 extending in the first direction; a second common electrode line 3 extending in the second direction; and a common electrode 9 on both sides of the second common electrode line And the adjacent common electrode and the second common electrode line are electrically connected.
  • a pixel unit is formed in a region divided by the gate line 1 and the data line 5, the pixel unit having a pixel electrode and a common electrode.
  • the common electrodes of the plurality of pixel units arranged in the second direction are preferably all separated by the gate lines 1.
  • the common electrode of at least a part of the plurality of pixel units arranged in the second direction may be separated.
  • a bilaterally driven array substrate is shown, it should be The driving method of the present embodiment is not limited to the bilateral driving, and may be a single-sided driving or any other driving method known to those skilled in the art.
  • the drive circuit 6 shown in FIG. 1(a) is a COF
  • the drive circuit of the present embodiment is not limited to the COF, and may be a GOA or any other drive circuit known to those skilled in the art.
  • the gate line 1 and the first common electrode line 2 are shown to extend in the lateral direction in FIG. 1(a), that is, the first direction is the lateral direction, the array substrate of the present embodiment is not limited thereto.
  • the pole line 1 and the first common electrode line 2 may also extend in the longitudinal direction.
  • the second direction is preferably perpendicular to the first direction. The following description will be made by taking the first direction as the lateral direction and the second direction as the longitudinal direction.
  • the gate line 1, the first common electrode line 2, and the second common electrode line 3 are formed of the same conductive material in the same layer. More preferably, as shown in Fig. 1(a), the first common electrode line 2 and the second common electrode line 3 are directly connected, and a shape similar to an intersection is formed at the intersection.
  • the uniformity of resistance of the common electrode is improved without increasing the manufacturing cost. Further, by directly connecting the first common electrode line and the second common electrode line to form a common electrode line network, the resistance uniformity of the common electrode can be further improved.
  • the gate line 1 and the first common electrode line 2 are preferably formed in plurality.
  • the second common electrode line 3 may be one or plural.
  • each pixel unit has a switching circuit 4, which may be any switching circuit known to those skilled in the art, such as a TFT transistor, which is not limited in this embodiment.
  • a TFT transistor will be described as an example.
  • One of the source and the drain of the TFT transistor is connected to the data line 5, the other is connected to the pixel electrode 10, and the gate of the TFT transistor is connected to the gate line 1.
  • the gate line, the first common electrode line, and the second common electrode line preferably include a metal or other conductive material having high conductivity, which is not limited in this embodiment.
  • the common electrode 9 and the pixel electrode 10 preferably include indium tin oxide (ITO) or other materials having high conductivity and high transparency, and the present embodiment is not limited thereto.
  • ITO indium tin oxide
  • the common electrodes 9 on both sides of the second common electrode line 3 and adjacent thereto are directly connected to the second common electrode line 3
  • the electrical connection can improve the uniformity of the resistance of the longitudinal common electrode and improve the defects such as afterimage, flashing green and crosstalk.
  • the common electrode which is not adjacent to the second common electrode line 3 in the longitudinal direction is interrupted by the gate line 1 in the longitudinal direction, and these common electrodes 9 on both sides of the gate line 1 (i.e., Fig. 1(a)
  • the outermost four common electrodes) are preferably electrically connected via the pixel electrode material 8 and the two vias 7.
  • Fig. 1(a) shows an embodiment in which the second common electrode line 3 is inserted beside the data line 5 without changing the arrangement of the pixel units, but the embodiment is not limited thereto.
  • the second common electrode line may be inserted at the position of the original data line 5. In this case, only the pixel units on both sides of the second common electrode line need to be arranged in a mirror image relationship, FIG. 1(b) Such an embodiment is shown.
  • the pixel units on both sides of the second common electrode line have a mirror image relationship.
  • the pixel units on both sides of the second common electrode line are mirrored, and the second side is added to the data line 5 as shown in FIG. 1(a).
  • the common electrode line it is possible to avoid a decrease in the aperture ratio.
  • the second common electrode lines can also be inserted as shown in Fig. 1(a), so that the arrangement of the pixel units can be omitted.
  • the second common electrode line 3 is not limited to one, and may be any strip.
  • the second common electrode lines 3 are plural and bilaterally driven will be described with reference to FIG.
  • the second common electrode lines are three, but it should be understood that the second common electrode lines may be any of the strips.
  • the following three examples are taken as an example.
  • each second common electrode line in the case where three second common electrode lines are inserted, the pixel units on both sides of each second common electrode line are also in a mirror image relationship, which is the same as described above in connection with FIG. Moreover, the common electrode adjacent to each of the second common electrode lines in the longitudinal direction is directly electrically connected to each of the second common electrode lines, and is also the same as that described above in connection with FIG. 1, and details are not described herein again.
  • the gate lines on both sides of the second common electrode line in the middle are the same as in FIG. 1, and are not connected. Different from FIG. 1, the gate lines on both sides of the second common electrode line on the left and right sides are electrically connected via the pixel electrode material 13 and the two via holes 12 across the second common electrode line.
  • the gate lines on both sides of the intermediate second common electrode line are not connected in FIG. 2, they are not limited thereto.
  • the gate lines on both sides of one second common electrode line are allowed to be disconnected, and the second common electrode line may be any one of the second common electrode lines, and
  • the gate lines on both sides of the remaining second common electrode lines outside the strip need to be electrically connected via the pixel electrode material 13 and the via holes 12 across the remaining second common electrode lines to ensure the alignment to each pixel unit.
  • the gate of the switching circuit inputs the driving voltage.
  • the driving method of the array substrate is not limited to the bilateral driving, and may be any driving method known to those skilled in the art, such as single-sided driving.
  • the embodiment of the single-sided driving will be described below with reference to Figs.
  • the array substrate is driven by a driving circuit (for example, COF) 6 provided on one side.
  • a driving circuit for example, COF
  • the gate line interrupted by the second common electrode line 3 An electrical connection is required.
  • the gate lines on both sides of the second common electrode line are electrically connected via the pixel electrode material 8 and the two via holes 7 across the second common electrode line.
  • the other structure of the unilaterally driven array substrate shown in FIG. 3 is the same as the bilaterally driven array substrate described above with reference to FIG. 1 except that the broken gate lines need to be connected, and the description thereof is omitted here.
  • FIG. 3 shows only one second common electrode line, in the case of single-sided driving, a plurality of second common electrode lines may be provided.
  • a plurality of second common electrode lines may be provided.
  • gate lines on both sides of all the second common electrode lines are electrically connected via the pixel electrode material 13 and the via hole 12 across the second common electrode line.
  • the other configuration is the same as the embodiment described above in connection with FIG. 3, and the description thereof is omitted here.
  • the embodiment in which the second common electrode line 3 and the gate line 1 and the first common electrode line 2 are located in the same layer and formed of the same conductive material has been described above, the embodiment is not limited thereto, and the second embodiment may be used.
  • the common electrode line is disposed in a layer different from the gate line 1 and the first common electrode line 2.
  • the second common electrode line is located in the upper layer, and at the intersection of the first common electrode line 2 and the second common electrode line 3, both of The vias 11 are electrically connected.
  • the second common electrode line 3 In the case where the second common electrode line 3 is not in the same layer as the gate line 1 and the first common electrode line 2, the second common electrode line 3 does not interrupt the gate line 1, so that it is not necessary to The broken gate line is connected.
  • the pixel unit on both sides of the second common electrode line 3 is also in the mirror image relationship as in the above embodiment, so that the aperture ratio can be prevented from being lowered.
  • the second common electrode line 3 is made of a metal or a material having high conductivity, whereby the uniformity of the resistance of the longitudinal common electrode can be improved, and the residual is improved. Poor image, flash green and crosstalk.
  • the COF bilaterally driven array substrate of the embodiment of the present disclosure is disposed in the longitudinal direction as shown in FIG. Common electrode line.
  • FIG. 7 Although one second common electrode line is shown in FIG. 7, it should be understood that the second common electrode line may be plural.
  • the driving method may be GOA or other driving methods known to those skilled in the art.
  • the second common electrode line may be disposed in the longitudinal direction.
  • one longitudinal common electrode line is shown in FIG. 6, as in the above-described embodiment, a plurality of longitudinal common electrode lines may be provided.
  • Another embodiment of the present disclosure provides a display panel including the array substrate according to one of the above embodiments.
  • the uniformity of the resistance of the vertical common electrode can be improved, and defects such as afterimage, flashing green, and crosstalk can be improved.
  • Another embodiment of the present disclosure provides a display device including the array substrate according to one of the above embodiments.
  • the uniformity of the resistance of the vertical common electrode can be improved, and defects such as afterimage, flashing green, and crosstalk can be improved.
  • Another embodiment of the present disclosure provides a method of fabricating an array substrate, comprising: forming a common electrode on a substrate; forming a gate line extending in a first direction on the substrate; Forming a first common electrode line extending along the first direction on the substrate; and forming a second common electrode line extending in a second direction different from the first direction on the substrate; wherein, in the second A common electrode on both sides of the common electrode line and adjacent thereto is electrically connected to the second common electrode line.
  • the uniformity of the resistance of the common electrode is improved, and defects such as afterimage, flashing green, and crosstalk are improved.

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Abstract

一种阵列基板、阵列基板的制造方法、显示面板及显示装置。阵列基板包括：栅极线（1），其在第一方向上延伸；数据线（5），其在与第一方向不同的第二方向上延伸；第一公共电极线（2），其在第一方向上延伸；第二公共电极线（3），其在第二方向上延伸；和公共电极（9），在第二公共电极线（3）两侧并与其相邻的公共电极（9）与第二公共电极线（3）电连接。

Description

阵列基板、其制造方法、显示面板及显示装置 技术领域
本公开的实施方式涉及显示领域，更具体地说，涉及阵列基板、阵列基板的制造方法、显示面板以及显示装置。
背景技术
在液晶显示装置的液晶驱动过程中，像素电极与公共电极形成电场，液晶偏转，通过控制像素电极的信号，液晶偏转的角度不同，透过率不同，形成不同画面的显示。
在液晶驱动过程中，公共电极的理想状态是一个恒定值。然而，实际过程中，公共电极与面内栅极线和数据线之间都有交叠，会有耦合电容。由于栅极线和数据线的信号不停变化，公共电极信号会在耦合电容的作用下被拉动。公共电极被拉动后会造成残像、闪绿(Greenish)、串扰(Crosstalk)等不良，其是显示屏几大难以解决的不良。
通常，主要是通过显示面板的周边公共电极线优化及电路公共电极信号补偿来解决相关不良。然而随着产品升级，产品边框越来越窄，周边公共电极线的空间被压缩，布线电阻增加，以至于电路补偿也无法改善相关不良。现有设计在显示面板内部只有横向存在金属公共电极(由栅极线金属形成)，而纵向主要通过像素电极ITO(氧化铟锡)和过孔进行连接，纵向的公共电极均一性较差。
发明内容
为了解决现有技术中存在的上述问题，本公开的实施方式通过加入纵向的公共电极线，大大提升了公共电极的电阻均一性。具体地，提供了以下技术方案。
[1]一种阵列基板，包括：
栅极线，其在第一方向上延伸；
数据线，其在与所述第一方向不同的第二方向上延伸；
第一公共电极线，其在所述第一方向上延伸；
第二公共电极线，其在所述第二方向上延伸；和
公共电极，在所述第二公共电极线两侧并与其相邻的公共电极与所述第二公共电极线电连接。
上述方案[1]的阵列基板中，通过在第二方向上增加第二公共电极线，提升了公共电极的电阻均一性，改善了残像、闪绿及串扰等不良。
[2]根据上述方案[1]所述的阵列基板，其中，所述栅极线、所述第一公共电极线和所述第二公共电极线在同一层中由同一导电材料形成。
[3]根据上述方案[2]所述的阵列基板，其中，所述第一公共电极线和所述第二公共电极线直接连接。
上述方案[2]和[3]的阵列基板中，通过在同一层中，由同一导电材料形成栅极线、第一公共电极线和第二公共电极线，在提升了公共电极的电阻均一性的同时不会增加制造成本。进而，通过将第一公共电极线和第二公共电极线直接连接，形成公共电极线网络，能够进一步提升公共电极的电阻均一性。
[4]根据上述方案[1]-[3]中任一方案所述的阵列基板，其中，位于所述栅极线两侧且不与所述第二公共电极线相邻的公共电极，经由跨过所述栅极线的像素电极材料电连接。
[5]根据上述方案[1]-[4]中任一方案所述的阵列基板，其中，所述第二公共电极线两侧的像素单元呈镜像关系。
上述方案[5]的阵列基板中，通过使第二公共电极线两侧的像素单元呈镜像关系，在提升公共电极电阻均一性的同时不会影响开口率。
[6]根据上述方案[1]-[5]中任一方案所述的阵列基板，其中，在所述第二公共电极线的两侧都具有与所述栅极线连接的驱动电路。
[7]根据上述方案[6]所述的阵列基板，其中，在所述第二公共电极线为1条的情况下，所述第二公共电极线两侧的所述栅极线不连接。
[8]根据上述方案[6]所述的阵列基板，其中，在所述第二公共电极线为多条的情况下，多条第二公共电极线中的一条第二公共电极线两侧的栅极线不连接，多条第二公共电极线中的其余的第二公共电极线两侧的栅极线，经由跨过其余的第二公共电极线的像素电极材料电连接。
[9]根据上述方案[1]-[8]中任一方案所述的阵列基板，其中，仅在所述第二公共电极线的一侧具有与所述栅极线连接的驱动电路。
[10]根据上述方案[9]所述的阵列基板，其中，所述第二公共电极线两侧的栅极线，经由跨过所述第二公共电极线的像素电极材料电连接。
[11]根据上述方案[1]-[10]中任一方案所述的阵列基板，其中，所述第一方向和所述第二方向垂直。
[12]根据上述方案[1]-[11]中任一方案所述的阵列基板，其中，所述栅极线、所述第一公共电极线和所述第二公共电极线中的至少一个包括金属。
[13]根据上述方案[1]-[12]中任一方案所述的阵列基板，其中，所述公共电极和所述像素电极材料中的至少一个包括氧化铟锡。
[14]根据上述方案[1]、[4]、[6]、[9]、[11]-[13]中任一方案所述的阵列基板，其中，所述第一公共电极线和所述第二公共电极线位于不同层。
[15]根据上述方案[14]所述的阵列基板，其中，所述第一公共电极线和所述第二公共电极线在交叉处经由过孔电连接。
[16]一种显示面板，包括上述方案[1]-[15]中任一方案所述的阵列基板。
[17]一种显示装置，包括上述方案[1]-[15]中任一方案所述的阵列基板。
上述显示面板和显示装置，具有上述阵列基板的优点，即提升了公共电极的电阻均一性，改善了残像、闪绿及串扰等不良。
[18]一种阵列基板的制造方法，包括：
在基板上形成公共电极；
在基板上形成沿第一方向延伸的栅极线；
在基板上形成沿所述第一方向延伸的第一公共电极线；和
在基板上形成沿与所述第一方向不同的第二方向延伸的第二公共电极线；
其中，在所述第二公共电极线两侧并与其相邻的公共电极与所述第二公共电极线电连接。
上述方案[18]的阵列基板的制造方法中，通过在第二方向上形成第二公共电极线，提升了公共电极的电阻均一性，改善了残像、闪绿及串扰等不良。
附图说明
为了更清楚地说明本公开的实施方式的技术方案，下面将对实施方式的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施方式，而非对本公开的限制。
图1(a)是根据本公开的一个实施方式的双边驱动阵列基板的示意图，图1(b)是根据本公开的另一个实施方式的双边驱动阵列基板的示意图，图1(c)是图1(b)中A-A线的截面图。
图2(a)是根据本公开的另一个实施方式的双边驱动阵列基板的示意图，图2(b)是图2(a)中B-B线的截面图。
图3(a)是根据本公开的另一个实施方式的单边驱动阵列基板的示意图，图3(b)是图3(a)中C-C线的截面图。
图4(a)是根据本公开的另一个实施方式的单边驱动阵列基板 的示意图，图4(b)是图4(a)中D-D的线的截面图。
图5是根据本公开的另一个实施方式的单边驱动阵列基板的示意图。
图6是根据本公开的另一个实施方式的GOA驱动阵列基板的示意图。
图7是根据本公开的另一个实施方式的COF驱动阵列基板的示意图。
图8(a)是根据现有技术的阵列基板的示意图，图8(b)是图8(a)中E-E线的截面图。
图9是现有技术的GOA驱动阵列基板的示意图。
图10是现有技术的COF驱动阵列基板的示意图。
具体实施方式
为使本公开的实施方式的目的、技术方案和优点更加清楚，下面将结合本公开的实施方式的附图，对本公开的实施方式的技术方案进行清楚、完整地描述。显然，所描述的实施方式是本公开的一部分实施方式，而不是全部的实施方式。基于所描述的本公开的实施方式，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施方式，都属于本公开保护的范围。
在本公开的描述中，需要说明的是，术语“上”、“下”、“顶”、“底”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
此外，在本公开的描述中，除非另有说明，“多个”的含义是两个或两个以上，“多条”的含义是两条或两条以上。
图8-10示出了现有的阵列基板。具体地，图8(a)是根据现 有的阵列基板的示意图，图8(b)是图8(a)中E-E线的截面图，图9是现有技术的GOA驱动(Gate Driver on Array，阵列基板栅极驱动)的阵列基板的示意图，图10是现有技术的COF(Chip On Flex或Chip On Film，覆晶薄膜)驱动阵列基板的示意图。
如图8所示，与栅极线1平行地形成横向公共电极线，在纵向上，在栅极线1两侧的公共电极9，经由像素电极材料(例如ITO)8和2个过孔7连接。由于像素电极材料8的电阻率比金属大很多，纵向的公共电极的面内电阻均一性较差。
本公开的实施方式通过加入纵向的公共电极线，大大提升了公共电极的电阻均一性。
下面就结合附图对本公开的各个优选实施方式进行详细的说明。
<阵列基板>
图1(a)是根据本公开的一个实施方式的双边驱动阵列基板的示意图，图(b)是根据本公开的另一个实施方式的双边驱动阵列基板的示意图，图1(c)是图1(b)中A-A线的截面图。
如图1(a)所示，本实施方式的阵列基板，包括：栅极线1，其在第一方向上延伸；数据线5，其在与所述第一方向不同的第二方向上延伸；第一公共电极线2，其在所述第一方向上延伸；第二公共电极线3，其在所述第二方向上延伸；和公共电极9，在所述第二公共电极线两侧并与其相邻的公共电极与所述第二公共电极线电连接。
如图1所示，在由栅极线1和数据线5划分的区域形成像素单元，像素单元具有像素电极和公共电极。在第二方向上排列的多个像素单元的公共电极优选全部被栅极线1分隔开。另外，在公共电极和栅极线1不在同一层的情况下，也可以是在第二方向上排列的多个像素单元中的至少一部分像素单元的公共电极被分隔开。
在图1(a)中，虽然示出了双边驱动的阵列基板，但是应该理 解，本实施方式的驱动方式不限于双边驱动，也可以是单边驱动或本领域技术人员公知的任何其他驱动方式。
另外，虽然图1(a)所示的驱动电路6是COF，但是本实施方式的驱动电路并不限于COF，也可以是GOA或本领域技术人员公知的任何其他驱动电路。
另外，虽然在图1(a)中示出了栅极线1和第一公共电极线2在横向上延伸，即第一方向是横向，但是，本实施方式的阵列基板并不限于此，栅极线1和第一公共电极线2也可以在纵向上延伸。在本实施方式中，第二方向优选与第一方向垂直。下面以第一方向是横向，第二方向是纵向为例进行说明。
在本实施方式中，优选，如图1(a)所示，栅极线1、第一公共电极线2和第二公共电极线3在同一层中由同一导电材料形成。更优选，如图1(a)所示，第一公共电极线2和第二公共电极线3直接连接，在交叉处形成类似于十字路口的形状。
在本实施方式中，通过在同一层中，由同一导电材料形成栅极线、第一公共电极线和第二公共电极线，在提升了公共电极的电阻均一性的同时不会增加制造成本。进而，通过将第一公共电极线和第二公共电极线直接连接，形成公共电极线网络，能够进一步提升公共电极的电阻均一性。
在本实施方式中，栅极线1和第一公共电极线2优选形成多条。第二公共电极线3可以为1条，也可以为多条。下面结合图1(a)说明第二公共电极线3为1条且为双边驱动的阵列基板。
如图1(a)所示，每个像素单元具有一个开关电路4，开关电路4可以是本领域的技术人员公知的任何开关电路，例如TFT晶体管，本实施方式对此没有任何限制。下面以TFT晶体管为例进行说明。
TFT晶体管的源极和漏极的一方连接于数据线5，另一方连接于像素电极10，TFT晶体管的栅极连接于栅极线1。
在本实施例中，栅极线、第一公共电极线和第二公共电极线优选包括金属或者其他导电性高的导电材料，本实施方式对此没有任何限制。
在本实施方式中，公共电极9和像素电极10优选包括氧化铟锡(ITO)或者其他导电性高且透明度高的材料，本实施方式对此没有任何限制。
如图1(a)所示，在第二公共电极线3两侧并与其相邻的公共电极9(即图1(a)中中间的4个公共电极)，直接与第二公共电极线3电连接，从而可以提升纵向公共电极的电阻均一性，改善残像、闪绿及串扰等不良。
另外，在纵向上不与第二公共电极线3相邻的公共电极，在纵向上被栅极线1打断，这些位于栅极线1两侧的公共电极9(即图1(a)中最外侧的4个公共电极)，优选经由像素电极材料8和2个过孔7电连接。
如图1(a)所示，由于阵列基板是双边驱动且仅***1条第二公共电极线3，因此不需要对第二公共电极线两侧的被第二公共电极线打断的栅极线进行连接。
图1(a)示出了在不改变像素单元排列的情况下，在数据线5的旁边***第二公共电极线3的实施方式，但是本实施方式并不限于此。为了不使开口率下降，也可以在原有数据线5的位置***第二公共电极线，此时只需要将第二公共电极线两侧的像素单元排列为镜像关系即可，图1(b)示出了这样的实施方式。
如图1(b)所示，优选，第二公共电极线两侧的像素单元呈镜像关系。在本实施方式中，通过改变阵列基板内部的像素单元的排布，使第二公共电极线两侧的像素单元呈镜像关系，与图1(a)所示的在数据线5旁边增加第二公共电极线的实施方式相比，可以避免开口率下降。
以下的实施方式以第二公共电极线两侧的像素单元呈镜像关系为例进行说明，但是应该理解，在下面的实施方式中，第二公共 电极线也可以如图1(a)那样***，这样可以不对像素单元的排列方式进行改变。
以上说明了第二公共电极线3为1条的实施方式，但是第二公共电极线并不限于1条，可以为任意条。下面结合图2说明第二公共电极线3为多条且为双边驱动的情况。
如图2所示，第二公共电极线为3条，但是应该理解，第二公共电极线可以为任意条。下面以3条为例进行说明。
如图2(a)所示，在***3条第二公共电极线的情况下，每条第二公共电极线两侧的像素单元也呈镜像关系，与上述结合图1的说明相同。并且，在纵向上与每条第二公共电极线相邻的公共电极与每条第二公共电极线直接电连接，也与上述结合图1的说明相同，在此不再赘述。
在中间的第二公共电极线两侧的栅极线，与图1相同，也没有连接。与图1不同的是，在左侧和右侧的第二公共电极线两侧的栅极线，经由跨过第二公共电极线的像素电极材料13和两个过孔12电连接。
在图2中虽然图示了中间的第二公共电极线两侧的栅极线没有连接，但是并不限于此。在双边驱动的情况下，对于多条第二公共电极线，允许一条第二公共电极线两侧的栅极线不连接，该条第二公共电极线可以是任意一条第二公共电极线，而该条之外的其余的第二公共电极线两侧的栅极线，需要经由跨过其余的第二公共电极线的像素电极材料13和过孔12电连接，以确保向每个像素单元的开关电路的栅极输入驱动电压。
以上说明了阵列基板为双边驱动的实施方式，但是，阵列基板的驱动方式不限于双边驱动，可以为本领域的技术人员公知的任何驱动方式，例如单边驱动。下面结合图3和4对单边驱动的实施方式进行说明。
如图3所示，阵列基板通过在一侧设置的驱动电路(例如COF)6驱动。在单边驱动的情况下，被第二公共电极线3打断的栅极线 需要进行电连接。如图3所示，第二公共电极线两侧的栅极线，经由跨过第二公共电极线的像素电极材料8和两个过孔7电连接。
除了被打断的栅极线需要进行连接，图3所示的单边驱动的阵列基板的其他结构与上述结合图1说明的双边驱动的阵列基板相同，在此省略其说明。
图3虽然仅示出了一条第二公共电极线，但是在单边驱动的情况下，也可以设置多条第二公共电极线。下面结合图4说明在单边驱动的情况下，设置3条第二公共电极线的实施方式，但是，应该理解，第二公共电极线可以设置任意条。
如图4所示，在单边驱动的情况下，在所有第二公共电极线两侧的栅极线，都经由跨过第二公共电极线的像素电极材料13和过孔12电连接。除此之外，其他结构与上述结合图3说明的实施方式相同，在此省略其说明。
以上虽然说明了第二公共电极线3与栅极线1和第一公共电极线2位于同一层，并由同一导电材料形成的实施方式，但是本实施方式并不限于此，也可以将第二公共电极线设置在与栅极线1和第一公共电极线2不同的层。
下面结合图5说明第二公共电极线3与栅极线1和第一公共电极线2不在同一层的实施方式。
如图5所示，与栅极线1和第一公共电极线2相比，第二公共电极线位于上层，在第一公共电极线2和第二公共电极线3的交叉处，二者经由过孔11电连接。
在第二公共电极线3与栅极线1和第一公共电极线2不在同一层的情况下，第二公共电极线3不会将栅极线1打断，从而无需向上述实施方式那样对打断的栅极线进行连接。
另外，在第二公共电极线3两侧的像素单元，也与上述实施方式相同，呈镜像关系，从而同样可以避免开口率下降。
在本实施方式中，优选，第二公共电极线3由金属或导电性高的材料构成，由此可以提升纵向公共电极的电阻均一性，改善了残 像、闪绿及串扰等不良。
另外，为了更容易理解本公开的实施方式，与图10的现有技术的阵列基板的示意图相对应，本公开的实施方式的COF双边驱动的阵列基板如图7所示，在纵向设置第二公共电极线。虽然在图7中示出了1条第二公共电极线，但是应该理解，第二公共电极线可以为多条。
上述虽然以COF驱动为例说明了阵列基板的实施方式，但是可以理解，驱动方式也可以为GOA或本领域技术人员公知的其他驱动方式。
例如在阵列基板为GOA驱动的情况下，如图6所示，也可以在纵向设置第二公共电极线。虽然在图6中示出了1条纵向公共电极线，但是与上述说明的实施方式相同，也可以设置多条纵向公共电极线。
<显示面板>
本公开的另一实施方式提供一种显示面板，包括上述实施方式之一所述的阵列基板。
本实施方式的显示面板，由于具有上述实施方式之一的阵列基板，由此可以提升纵向公共电极的电阻均一性，改善了残像、闪绿及串扰等不良。
<显示装置>
本公开的另一实施方式提供一种显示装置，包括上述实施方式之一所述的阵列基板。
本实施方式的显示装置，由于具有上述实施方式之一的阵列基板，由此可以提升纵向公共电极的电阻均一性，改善了残像、闪绿及串扰等不良。
<阵列基板的制造方法>
本公开的另一实施方式提供一种阵列基板的制造方法，包括：在基板上形成公共电极；在基板上形成沿第一方向延伸的栅极线； 在基板上形成沿所述第一方向延伸的第一公共电极线；和在基板上形成沿与所述第一方向不同的第二方向延伸的第二公共电极线；其中，在所述第二公共电极线两侧并与其相邻的公共电极与所述第二公共电极线电连接。
本实施方式的阵列基板的制造方法，通过在第二方向上形成第二公共电极线，提升了公共电极的电阻均一性，改善了残像、闪绿及串扰等不良。
以上虽然通过一些示例性的实施方式详细地描述了本公开的阵列基板、阵列基板的制造方法、显示面板及显示装置，但是以上这些实施方式并不是穷举的，本领域技术人员可以在本公开的精神和范围内实现各种变化和修改。因此，本公开并不限于这些实施方式，本公开的范围仅以所附权利要求为准。

Claims (18)

  1. 一种阵列基板，包括：
    栅极线，其在第一方向上延伸；
    数据线，其在与所述第一方向不同的第二方向上延伸；
    第一公共电极线，其在所述第一方向上延伸；
    第二公共电极线，其在所述第二方向上延伸；和
    公共电极，在所述第二公共电极线两侧并与其相邻的公共电极与所述第二公共电极线电连接。
  2. 根据权利要求1所述的阵列基板，其中，所述栅极线、所述第一公共电极线和所述第二公共电极线在同一层中由同一导电材料形成。
  3. 根据权利要求2所述的阵列基板，其中，所述第一公共电极线和所述第二公共电极线直接连接。
  4. 根据权利要求1或2所述的阵列基板，其中，位于所述栅极线两侧且不与所述第二公共电极线相邻的公共电极，经由跨过所述栅极线的像素电极材料电连接。
  5. 根据权利要求1或2所述的阵列基板，其中，所述第二公共电极线两侧的像素单元呈镜像关系。
  6. 根据权利要求1或2所述的阵列基板，其中，在所述第二公共电极线的两侧都具有与所述栅极线连接的驱动电路。
  7. 根据权利要求6所述的阵列基板，其中，在所述第二公共电极线为1条的情况下，所述第二公共电极线两侧的所述栅极线不连接。
  8. 根据权利要求6所述的阵列基板，其中，在所述第二公共电极线为多条的情况下，多条第二公共电极线中的一条第二公共电极线两侧的栅极线不连接，多条第二公共电极线中的其余的第二公共电极线两侧的栅极线，经由跨过其余的第二公共电极线的像素电极材料电连接。
  9. 根据权利要求1或2所述的阵列基板，其中，仅在所述第二 公共电极线的一侧具有与所述栅极线连接的驱动电路。
  10. 根据权利要求9所述的阵列基板，其中，所述第二公共电极线两侧的栅极线，经由跨过所述第二公共电极线的像素电极材料电连接。
  11. 根据权利要求1或2所述的阵列基板，其中，所述第一方向和所述第二方向垂直。
  12. 根据权利要求1或2所述的阵列基板，其中，所述栅极线、所述第一公共电极线和所述第二公共电极线中的至少一个包括金属。
  13. 根据权利要求1或2所述的阵列基板，其中，所述公共电极和所述像素电极材料中的至少一个包括氧化铟锡。
  14. 根据权利要求1所述的阵列基板，其中，所述第一公共电极线和所述第二公共电极线位于不同层。
  15. 根据权利要求14所述的阵列基板，其中，所述第一公共电极线和所述第二公共电极线在交叉处经由过孔电连接。
  16. 一种显示面板，包括权利要求1-15中任一项所述的阵列基板。
  17. 一种显示装置，包括权利要求1-15中任一项所述的阵列基板。
  18. 一种阵列基板的制造方法，包括：
    在基板上形成公共电极；
    在基板上形成沿第一方向延伸的栅极线；
    在基板上形成沿所述第一方向延伸的第一公共电极线；和
    在基板上形成沿与所述第一方向不同的第二方向延伸的第二公共电极线；
    其中，在所述第二公共电极线两侧并与其相邻的公共电极与所述第二公共电极线电连接。
PCT/CN2016/095663 2016-04-15 2016-08-17 阵列基板、其制造方法、显示面板及显示装置 WO2017177589A1 (zh)

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