WO2017148221A1 - Transmission control method, apparatus and system for serial peripheral interface - Google Patents

Transmission control method, apparatus and system for serial peripheral interface Download PDF

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Publication number
WO2017148221A1
WO2017148221A1 PCT/CN2017/071163 CN2017071163W WO2017148221A1 WO 2017148221 A1 WO2017148221 A1 WO 2017148221A1 CN 2017071163 W CN2017071163 W CN 2017071163W WO 2017148221 A1 WO2017148221 A1 WO 2017148221A1
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spi
flash
programmable device
spi flash
signal
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PCT/CN2017/071163
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French (fr)
Chinese (zh)
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刘佳妮
周武
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中兴通讯股份有限公司
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Publication of WO2017148221A1 publication Critical patent/WO2017148221A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

Definitions

  • This application relates to, but is not limited to, the field of intelligent transportation technology.
  • Serial Peripheral Interface Master (SPI) flash memory Flash EEPROM Memory, referred to as: Flash
  • SPI Flash Serial Peripheral Interface Master
  • This paper provides a transmission control method, device and system for a serial peripheral interface to solve the problem that multiple SPI controllers are required to control multiple SPI Flash in the related art.
  • An SPI transmission control method includes:
  • the transmission of the plurality of serial peripheral interface flash SPI Flash is controlled by the programmable device configured.
  • the controlling, by the configured programmable device, the transmission of the multiple pieces of SPI Flash including:
  • the clock signal outputted by the SPI controller is divided by the programmable device, and the plurality of frequency-divided clock signals generated by the frequency division are respectively transmitted to the plurality of phases.
  • Slice SPI Flash access to the multi-chip SPI Flash.
  • controlling, by the configured programmable device, the transmission of the multiple pieces of SPI Flash further comprising:
  • the write operation is that, by sequentially outputting data to be written to the output MOSI of the SPI controller, the output MOSI of the SPI controller is respectively connected to the output MOSI of each piece of the SPI Flash, wherein each The SPI Flash samples the signal on the output MOSI of the SPI Flash under the driving of the divided clock signal of the SPI Flash input as the input data of the SPI Flash; the read operation is: the multi-chip SPI Flash The returned data is restored to data that can be parsed.
  • the restoring the data returned by the multiple pieces of SPI Flash to data that can be parsed includes:
  • the output signals of the plurality of SPI Flashs are synthesized by the programmable device into an input MISO signal of the SPI controller, wherein the programmable device outputs a clock at the SPI controller
  • the rising edge of the signal sequentially samples the output signal of each SPI Flash, and the output signal of each SPI Flash is the SPI Flash according to the configuration mode of the SPI Flash, and the divided clock input in the SPI Flash.
  • the programmable device is a Complex Programmable Logic Device (CPLD) or a Field-Programmable Gate Array (FPGA).
  • CPLD Complex Programmable Logic Device
  • FPGA Field-Programmable Gate Array
  • a transmission control device for a serial peripheral interface SPI comprising:
  • the configuration module is configured to: configure a programmable device for a single serial peripheral interface SPI controller;
  • the control module is configured to: control the transmission of the plurality of serial peripheral interface flash SPI Flash by the programmable device configured by the configuration module.
  • control module includes:
  • a frequency dividing unit configured to: divide, by the programmable device configured by the configuration module, an output clock signal of the SPI controller;
  • the access unit is configured to: divide the frequency dividing unit to generate multiple frequency divisions with different phases
  • the one-to-one correspondence of the clock signals is transmitted to the plurality of SPI Flash to access the plurality of SPI Flash.
  • a transmission control system for a serial peripheral interface includes: a serial peripheral interface SPI controller, a programmable device, and a plurality of serial peripheral interface flash SPI Flash;
  • the SPI controller is connected to the programmable device
  • the programmable devices are respectively connected to the plurality of SPI Flash, and the programmable device is configured to control data transmission of the plurality of SPI Flash by the programmable device.
  • the clock signal of the SPI controller, the input MISO signal, and the output chip select SS signal are processed by the programmable device, and then transmitted to the plurality of SPI Flash respectively; the SPI controller outputs The MOSI signal is directly output to the multi-chip SPI Flash.
  • the programmable device is a logic programmable device CPLD or a field programmable gate array FPGA.
  • a transmission control method, device and system for a serial peripheral interface provided by an embodiment of the present invention, by configuring a programmable device for a single SPI controller, and controlling transmission of multiple SPI Flash by the configured programmable device;
  • multiple SPI controllers are required to control multiple SPI Flash, which saves CPU usage and improves access speed.
  • FIG. 1 is a flowchart of a method for controlling transmission of a serial peripheral interface according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a transmission control apparatus for a serial peripheral interface according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of another transmission control device for a serial peripheral interface according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a transmission control system of a serial peripheral interface according to an embodiment of the present invention.
  • FIG. 5 is a diagram showing another structure of a transmission control system for a serial peripheral interface according to an embodiment of the present invention. schematic diagram;
  • FIG. 6 is a flowchart of an SPI access control method in a transmission control method of a serial peripheral interface according to an embodiment of the present invention
  • FIG. 7 is a timing diagram of a single SPI controller connecting two SPI Flashs in the embodiment shown in FIG. 6;
  • FIG. 8 is a timing diagram of another single SPI controller connected to four SPI Flashs in the embodiment shown in FIG. 6.
  • FIG. 8 is a timing diagram of another single SPI controller connected to four SPI Flashs in the embodiment shown in FIG. 6.
  • FIG. 1 is a flowchart of a transmission control method for a serial peripheral interface according to an embodiment of the present invention.
  • the method provided by the example may include the following steps, that is, steps 110 to 120:
  • Step 110 configuring a programmable device for a single SPI controller
  • Step 120 Control the transmission of the plurality of SPI Flash by the configured programmable device.
  • the transmission control method of the serial peripheral interface solves the need in the related art by configuring a programmable device for a single SPI controller and controlling the transmission of multiple SPI Flash through the configured programmable device.
  • Multiple SPI controllers control the problem of multiple SPI Flash, which saves the resource usage of the Central Processing Unit (CPU) and improves the access speed.
  • CPU Central Processing Unit
  • the implementation of controlling the transmission of the plurality of SPI Flash by the programmable device configured in the foregoing step 120 may include: outputting the clock of the SPI controller by the programmable device (Clock, abbreviated as: CLK) The signal is divided, and a plurality of frequency-divided clock signals generated by the frequency division are transmitted one by one to the multi-chip SPI Flash. Ask for multiple SPI Flash.
  • CLK clock of the SPI controller by the programmable device
  • the implementation of controlling the transmission of the multiple SPI Flash by the programmable device configured in the foregoing step 120 may include: configuring the multi-chip SPI Flash by using the programmable device.
  • the write operation and the read operation are controlled; wherein the write operation is performed by sequentially outputting the data to be written to the output MOSI (ie, Master Output Slave Input) of the SPI controller, and the output MOSI of the SPI controller is respectively connected to each The output MOSI of the SPI Flash, wherein each SPI Flash samples the signal on the output MOSI of the SPI Flash under the driving of the divided clock signal of the SPI Flash input, as the input data of the SPI Flash; the above read operation is Restores the data returned by multiple SPI Flash to data that can be parsed.
  • MOSI ie, Master Output Slave Input
  • the implementation of restoring the data returned by the multiple SPI Flash to the parsable data may include: in the data transmission phase, the multi-chip SPI is adopted by the programmable device.
  • the output signal of the flash is synthesized into an input MISO (Maser Input Slave Output) signal of the SPI controller, wherein the programmable device is respectively applied to each SPI Flash on the rising edge of the clock signal (CLK signal) output by the SPI controller.
  • the output signals are sequentially sampled, and the output signal of each SPI Flash is the data sent by the SPI Flash according to its own configuration mode, on the rising or falling edge of the divided clock signal (CLK signal) corresponding to the SPI Flash.
  • FPGA Field-Programmable Gate Array
  • FIG. 2 is a schematic structural diagram of a transmission control device for a serial peripheral interface according to an embodiment of the present invention.
  • the device provided by the example may include:
  • the configuration module 10 is configured to: configure a programmable device for a single SPI controller;
  • the control module 20 is configured to control the transmission of the plurality of SPI Flashs by the programmable device configured by the configuration module 10.
  • FIG. 3 is a schematic structural diagram of another transmission control apparatus for a serial peripheral interface according to an embodiment of the present invention.
  • the control module 20 in this embodiment may include:
  • the frequency dividing unit 21 is configured to: divide the output clock signal (CLK) of the SPI controller by a programmable device configured by the configuration module 10;
  • the access unit 22 is configured to: transmit the frequency-divided unit 21 to generate a plurality of transmission clock signals with different phases and transmit the signals to the plurality of SPI Flash, and access the plurality of SPI Flash.
  • FIG. 4 is a schematic structural diagram of a transmission control system for a serial peripheral interface according to an embodiment of the present invention, as shown in FIG.
  • the system provided by the embodiment may include: an SPI controller 100, a programmable device 200, and a plurality of SPI Flash 300.
  • the SPI controller 100 is connected to the programmable device 200;
  • the programmable device 200 is respectively connected to a plurality of SPI Flash 300s, and the programmable device 200 is configured to control data transmission of the plurality of SPI Flash300s through the programmable device 200.
  • the clock signal (CLK signal) output by the SPI controller 100, the input MISO signal, and the output chip select signal (Slave Select, referred to as SS) are processed by the programmable device. , respectively, transmitted to each SPI Flash; the MOSI signal of the output of the SPI controller is directly output to each SPI Flash.
  • the programmable device is a logic programmable device (CPLD) or a field programmable gate array (FPGA).
  • CPLD logic programmable device
  • FPGA field programmable gate array
  • the embodiment of the invention provides a single SPI controller to implement multi-chip SPI Flash access method, which can multiply the read/write transmission and erasing speed of SPI Flash without changing the SPI and Flash communication protocols.
  • FIG. 5 is a schematic structural diagram of another transmission control system for a serial peripheral interface according to an embodiment of the present invention.
  • the programmable device in this embodiment is a CPLD, and two SPI Flash are shown.
  • SPI controller has four ports, corresponding to four signals, respectively, clock (CLK) port for output clock signal (CLK signal), SPI controller output (MOSI) port For outputting MOSI information, the input (MISO) port of the SPI controller, for inputting the MISO signal, and the chip select port of the SPI controller output for output chip selection Signal (SS).
  • CLK clock
  • MOSI SPI controller output
  • MISO chip select port of the SPI controller output for output chip selection Signal
  • the MOSI signal is directly output to the MISO port of the SPI Flash, that is, the MISO0 port of the SPI Flash0 in FIG. 5 and the MISO1 port of the SPI Flash1, and the other three signals are processed by the programmable logic device, and then interact with the SPI Flash respectively. .
  • the programmable logic device that is, the CPLD divides the CLK signal outputted by the SPI controller by N, outputs a divided frequency signal with a phase difference of one CLK period, and outputs the plurality of divided clock signals one by one to the plurality of slices.
  • the clock input port of SPI Flash for example, CPLD in Figure 5 divides the CLK signal into CLK0 and CLK1, transfers CLK0 to the CLK0 port of SPI Flash0, and transmits CLK1 to the CLK1 port of SPI Flash1; in practical applications, N should For an integer multiple of 2, the maximum number of FLASHs that can be connected is N slices.
  • the transmission process is basically consistent with the basic SPI transmission. It is divided into three phases, namely the command transmission phase, the address transmission phase and the data transmission phase.
  • the command word and address are transmitted to the SPI Flash terminal, and are sampled and transmitted on the rising or falling edge of the divided CLKn according to the operating mode.
  • the CPU sequentially outputs the data to be written to the MOSI port of the SPI controller, and the MOSI port of the SPI controller is respectively connected to the MOSI of each SPI Flash (ie, MOSI0 to MOSI ( N-1)).
  • each SPI Flash chip samples the signal on the MOSI of the SPI Flash under the driving of the divided clock signal (CLKi) of the SPI Flash input after the frequency division, as the input data of the SPI Flash.
  • CLKi divided clock signal
  • each SPI Flash can transmit data on the rising or falling edge of the divided clock signal (CLKi) of the SPI Flash input according to the configuration mode of the SPI Flash.
  • CLKi divided clock signal
  • the programmable logic device is In the data transmission phase, the multiple outputs are sequentially sampled at the rising edge of the clock signal (CLK) outputted by each CPU, and one cycle time is maintained, and the multiple outputs are combined into one MISO input to the CPU end for analysis.
  • the single SPI controller proposed in the embodiment of the present invention implements a multi-chip SPI FLASH access method, uses only one SPI controller, does not require an additional SPI controller of the CPU, and can solve the SPI transmission limited by the operable clock signal.
  • the frequency range and the limitation of slow writing speed have very good practical value.
  • the system consists mainly of an SPI controller and two SPI Flash.
  • the clock signal (CLK signal) of the SPI controller, the input signal (MISO signal), and the chip select signal (SS signal) are processed by the CPLD and transmitted to the two SPI Flashs connected to the CPLD; the MOSI signal is directly output to the SPI. MOSI of Flash.
  • the transmission phase is divided into three phases.
  • the first phase SPI controller (SPI Master) outputs the command word signal
  • the second phase SPI controller (SPI Master) outputs the access address signal
  • the third phase SPI Flash outputs the readback data.
  • FIG. 6 is a flowchart of a method for controlling SPI access in a serial peripheral interface transmission control method according to an embodiment of the present invention. As shown in FIG. 6, this embodiment implements multiple SPI Flash accesses through a single SPI controller. The method may include the following steps, that is, steps 201 to 207:
  • Step 201 Configure the working mode of the SPI controller; configure the SPI controller to work in mode 1 as an example, send data on the rising edge, and sample the data on the falling edge.
  • FIG. 7 is a timing diagram of a single SPI controller connecting two SPI Flashs in the embodiment shown in FIG. 6. The following describes each type of signal in FIG. 7:
  • MOSI CPU SPI controller output data signal, directly transmitted to the data input pin of two SPI FLASH;
  • CLK0/CLK1 CLK is divided by CPLD and the frequency-divided clock signal after the phase is shifted, one-to-one corresponding transmission to the clock pins of two SPI FLASH;
  • MISO0/MISO1 two SPI FLASH output data signals are transmitted to the corresponding pins of the CPLD;
  • MISO Two SPI FLASH data output signals, which are combined into MISO signals by CPLD logic sampling and output to the MISO pin of the CPU SPI controller.
  • step 202 is: in the first stage of transmission, the SS signal is first pulled low, and the SPI controller sequentially sends a command word signal on the rising edge of each clock signal, and the command word length is 8 bits (bit).
  • the command word length is 8 bits (bit).
  • two SPI Flash are called a and b respectively, and the sending mode is:
  • the contents of the 7th (0-base) bit of the command word of the two SPI Flashs are transmitted, and so on, until the contents of the 0th (0-base) bits of the two SPI Flashs are transmitted.
  • the actual steps are as follows: on the first rising edge, the 7th bit (0-base) of the command word sent to a, the second rising edge, the 7th bit (0-base) of the command word sent to b And so on, the command word bits sent to a on the odd rising edge, and the command word bits sent to b on the even rising edge, the transmission order is from the high bit to the low bit, that is, from the 7th bit to the 0th bit.
  • a total of 16-bit word length command word signals are transmitted.
  • Table 1 transmits data in the first phase
  • Step 203 in the second phase of the transmission, the SPI controller sequentially sends an access address signal on the rising edge of each clock signal, and the access address word length of the single-chip SPI Flash is 24 bits, and the transmission mode and the method of the first stage (step 202) Similarly, the address also needs to be sent N times (two times in this embodiment), sequentially transmitted according to the rising edge of the parity, and transmitted from the high bit, and the address signal of 24*N bit word length is transmitted in total (transmit 48 in this embodiment) The bit word length address signal) is transmitted in the same manner as step 202.
  • Step 204 determining whether it is a read operation or a write operation; in the case where the determination result is a write operation, step 205 is performed, and if the result of the determination is a read operation, step 206 is performed;
  • Step 205 in the third stage of transmission, the CPU sequentially outputs the data to be written to the MOSI of the SPI controller, and the MOSI of the SPI controller is respectively connected to the MOSI of each SPI Flash (ie, MOSI0 to MOSI(n-1) ).
  • each SPI Flash samples the signal on the MOSI of the SPI Flash under the driving of the divided clock signal (CLKi) of the SPI Flash input as the input data of the SPI Flash.
  • Step 206 In the third phase of transmission, the N-chip SPI Flash sequentially outputs N-channel readback data, including readback data output from MISO0 to MISO(n-1).
  • the CPLD is triggered by the clock signal (CLK) output by the SPI controller, and sequentially collects 8 ratios from MISO0 to MISO(n-1) in the CPLD.
  • the special data is then held for one clock signal (CLK) cycle, and the total 8*N bit word length MISO signal is obtained from the high bit to the low bit and transmitted to the SPI controller.
  • Step 207 in the third stage of completing the transmission, the chip select signal is pulled high, and a complete transmission is ended.
  • SPI Flash In the third phase of transmission, SPI Flash outputs readback data on the falling edge of CLKi, a data MISO0 signal output by a, and a data MISO1 signal output by b. Because the frequency difference is divided by an even multiple, the falling edge of the divided frequency can be in one-to-one correspondence with the rising edge of the clock signal (CLK).
  • the CPLD is triggered by the rising edge of the clock signal (CLK) output by the SPI controller, and sequentially acquired.
  • the 8-bit data of the MISOi signal of a, b is held for one CLK cycle, and the output MISO of the total 16-bit word length is obtained and directly transmitted to the SPI controller. A complete transfer process is completed at this point.
  • FIG. 8 is a timing diagram of another single SPI controller connected to four SPI Flashs in the embodiment shown in FIG. The timing of the signals is shown in FIG. 8.
  • FIG. 8 For the type of each signal in FIG. 8, reference may be made to the description of the signal types in FIG. 7, and therefore no further details are provided herein.
  • only a single SPI controller can be used, that is, the transmission of multiple SPI Flash can be controlled, and the SPI controller of the CPU is not required to be used, and the clock signal of the CPU is divided and
  • the method of staggering the phase, using the divided frequency-divided clock signal to access each SPI Flash chip, can not only double the transmission frequency of the combined SPI Flash, but also double the erasing speed after the combination of multiple SPI Flash chips. Suitable for applications in embedded systems.
  • all or part of the steps of the above embodiments may also be implemented by using an integrated circuit. These steps may be separately fabricated into individual integrated circuit modules, or multiple modules or steps may be fabricated into a single integrated circuit module. achieve.
  • the devices/function modules/functional units in the above embodiments may be implemented by a general-purpose computing device, which may be centralized on a single computing device or distributed over a network of multiple computing devices.
  • the device/function module/functional unit in the above embodiment When the device/function module/functional unit in the above embodiment is implemented in the form of a software function module and sold or used as a stand-alone product, it can be stored in a computer readable storage medium.
  • the above mentioned computer readable storage medium may be a read only memory, a magnetic disk or an optical disk or the like.
  • the technical solution provided by the embodiment of the invention provides a programmable device for a single SPI controller, and controls transmission of multiple SPI Flash by the configured programmable device; and solves the need for multiple SPI controller control in the related art.
  • the problem of multiple SPI Flash saves CPU resources and improves access speed.

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Abstract

A transmission control method, apparatus and system for a serial peripheral interface (SPI). The method comprises: configuring a programmable device for a single SPI controller; and controlling the transmission of multiple SPI Flashes by means of the configured programmable device.

Description

串行外设接口的传输控制方法、装置及***Transmission control method, device and system for serial peripheral interface 技术领域Technical field
本申请涉及但不限于智能交通技术领域。This application relates to, but is not limited to, the field of intelligent transportation technology.
背景技术Background technique
串行外设接口(Serial Peripheral Interface Master，简称为：SPI)闪存(Flash EEPROM Memory，简称为：Flash)(即SPI Flash)因其使用方便，易于连接，管脚较少等特点，在嵌入式***中应用比较多。但是因为其使用串行传输数据，受限于可工作的时钟的频率范围，传输较慢。并且单片Flash的擦除和写入速度也会成为***瓶颈。Serial Peripheral Interface Master (SPI) flash memory (Flash EEPROM Memory, referred to as: Flash) (ie SPI Flash) is easy to connect due to its ease of use, fewer pins, etc. There are many applications in the system. However, because it uses serial transmission of data, it is limited by the frequency range of the working clock, and the transmission is slow. And the erasing and writing speed of single-chip Flash will also become the system bottleneck.
针对相关技术中需要多个SPI控制器控制多片SPI Flash的问题，还未提出有效的解决方案。In view of the related art that requires multiple SPI controllers to control multiple SPI Flash, an effective solution has not been proposed.
发明内容Summary of the invention
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。The following is an overview of the topics detailed in this document. This Summary is not intended to limit the scope of the claims.
本文提供了一种串行外设接口的传输控制方法、装置及***，以解决相关技术中需要多个SPI控制器控制多片SPI Flash的问题。This paper provides a transmission control method, device and system for a serial peripheral interface to solve the problem that multiple SPI controllers are required to control multiple SPI Flash in the related art.
一种SPI的传输控制方法，包括：An SPI transmission control method includes:
为单个串行外设接口SPI控制器配置可编程器件；Configuring a programmable device for a single serial peripheral interface SPI controller;
通过配置的所述可编程器件对多片串行外设接口闪存SPI Flash的传输进行控制。The transmission of the plurality of serial peripheral interface flash SPI Flash is controlled by the programmable device configured.
可选地，所述通过配置的所述可编程器件对所述多片SPI Flash的传输进行控制，包括：Optionally, the controlling, by the configured programmable device, the transmission of the multiple pieces of SPI Flash, including:
通过配置的所述可编程器件将所述SPI控制器输出的时钟信号进行分频，将分频后产生的多个相位不同的分频时钟信号一一对应的传输到所述多 片SPI Flash，访问所述多片SPI Flash。The clock signal outputted by the SPI controller is divided by the programmable device, and the plurality of frequency-divided clock signals generated by the frequency division are respectively transmitted to the plurality of phases. Slice SPI Flash, access to the multi-chip SPI Flash.
可选地，所述通过配置的所述可编程器件对所述多片SPI Flash的传输进行控制，还包括：Optionally, the controlling, by the configured programmable device, the transmission of the multiple pieces of SPI Flash, further comprising:
通过配置的所述可编程器件对所述多片SPI Flash的写操作和读操作进行控制；Controlling a write operation and a read operation of the plurality of SPI Flash by the programmable device configured;
其中，所述写操作为，通过将待写入数据依次输出到所述SPI控制器的输出MOSI，所述SPI控制器的输出MOSI分别连接到每片所述SPI Flash的输出MOSI，其中，每片所述SPI Flash在本SPI Flash输入的分频时钟信号的驱动下采样本SPI Flash的输出MOSI上的信号，作为本SPI Flash的输入数据；所述读操作为，将所述多片SPI Flash返回的数据还原为能够解析的数据。The write operation is that, by sequentially outputting data to be written to the output MOSI of the SPI controller, the output MOSI of the SPI controller is respectively connected to the output MOSI of each piece of the SPI Flash, wherein each The SPI Flash samples the signal on the output MOSI of the SPI Flash under the driving of the divided clock signal of the SPI Flash input as the input data of the SPI Flash; the read operation is: the multi-chip SPI Flash The returned data is restored to data that can be parsed.
可选地，所述将所述多片SPI Flash返回的数据还原为能够解析的数据，包括：Optionally, the restoring the data returned by the multiple pieces of SPI Flash to data that can be parsed includes:
在数据传输阶段，通过所述可编程器件将所述多片SPI Flash的输出信号合成为一路所述SPI控制器的输入MISO信号，其中，所述可编程器件在所述SPI控制器输出的时钟信号的上升沿分别对每片所述SPI Flash的输出信号依次采样，每片所述SPI Flash的输出信号为本SPI Flash根据所述本SPI Flash的配置模式，在本SPI Flash输入的分频时钟信号的上升沿或下降沿发送的数据。In the data transmission phase, the output signals of the plurality of SPI Flashs are synthesized by the programmable device into an input MISO signal of the SPI controller, wherein the programmable device outputs a clock at the SPI controller The rising edge of the signal sequentially samples the output signal of each SPI Flash, and the output signal of each SPI Flash is the SPI Flash according to the configuration mode of the SPI Flash, and the divided clock input in the SPI Flash. The data sent on the rising or falling edge of the signal.
可选地，所述可编程器件为逻辑可编程器件(Complex Programmable Logic Device，简称为：CPLD)或现场可编程门阵列(Field－Programmable Gate Array，简称为：FPGA)。Optionally, the programmable device is a Complex Programmable Logic Device (CPLD) or a Field-Programmable Gate Array (FPGA).
一种串行外设接口SPI的传输控制装置，包括：A transmission control device for a serial peripheral interface SPI, comprising:
配置模块，设置为：为单个串行外设接口SPI控制器配置可编程器件；The configuration module is configured to: configure a programmable device for a single serial peripheral interface SPI controller;
控制模块，设置为：通过所述配置模块配置的所述可编程器件对多片串行外设接口闪存SPI Flash的传输进行控制。The control module is configured to: control the transmission of the plurality of serial peripheral interface flash SPI Flash by the programmable device configured by the configuration module.
可选地，所述控制模块包括：Optionally, the control module includes:
分频单元，设置为：通过所述配置模块配置的所述可编程器件将所述SPI控制器的输出时钟信号进行分频；a frequency dividing unit, configured to: divide, by the programmable device configured by the configuration module, an output clock signal of the SPI controller;
访问单元，设置为：将所述分频单元分频后产生多个相位不同的分频时 钟信号一一对应的传传输到所述多片SPI Flash，访问所述多片SPI Flash。The access unit is configured to: divide the frequency dividing unit to generate multiple frequency divisions with different phases The one-to-one correspondence of the clock signals is transmitted to the plurality of SPI Flash to access the plurality of SPI Flash.
一种串行外设接口的传输控制***，包括：一个串行外设接口SPI控制器、可编程器件和多片串行外设接口闪存SPI Flash；A transmission control system for a serial peripheral interface includes: a serial peripheral interface SPI controller, a programmable device, and a plurality of serial peripheral interface flash SPI Flash;
其中，所述SPI控制器与所述可编程器件连接；Wherein the SPI controller is connected to the programmable device;
所述可编程器件分别与所述多片SPI Flash连接，所述可编程器件设置为：通过所述可编程器件对所述多片SPI Flash的数据传输进行控制。The programmable devices are respectively connected to the plurality of SPI Flash, and the programmable device is configured to control data transmission of the plurality of SPI Flash by the programmable device.
可选地，所述SPI控制器的时钟信号，输入的MISO信号，输出的片选SS信号经所述可编程器件处理后，分别传输到所述多片SPI Flash；所述SPI控制器输出的MOSI信号直接输出到所述多片SPI Flash。Optionally, the clock signal of the SPI controller, the input MISO signal, and the output chip select SS signal are processed by the programmable device, and then transmitted to the plurality of SPI Flash respectively; the SPI controller outputs The MOSI signal is directly output to the multi-chip SPI Flash.
可选地，所述可编程器件为逻辑可编程器件CPLD或现场可编程门阵列FPGA。Optionally, the programmable device is a logic programmable device CPLD or a field programmable gate array FPGA.
本发明实施例提供的串行外设接口的传输控制方法、装置及***，通过为单个SPI控制器配置可编程器件，并通过配置的该可编程器件对多片SPI Flash的传输进行控制；解决了相关技术中需要多个SPI控制器控制多片SPI Flash的问题，节省了CPU的占用，提高了访问速度。A transmission control method, device and system for a serial peripheral interface provided by an embodiment of the present invention, by configuring a programmable device for a single SPI controller, and controlling transmission of multiple SPI Flash by the configured programmable device; In the related art, multiple SPI controllers are required to control multiple SPI Flash, which saves CPU usage and improves access speed.
在阅读并理解了附图和详细描述后，可以明白其他方面。Other aspects will be apparent upon reading and understanding the drawings and detailed description.
附图概述BRIEF abstract
图1为本发明实施例提供的一种串行外设接口的传输控制方法的流程图；1 is a flowchart of a method for controlling transmission of a serial peripheral interface according to an embodiment of the present invention;
图2为本发明实施例提供的一种串行外设接口的传输控制装置的结构示意图；2 is a schematic structural diagram of a transmission control apparatus for a serial peripheral interface according to an embodiment of the present invention;
图3为本发明实施例提供的另一种串行外设接口的传输控制装置的结构示意图；3 is a schematic structural diagram of another transmission control device for a serial peripheral interface according to an embodiment of the present invention;
图4为本发明实施例提供的一种串行外设接口的传输控制***的结构示意图；4 is a schematic structural diagram of a transmission control system of a serial peripheral interface according to an embodiment of the present invention;
图5为本发明实施例提供另一种的串行外设接口的传输控制***的结构 示意图；FIG. 5 is a diagram showing another structure of a transmission control system for a serial peripheral interface according to an embodiment of the present invention; schematic diagram;
图6为本发明实施例提供的串行外设接口的传输控制方法中一种SPI访问控制方法的流程图；6 is a flowchart of an SPI access control method in a transmission control method of a serial peripheral interface according to an embodiment of the present invention;
图7为图6所示实施例中一种单个SPI控制器连接两片SPI Flash的时序示意图；7 is a timing diagram of a single SPI controller connecting two SPI Flashs in the embodiment shown in FIG. 6;
图8为图6所示实施例中另一种单个SPI控制器连接四片SPI Flash的时序示意图。FIG. 8 is a timing diagram of another single SPI controller connected to four SPI Flashs in the embodiment shown in FIG. 6. FIG.
本发明的实施方式Embodiments of the invention
下文中将结合附图对本发明的实施方式进行详细说明。需要说明的是，在不冲突的情况下，本文中的实施例及实施例中的特征可以相互任意组合。Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the features in the embodiments and the embodiments herein may be arbitrarily combined with each other.
在附图的流程图示出的步骤可以在诸根据一组计算机可执行指令的计算机***中执行。并且，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤。The steps illustrated in the flowchart of the figures may be executed in a computer system in accordance with a set of computer executable instructions. Also, although logical sequences are shown in the flowcharts, in some cases the steps shown or described may be performed in a different order than the ones described herein.
本发明实施例提供了一种串行外设接口的传输控制方法，图1为本发明实施例提供的一种串行外设接口的传输控制方法的流程图，如图1所示，本实施例提供的方法可以包括如下步骤，即步骤110～步骤120：The embodiment of the invention provides a transmission control method for a serial peripheral interface. FIG. 1 is a flowchart of a transmission control method for a serial peripheral interface according to an embodiment of the present invention. The method provided by the example may include the following steps, that is, steps 110 to 120:
步骤110，为单个SPI控制器配置可编程器件；Step 110, configuring a programmable device for a single SPI controller;
步骤120，通过配置的该可编程器件对多片SPI Flash的传输进行控制。Step 120: Control the transmission of the plurality of SPI Flash by the configured programmable device.
本实施例提供的串行外设接口的传输控制方法，通过为单个SPI控制器配置可编程器件，并通过配置的该可编程器件对多片SPI Flash的传输进行控制，解决了相关技术中需要多个SPI控制器控制多片SPI Flash的问题，节省了中央处理器(Central Processing Unit，简称为：CPU)的资源占用，提高了访问速度。The transmission control method of the serial peripheral interface provided by this embodiment solves the need in the related art by configuring a programmable device for a single SPI controller and controlling the transmission of multiple SPI Flash through the configured programmable device. Multiple SPI controllers control the problem of multiple SPI Flash, which saves the resource usage of the Central Processing Unit (CPU) and improves the access speed.
可选地，在本发明实施例中，上述步骤120中通过配置的该可编程器件对多片SPI Flash的传输进行控制的实现方式可以包括：通过该可编程器件将该SPI控制器输出的时钟(Clock，简称为：CLK)信号进行分频，将分频后产生的多个相位不同的分频时钟信号一一对应的传输出到多片SPI Flash，访 问多片SPI Flash。Optionally, in the embodiment of the present invention, the implementation of controlling the transmission of the plurality of SPI Flash by the programmable device configured in the foregoing step 120 may include: outputting the clock of the SPI controller by the programmable device (Clock, abbreviated as: CLK) The signal is divided, and a plurality of frequency-divided clock signals generated by the frequency division are transmitted one by one to the multi-chip SPI Flash. Ask for multiple SPI Flash.
可选地，在本发明实施例中，上述步骤120中通过配置的该可编程器件对多片SPI Flash的传输进行控制的实现方式可以包括：通过配置的可编程器件对该多片SPI Flash的写操作和读操作进行控制；其中，上述写操作为，通过将待写入数据依次输出到该SPI控制器的输出MOSI(即Master Output Slave Input)，该SPI控制器的输出MOSI分别连接到每片SPI Flash的输出MOSI，其中，每片SPI Flash在本SPI Flash输入的分频时钟信号的驱动下采样本SPI Flash的输出MOSI上的信号，作为本SPI Flash的输入数据；上述读操作为，将多片SPI Flash返回的数据还原为能够解析的数据。Optionally, in the embodiment of the present invention, the implementation of controlling the transmission of the multiple SPI Flash by the programmable device configured in the foregoing step 120 may include: configuring the multi-chip SPI Flash by using the programmable device. The write operation and the read operation are controlled; wherein the write operation is performed by sequentially outputting the data to be written to the output MOSI (ie, Master Output Slave Input) of the SPI controller, and the output MOSI of the SPI controller is respectively connected to each The output MOSI of the SPI Flash, wherein each SPI Flash samples the signal on the output MOSI of the SPI Flash under the driving of the divided clock signal of the SPI Flash input, as the input data of the SPI Flash; the above read operation is Restores the data returned by multiple SPI Flash to data that can be parsed.
可选地，在本发明实施例中，上述读操作中，将多片SPI Flash返回的数据还原为能够解析的数据的实现方式可以包括：在数据传输阶段，通过该可编程器件将多片SPI Flash的输出信号合成为一路SPI控制器的输入MISO(即Maser Input Slave Output)信号，其中，该可编程器件在该SPI控制器输出的时钟信号(CLK信号)的上升沿分别对每片SPI Flash的输出信号依次采样，每片SPI Flash的输出信号为本SPI Flash根据自身的配置模式的不同，在本SPI Flash对应的分频时钟信号(CLK信号)的上升沿或下降沿发送的数据。Optionally, in the embodiment of the present invention, in the foregoing read operation, the implementation of restoring the data returned by the multiple SPI Flash to the parsable data may include: in the data transmission phase, the multi-chip SPI is adopted by the programmable device. The output signal of the flash is synthesized into an input MISO (Maser Input Slave Output) signal of the SPI controller, wherein the programmable device is respectively applied to each SPI Flash on the rising edge of the clock signal (CLK signal) output by the SPI controller. The output signals are sequentially sampled, and the output signal of each SPI Flash is the data sent by the SPI Flash according to its own configuration mode, on the rising or falling edge of the divided clock signal (CLK signal) corresponding to the SPI Flash.
可选地，在本发明实施例中，上述可编程器件可以为逻辑可编程器件(Complex Programmable Logic Device，简称为：CPLD)或现场可编程门阵列(Field－Programmable Gate Array，简称为：FPGA)。Optionally, in the embodiment of the present invention, the programmable device may be a Complex Programmable Logic Device (CPLD) or a Field-Programmable Gate Array (FPGA). .
本发明实施例提供了一种串行外设接口的传输控制装置，图2为本发明实施例提供的一种串行外设接口的传输控制装置的结构示意图，如图2所示，本实施例提供的装置可以包括：The embodiment of the invention provides a transmission control device for a serial peripheral interface, and FIG. 2 is a schematic structural diagram of a transmission control device for a serial peripheral interface according to an embodiment of the present invention. The device provided by the example may include:
配置模块10，设置为：为单个SPI控制器配置可编程器件；The configuration module 10 is configured to: configure a programmable device for a single SPI controller;
控制模块20，设置为：通过配置模块10配置的可编程器件对多片SPI Flash的传输进行控制。The control module 20 is configured to control the transmission of the plurality of SPI Flashs by the programmable device configured by the configuration module 10.
可选地，图3为本发明实施例提供的另一种串行外设接口的传输控制装置的结构示意图。如图3所示，在图2所示装置的结构基础上，本实施例中的控制模块20可以包括： Optionally, FIG. 3 is a schematic structural diagram of another transmission control apparatus for a serial peripheral interface according to an embodiment of the present invention. As shown in FIG. 3, based on the structure of the apparatus shown in FIG. 2, the control module 20 in this embodiment may include:
分频单元21，设置为：通过配置模块10配置的可编程器件将该SPI控制器的输出时钟信号(CLK)进行分频；The frequency dividing unit 21 is configured to: divide the output clock signal (CLK) of the SPI controller by a programmable device configured by the configuration module 10;
访问单元22，设置为：将分频单元21分频后产生多个相位不同的分配时钟信号一一对应的传传输到多片SPI Flash，访问多片SPI Flash。The access unit 22 is configured to: transmit the frequency-divided unit 21 to generate a plurality of transmission clock signals with different phases and transmit the signals to the plurality of SPI Flash, and access the plurality of SPI Flash.
本发明实施例还提供了一种串行外设接口的传输控制***，图4为本发明实施例提供的一种串行外设接口的传输控制***的结构示意图，如图4所示，本实施例提供的***可以包括：包括：一个SPI控制器100、可编程器件200和多片SPI Flash300。The embodiment of the present invention further provides a transmission control system for a serial peripheral interface, and FIG. 4 is a schematic structural diagram of a transmission control system for a serial peripheral interface according to an embodiment of the present invention, as shown in FIG. The system provided by the embodiment may include: an SPI controller 100, a programmable device 200, and a plurality of SPI Flash 300.
其中，SPI控制器100与可编程器件连接200；Wherein, the SPI controller 100 is connected to the programmable device 200;
可编程器件200分别与多片SPI Flash连接300，可编程器件200设置为：通过可编程器件200对多片SPI Flash300的数据传输进行控制。The programmable device 200 is respectively connected to a plurality of SPI Flash 300s, and the programmable device 200 is configured to control data transmission of the plurality of SPI Flash300s through the programmable device 200.
可选地，在本发明实施例中，该SPI控制器100输出的时钟信号(CLK信号)，输入的MISO信号，输出的片选信号(Slave Select，简称为：SS)经可编程器件处理后，分别传输到每片SPI Flash；该SPI控制器的输出的MOSI信号直接输出到每片SPI Flash。Optionally, in the embodiment of the present invention, the clock signal (CLK signal) output by the SPI controller 100, the input MISO signal, and the output chip select signal (Slave Select, referred to as SS) are processed by the programmable device. , respectively, transmitted to each SPI Flash; the MOSI signal of the output of the SPI controller is directly output to each SPI Flash.
可选地，在本发明实施例中，上述可编程器件为逻辑可编程器件(CPLD)或现场可编程门阵列(FPGA)。Optionally, in the embodiment of the present invention, the programmable device is a logic programmable device (CPLD) or a field programmable gate array (FPGA).
下面以可编程器件为CPLD为例，结合应用实例对本发明实施例进行详细说明。The following describes the embodiment of the present invention in detail by using a programmable device as a CPLD as an example.
本发明实施例提供了一种单SPI控制器实现多片SPI Flash的访问方法，在不改变SPI和Flash通信协议的情况下，可以成倍地提高SPI Flash的读写传输和擦写速度。The embodiment of the invention provides a single SPI controller to implement multi-chip SPI Flash access method, which can multiply the read/write transmission and erasing speed of SPI Flash without changing the SPI and Flash communication protocols.
图5为本发明实施例提供另一种的串行外设接口的传输控制***的结构示意图，如图5所示，本实施例中的可编程器件为CPLD，并且示出了两个SPI Flash，分别为SPI Flash0和SPI Flash1；SPI控制器有四个端口，分别对应四种信号，分别是时钟(CLK)端口，用于输出时钟信号(CLK信号)，SPI控制器的输出(MOSI)端口，用于输出MOSI信息，SPI控制器的输入(MISO)端口，用于输入MISO信号，以及SPI控制器输出的片选端口，用于输出片选 信号(SS)。其中，MOSI信号直接输出到SPI Flash的MISO端口，即图5中SPI Flash0的MISO0端口，SPI Flash1的MISO1端口，其它三个信号都要经过可编程逻辑器件处理后，再分别与SPI Flash进行交互。FIG. 5 is a schematic structural diagram of another transmission control system for a serial peripheral interface according to an embodiment of the present invention. As shown in FIG. 5, the programmable device in this embodiment is a CPLD, and two SPI Flash are shown. SPI Flash0 and SPI Flash1 respectively; SPI controller has four ports, corresponding to four signals, respectively, clock (CLK) port for output clock signal (CLK signal), SPI controller output (MOSI) port For outputting MOSI information, the input (MISO) port of the SPI controller, for inputting the MISO signal, and the chip select port of the SPI controller output for output chip selection Signal (SS). The MOSI signal is directly output to the MISO port of the SPI Flash, that is, the MISO0 port of the SPI Flash0 in FIG. 5 and the MISO1 port of the SPI Flash1, and the other three signals are processed by the programmable logic device, and then interact with the SPI Flash respectively. .
可编程逻辑器件，即CPLD将SPI控制器输出的CLK信号进行N分频，输出多路相位相差1个CLK周期的分频时钟信号，将多个分频时钟信号一一对应的输出到多片SPI Flash的时钟输入端口，例如，图5中CPLD将CLK信号分频为CLK0和CLK1，将CLK0传输到SPI Flash0的CLK0端口，将CLK1传输到SPI Flash1的CLK1端口；在实际应用中，N应为2的整数倍，能够连接的最大FLASH数为N片。The programmable logic device, that is, the CPLD divides the CLK signal outputted by the SPI controller by N, outputs a divided frequency signal with a phase difference of one CLK period, and outputs the plurality of divided clock signals one by one to the plurality of slices. The clock input port of SPI Flash, for example, CPLD in Figure 5 divides the CLK signal into CLK0 and CLK1, transfers CLK0 to the CLK0 port of SPI Flash0, and transmits CLK1 to the CLK1 port of SPI Flash1; in practical applications, N should For an integer multiple of 2, the maximum number of FLASHs that can be connected is N slices.
传输流程与基本SPI传输基本保持一致，分为三个阶段，分别为命令字(command)传输阶段，地址(address)传输阶段和数据(data)传输阶段。命令字和地址传输到SPI Flash端，根据工作模式的不同，在分频后的CLKn的上升沿或下降沿进行采样和发送。The transmission process is basically consistent with the basic SPI transmission. It is divided into three phases, namely the command transmission phase, the address transmission phase and the data transmission phase. The command word and address are transmitted to the SPI Flash terminal, and are sampled and transmitted on the rising or falling edge of the divided CLKn according to the operating mode.
在本发明实施例中，对于写操作，CPU将需要写入的数据依次输出到SPI控制器的MOSI端口，该SPI控制器的MOSI端口分别连接到每片SPI Flash的MOSI(即MOSI0到MOSI(n-1))。在该阶段，每片SPI Flash芯片在分频后本SPI Flash输入的分频时钟信号(CLKi)的驱动下采样本SPI Flash的MOSI上的信号，作为本SPI Flash的输入数据。写操作只需关注SPI Flash可正确采样数据，但对于一次读操作，还需要将多片SPI Flash返回的数据还原为CPU可以解析的数据。读操作的数据(data)传输阶段，每片SPI Flash可以根据本SPI Flash的配置模式，在本SPI Flash输入的分频时钟信号(CLKi)的上升沿或下降沿发送数据，可编程逻辑器件在数据传输阶段，在每个CPU输出的时钟信号(CLK)的上升沿分别对多路输出依次采样，并保持一个周期时间，将多路输出合成为一路MISO输入到CPU端解析。In the embodiment of the present invention, for a write operation, the CPU sequentially outputs the data to be written to the MOSI port of the SPI controller, and the MOSI port of the SPI controller is respectively connected to the MOSI of each SPI Flash (ie, MOSI0 to MOSI ( N-1)). At this stage, each SPI Flash chip samples the signal on the MOSI of the SPI Flash under the driving of the divided clock signal (CLKi) of the SPI Flash input after the frequency division, as the input data of the SPI Flash. Write operations only need to pay attention to SPI Flash to correctly sample data, but for a read operation, you need to restore the data returned by multiple SPI Flash to the data that the CPU can parse. During the data transfer phase of the read operation, each SPI Flash can transmit data on the rising or falling edge of the divided clock signal (CLKi) of the SPI Flash input according to the configuration mode of the SPI Flash. The programmable logic device is In the data transmission phase, the multiple outputs are sequentially sampled at the rising edge of the clock signal (CLK) outputted by each CPU, and one cycle time is maintained, and the multiple outputs are combined into one MISO input to the CPU end for analysis.
本发明实施例提出的单SPI控制器实现多片SPI FLASH的访问方法，仅使用一个SPI控制器，不需要额外占用CPU的SPI控制器，并且能够解决SPI的传输受限于可工作的时钟信号的频率范围和擦写速度慢的局限，具有非常好的实用价值。The single SPI controller proposed in the embodiment of the present invention implements a multi-chip SPI FLASH access method, uses only one SPI controller, does not require an additional SPI controller of the CPU, and can solve the SPI transmission limited by the operable clock signal. The frequency range and the limitation of slow writing speed have very good practical value.
在一个读SPI操作实例中，***主要由SPI控制器和两片SPI Flash组成， SPI控制器的时钟信号(CLK信号)，输入信号(MISO信号)，片选信号(SS信号)经CPLD处理后，分别传输到与该CPLD连接的两片SPI Flash中；MOSI信号直接输出到SPI Flash的MOSI。In a read SPI operation example, the system consists mainly of an SPI controller and two SPI Flash. The clock signal (CLK signal) of the SPI controller, the input signal (MISO signal), and the chip select signal (SS signal) are processed by the CPLD and transmitted to the two SPI Flashs connected to the CPLD; the MOSI signal is directly output to the SPI. MOSI of Flash.
传输阶段分为三个阶段，第一阶段SPI控制器(SPI Master)输出命令字信号，第二阶段SPI控制器(SPI Master)输出访问地址信号，第三阶段SPI Flash输出回读数据。The transmission phase is divided into three phases. The first phase SPI controller (SPI Master) outputs the command word signal, the second phase SPI controller (SPI Master) outputs the access address signal, and the third phase SPI Flash outputs the readback data.
图6为本发明实施例提供的串行外设接口的传输控制方法中一种SPI访问控制方法的流程图，如图6所示，本实施例通过单个SPI控制器实现多片SPI Flash的访问方法，可以包括如下步骤，即步骤201～步骤207：FIG. 6 is a flowchart of a method for controlling SPI access in a serial peripheral interface transmission control method according to an embodiment of the present invention. As shown in FIG. 6, this embodiment implements multiple SPI Flash accesses through a single SPI controller. The method may include the following steps, that is, steps 201 to 207:
步骤201，配置SPI控制器的工作模式；以配置SPI控制器工作在模式1为例，在上升沿发送数据，下降沿采样数据。Step 201: Configure the working mode of the SPI controller; configure the SPI controller to work in mode 1 as an example, send data on the rising edge, and sample the data on the falling edge.
步骤202，图7为图6所示实施例中一种单个SPI控制器连接两片SPI Flash的时序示意图，以下对图7中每种信号的类型进行说明：Step 202, FIG. 7 is a timing diagram of a single SPI controller connecting two SPI Flashs in the embodiment shown in FIG. 6. The following describes each type of signal in FIG. 7:
1)、CLK：CPU SPI控制器输出的时钟信号；1), CLK: the clock signal output by the CPU SPI controller;
2)、MOSI：CPU SPI控制器的输出数据信号，直接传输到两片SPI FLASH的数据输入管脚上；2), MOSI: CPU SPI controller output data signal, directly transmitted to the data input pin of two SPI FLASH;
3)、CLK0/CLK1：CLK经CPLD分频并错开相位之后的分频时钟信号，一一对应的传输到两片SPI FLASH的时钟管脚上；3), CLK0/CLK1: CLK is divided by CPLD and the frequency-divided clock signal after the phase is shifted, one-to-one corresponding transmission to the clock pins of two SPI FLASH;
4)、MISO0/MISO1：两片SPI FLASH的输出数据信号，传输到CPLD对应的管脚上；4), MISO0/MISO1: two SPI FLASH output data signals are transmitted to the corresponding pins of the CPLD;
5)、MISO：两片SPI FLASH的数据输出信号，通过CPLD逻辑采样保持组合成MISO信号，输出到CPU SPI控制器的MISO管脚。5), MISO: Two SPI FLASH data output signals, which are combined into MISO signals by CPLD logic sampling and output to the MISO pin of the CPU SPI controller.
如图7所示，步骤202为：在传输第一阶段，首先将SS信号拉低，SPI控制器在每个时钟信号的上升沿依次发送命令字信号，命令字字长8比特(bit)，其中，若连接有N片SPI Flash，命令字的每一个bit需连续发送N遍，例如N＝4时，命令字“C7C6……C0”的发送顺序为：C7C7C7C7C6C6C6C6……C0C0C0C0。因为本实施例中连接有两片SPI Flash，所以命令字的每一个比特需连续发送两遍。其中，两片SPI Flash分别称为a和b，发送方式为：依次 发送两片SPI Flash的命令字的第7(0-base)比特的内容，依次类推，直至发送完两片SPI Flash的第0(0-base)比特的内容。实际步骤如下：在第一个上升沿，发送给a的命令字的第7个比特(0-base)，第二个上升沿，发送给b的命令字的第7个比特(0-base)；依次类推，在奇数上升沿发送给a的命令字比特，在偶数上升沿发送给b的命令字比特，发送顺序由高比特至低比特，即由第7比特发送至第0比特。总共发送16比特字长的命令字信号。As shown in FIG. 7, step 202 is: in the first stage of transmission, the SS signal is first pulled low, and the SPI controller sequentially sends a command word signal on the rising edge of each clock signal, and the command word length is 8 bits (bit). Wherein, if N pieces of SPI Flash are connected, each bit of the command word needs to be continuously transmitted N times. For example, when N=4, the order of sending the command words “C7C6...C0” is: C7C7C7C7C6C6C6C6...C0C0C0C0. Since two SPI Flashs are connected in this embodiment, each bit of the command word needs to be transmitted twice in succession. Among them, two SPI Flash are called a and b respectively, and the sending mode is: The contents of the 7th (0-base) bit of the command word of the two SPI Flashs are transmitted, and so on, until the contents of the 0th (0-base) bits of the two SPI Flashs are transmitted. The actual steps are as follows: on the first rising edge, the 7th bit (0-base) of the command word sent to a, the second rising edge, the 7th bit (0-base) of the command word sent to b And so on, the command word bits sent to a on the odd rising edge, and the command word bits sent to b on the even rising edge, the transmission order is from the high bit to the low bit, that is, from the 7th bit to the 0th bit. A total of 16-bit word length command word signals are transmitted.
上述传输的数据如下表1所示：The above transmitted data is shown in Table 1 below:
表1第一阶段传输数据Table 1 transmits data in the first phase
Figure PCTCN2017071163-appb-000001
Figure PCTCN2017071163-appb-000001
步骤203，在传输第二阶段，SPI控制器在每个时钟信号的上升沿依次发送访问地址信号，单片SPI Flash的访问地址字长24比特，发送方式与第一阶段(步骤202)的方法相同，地址也需要发送N遍(本实施例中为两遍)，按奇偶上升沿依次发送，从高比特位开始发送，总共发送24*N比特字长的地址信号(本实施例中发送48比特字长的地址信号)，发送方法与步骤202相同。Step 203, in the second phase of the transmission, the SPI controller sequentially sends an access address signal on the rising edge of each clock signal, and the access address word length of the single-chip SPI Flash is 24 bits, and the transmission mode and the method of the first stage (step 202) Similarly, the address also needs to be sent N times (two times in this embodiment), sequentially transmitted according to the rising edge of the parity, and transmitted from the high bit, and the address signal of 24*N bit word length is transmitted in total (transmit 48 in this embodiment) The bit word length address signal) is transmitted in the same manner as step 202.
步骤204，判断是读操作还是写操作；在判断结果为写操作的情况下，执行步骤205，在判断结果为读操作的情况下，执行步骤206；Step 204, determining whether it is a read operation or a write operation; in the case where the determination result is a write operation, step 205 is performed, and if the result of the determination is a read operation, step 206 is performed;
步骤205，在传输第三阶段，CPU将需要写入的数据依次输出到SPI控制器的MOSI，该SPI控制器的MOSI分别连接到每片SPI Flash的MOSI(即MOSI0到MOSI(n-1))。在该阶段，每片SPI Flash在本SPI Flash输入的分频时钟信号(CLKi)的驱动下采样本SPI Flash的MOSI上的信号，作为本SPI Flash的输入数据。Step 205, in the third stage of transmission, the CPU sequentially outputs the data to be written to the MOSI of the SPI controller, and the MOSI of the SPI controller is respectively connected to the MOSI of each SPI Flash (ie, MOSI0 to MOSI(n-1) ). At this stage, each SPI Flash samples the signal on the MOSI of the SPI Flash under the driving of the divided clock signal (CLKi) of the SPI Flash input as the input data of the SPI Flash.
步骤206，在传输第三阶段，N片SPI Flash依次输出N路回读数据，包括从MISO0到MISO(n-1)输出的回读数据。在该阶段，CPLD由SPI控制器输出的时钟信号(CLK)的触发，依次采集CPLD中从MISO0到MISO(n-1)的8比 特数据，然后保持一个时钟信号(CLK)周期，从高比特到低比特得到总的8*N比特字长的MISO信号，传输到SPI控制器。Step 206: In the third phase of transmission, the N-chip SPI Flash sequentially outputs N-channel readback data, including readback data output from MISO0 to MISO(n-1). At this stage, the CPLD is triggered by the clock signal (CLK) output by the SPI controller, and sequentially collects 8 ratios from MISO0 to MISO(n-1) in the CPLD. The special data is then held for one clock signal (CLK) cycle, and the total 8*N bit word length MISO signal is obtained from the high bit to the low bit and transmitted to the SPI controller.
步骤207，在完成传输第三阶段，将片选信号拉高，结束一次完整传输。Step 207, in the third stage of completing the transmission, the chip select signal is pulled high, and a complete transmission is ended.
在传输第三阶段，SPI Flash在CLKi下降沿输出回读数据，a输出的数据MISO0信号，b输出的数据MISO1信号。因为经过偶数倍分频，分频后的下降沿可与时钟信号(CLK)的上升沿一一对应，在该阶段，CPLD由SPI控制器输出的时钟信号(CLK)的上升沿触发，依次采集a，b的MISOi信号的8比特数据，并保持一个CLK周期，得到总的16比特字长的输出MISO，直接传输到SPI控制器。此时完成了一个完整的传输过程。In the third phase of transmission, SPI Flash outputs readback data on the falling edge of CLKi, a data MISO0 signal output by a, and a data MISO1 signal output by b. Because the frequency difference is divided by an even multiple, the falling edge of the divided frequency can be in one-to-one correspondence with the rising edge of the clock signal (CLK). At this stage, the CPLD is triggered by the rising edge of the clock signal (CLK) output by the SPI controller, and sequentially acquired. The 8-bit data of the MISOi signal of a, b is held for one CLK cycle, and the output MISO of the total 16-bit word length is obtained and directly transmitted to the SPI controller. A complete transfer process is completed at this point.
单片SPI连接四片SPI Flash的情况与上述的单片SPI连接两片SPI Flash类似，图8为图6所示实施例中另一种单个SPI控制器连接四片SPI Flash的时序示意图，每种信号的时序如图8所示，图8中每种信号的类型可以参见上述对图7中信号类型的说明，故在此不再赘述。The case of a single SPI connected to four SPI Flash is similar to the above single SPI connection of two SPI Flash. FIG. 8 is a timing diagram of another single SPI controller connected to four SPI Flashs in the embodiment shown in FIG. The timing of the signals is shown in FIG. 8. For the type of each signal in FIG. 8, reference may be made to the description of the signal types in FIG. 7, and therefore no further details are provided herein.
本发明实施例和可选实现方式，仅使用单个SPI控制器，即可以实现对多片SPI Flash的传输进行控制，不需要额外占用CPU的SPI控制器，并通过将CPU的时钟信号分频并错开相位的方法，使用分频后的分频时钟信号访问每片SPI Flash芯片，不仅可以使组合之后的SPI Flash的传输频率倍增，并且多片SPI Flash芯片组合之后的擦写速度也相应的倍增，适合应用在嵌入式***中使用。In the embodiment and the optional implementation manner of the present invention, only a single SPI controller can be used, that is, the transmission of multiple SPI Flash can be controlled, and the SPI controller of the CPU is not required to be used, and the clock signal of the CPU is divided and The method of staggering the phase, using the divided frequency-divided clock signal to access each SPI Flash chip, can not only double the transmission frequency of the combined SPI Flash, but also double the erasing speed after the combination of multiple SPI Flash chips. Suitable for applications in embedded systems.
本领域普通技术人员可以理解上述实施例的全部或部分步骤可以使用计算机程序流程来实现，所述计算机程序可以存储于一计算机可读存储介质中，所述计算机程序在相应的硬件平台上(根据***、设备、装置、器件等)执行，在执行时，包括方法实施例的步骤之一或其组合。One of ordinary skill in the art will appreciate that all or a portion of the steps of the above-described embodiments can be implemented using a computer program flow, which can be stored in a computer readable storage medium on a corresponding hardware platform (according to The system, device, device, device, etc. are executed, and when executed, include one or a combination of the steps of the method embodiments.
可选地，上述实施例的全部或部分步骤也可以使用集成电路来实现，这些步骤可以被分别制作成一个个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。Alternatively, all or part of the steps of the above embodiments may also be implemented by using an integrated circuit. These steps may be separately fabricated into individual integrated circuit modules, or multiple modules or steps may be fabricated into a single integrated circuit module. achieve.
上述实施例中的装置/功能模块/功能单元可以采用通用的计算装置来实现，它们可以集中在单个的计算装置上，也可以分布在多个计算装置所组成的网络上。 The devices/function modules/functional units in the above embodiments may be implemented by a general-purpose computing device, which may be centralized on a single computing device or distributed over a network of multiple computing devices.
上述实施例中的装置/功能模块/功能单元以软件功能模块的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。上述提到的计算机可读取存储介质可以是只读存储器，磁盘或光盘等。When the device/function module/functional unit in the above embodiment is implemented in the form of a software function module and sold or used as a stand-alone product, it can be stored in a computer readable storage medium. The above mentioned computer readable storage medium may be a read only memory, a magnetic disk or an optical disk or the like.
工业实用性Industrial applicability
本发明实施例提供的技术方案，通过为单个SPI控制器配置可编程器件，并通过配置的该可编程器件对多片SPI Flash的传输进行控制；解决了相关技术中需要多个SPI控制器控制多片SPI Flash的问题，节省了CPU的资源占用，提高了访问速度。 The technical solution provided by the embodiment of the invention provides a programmable device for a single SPI controller, and controls transmission of multiple SPI Flash by the configured programmable device; and solves the need for multiple SPI controller control in the related art. The problem of multiple SPI Flash saves CPU resources and improves access speed.

Claims (10)

  1. 一种串行外设接口的传输控制方法，包括：A transmission control method for a serial peripheral interface, comprising:
    为单个串行外设接口SPI控制器配置可编程器件；Configuring a programmable device for a single serial peripheral interface SPI controller;
    通过配置的所述可编程器件对多片串行外设接口闪存SPI Flash的传输进行控制。The transmission of the plurality of serial peripheral interface flash SPI Flash is controlled by the programmable device configured.
  2. 根据权利要求1所述的方法，其中，所述通过配置的所述可编程器件对所述多片串行外设接口闪存SPI Flash的传输进行控制，包括：The method of claim 1 wherein said controlling said plurality of serial peripheral interface flash SPI Flash transmissions by said programmable device comprises:
    通过配置的所述可编程器件将所述SPI控制器输出的时钟信号进行分频，将分频后产生的多个相位不同的分频时钟信号一一对应的传输到所述多片SPI Flash，访问所述多片SPI Flash。The clock signal outputted by the SPI controller is divided by the programmable device, and a plurality of frequency-divided clock signals generated by the frequency division are transmitted to the plurality of SPI Flash in a one-to-one correspondence. Access the multi-chip SPI Flash.
  3. 根据权利要求2所述的方法，其中，所述通过配置的所述可编程器件对所述多片串行外设接口闪存SPI Flash的传输进行控制，还包括：The method of claim 2, wherein the controlling the transmission of the plurality of serial peripheral interface flash SPI Flash by the programmable device configured further comprises:
    通过配置的所述可编程器件对所述多片SPI Flash的写操作和读操作进行控制；Controlling a write operation and a read operation of the plurality of SPI Flash by the programmable device configured;
    其中，所述写操作为，通过将待写入数据依次输出到所述SPI控制器的输出MOSI，所述SPI控制器的输出MOSI分别连接到每片所述SPI Flash的输出MOSI，其中，每片所述SPI Flash在本SPI Flash输入的分频时钟信号的驱动下采样本SPI Flash的输出MOSI上的信号，作为本SPI Flash的输入数据；所述读操作为，将所述多片SPI Flash返回的数据还原为能够解析的数据。The write operation is that, by sequentially outputting data to be written to the output MOSI of the SPI controller, the output MOSI of the SPI controller is respectively connected to the output MOSI of each piece of the SPI Flash, wherein each The SPI Flash samples the signal on the output MOSI of the SPI Flash under the driving of the divided clock signal of the SPI Flash input as the input data of the SPI Flash; the read operation is: the multi-chip SPI Flash The returned data is restored to data that can be parsed.
  4. 根据权利要求3所述的方法，其中，所述将所述多片SPI Flash返回的数据还原为能够解析的数据，包括：The method of claim 3, wherein the restoring the data returned by the plurality of SPI Flash to data that can be parsed comprises:
    在数据传输阶段，通过所述可编程器件将所述多片SPI Flash的输出信号合成为一路所述SPI控制器的输入MISO信号，其中，所述可编程器件在所述SPI控制器输出的时钟信号的上升沿分别对每片所述SPI Flash的输出信号依次采样，每片所述SPI Flash的输出信号为本SPI Flash根据所述本SPI Flash的配置模式，在本SPI Flash输入的分频时钟信号的上升沿或下降沿发送的数据。In the data transmission phase, the output signals of the plurality of SPI Flashs are synthesized by the programmable device into an input MISO signal of the SPI controller, wherein the programmable device outputs a clock at the SPI controller The rising edge of the signal sequentially samples the output signal of each SPI Flash, and the output signal of each SPI Flash is the SPI Flash according to the configuration mode of the SPI Flash, and the divided clock input in the SPI Flash. The data sent on the rising or falling edge of the signal.
  5. 根据权利要求1至4中任一项所述的方法，其中，所述可编程器件为逻辑可编程器件CPLD或现场可编程门阵列FPGA。 The method of any of claims 1 to 4, wherein the programmable device is a logic programmable device CPLD or a field programmable gate array FPGA.
  6. 一种串行外设接口的传输控制装置，包括：A transmission control device for a serial peripheral interface, comprising:
    配置模块，设置为：为单个串行外设接口SPI控制器配置可编程器件；The configuration module is configured to: configure a programmable device for a single serial peripheral interface SPI controller;
    控制模块，设置为：通过所述配置模块配置的所述可编程器件对多片串行外设接口闪存SPI Flash的传输进行控制。The control module is configured to: control the transmission of the plurality of serial peripheral interface flash SPI Flash by the programmable device configured by the configuration module.
  7. 根据权利要求6所述的装置，其中，所述控制模块包括：The apparatus of claim 6 wherein said control module comprises:
    分频单元，设置为：通过所述配置模块配置的所述可编程器件将所述SPI控制器的输出时钟信号进行分频；a frequency dividing unit, configured to: divide, by the programmable device configured by the configuration module, an output clock signal of the SPI controller;
    访问单元，设置为：将所述分频单元分频后产生多个相位不同的分频时钟信号一一对应的传传输到所述多片SPI Flash，访问所述多片SPI Flash。The access unit is configured to: transmit the frequency-divided unit to generate a plurality of frequency-divided clock signals of different phases and transmit the one-to-one correspondence to the plurality of SPI Flash, and access the plurality of SPI Flash.
  8. 一种串行外设接口的传输控制***，包括：一个串行外设接口SPI控制器、可编程器件和多片串行外设接口闪存SPI Flash；A transmission control system for a serial peripheral interface includes: a serial peripheral interface SPI controller, a programmable device, and a plurality of serial peripheral interface flash SPI Flash;
    其中，所述SPI控制器与所述可编程器件连接；Wherein the SPI controller is connected to the programmable device;
    所述可编程器件分别与所述多片SPI Flash连接，所述可编程器件设置为：通过所述可编程器件对所述多片SPI Flash的数据传输进行控制。The programmable devices are respectively connected to the plurality of SPI Flash, and the programmable device is configured to control data transmission of the plurality of SPI Flash by the programmable device.
  9. 根据权利要求8所述的***，其中，所述SPI控制器的时钟信号，输入的MISO信号，输出的片选SS信号经所述可编程器件处理后，分别传输到所述多片SPI Flash；所述SPI控制器输出的MOSI信号直接输出到所述多片SPI Flash。The system of claim 8, wherein the clock signal of the SPI controller, the input MISO signal, and the output chip select SS signal are processed by the programmable device and then transmitted to the plurality of SPI Flash respectively; The MOSI signal output by the SPI controller is directly output to the multi-chip SPI Flash.
  10. 根据权利要求8或9所述的***，其中，所述可编程器件为逻辑可编程器件CPLD或现场可编程门阵列FPGA。 The system of claim 8 or 9, wherein the programmable device is a logic programmable device CPLD or a field programmable gate array FPGA.
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CN204515764U (en) * 2015-03-19 2015-07-29 西电通用电气自动化有限公司 A kind of SPI interface bus structure
CN204650202U (en) * 2015-05-06 2015-09-16 重庆电讯职业学院 A kind of CPLD of utilization realizes the single-chip computer control system of ports-Extending

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CN111381889A (en) * 2018-12-27 2020-07-07 西安诺瓦星云科技股份有限公司 Multi-device system and programmable logic device loading method and device
CN111381889B (en) * 2018-12-27 2024-04-05 西安诺瓦星云科技股份有限公司 Multi-device system and programmable logic device loading method and device
CN112965926A (en) * 2021-03-05 2021-06-15 张玉禄 SPI interface safety chip and SPI interface electron device
CN112965926B (en) * 2021-03-05 2024-04-30 张玉禄 SPI interface safety chip and SPI interface electronic device

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