CN111381889B - Multi-device system and programmable logic device loading method and device - Google Patents
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Abstract
The embodiment of the invention relates to a multi-device system and a programmable logic device loading method and device, which can improve the loading efficiency of the programmable logic device. Wherein the multi-device system comprises, for example: a system-in-chip with a plurality of synchronous serial controllers; the programmable logic devices are respectively connected with the synchronous serial controllers; the system level chip is used for running a configuration driver to start a plurality of kernel threads, and utilizing the plurality of kernel threads to respectively control the plurality of synchronous serial controllers to respectively load configuration files to the plurality of programmable logic devices.
Description
Technical Field
The present invention relates to the field of device configuration technologies, and in particular, to a multi-device system, a programmable logic device loading method, and a programmable logic device loading apparatus.
Background
Programmable logic devices, such as FPGA devices, are now increasingly used. Because the FPGA device is a volatile memory device, the FPGA device needs to be loaded (namely, the FPGA device is configured) after the system is powered on, and then the FPGA device can work normally. The loading efficiency of the FPGA device directly determines the starting time of the system. When a plurality of FPGA devices are arranged in the system and the configuration files of the FPGA devices are large in size, how to efficiently complete the loading of the configuration files of the FPGA devices is important.
The configuration file of the FPGA device is generally a binary file (such as a bin file or a bit file), and the singlechip cannot execute a plurality of tasks at the same time because the singlechip is not supported by an operating system, so that the configuration file of a plurality of FPGA devices can be loaded sequentially; the total time consumption is equal to the sum of the loading time of the configuration files of all the FPGA devices, and the time consumption is long.
Disclosure of Invention
Therefore, the embodiment of the invention provides a multi-device system, a programmable logic device loading method and a programmable logic device loading device, so as to achieve the technical effect of improving the loading efficiency of the programmable logic device.
In one aspect, an embodiment of the present invention provides a multi-device system, including: a system-in-chip with a plurality of synchronous serial controllers; the programmable logic devices are respectively connected with the synchronous serial controllers; the system level chip is used for running a configuration driver to start a plurality of kernel threads, and utilizing the plurality of kernel threads to respectively control the plurality of synchronous serial controllers to respectively load configuration files to the plurality of programmable logic devices.
In one embodiment of the present invention, each of the programmable logic devices has a plurality of configuration pins, a configuration clock input pin and a configuration data input pin of the plurality of configuration pins are respectively connected to a serial clock signal line and a serial data output line of the synchronous serial controller of the plurality of synchronous serial controllers connected to the programmable logic device, and a reset pin, an initialization pin and a configuration status indication pin of the plurality of configuration pins are connected to a plurality of general purpose input/output ports of the system-in-chip.
In one embodiment of the present invention, the plurality of synchronous serial controllers are each a Serial Peripheral Interface (SPI) controller, and the plurality of programmable logic devices are each field programmable gate array devices.
On the other hand, the loading method of the programmable logic device provided by the embodiment of the invention comprises the following steps: running a configuration driver to launch a kernel thread; and utilizing the kernel thread to control a built-in synchronous serial controller to load a configuration file to the programmable logic device; the synchronous serial controller inputs a configuration clock signal to the programmable logic device through a serial clock signal line and sends configuration data in the configuration file to the programmable logic device through a serial data output line.
In one embodiment of the present invention, the running configures a driver to launch a kernel thread as launching a plurality of kernel threads; correspondingly, the method comprises the steps that the built-in synchronous serial controllers controlled by the kernel threads are used for loading configuration files to the programmable logic devices, and the built-in synchronous serial controllers controlled by the kernel threads are used for loading configuration files to the programmable logic devices.
In one embodiment of the present invention, the programmable logic device loading method further includes: utilizing the plurality of kernel threads to respectively control the plurality of programmable logic devices to work in a slave string configuration mode; the phase and polarity of the serial clock signal line are 0, or the phase and polarity of the serial clock signal line are 1.
In one embodiment of the present invention, the plurality of synchronous serial controllers are each a serial peripheral interface controller, and the plurality of programmable logic devices are each field programmable gate array devices.
In still another aspect, a programmable logic device loading apparatus provided in an embodiment of the present invention includes: the thread starting module is used for running a configuration driver to start a plurality of kernel threads; and the file loading module is used for respectively controlling a plurality of built-in synchronous serial controllers to respectively load configuration files to a plurality of programmable logic devices by utilizing the plurality of kernel threads, wherein each synchronous serial controller inputs a configuration clock signal to the corresponding programmable logic device through a serial clock signal line and sends configuration data in the configuration files to the corresponding programmable logic device through a serial data output line.
In one embodiment of the present invention, the file loading module is further configured to control the plurality of programmable logic devices to operate in a slave string configuration mode by using the plurality of kernel threads, respectively; the phase and polarity of the serial clock signal line are 0, or the phase and polarity of the serial clock signal line are 1.
In one embodiment of the invention, the programmable logic device loading apparatus is integrated into a system on chip that has an operating system and a file system installed.
From the above, the technical features of the embodiments of the present invention may have one or more of the following advantages: the synchronous serial controller of the system-level chip is utilized to provide the configuration clock required by the programmable logic device to load the configuration file, so that higher clock frequency can be achieved, and the loading efficiency of the programmable logic device can be improved; furthermore, because a single system-in-chip can load configuration files of a plurality of programmable logic devices at the same time, the total time consumption of the configuration file loading of the plurality of programmable logic devices is almost equal to the time of the configuration file loading of the single programmable logic device, the time consumption of the loading of the plurality of programmable logic devices is generally shortened, and especially when the volume of the configuration file of the programmable logic device is larger, the efficiency is more considerable.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a multi-device system according to a first embodiment of the present invention.
FIG. 2 is a schematic diagram of the connection of a single programmable logic device and a system-on-chip in the multi-device system of FIG. 1.
Fig. 3 is a timing diagram of the operation of the programmable logic device in a slave string configuration mode.
Fig. 4A is a timing diagram of SPI bus data transmission under Mode 0.
Fig. 4B is a timing chart of SPI bus data transmission under Mode 1.
Fig. 5A is a flowchart of a loading method of a programmable logic device according to a second embodiment of the present invention.
FIG. 5B is a flowchart of another loading method of a programmable logic device according to a second embodiment of the present invention.
Fig. 6 is a schematic block diagram of a programmable logic device loading apparatus according to a third embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
[ first embodiment ]
As shown in fig. 1, a multi-device system 10 according to a first embodiment of the present invention includes: a system-in-chip 11 having a plurality of synchronous serial controllers 111 built therein; and a plurality of programmable logic devices 13 connected to the plurality of synchronous serial controllers 111, respectively.
Referring to fig. 2, the single programmable logic device 13 has a plurality of configuration pins, such as a reset pin program_b, an initialization pin init_b, a configuration clock input pin CCLK, a configuration data input pin d01_din, and a configuration status indication pin DONE. The configuration clock input pin CCLK and the configuration data input pin d01_din are respectively connected to the serial clock signal line SCK and the serial data output line MOSI of the corresponding synchronous serial controller 111, and the reset pin program_b, the initialization pin init_b and the configuration status indication pin DONE are connected to the plurality of general purpose input/output ports GPIO of the system-in-chip 11.
As described above, the system-on-chip 11 of the present embodiment may be provided with an operating system and a file system, so that the configuration file of the programmable logic device 13 may be conveniently read (i.e., the binary file is put into the file system), and then the configuration file of the programmable logic device 13 is loaded. The programmable logic device 13 of the present embodiment, for example, operates in a Slave Serial configuration mode (Slave Serial mode), uses a Serial bus, and occupies fewer pins of the system-in-chip 11; the operation timing of the programmable logic device 13 in the slave string configuration mode is shown in fig. 3. According to the characteristic of loading the configuration file in the serial configuration mode, the configuration file loading of the programmable logic device 13 is implemented by utilizing two signal lines in the synchronous serial controller 111 built in the system-in-chip 11 and three GPIO ports of the system-in-chip, namely, the configuration file loading of one programmable logic device 13 is implemented by using one synchronous serial controller 111; the loading of the configuration files of the plurality of programmable logic devices 13 can be achieved by the built-in plurality of synchronous serial controllers 111. The configuration file loading of the programmable logic devices 13 can be implemented by starting a plurality of kernel threads by running a configuration driver in the operating system of the system-level chip 11, and one kernel thread controls the configuration file loading of one programmable logic device 13; in this way, the plurality of programmable logic devices 13 can be loaded at the same time, so that the loading efficiency of the programmable logic devices is greatly improved, especially when the configuration files of the programmable logic devices are large. Furthermore, because the serial clock signal line SCK of the synchronous serial controller 111 is used to provide the configuration clock required by the programmable logic device 13, the clock frequency can be increased compared with the case of directly providing the configuration clock by using the GIPO, thereby improving the loading efficiency and shortening the time consumption for configuring the programmable logic device 13.
To facilitate a clearer understanding of the multi-device system 10 of the present embodiment, a Serial Peripheral Interface (SPI) controller and an FPGA (field programmable gate array) device are described in detail below as examples of the synchronous serial controller 111 and the programmable logic device 13, respectively.
A System On Chip (SOC) such as an ARM core-based system on chip typically has a plurality of SPI controllers built therein, and this embodiment is designed such that each SPI controller controls the loading of a configuration file of an FPGA device, and then writes a configuration driver of the FPGA device to start a plurality of kernel threads to implement the loading of the FPGA device. When the configuration driver operates, a plurality of kernel threads are started to load configuration files for a plurality of FPGA devices.
In view of the foregoing, SPI is a full duplex, synchronous communication bus that operates in a master-slave manner, typically having a master device and one or more slave devices, typically having four signal lines, MOSI, MISO, SCK and CS, respectively; MOSI is Master Output/Slave Input (serial data Output line of Master), MISO is Master Input/Slave Output (serial data Input line of Master), SCK is serial clock signal line, CS is Chip select (Chip select signal line of Slave).
There are four modes of operation for SPI, based on the phase (CPHA) and polarity (CPOL) of the serial clock signal line SCK:
Mode0：CPOL＝0,CPHA＝0
Mode1：CPOL＝0,CPHA＝1
Mode2：CPOL＝1,CPHA＝0
Mode3：CPOL＝1,CPHA＝1
wherein, phase CPHA of SCK: i.e. which edge of the serial clock signal line SCK the SPI starts to sample, 0 representing the first edge, 1 representing the second edge;
polarity CPOL of SCK: that is, when the SPI bus is idle, the serial clock signal line SCK has a level of 0 indicating a low level and 1 indicating a high level.
According to the time sequence of loading the configuration file in the string configuration Mode, the configuration data input pin D01_DIN is used for sampling at the rising edge of the SCK, the embodiment is designed to send out the configuration data of the FPGA device at the rising edge, and the Mode0 or the Mode3 is correspondingly selected to load the configuration file of the FPGA device; the SPI bus data transmission timing under Mode0 is shown in fig. 4A, and the SPI bus data transmission timing under Mode1 is shown in fig. 4B.
In summary, since a single system-in-chip can load configuration files of multiple programmable logic devices at the same time, the total time of loading configuration files of multiple programmable logic devices is almost the same as the time of loading configuration files of a single programmable logic device, so that the time consumption of loading multiple programmable logic devices is generally shortened, and especially when the configuration files of the programmable logic devices are large in size, the efficiency is more considerable. Of course, this embodiment also does not exclude the use of one programmable logic device for the entire multi-device system 10.
[ second embodiment ]
Referring to fig. 5A, a loading method of a programmable logic device according to a second embodiment of the present invention includes:
step S51: running a configuration driver to launch a plurality of kernel threads; and
step S53: respectively controlling a plurality of built-in synchronous serial controllers to load configuration files to a plurality of programmable logic devices by using the plurality of kernel threads; each synchronous serial controller inputs configuration clock signals to the corresponding programmable logic device through serial clock signal lines and sends configuration data in the configuration file to the corresponding programmable logic device through serial data output lines.
Steps S51 and S53 may be performed by the multi-device system 10 of the first embodiment, and their specific details may be referred to the related description of the foregoing first embodiment, so that the description is omitted herein.
Referring to fig. 5B, before step S53, step S52 may be further included: and respectively controlling the programmable logic devices to work in a slave string configuration mode by utilizing the kernel threads. It should be noted that, the configuration modes of the programmable logic device commonly include a Master serial (Master serial), a Master Parallel (Master Parallel), a Slave serial (Slave serial), a Slave Parallel (Slave select map), and the like; these configuration MODEs are typically configured by hardware pins MODE [2:0] of the programmable logic device. Typically, these pins are implemented by pull-up resistors and pull-down resistors in hardware, and these mode configuration pins may be connected to GPIO ports of the system-in-chip, and the configuration mode of the programmable logic device may be configured by the system-in-chip (or software) as described in this embodiment. In addition, it should be noted that the loading method of the programmable logic device of the present embodiment is also applicable to the loading situation of the configuration file of a single programmable logic device, and in this situation, only one kernel thread needs to be started to implement the loading of the configuration file of the programmable logic device.
[ third embodiment ]
Referring to fig. 6, a programmable logic device loading apparatus according to a third embodiment of the present invention includes, for example: a thread start module 61 and a file load module 63.
Wherein the thread start module 61 is for example for running a configuration driver to start a plurality of kernel threads; the file loading module 63 is configured to control, for example, the built-in synchronous serial controllers to load configuration files to the programmable logic devices respectively by using the plurality of kernel threads, where each synchronous serial controller inputs a configuration clock signal to the corresponding programmable logic device through a serial clock signal line, and sends configuration data in the configuration files to the corresponding programmable logic device through a serial data output line.
Furthermore, the file loading module 63 may be further configured to control the plurality of programmable logic devices to operate in a slave string configuration mode by using the plurality of kernel threads, for example; the phase and polarity of the serial clock signal line are 0, or the phase and polarity of the serial clock signal line are 1. Furthermore, the programmable logic device loading apparatus of the present embodiment may be integrated with a system-on-chip installed with an operating system and a file system, for example, a controller based on an ARM core, which may be installed with an Android system, a Linux system, or the like.
As for the functional details of the thread start module 61 and the file load module 63, reference may be made to the description related to the foregoing first embodiment, and the details are not repeated here.
In addition, it should be understood that the foregoing embodiments are merely exemplary illustrations of the present invention, and the technical solutions of the embodiments may be arbitrarily combined and matched without conflict in technical features, contradiction in structure, and departure from the purpose of the present invention.
In the several embodiments provided herein, it should be understood that the disclosed systems, devices, and/or methods may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and the division of the units/modules is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or modules may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units/modules described as separate units may or may not be physically separate, and units/modules may or may not be physically units, may be located in one place, or may be distributed on multiple network units. Some or all of the units/modules may be selected according to actual needs to achieve the purpose of the embodiment.
In addition, each functional unit/module in the embodiments of the present invention may be integrated in one processing unit/module, or each unit/module may exist alone physically, or two or more units/modules may be integrated in one unit/module. The integrated units/modules may be implemented in hardware or in hardware plus software functional units/modules.
The integrated units/modules implemented in the form of software functional units/modules described above may be stored in a computer readable storage medium. The software functional units described above are stored in a storage medium and include instructions for causing one or more processors of a computer device (which may be a personal computer, a server, or a network device, etc.) to perform some steps of the methods described in the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (9)
1. A multi-device system, comprising:
a system-in-chip with a plurality of synchronous serial controllers; and
the programmable logic devices are respectively connected with the synchronous serial controllers;
the system level chip is used for running a configuration driver to start a plurality of kernel threads, and utilizing the plurality of kernel threads to respectively control the plurality of synchronous serial controllers to respectively load configuration files to the plurality of programmable logic devices, wherein the plurality of programmable logic devices simultaneously load the configuration files, an operating system and a file system are installed on the system level chip, the programmable logic devices work in a slave string configuration mode, and the synchronous serial controllers input configuration clock signals to the programmable logic devices through serial clock signal lines.
2. The multi-device system of claim 1, wherein each of the programmable logic devices has a plurality of configuration pins, a configuration clock input pin and a configuration data input pin of the plurality of configuration pins are respectively connected to the serial clock signal line and the serial data output line of the synchronous serial controller of the plurality of synchronous serial controllers connected to the programmable logic device, and a reset pin, an initialization pin, and a configuration status indication pin of the plurality of configuration pins are connected to a plurality of general purpose input/output ports of the system-in-chip.
3. The multi-device system of claim 1 or 2, wherein the plurality of synchronous serial controllers are each a Serial Peripheral Interface (SPI) controller, and the plurality of programmable logic devices are each field programmable gate array devices.
4. A method for loading a programmable logic device, comprising:
running a configuration driver to launch a kernel thread; and
loading a configuration file to a programmable logic device by utilizing the kernel thread to control a built-in synchronous serial controller; the synchronous serial controller inputs configuration clock signals to the programmable logic device through serial clock signal lines and sends configuration data in the configuration file to the programmable logic device through serial data output lines, wherein the number of the programmable logic devices is multiple, and the configuration file is loaded by the multiple programmable logic devices at the same time;
the programmable logic device loading method is executed by a multi-device system, the multi-device system comprises a system-level chip and the programmable logic device, which are connected with each other, the system-level chip is provided with an operating system and a file system, and the running configuration driver is used for starting kernel threads to start a plurality of kernel threads;
the loading method of the programmable logic device further comprises the following steps: and respectively controlling the programmable logic devices to work in a slave string configuration mode by utilizing the kernel threads.
5. The method of loading a programmable logic device according to claim 4, wherein the loading of the configuration file into the programmable logic device by the embedded synchronous serial controller controlled by the kernel thread is to load the configuration file into the plurality of programmable logic devices by the embedded synchronous serial controllers controlled by the plurality of kernel threads, respectively.
6. The programmable logic device loading method of claim 5, further comprising: the phase and polarity of the serial clock signal line are 0, or the phase and polarity of the serial clock signal line are 1.
7. The method for loading a programmable logic device according to any one of claims 4 to 6, wherein the plurality of synchronous serial controllers are serial peripheral interface controllers, respectively, and the plurality of programmable logic devices are field programmable gate array devices, respectively.
8. A programmable logic device loading apparatus, comprising:
the thread starting module is used for running a configuration driver to start a plurality of kernel threads; and
the file loading module is used for respectively controlling a plurality of built-in synchronous serial controllers to respectively load configuration files to a plurality of programmable logic devices by utilizing the plurality of kernel threads, wherein each synchronous serial controller inputs a configuration clock signal to the corresponding programmable logic device through a serial clock signal line and sends configuration data in the configuration files to the corresponding programmable logic device through a serial data output line, and the plurality of programmable logic devices simultaneously load the configuration files;
the programmable logic device loading device is integrated with a system-on-chip provided with an operating system and a file system;
the file loading module is further used for controlling the programmable logic devices to work in a slave string configuration mode by utilizing the kernel threads respectively.
9. The programmable logic device loading apparatus of claim 8, wherein the phase and polarity of the serial clock signal line is 0 or the phase and polarity of the serial clock signal line is 1.
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| 基于FPGA的多通道数据采集控制器设计与实现;赵涛;郭猛;顾亚浏;章阳;;计算机工程;20170615(06);全文 * |
| 基于FPGA的多通道数据采集***设计与实现;谈良;纪凌;;电子测量技术;20180308(05);全文 * |
| 基于Microblaze多核***的设计及在FPGA上的实现;李剑阳;付宇卓;刘婷;;微电子学与计算机;20090705(07);全文 * |
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