CN107145465B - Transmission control method, device and system for Serial Peripheral Interface (SPI) - Google Patents
Transmission control method, device and system for Serial Peripheral Interface (SPI) Download PDFInfo
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- CN107145465B CN107145465B CN201610116770.1A CN201610116770A CN107145465B CN 107145465 B CN107145465 B CN 107145465B CN 201610116770 A CN201610116770 A CN 201610116770A CN 107145465 B CN107145465 B CN 107145465B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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Abstract
The invention discloses a transmission control method, a device and a system of a Serial Peripheral Interface (SPI), wherein the method comprises the following steps: configuring a programmable device for a single SPI controller; the transmission of a plurality of SPI Flash is controlled by the configured programmable device, the problem that a plurality of SPI controllers are needed to control the plurality of SPI Flash in the related technology is solved, the occupation of a CPU is saved, and the access speed is improved.
Description
Technical Field
The invention relates to the technical field of intelligent traffic, in particular to a transmission control method, a device and a system of a Serial Peripheral Interface (SPI).
Background
Serial Peripheral Interface (SPI) Flash is used in embedded systems because of its features of convenience, ease of connection, few pins, etc. But because it uses serial transmission of data, transmission is slow, limited by the frequency range of the operational clock. And the erase and write speed of the Flash on chip can also become a system bottleneck.
Aiming at the problem that a plurality of SPI controllers are needed to control a plurality of SPI Flash in the related technology, an effective solution is not provided yet.
Disclosure of Invention
The invention provides a transmission control method and device of SPI (Serial peripheral interface), which at least solve the problem that a plurality of SPI controllers are needed to control a plurality of SPI Flash in the related technology.
According to an aspect of the present invention, there is provided a transmission control method of an SPI, including: configuring a programmable device for a single SPI controller; and controlling the transmission of a plurality of SPI Flash through the configured programmable device.
Further, the controlling the transmission of the multiple pieces of SPI Flash by the configured programmable device includes: and dividing the frequency of the output clock CLK of the SPI controller through the programmable device to generate a plurality of clocks with different phases, and respectively transmitting the clocks into the plurality of SPI Flash to access the plurality of SPI Flash.
Further, the controlling the transmission of the multiple pieces of SPI Flash by the configured programmable device includes: controlling the write operation and the read operation of the multiple SPI Flash through the configured programmable device; the writing operation is that data to be written are sequentially output to the output MOSI of the SPI controller and are respectively connected to the output MOSI of the SPI Flash, wherein signals on the MOSI are driven by clocks CLK after respective frequency division of the SPI Flash to be used as input data of the SPI Flash; and the reading operation is to restore the data returned by the multiple pieces of SPI Flash into data capable of being analyzed.
Further, the restoring the data returned by the multiple pieces of SPI Flash to data that can be analyzed includes: and in the data transmission stage, synthesizing the outputs of the multiple SPI Flash into one path of input MISO of the SPI controller through the programmable device, wherein the programmable device respectively and sequentially samples the outputs of the multiple SPI Flash on the rising edge of an output clock CLK of the SPI controller, and the outputs of the multiple SPI Flash are data sent by the multiple SPI Flash on the rising edge or the falling edge of the CLK after frequency division according to different configuration modes.
Further, the Programmable devices are Logic Programmable devices (CPLDs) and Field Programmable Gate Arrays (FPGAs).
According to another aspect of the present invention, there is provided a transmission control apparatus for a serial peripheral interface SPI, comprising: the configuration module is used for configuring the programmable device for the single SPI controller; and the control module is used for controlling the transmission of a plurality of SPI Flash through the configured programmable device.
Further, the control module includes: and the access unit is used for dividing the frequency of the output clock CLK of the SPI controller through the programmable device to generate a plurality of clocks with different phases, and the clocks are respectively transmitted into the plurality of SPI Flash chips to access the plurality of SPI Flash chips.
According to another aspect of the present invention, there is also provided a transmission control system of a serial peripheral interface SPI, comprising: the system comprises an SPI controller, a programmable device and a plurality of SPI flashes, wherein the SPI controller is connected with the programmable device; and the programmable device is respectively connected with the plurality of SPI Flash and is used for controlling the data transmission of the plurality of SPI Flash through the programmable device.
Furthermore, a clock signal CLK of the SPI controller is input into MISO, and the output chip selection SS is respectively connected with the plurality of SPI Flash after being processed by the programmable device; and the output MOSI of the SPI controller is directly output to the plurality of SPI flashes.
Furthermore, the programmable device is a logic programmable device CPLD and a field programmable gate array FPGA.
According to the invention, a programmable device is configured for a single SPI controller; the transmission of a plurality of SPI Flash is controlled by the configured programmable device, so that the problem that a plurality of SPI controllers are needed to control the plurality of SPI Flash in the related technology is solved, the occupation of a CPU is saved, and the access speed is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
fig. 1 is a flowchart of a transmission control method of a serial peripheral interface SPI according to an embodiment of the present invention;
fig. 2 is a block diagram of a transmission control apparatus of a serial peripheral interface SPI according to an embodiment of the present invention;
FIG. 3 is a block diagram I of a transmission control apparatus of the SPI according to the preferred embodiment of the present invention;
FIG. 4 is a block diagram of SPI access control system connections according to an embodiment of the present invention;
FIG. 5 is a flow chart of a method of SPI access control according to an embodiment of the present invention;
FIG. 6 is a timing diagram of a single SPI connecting two SPI flashes according to an embodiment of the present invention;
fig. 7 is a timing diagram of a single SPI connected to four SPI flashes according to an embodiment of the present invention.
Detailed Description
The invention will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
An embodiment of the present invention provides a transmission control method for a serial peripheral interface SPI, and fig. 1 is a flowchart of the transmission control method for the serial peripheral interface SPI according to the embodiment of the present invention, and as shown in fig. 1, the method includes:
step S102, configuring a programmable device for a single SPI controller;
and step S104, controlling the transmission of the plurality of SPI Flash through the configured programmable device.
Through the steps, a programmable device is configured for a single SPI controller; the transmission of a plurality of SPI Flash is controlled by the configured programmable device, the problem that a plurality of SPI controllers are needed to control the plurality of SPI Flash in the related technology is solved, the occupation of a CPU is saved, and the access speed is improved.
In an optional embodiment, controlling the transmission of the multiple pieces of SPI Flash by the configured programmable device may include: and dividing the frequency of the output clock CLK of the SPI controller through the programmable device to generate a plurality of clocks with different phases, and respectively transmitting the clocks into the plurality of SPI Flash chips to access the plurality of SPI Flash chips.
In another alternative embodiment, controlling the transmission of the multiple pieces of SPI Flash by the configured programmable device may include: controlling the write operation and the read operation of the multiple SPI Flash through the configured programmable device; the write operation is that data to be written are sequentially output to the output MOSI of the SPI controller and are respectively connected to the output MOSI of the SPI Flash, wherein the SPI Flash drives signals on the MOSI under the driving of a clock CLK after respective frequency division to serve as input data of the SPI Flash; the read operation is to restore the data returned by the multiple pieces of SPI Flash to data that can be analyzed.
Further, the restoring the data returned by the multiple pieces of SPI Flash to data that can be analyzed may include: and in the data transmission stage, synthesizing the outputs of the multiple SPI Flash into one input MISO of the SPI controller through the programmable device, wherein the programmable device respectively and sequentially samples the outputs of the multiple SPI Flash on the rising edge of an output clock CLK of the SPI controller, and the outputs of the multiple SPI Flash are data sent by the multiple SPI Flash on the rising edge or the falling edge of the CLK after frequency division according to different configuration modes.
Further, the programmable device can be a logic programmable device CPLD and a field programmable gate array FPGA.
An embodiment of the present invention provides a transmission control device for a serial peripheral interface SPI, and fig. 2 is a block diagram of the transmission control device for the serial peripheral interface SPI according to the embodiment of the present invention, and as shown in fig. 2, the transmission control device includes:
a configuration module 22 for configuring the programmable device for a single SPI controller;
and the control module 24 is configured to control transmission of the multiple pieces of SPI Flash through the configured programmable device.
Fig. 3 is a block diagram one of the transmission control apparatus of the serial peripheral interface SPI according to the preferred embodiment of the present invention, and as shown in fig. 3, the control module 24 includes:
and the access unit 32 is used for dividing the frequency of the output clock CLK of the SPI controller through the programmable device to generate a plurality of clocks with different phases, and the clocks are respectively transmitted into the plurality of SPI Flash chips to access the plurality of SPI Flash chips.
The embodiment of the present invention further provides a transmission control system for a serial peripheral interface SPI, including: an SPI controller, a programmable device and a plurality of SPI flashes,
the SPI controller is connected with the programmable device;
the programmable device is respectively connected with the plurality of SPI Flash and is used for controlling the data transmission of the plurality of SPI Flash through the programmable device.
Furthermore, a clock signal CLK of the SPI controller is input into MISO, and the output chip selection SS is respectively connected with the plurality of SPI Flash after being processed by the programmable device; the output MOSI of the SPI controller is directly output to the plurality of SPI flashes.
Further, the programmable device is a logic programmable device CPLD and a field programmable gate array FPGA.
The embodiments of the present invention are further described below with reference to specific embodiments by taking CPLDs as examples.
The embodiment of the invention provides a method for realizing access to multiple SPI Flash by a single SPI controller, which can improve the read-write transmission and erasing speed of the SPI Flash by times under the condition of not changing SPI and Flash communication protocols. The method comprises the following specific steps:
fig. 4 is a block diagram of the SPI access control system connection according to the embodiment of the present invention, and as shown in fig. 4, there are four signals at the SPI controller end, which are respectively the clock signal clk (clock), the Output mosi (master Output Slave Input) of the SPI controller, the Input miso (master Input Slave Output) of the SPI controller, and the chip select ss (Slave) Output by the SPI controller. The MOSI signal is directly output to the SPI Flash, and other three signals are processed by the programmable logic device and then are respectively connected with the SPI Flash;
the programmable logic device divides the CLK signal by N frequency, outputs a plurality of paths of clocks with the phase difference of 1 CLK cycle, and respectively outputs and connects the clocks to the clock inputs of a plurality of SPI Flash, wherein N is an integral multiple of 2, and the maximum number of the connected FLASH is N;
the transmission flow is basically consistent with the basic SPI transmission and is divided into three stages, namely a command word (command) transmission stage, an address (address) transmission stage and a data (data) transmission stage. And transmitting the command word and the address to an SPI Flash end, and sampling and transmitting the rising edge or the falling edge of the CLKn after frequency division according to different working modes.
For a typical write operation, the CPU outputs the data to be written to MOSI in turn, directly connected to MOSI0 through MOSI (N-1) of each SPI Flash. At this stage, the SPI Flash chip samples the signals on the MOSI as its own input data under the drive of the respective divided clock CLKn. The writing operation only needs to pay attention to the fact that the SPI Flash can correctly sample data, but for one reading operation, the data returned by the SPI Flash needs to be restored to the data which can be analyzed by the CPU. In the data (data) transmission stage of the read operation, the SPI Flash end sends data on the rising edge or the falling edge of the CLKn after frequency division according to different configured modes, and the programmable logic device samples multiple paths of output in sequence on the rising edge of a clock CLK output by each CPU in the data transmission stage, keeps a period of time, and synthesizes the multiple paths of output into a path of MISO to be input to the CPU end for analysis.
The method for realizing the speed-up access of the plurality of SPI FLASH chips by the single SPI controller provided by the embodiment of the invention only uses the single SPI controller without additionally occupying the SPI controller of the CPU, can solve the problem that the SPI transmission is limited by the frequency range of a working clock and the limitation of low erasing speed, and has very good practical value.
In an SPI reading operation example, the system mainly comprises an SPI controller and two SPI flashes, and clock signals CLK, MISO and SS at the end of the SPI controller are processed by a CPLD and then are respectively connected with the two SPI flashes; and directly outputting the MOSI to the SPI Flash.
The transmission stage is divided into three stages, a first stage SPI controller (SPI Master) outputs a command word signal, a second stage SPI controller (SPI Master) outputs an access address signal, and a third stage SPI Flash outputs readback data.
Fig. 5 is a flowchart of an SPI access control method according to an embodiment of the present invention, and as shown in fig. 5, the specifically transmitted data is as follows:
the method for realizing the speed-up access of the plurality of SPI Flash through the single SPI controller specifically comprises the following steps:
step S1, configuring the operation mode of the SPI controller, taking the configuration of the SPI controller operating in mode 1 as an example, sending data on the rising edge and sampling data on the falling edge.
Step S2, as shown in fig. 6, which is a timing diagram illustrating that a single SPI connects two pieces of SPI Flash according to the embodiment of the present invention, as shown in fig. 6, in the first stage of transmission, the chip select SS is pulled down first. The SPI controller sends command word signals in sequence on the rising edge, the length of the command word is 8 bits, and because two SPI flashes are connected, the command word needs to be sent twice. Wherein, two SPI Flash are called a, b respectively, and the sending mode is: and sequentially sending the 7 th (0-base) bit contents of the two SPI Flash command words, and repeating the steps until the 0 th (0-base) bit contents of the two SPI Flash commands are sent, wherein the specific steps are as follows. On the first rising edge, to the 7 th bit (0-base) of the a command word, and on the second rising edge to the 7 th bit (0-base) of the b command word; by analogy, the command word bit sent to a on the odd rising edge and the command word bit sent to b on the even rising edge are sent sequentially from the high bit to the low bit, i.e., from the 7 th bit to the 0 th bit. A total of 16 bit word long command word signals are transmitted.
The specific data transmitted are as follows:
the first stage transmits data:
in step S3, in the second stage of transmission, the SPI controller sequentially transmits the access address signal at the rising edge, the access address word length is 24 bits, the transmission method is the same as the first stage (S2), the address is also transmitted twice, the address is sequentially transmitted at the odd-even rising edge, the address is transmitted from the high bit, and the address signal with the word length of 48 bits is transmitted in total, which is the same as the step S2.
A step S4 of determining whether the operation is a read operation or a write operation, executing a step S5 when the determination result is a write operation, and executing a step S6 when the determination result is a read operation;
step S5, in the third stage of transmission, the CPU outputs the data to be written to the MOSI in turn, and directly connects to the MOSI0 to MOSI (N-1) of each SPI Flash. At this stage, the SPI Flash chip samples the signals on the MOSI as its own input data under the drive of the respective divided clock CLKn.
In the step S6, in the third stage of transmission, N SPI Flash sequentially outputs N read-back data MISO0 to MISO (N-1). At this stage, the CPLD is triggered by the SPI controller output clock CLK to sequentially capture 8-bit data of the MISOs 0 to MISO (N-1), and then keep one CLK period to obtain a total output MISO of 8 × N bit word length from high bit to low bit, which is input to the SPI controller.
In step S7, in the third stage of completing the transmission, the chip select is pulled high, and the one-time complete transmission is finished.
In the third phase of transmission, SPI Flash outputs read-back data on CLKn falling edge, a outputs data MISO0, b outputs data MISO 1. Because of even number frequency multiplication, the falling edge after frequency division can correspond to the rising edge of CLK one by one, at this stage, CPLD is triggered by the rising edge of output clock CLK of SPI controller, collects the 8 bit data of MISOn of a, b in turn, and keeps a CLK period, obtains the output MISO of 16 bit word length, and inputs it to SPI controller directly. At this point a complete transmission process is completed.
The situation that the single SPI is connected with the four SPI flashes is similar to the situation that the single SPI is connected with the two SPI flashes, and fig. 7 is a timing diagram of the single SPI connected with the four SPI flashes according to the embodiment of the present invention, as shown in fig. 7, which is not described herein again.
In the embodiment of the invention, only a single SPI controller is utilized to realize the control of the transmission of a plurality of SPI Flash chips, the SPI controller of a CPU is not required to be additionally occupied, and the single SPI Flash chip is accessed by using the low-frequency clock after frequency division by a method of dividing the frequency of the CPU clock and staggering the phase, so that the transmission frequency of the SPI Flash after combination is multiplied, the erasing speed of the SPI Flash after combination of the plurality of chips is correspondingly multiplied, and the SPI Flash controller is suitable for being used in an embedded system.
It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A transmission control method of a Serial Peripheral Interface (SPI) is characterized by comprising the following steps:
configuring a programmable device for a single SPI controller;
controlling the transmission of a plurality of SPI Flash through the configured programmable device;
the control of the transmission of the plurality of SPI Flash through the configured programmable device comprises the following steps: and dividing the frequency of the output clock CLK of the SPI controller through the programmable device to generate a plurality of clocks with different phases, and respectively transmitting the plurality of clocks into the plurality of SPI Flash memories to access the plurality of SPI Flash memories so as to control the transmission of the plurality of SPIFlash.
2. The method according to claim 1, wherein controlling the transmission of the multiple pieces of SPI Flash by the configured programmable device comprises:
controlling the write operation and the read operation of the multiple SPI Flash through the configured programmable device;
the write operation is to output data to be written to the output MOSI of the SPI controller in sequence and respectively connect the output MOSI of the SPI Flash, wherein signals on the MOSI are sampled by the SPIFlash under the drive of the clock CLK after respective frequency division and serve as input data of the SPI Flash; and the reading operation is to restore the data returned by the multiple pieces of SPI Flash into data capable of being analyzed.
3. The method of claim 2, wherein restoring the data returned by the multiple pieces of SPIFlash to parsable data comprises:
and in the data transmission stage, synthesizing the outputs of the multiple SPI Flash into one path of input MISO of the SPI controller through the programmable device, wherein the programmable device respectively and sequentially samples the outputs of the multiple SPI Flash on the rising edge of an output clock CLK of the SPI controller, and the outputs of the multiple SPI Flash are data sent by the multiple SPI Flash on the rising edge or the falling edge of the CLK after frequency division according to different configuration modes.
4. The method according to any of claims 1 to 3, characterized in that the programmable devices are logic programmable devices (CPLDs) and Field Programmable Gate Arrays (FPGAs).
5. A transmission control device of a Serial Peripheral Interface (SPI) is characterized by comprising:
the configuration module is used for configuring the programmable device for the single SPI controller;
the control module is used for controlling the transmission of a plurality of SPI Flash through the configured programmable device;
the control module comprises an access unit, and the access unit is used for dividing the frequency of the output clock CLK of the SPI controller through the programmable device, generating a plurality of clocks with different phases, and respectively transmitting the clocks into the plurality of SPI Flash memories to access the plurality of SPI Flash memories so as to control the transmission of the plurality of SPIFlash memories.
6. A transmission control system of a Serial Peripheral Interface (SPI) is characterized by comprising: an SPI controller, a programmable device and a plurality of SPI flashes,
the SPI controller is connected with the programmable device;
the programmable device is respectively connected with the multiple SPIFlases and is used for dividing the frequency of the output clock of the SPI controller through the programmable device to generate a plurality of clocks with different phases, and the clocks are respectively transmitted to the multiple SPIFlases to access the multiple SPIFlases so as to control the data transmission of the multiple SPIFlases.
7. The system of claim 6, wherein the clock signal CLK of the SPI controller, the input MISO, and the output chip select SS are processed by the programmable device and then respectively connected to the plurality of pieces of SPI Flash; and the output MOSI of the SPI controller is directly output to the plurality of SPI flashes.
8. The system according to claim 6 or 7, characterized in that the programmable devices are logic programmable devices (CPLDs) and Field Programmable Gate Arrays (FPGAs).
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| CN201610116770.1A CN107145465B (en) | 2016-03-01 | 2016-03-01 | Transmission control method, device and system for Serial Peripheral Interface (SPI) |
| PCT/CN2017/071163 WO2017148221A1 (en) | 2016-03-01 | 2017-01-13 | Transmission control method, apparatus and system for serial peripheral interface |
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| CN201610116770.1A CN107145465B (en) | 2016-03-01 | 2016-03-01 | Transmission control method, device and system for Serial Peripheral Interface (SPI) |
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| CN111381889B (en) * | 2018-12-27 | 2024-04-05 | 西安诺瓦星云科技股份有限公司 | Multi-device system and programmable logic device loading method and device |
| CN110928813B (en) * | 2019-11-18 | 2021-04-30 | 珠海运控电机有限公司 | System and method for outputting low-frequency synchronous signal based on double SPI |
| CN111782574A (en) * | 2020-07-14 | 2020-10-16 | 北京四季豆信息技术有限公司 | Serial peripheral interface control method and serial peripheral interface controller |
| CN112052213B (en) * | 2020-10-10 | 2022-12-02 | 乐鑫信息科技（上海）股份有限公司 | Enhanced SPI controller and method of operating an SPI controller |
| CN112965926B (en) * | 2021-03-05 | 2024-04-30 | 张玉禄 | SPI interface safety chip and SPI interface electronic device |
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| CN203433337U (en) * | 2013-07-26 | 2014-02-12 | 南京第五十五所技术开发有限公司 | Multi-channel expansion structure capable of multiplexing SPI control bus |
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| US7171577B2 (en) * | 2003-10-06 | 2007-01-30 | Texas Instruments Incorporated | Methods and apparatus for a system clock divider |
| CN101819560B (en) * | 2009-02-27 | 2012-05-30 | 杭州晟元芯片技术有限公司 | Method and device for executing program of SPI interface memory |
| CN102253913B (en) * | 2011-05-30 | 2013-11-20 | 神州数码网络(北京)有限公司 | Device for carrying out state acquisition and output control on multi-board-card port |
| CN202453878U (en) * | 2012-01-12 | 2012-09-26 | 河南科技大学 | SPI (Serial Peripheral Interface) communication port based on CPLD (Complex Programmable Logic Device) |
| CN102622191B (en) * | 2012-02-24 | 2014-11-19 | 北京经纬恒润科技有限公司 | High-speed mass storage plate |
| US9348783B2 (en) * | 2012-04-19 | 2016-05-24 | Lockheed Martin Corporation | Apparatus and method emulating a parallel interface to effect parallel data transfer from serial flash memory |
| CN103064805B (en) * | 2012-12-25 | 2015-12-09 | 深圳先进技术研究院 | SPI controller and communication means |
| CN103927131B (en) * | 2014-03-25 | 2017-02-15 | 四川和芯微电子股份有限公司 | Synchronous flash memory and USB (universal serial bus) flash disk starting method and control system thereof |
| CN204515764U (en) * | 2015-03-19 | 2015-07-29 | 西电通用电气自动化有限公司 | A kind of SPI interface bus structure |
| CN204650202U (en) * | 2015-05-06 | 2015-09-16 | 重庆电讯职业学院 | A kind of CPLD of utilization realizes the single-chip computer control system of ports-Extending |
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| CN203433337U (en) * | 2013-07-26 | 2014-02-12 | 南京第五十五所技术开发有限公司 | Multi-channel expansion structure capable of multiplexing SPI control bus |
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