CN111381889A - Multi-device system and programmable logic device loading method and device - Google Patents
Multi-device system and programmable logic device loading method and device Download PDFInfo
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Abstract
The embodiment of the invention relates to a multi-device system and a method and a device for loading a programmable logic device, which can improve the loading efficiency of the programmable logic device. Wherein the multi-device system comprises, for example: the system level chip is internally provided with a plurality of synchronous serial controllers; and a plurality of programmable logic devices respectively connected with the plurality of synchronous serial controllers; the system-on-chip is used for running a configuration driver to start a plurality of kernel threads and respectively controlling the synchronous serial controllers to respectively load configuration files to the programmable logic devices by utilizing the kernel threads.
Description
Technical Field
The invention relates to the technical field of device configuration, in particular to a multi-device system, a programmable logic device loading method and a programmable logic device loading device.
Background
Programmable logic devices, such as FPGA devices, are now increasingly used. Because the FPGA device is a volatile memory device, the system needs to be loaded (i.e., the FPGA device is configured) after being powered on, and then the FPGA device can normally work. The loading efficiency of the FPGA device directly determines the starting time of the system. When a plurality of FPGA devices are arranged in the system and the configuration file of the FPGA devices is large in size, how to efficiently load the configuration file of the FPGA devices is very important.
The configuration file of the FPGA device is generally a binary file (such as a bin file or a bit file), and the single chip microcomputer can only load the configuration files of a plurality of FPGA devices in sequence because the single chip microcomputer is not supported by an operating system and cannot execute a plurality of tasks at the same time; the total time consumption is equal to the sum of the configuration file loading time of each FPGA device, and the time consumption is long.
Disclosure of Invention
Therefore, the embodiment of the invention provides a multi-device system, a programmable logic device loading method and a programmable logic device loading device, so as to achieve the technical effect of improving the loading efficiency of the programmable logic device.
In one aspect, a multi-device system provided in an embodiment of the present invention includes: the system level chip is internally provided with a plurality of synchronous serial controllers; and a plurality of programmable logic devices respectively connected with the plurality of synchronous serial controllers; the system-on-chip is used for running a configuration driver to start a plurality of kernel threads and respectively controlling the synchronous serial controllers to respectively load configuration files to the programmable logic devices by utilizing the kernel threads.
In one embodiment of the invention, each programmable logic device has a plurality of configuration pins, a configuration clock input pin and a configuration data input pin in the plurality of configuration pins are respectively connected with a serial clock signal line and a serial data output line of the synchronous serial controller connected with the programmable logic device in the plurality of synchronous serial controllers, and a reset pin, an initialization pin and a configuration state indication pin in the plurality of configuration pins are connected with a plurality of universal input/output ports of the system-on-chip.
In one embodiment of the invention, the plurality of synchronous serial controllers are respectively Serial Peripheral Interface (SPI) controllers, and the plurality of programmable logic devices are respectively field programmable gate array devices.
On the other hand, a method for loading a programmable logic device provided by the embodiment of the present invention includes: running a configuration driver to start a kernel thread; loading a configuration file to a programmable logic device by utilizing the built-in synchronous serial controller controlled by the kernel thread; and the synchronous serial controller inputs a configuration clock signal to the programmable logic device through a serial clock signal line and sends configuration data in the configuration file to the programmable logic device through a serial data output line.
In one embodiment of the present invention, the running the configuration driver to start the kernel thread is to start a plurality of kernel threads; correspondingly, the step of loading the configuration file to the programmable logic device by using the built-in synchronous serial controller controlled by the kernel thread is to load the configuration file to the plurality of programmable logic devices by using the plurality of kernel threads to respectively control the built-in synchronous serial controllers.
In an embodiment of the present invention, the method for loading a programmable logic device further includes: respectively controlling the programmable logic devices to work in a slave string configuration mode by utilizing the kernel threads; the phase and polarity of the serial clock signal line are 0, or the phase and polarity of the serial clock signal line are 1.
In an embodiment of the present invention, the plurality of synchronous serial controllers are serial peripheral interface controllers respectively, and the plurality of programmable logic devices are field programmable gate array devices respectively.
In another aspect, an embodiment of the present invention provides a programmable logic device loading apparatus, including: the thread starting module is used for running a configuration driver to start a plurality of kernel threads; and the file loading module is used for respectively controlling a plurality of built-in synchronous serial controllers to respectively load configuration files to a plurality of programmable logic devices by utilizing the plurality of kernel threads, wherein each synchronous serial controller inputs configuration clock signals to the corresponding programmable logic devices through serial clock signal lines and sends configuration data in the configuration files to the corresponding programmable logic devices through serial data output lines.
In an embodiment of the present invention, the file loading module is further configured to control the plurality of programmable logic devices to operate in a slave string configuration mode by using the plurality of kernel threads, respectively; the phase and polarity of the serial clock signal line are 0, or the phase and polarity of the serial clock signal line are 1.
In an embodiment of the present invention, the plc loading apparatus is integrated into a system on chip with an operating system and a file system installed therein.
As can be seen from the above, the above technical features of the embodiments of the present invention may have one or more of the following advantages: because the configuration clock required by the programmable logic device for loading the configuration file is provided by using the synchronous serial controller of the system-level chip, higher clock frequency can be achieved, and the loading efficiency of the programmable logic device can be improved; moreover, since a single system-on-chip can load configuration files of a plurality of programmable logic devices at the same time, the total time consumption for loading the configuration files of the plurality of programmable logic devices is about the same as the time consumption for loading the configuration files of the single programmable logic device, so that the time consumption for loading the plurality of programmable logic devices is reduced on the whole, and particularly, when the configuration files of the programmable logic devices are large in size, the efficiency is considerable.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a multi-device system according to a first embodiment of the present invention.
Fig. 2 is a schematic diagram of the connection of a single programmable logic device and a system-on-chip in the multi-device system shown in fig. 1.
Fig. 3 is a timing diagram illustrating operation of the programmable logic device in a slave string configuration mode.
Fig. 4A is a timing diagram of SPI bus data transmission under Mode 0.
Fig. 4B is a timing diagram of SPI bus data transmission under Mode 1.
Fig. 5A is a flowchart of a method for loading a programmable logic device according to a second embodiment of the present invention.
Fig. 5B is a flowchart of another method for loading a programmable logic device according to a second embodiment of the present invention.
Fig. 6 is a block diagram of a loading apparatus of a programmable logic device according to a third embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
[ first embodiment ] A method for manufacturing a semiconductor device
As shown in fig. 1, a multi-device system 10 according to a first embodiment of the present invention includes: a system-on-chip 11 having a plurality of synchronous serial controllers 111 built therein; and a plurality of programmable logic devices 13 connected to the plurality of synchronous serial controllers 111, respectively.
Referring to fig. 2, the single programmable logic device 13 has a plurality of configuration pins, such as a reset pin PROGRAM _ B, an initialization pin INIT _ B, a configuration clock input pin CCLK, a configuration data input pin D01_ DIN, and a configuration status indication pin DONE. The configuration clock input pin CCLK and the configuration data input pin D01_ DIN are respectively connected to the serial clock signal line SCK and the serial data output line MOSI of the corresponding synchronous serial controller 111, and the reset pin PROGRAM _ B, the initialization pin INIT _ B, and the configuration status indication pin DONE are connected to the plurality of general purpose input/output ports GPIO of the system on chip 11.
As mentioned above, the system on chip 11 of this embodiment can be installed with an operating system and a file system, so that the configuration file of the programmable logic device 13 can be conveniently read (i.e. the binary file is put into the file system), and then the configuration file is loaded on the programmable logic device 13. The programmable logic device 13 of the present embodiment operates in a Slave string configuration mode (Slave Serial mode), for example, and uses a Serial bus, which occupies fewer pins of the system on chip 11; the timing of operation of programmable logic device 13 in slave string configuration mode is shown in fig. 3. According to the feature of configuration file loading in the slave string configuration mode, the configuration file loading of the programmable logic device 13 is implemented by using two signal lines in the synchronous serial controller 111 built in the system-on-chip 11 and three GPIO ports of the system-on-chip, that is, the configuration file loading of one programmable logic device 13 is implemented by using one synchronous serial controller 111; configuration file loading for a plurality of programmable logic devices 13 can be realized through a plurality of built-in synchronous serial controllers 111. Configuration file loading of a plurality of programmable logic devices 13 can be implemented in the operating system of the system-on-chip 11 by running a configuration driver to start a plurality of kernel threads, one kernel thread controlling the configuration file loading of one programmable logic device 13; thus, a plurality of programmable logic devices 13 can be loaded simultaneously, which greatly improves the loading efficiency of the programmable logic devices, especially when the configuration files of the programmable logic devices have large volumes. Furthermore, because the serial clock signal line SCK of the synchronous serial controller 111 is used to provide the configuration clock for the programmable logic device 13, the clock frequency can be increased compared to the situation where the configuration clock is provided directly by the gio, thereby increasing the loading efficiency and reducing the time consumption for configuring the programmable logic device 13.
In order to make the multi-device system 10 of the present embodiment more clearly understood, a Serial Peripheral Interface (SPI) controller and an FPGA (field programmable gate array) device are described in detail below as examples of the synchronous serial controller 111 and the programmable logic device 13, respectively.
A System On Chip (SOC), such as an ARM core-based SOC, is generally built with a plurality of SPI controllers, and in this embodiment, each SPI controller controls loading of a configuration file of an FPGA device, and then writes a configuration driver of the FPGA device to start a plurality of core threads to implement loading of the FPGA device. When the configuration driver program runs, the plurality of kernel threads are started, and configuration file loading is started on the plurality of FPGA devices.
In view of the above, SPI is a full-duplex, synchronous communication bus that operates in a master-slave manner, typically having a master device and one or more slave devices, and typically having four signal lines, namely MOSI, MISO, SCK, and CS; MOSI is Master Output/Slave Input (serial data Output line of Master device), MISO is Master Input/Slave Output (serial data Input line of Master device), SCK is serial clock signal line, and CS is Chip select (Chip select signal line of Slave device).
According to the phase (CPHA) and polarity (CPOL) of the serial clock signal line SCK, the SPI has four operation modes:
Mode0：CPOL＝0,CPHA＝0
Mode1：CPOL＝0,CPHA＝1
Mode2：CPOL＝1,CPHA＝0
Mode3：CPOL＝1,CPHA＝1
wherein, phase CPHA of SCK: that is, SPI starts sampling at the second edge of the serial clock signal line SCK, 0 indicates the first edge, and 1 indicates the second edge;
polar CPOL of SCK: that is, when the SPI bus is idle, 0 indicates a low level and 1 indicates a high level of the serial clock signal line SCK.
According to the time sequence of configuration file loading in the string configuration Mode, the configuration data input pin D01_ DIN samples at the rising edge of SCK, the embodiment is designed to send out the configuration data of the FPGA device at the rising edge, and correspondingly selects the Mode0 or the Mode3 to load the configuration file of the FPGA device; the SPI bus data transmission timing under Mode0 is shown in fig. 4A, and the SPI bus data transmission timing under Mode1 is shown in fig. 4B.
In summary, since a single system-on-chip can load configuration files for multiple programmable logic devices at the same time, the total time consumed for loading the configuration files of the multiple programmable logic devices is about the same as the time consumed for loading the configuration files of a single programmable logic device, which generally shortens the time consumed for loading the multiple programmable logic devices, and particularly when the configuration files of the programmable logic devices are large in size, the efficiency is considerable. Of course, this embodiment also does not exclude the use of one programmable logic device for the entire multi-device system 10.
[ second embodiment ]
Referring to fig. 5A, a method for loading a programmable logic device according to a second embodiment of the present invention includes:
step S51: running a configuration driver to start a plurality of kernel threads; and
step S53: respectively controlling a plurality of built-in synchronous serial controllers to respectively load configuration files to a plurality of programmable logic devices by utilizing the plurality of kernel threads; and each synchronous serial controller inputs a configuration clock signal to the corresponding programmable logic device through a serial clock signal line and sends configuration data in the configuration file to the corresponding programmable logic device through a serial data output line.
Steps S51 and S53 can be executed by the multi-device system 10 of the first embodiment, and specific details thereof can be referred to the related description of the first embodiment, and therefore will not be described herein again.
Referring to fig. 5B, before the step S53, a step S52 may be further included: and respectively controlling the plurality of programmable logic devices to work in a slave string configuration mode by using the plurality of kernel threads. It is worth to be noted here that the configuration modes of the programmable logic device are commonly known as Master serial (Master serial), Master Parallel (Master Parallel), Slave serial (Slave serial), Slave Parallel (Slave select map), and the like; these configuration MODEs are typically configured by the hardware pins MODE [2:0] of the programmable logic device. However, these pins are usually implemented by pull-up resistors and pull-down resistors in hardware design, and it is needless to say that these several mode configuration pins may also be connected to GPIO ports of the system-on-chip as described in this embodiment, and the configuration mode of the programmable logic device is configured by the system-on-chip (or software). In addition, it is worth mentioning that the method for loading a programmable logic device of the present embodiment is also applicable to the situation of loading a configuration file of a single programmable logic device, and in this situation, only one kernel thread needs to be started to implement the loading of the configuration file of the programmable logic device.
[ third embodiment ]
Referring to fig. 6, a programmable logic device loading apparatus according to a third embodiment of the present invention includes: a thread start module 61 and a file load module 63.
The thread starting module 61 is configured to run a configuration driver to start a plurality of kernel threads, for example; the file loading module 63 is, for example, configured to respectively control a plurality of built-in synchronous serial controllers to respectively load configuration files onto a plurality of programmable logic devices by using the plurality of kernel threads, where each synchronous serial controller inputs a configuration clock signal to a corresponding programmable logic device through a serial clock signal line and sends configuration data in the configuration file to the corresponding programmable logic device through a serial data output line.
In addition, the file loading module 63 may be further configured to control the plurality of programmable logic devices to operate in the slave string configuration mode by using the plurality of kernel threads, respectively; the phase and polarity of the serial clock signal line are 0, or the phase and polarity of the serial clock signal line are 1. Moreover, the plc loading device of the present embodiment may be integrated into a system on chip with an operating system and a file system installed therein, for example, a controller based on an ARM kernel may be installed with an Android system, a Linux system, and the like.
For the functional details of the thread starting module 61 and the file loading module 63, reference may be made to the related description of the foregoing first embodiment, which is not repeated herein.
In addition, it should be understood that the foregoing embodiments are merely exemplary illustrations of the present invention, and technical solutions of the embodiments can be arbitrarily combined and used without conflict between technical features and structures, and without departing from the purpose of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and/or method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units/modules is only one logical division, and there may be other divisions in actual implementation, for example, multiple units or modules may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units/modules described as separate parts may or may not be physically separate, and parts displayed as units/modules may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units/modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
In addition, each functional unit/module in the embodiments of the present invention may be integrated into one processing unit/module, or each unit/module may exist alone physically, or two or more units/modules may be integrated into one unit/module. The integrated units/modules may be implemented in the form of hardware, or may be implemented in the form of hardware plus software functional units/modules.
The integrated units/modules, which are implemented in the form of software functional units/modules, may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions for causing one or more processors of a computer device (which may be a personal computer, a server, or a network device) to execute some steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A multi-device system, comprising:
the system level chip is internally provided with a plurality of synchronous serial controllers; and
the plurality of programmable logic devices are respectively connected with the plurality of synchronous serial controllers;
the system-on-chip is used for running a configuration driver to start a plurality of kernel threads and respectively controlling the synchronous serial controllers to respectively load configuration files to the programmable logic devices by utilizing the kernel threads.
2. The multi-device system of claim 1, wherein each of the programmable logic devices has a plurality of configuration pins, a configuration clock input pin and a configuration data input pin of the plurality of configuration pins are respectively connected to a serial clock signal line and a serial data output line of the synchronous serial controller of the plurality of synchronous serial controllers connected to the programmable logic device, and a reset pin, an initialization pin, and a configuration status indication pin of the plurality of configuration pins are connected to a plurality of general purpose input output ports of the system-on-chip.
3. The multi-device system of claim 1 or 2, wherein the plurality of synchronous serial controllers are each a Serial Peripheral Interface (SPI) controller and the plurality of programmable logic devices are each field programmable gate array devices.
4. A method of loading a programmable logic device, comprising:
running a configuration driver to start a kernel thread; and
loading a configuration file to a programmable logic device by utilizing the kernel thread to control a built-in synchronous serial controller; and the synchronous serial controller inputs a configuration clock signal to the programmable logic device through a serial clock signal line and sends configuration data in the configuration file to the programmable logic device through a serial data output line.
5. The programmable logic device loading method of claim 4, wherein running the configuration driver to launch the kernel thread is to launch multiple kernel threads; correspondingly, the step of loading the configuration file to the programmable logic device by using the built-in synchronous serial controller controlled by the kernel thread is to load the configuration file to the plurality of programmable logic devices by using the plurality of kernel threads to respectively control the built-in synchronous serial controllers.
6. The programmable logic device loading method of claim 5, further comprising: respectively controlling the programmable logic devices to work in a slave string configuration mode by utilizing the kernel threads; the phase and polarity of the serial clock signal line are 0, or the phase and polarity of the serial clock signal line are 1.
7. The programmable logic device loading method according to any one of claims 4 to 6, wherein the plurality of synchronous serial controllers are serial peripheral interface controllers respectively, and the plurality of programmable logic devices are field programmable gate array devices respectively.
8. A programmable logic device loading apparatus, comprising:
the thread starting module is used for running a configuration driver to start a plurality of kernel threads; and
and the file loading module is used for respectively controlling a plurality of built-in synchronous serial controllers to respectively load configuration files to a plurality of programmable logic devices by utilizing the plurality of kernel threads, wherein each synchronous serial controller inputs configuration clock signals to the corresponding programmable logic device through a serial clock signal line and sends configuration data in the configuration files to the corresponding programmable logic device through a serial data output line.
9. The programmable logic device loading apparatus of claim 8, wherein the file loading module is further configured to control the plurality of programmable logic devices to operate in a slave string configuration mode by using the plurality of kernel threads, respectively; the phase and polarity of the serial clock signal line are 0, or the phase and polarity of the serial clock signal line are 1.
10. The programmable logic device loading apparatus of claim 8 or 9, wherein the programmable logic device loading apparatus is integrated into a system-on-chip on which an operating system and a file system are installed.
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| 谈良;纪凌;: "基于FPGA的多通道数据采集***设计与实现", 电子测量技术, no. 05, 8 March 2018 (2018-03-08) * |
| 赵涛;郭猛;顾亚浏;章阳;: "基于FPGA的多通道数据采集控制器设计与实现", 计算机工程, no. 06, 15 June 2017 (2017-06-15) * |
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