WO2017118092A1 - 移位寄存器单元及其驱动方法、扫描驱动电路、显示装置 - Google Patents
移位寄存器单元及其驱动方法、扫描驱动电路、显示装置 Download PDFInfo
- Publication number
- WO2017118092A1 WO2017118092A1 PCT/CN2016/099287 CN2016099287W WO2017118092A1 WO 2017118092 A1 WO2017118092 A1 WO 2017118092A1 CN 2016099287 W CN2016099287 W CN 2016099287W WO 2017118092 A1 WO2017118092 A1 WO 2017118092A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- transistor
- control signal
- terminal
- node
- Prior art date
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Definitions
- the present disclosure relates to the field of display technologies, and in particular, to a shift register unit and a driving method thereof, a scan driving circuit, and a display device.
- a typical active matrix light emitting diode (AMOLED) pixel circuit is shown in FIG.
- the first scanning signal line S1 controls the transistor T1 to be turned on, and the data line Dm writes the data voltage to the gate of the driving transistor Td through the transistor T1.
- the second scan signal line S2 supplies a single-pulse signal corresponding to the pulse width of the clock signal to the gate of the switching transistor T2 to drive the switching transistor T2 to be turned on for the time corresponding to the pulse width.
- the current flowing through the driving transistor Td and the switching transistor T2 can drive the OLED to emit light.
- the adjustment of the brightness gray scale can be achieved by adjusting the data voltage. However, there may be a large error between the adjusted grayscale value and the desired grayscale value, thereby affecting the display effect.
- Embodiments of the present disclosure provide a shift register unit and a driving method thereof, a scan driving circuit, and a display device.
- the proposed scan driving circuit can be used to control the illumination duration of the OLED in the OLED display panel, thereby adjusting the brightness of the displayed image.
- a shift register unit comprising: a first control signal end for receiving a first control signal; a second control signal end for receiving a second control signal; a first clock signal End, for receiving the first clock signal; the second clock signal end is for receiving the second clock signal; the first voltage end is for receiving the first voltage; the second voltage end is for receiving the second voltage; a signal output end and a second signal output terminal; the first control module operable to be responsive to the first control signal, the second control signal, the first clock signal, the second clock signal, and a first voltage and a) outputting a signal synchronized with the second clock signal to the second signal output during a duration, and b) generating a first internal control signal at the first node; the first output Mode a block operable to output the first voltage to the first signal output for the duration of time in response to the first internal control signal; the second control module operable to respond to a second control signal, the first clock signal, the second clock signal, the first voltage, and
- the first control module is configured to adjust the duration according to a length of a time period in which the first control signal and the second control signal are active.
- the first output module includes a first transistor having a gate connected to the first node, a first pole connected to the first voltage terminal, and a first signal coupled to the first signal The second pole of the output.
- the second output module includes a second transistor having a gate coupled to the second node, a first pole coupled to the second voltage terminal, and coupled to the first signal The second pole of the output.
- the first control module includes: a third transistor having a gate connected to the first clock signal end, a first pole connected to the first control signal end, and a third node connected a second transistor having a gate connected to the third node, a first pole connected to the first voltage terminal, and a second pole connected to the fourth node; and a sixth transistor having a connection a gate to the first clock signal terminal, a first pole connected to the second control signal terminal, and a second pole connected to the fourth node; a seventh transistor having a connection to the fourth node a gate, a first pole connected to the first voltage terminal, and a second pole connected to the second signal output; an eighth transistor having a gate connected to the third node, connected to the first a first pole of the second clock signal end and a second pole connected to the second signal output terminal; a ninth transistor having a gate connected to the second clock signal end and a first connected to the second signal output end pole And a second pole connected to the first node; a third capacitor having one end connected to the first clock
- the second control module includes: a fourth transistor having a gate connected to the first clock signal terminal, a first pole connected to the second control signal terminal, and connected to the first a second pole of the two nodes; a tenth transistor having a gate connected to the first node, a first pole connected to the first voltage terminal, and a second pole connected to the second node; And a second capacitor having one end connected to the second clock signal end and the other end connected to the second node.
- a scan driving circuit comprising a plurality of stages of shift register units as described in the first aspect.
- a first control signal end of the first stage shift register unit is configured to receive a first start signal
- a second control signal end of the first stage shift register unit is configured to receive a second start signal
- a first control signal terminal of each stage shift register unit other than the first stage shift register unit is coupled to a second signal output terminal of the upper stage shift register unit; and in addition to the first stage shift register unit
- the second control signal end of each stage of the shift register unit is connected to the first signal output end of the upper stage shift register unit.
- a display device comprising: a display panel including a plurality of pixel units arranged in an array, each of the pixel units including a pixel circuit, the pixel circuit including a light emitting device And a switching transistor having a gate and configured to allow a driving current to flow through the light emitting device depending on a voltage applied to the gate; and a scan driving circuit as described in the second aspect.
- a first signal output of each stage of the shift register unit in the scan drive circuit is coupled to a gate of a switch transistor in a corresponding row of pixel cells in the array.
- a method of driving a shift register unit including a first signal output and a second signal output
- the method comprising: responsive to the first control signal a second control signal, a first clock signal, a second clock signal, and a first voltage, outputting a signal synchronized with the second clock signal to the second signal output terminal and generating a first internal control signal; Outputting the first voltage to the first signal output terminal in response to the first internal control signal; responsive to the second control signal, the first clock signal, the second clock signal, the first Generating a second internal control signal with the voltage and the first internal control signal; and outputting a second voltage to the first signal output in response to the second internal control signal.
- outputting a signal synchronized with the second clock signal to the second signal output and outputting the first voltage to the first signal output is simultaneous Start and terminate.
- the output of the signal synchronized with the second clock signal to the output of the second signal and the output of the first voltage output to the first signal output are maintained for a duration.
- the method further comprises adjusting the duration by changing a length of a time period in which the first control signal and the second control signal are active.
- FIG. 1 is a schematic circuit diagram of a prior art pixel circuit
- FIG. 2 is a schematic block diagram of a shift register unit in accordance with an embodiment of the present disclosure
- FIG. 3 is an exemplary circuit diagram of the shift register unit shown in FIG. 2;
- FIG. 4 is a timing diagram of a circuit of the shift register unit shown in FIG. 3;
- FIG. 5 is a schematic block diagram of a scan driving circuit according to an embodiment of the present disclosure.
- FIG. 6 is a schematic diagram of a display device according to an embodiment of the present disclosure.
- FIG. 7 is a flow chart of a method of driving a shift register unit in accordance with an embodiment of the present disclosure.
- FIG. 2 is a schematic block diagram of a shift register unit 200 in accordance with an embodiment of the present disclosure.
- the shift register unit 200 includes a first control signal terminal STV1 for receiving a first control signal, a second control signal terminal STV2 for receiving a second control signal, and a second for receiving a first clock signal.
- the shift register unit 200 further includes a first output module 10.
- the first control module 30 is operable to output to the second signal output terminal OUTPUT2 during a duration in response to the first control signal, the second control signal, the first clock signal, the second clock signal, and the first voltage A signal synchronized with the second clock signal CKB, and b) a first internal control signal is generated at the first node (not shown in FIG. 2).
- the first control module 30 is configured to adjust the duration according to the length of the time period in which the first control signal and the second control signal are active.
- the first output module 10 is operative to output a first voltage to the first signal output terminal OUTPUT1 for the duration of time in response to the first internal control signal.
- the second control module 40 is operative to be in the second node in response to the second control signal, the first clock signal, the second clock signal, the first voltage, and the first internal control signal A second internal control signal is generated at 2 not shown).
- the second output module 20 is operative to output the second voltage to the first signal output terminal OUTPUT1 at the end of the duration in response to the second internal control signal.
- shift register unit 200 The details of the shift register unit 200 are described in detail below with reference to FIGS. 3 and 4.
- FIG. 3 is an exemplary circuit diagram of the shift register unit 200 shown in FIG. 2.
- the first output module 10 includes a first transistor M1.
- the first transistor M1 has a gate connected to the first node B, a first pole connected to the first voltage terminal VGH, and a second pole connected to the first signal output terminal OUTPUT1.
- the voltage signal at the first node B is the first internal control signal.
- the first output module 10 may further include one or more transistors in parallel with the first transistor M1, and/or one or more capacitors in parallel with the first capacitor C1.
- the second output module 20 includes a second transistor M2.
- the second transistor M2 has a gate connected to the second node C, a first pole connected to the second voltage terminal VGL, and a second pole connected to the first signal output terminal OUTPUT1.
- the voltage signal at the second node C is a second internal control signal.
- the second output module 20 may further include one or more transistors in parallel with the second transistor M2, and/or one or more capacitors in parallel with the second capacitor C2.
- the first control module 30 includes a third transistor M3, a fifth transistor M5, and a sixth crystal
- the third transistor M3 has a gate connected to the first clock signal terminal CK, a first pole connected to the first control signal terminal STV1, and a second pole connected to the third node D.
- the fifth transistor M5 has a gate connected to the third node D, a first pole connected to the first voltage terminal VGH, and a second pole connected to the fourth node E.
- the sixth transistor M6 has a gate connected to the first clock signal terminal CK, a first pole connected to the second control signal terminal STV2, and a second pole connected to the fourth node E.
- the seventh transistor M7 has a gate connected to the fourth node E, a first pole connected to the first voltage terminal VGH, and a second pole connected to the second signal output terminal OUTPUT2.
- the second signal output terminal OUTPUT2 is shown as being drawn from the node A.
- the eighth transistor M8 has a gate connected to the third node D, a first pole connected to the second clock signal terminal CKB, and a second pole connected to the second signal output terminal OUTPUT2.
- the ninth transistor M9 has a first pole connected to the second clock signal CKB gate, connected to the second signal output terminal OUTPUT2, and a second pole connected to the first node B.
- the third capacitor C3 has one end connected to the third node D and the other end connected to the second signal output terminal OUTPUT2.
- the fourth capacitor C4 has one end connected to the first voltage terminal VGH and the other end connected to the fourth node E.
- the first capacitor C1 has one end connected to the first voltage terminal VGH and the other end connected to the first node B.
- the first control module 30 may further include a plurality of transistors respectively connected in parallel with the third transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9, and/or A plurality of capacitors respectively connected in parallel with the third capacitor C3, the fourth capacitor C4, and the first capacitor C1.
- the second control module 40 includes a fourth transistor M4, a tenth transistor M10, and a second capacitor C2.
- the fourth transistor M4 has a gate connected to the first clock signal terminal CK, a first pole connected to the second control signal terminal STV2, and a second pole connected to the second node C.
- the tenth transistor M10 has a gate connected to the first node B, a first pole connected to the first voltage terminal VGH, and a second pole connected to the second node C.
- the second capacitor C2 has one end connected to the second clock signal terminal CKB and the other end connected to the second node C.
- the second control module 40 may further include multiple A transistor in which the fourth transistor M4 and the tenth transistor M10 are connected in parallel.
- each transistor is shown as a P-type transistor, and the first voltage terminal VGH is supplied with a high level and the second voltage terminal VGL is supplied with a low level.
- the gate-on voltage for turning on the P-type transistor is a low level, and the gate-off voltage for turning off the P-type transistor is a high level.
- each transistor can be an N-type transistor.
- the gate-on voltage for turning on the N-type transistor is a high level, and the gate-off voltage for turning off the N-type transistor is a low level.
- the transistors are typically fabricated such that their first and second poles are used interchangeably.
- FIG. 4 is a timing diagram of a circuit of the shift register unit shown in FIG.
- the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned on.
- the low level of the first control signal terminal STV1 is transmitted to the third node D through the third transistor M3.
- the eighth transistor M8 and the fifth transistor M5 are turned on, and the third capacitor C3 stores the low level of the third node D.
- the high level of the first voltage terminal VGH is transmitted to the gates of the fourth node E and the seventh transistor M7 through the fifth transistor M5.
- the high level of the second control signal terminal STV2 is transmitted to the gates of the fourth node E and the seventh transistor M7 through the sixth transistor M6, and thus the seventh transistor M7 is turned off.
- the high level of the second clock signal terminal CKB is transmitted to the node A and the second signal output terminal OUTPUT2 through the eighth transistor M8.
- the ninth transistor M9 is turned off due to the high level of the second clock signal terminal CKB.
- the first capacitor C1 outputs the high level stored at the end of the previous cycle to the gates of the first and third tenth transistors M1 and M10 and the first node B, and thus the first and fourth transistors M1 and M10 are turned off.
- the fourth transistor M4 Since the fourth transistor M4 is turned on, the high level of the second control signal terminal STV2 is transmitted to the second node C through the fourth transistor M4, and is stored by the second capacitor C2. Under the control of the second node C, the second transistor M2 is turned off.
- the first signal output terminal OUTPUT1 maintains a low level at the end of the previous cycle.
- the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned off.
- the second capacitor C2 outputs the high level stored in the previous stage to the gate of the second transistor M2, and thus the second transistor M2 is turned off.
- the low level stored in one stage of the third capacitor C3 causes the third node D to remain at a low level, and thus the fifth transistor M5 and the eighth transistor M8 remain in an on state.
- the high level of the first voltage terminal VGH is transmitted to the gates of the fourth node E and the seventh transistor M7 through the fifth transistor M5, and thus the seventh transistor M7 is turned off.
- the low level of the second clock signal terminal CKB is transmitted to the node A and the second signal output terminal OUTPUT2 through the eighth transistor M8.
- the ninth transistor M9 is turned on, and the low level at the node A is transferred to the gate of the first transistor M1 and the first node B.
- the first capacitor C1 stores the low level.
- the first transistor M1 is turned on, and transmits a high level of the first voltage terminal VGH to the first signal output terminal OUTPUT1.
- the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned on.
- the low level of the first control signal terminal STV1 is output to the third node D through the third transistor M3.
- the eighth transistor M8 and the fifth transistor M5 are turned on.
- the third capacitor C3 stores the low level of the third node D.
- the high level of the first voltage terminal VGH is transmitted to the gates of the fourth node E and the seventh transistor M7 through the fifth transistor M5.
- the high level of the second control signal terminal STV2 is transmitted to the gates of M7 of the fourth node and the seventh transistor through the sixth transistor M6, and thus the seventh transistor M7 is turned off.
- the high level of the second clock signal terminal CKB is transmitted to the node A and the second signal output terminal OUTPUT2 through the eighth transistor M8.
- the ninth transistor M9 is turned off due to the high level of the second clock signal terminal CKB.
- Node B is at a low level due to the low level stored by the first capacitor C1.
- the tenth transistor M10 and the first transistor M1 are turned on.
- the high level of the first voltage terminal VGH is transmitted to the second node C through the tenth transistor M10, and is transmitted to the first signal output terminal OUTPUT1 through the first transistor M1.
- the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned off.
- the low level stored by the third capacitor C3 causes the third node D to be at a low level.
- the eighth transistor M8 and the fifth transistor M5 are turned on.
- the high level of the first voltage terminal VGH is transmitted to the gates of the fourth node E and the seventh transistor M7 through the fifth transistor M5, and thus the seventh transistor M7 is turned off.
- the low level of the second clock signal terminal CKB is transmitted to the node A and the second signal output terminal OUTPUT2 through the eighth transistor M8.
- the ninth transistor M9 Since the second clock signal terminal CKB is at a low level, the ninth transistor M9 is turned on. The low level at the node A is caused to be transmitted through the ninth transistor M9 to the tenth transistor M10 and the gate of the first transistor M1 and the first node B. The first capacitor C1 stores the low level. The tenth transistor M10 is turned on, and transmits a high level of the first voltage terminal VGH to the gate of the second transistor M2, so that the second transistor M2 is turned off. The high level of the first voltage terminal VGH is transmitted to the first signal output terminal OUTPUT1 through the first transistor M1.
- the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned on.
- the high level of the first control signal terminal STV1 is transmitted to the third node D through the third transistor M3.
- the third capacitor C3 stores the high level.
- the fifth transistor M5 and the eighth transistor M8 are turned off.
- the sixth transistor M6 is turned on, the low level of the second control signal terminal STV2 is transmitted to the gates of the fourth node E and the seventh transistor M7 through the sixth transistor M6, and thus the seventh transistor M7 is turned on.
- the fourth capacitor C4 stores the low level.
- the high level of the first voltage terminal VGH is transmitted to the node A and the second signal output terminal OUTPUT2 through the seventh transistor M7.
- the ninth transistor M9 Since the second clock signal terminal CKB is at the high level, the ninth transistor M9 is turned off.
- the low level stored by the first capacitor C1 causes the tenth transistor M10 and the first transistor M1 to be turned on.
- the high level of the first voltage terminal VGH is transmitted to the second node C through the tenth transistor M10, and the low level of the second signal control terminal STV2 is transmitted to the node C through the fourth transistor M4, so that the potential of the node C is located at the high voltage.
- the high level of the first voltage terminal VGH is transmitted to the first signal output terminal OUTPUT1 through the first transistor M1.
- the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned off.
- the high level stored by the third capacitor C3 causes the node D to be at a high level.
- the fifth transistor M5 and the eighth transistor M8 are turned off.
- the low level stored by the fourth capacitor C4 turns on the seventh transistor M7.
- the high level of the first voltage terminal VGH is transmitted to the node A and the second signal output terminal OUTPUT2 through the seventh transistor M7.
- the ninth transistor M9 Since the second clock signal terminal CKB is at a low level, the ninth transistor M9 is turned on, and the high level at the node A is transferred to the gates of the first transistor M1 and the tenth transistor M10, so that the first transistor M1 and The tenth transistor M10 is turned off.
- the low level of the second clock signal terminal CKB is pulled down the potential of the node C to turn on the second transistor M2.
- the low level of the second voltage terminal VGL is output through the second transistor M2 To the first signal output terminal OUTPUT1.
- the first signal output terminal OUTPUT1 remains output low until the second phase of the next cycle.
- the first signal output terminal OUTPUT1 outputs a high level signal
- the second signal output terminal OUTPUT2 outputs a signal synchronized with the second clock signal CKB ( They have the same waveform). This is achieved by means of the operation of the first control module 30 of the shift register unit shown in FIG.
- the operations of the second phase P2 and the third phase P3 may be alternately repeated such that the duration can be adjusted by changing the number of the second phase P2 and the third phase P3 included in the first control signal STV1 and the second control signal STV2 .
- the first control signal STV1 and the second control signal STV2 can be considered to be valid during the period from the first phase P1 to the last third phase P3.
- the effective first control signal STV1 is a square wave signal, and the effective second control signal STV2 is at the level of the first voltage.
- the high level signal output by the first output terminal OUTPUT1 can be used to drive OLED illumination in the pixel circuit. That is, the luminescence duration of the OLED can be adjusted by changing the length of the period in which the first control signal STV1 and the second control signal STV2 are valid. The more the second phase P2 and the third phase P3 are repeated, the longer the duration of the first signal output terminal OUTPUT1 outputting the high level signal, and the longer the OLED is illuminated. Thereby, the image can be displayed with an adjustable brightness.
- the adjustment of the duration of illumination can also be combined with the adjustment of the voltage to provide a flexible and fine adjustment of the brightness.
- FIG. 5 is a schematic block diagram of a scan driving circuit 500 in accordance with an embodiment of the present disclosure.
- the scan driving circuit 500 includes multi-stage shift register units SR1, SR2, ..., SRn-1, SRn, each of which may be the shift register unit 200 as described above.
- the first signal output terminal OUTPUT1 of the shift register units SR1, SR2, ... SRn-1, SRn provides output signals to the control lines EM1, EM2, ..., EMn-1, EMn, respectively.
- the details of the shift register unit 200 are described in detail in the above embodiments, and are omitted here for the sake of simplicity.
- the first control signal terminal STV1 of the first stage shift register unit SR1 is for receiving the first start signal
- the second control signal terminal STV2 of the first stage shift register unit SR1 For receiving the second control signal.
- the first control signal terminal STV1 of each of the shift register units SR2...SRn-1, SRn other than the first stage shift register unit SR1 is connected to the second signal output terminal OUTPUT2 of the previous stage shift register unit .
- the second control signal terminal STV2 of each of the shift register units SR2...SRn-1, SRn other than the first stage shift register unit SR1 is connected to the first signal output terminal OUTPUT1 of the shift register unit of the previous stage .
- the second signal output terminal OUTPUT2 of the last stage shift register unit SRn is vacant.
- FIG. 6 is a schematic diagram of a display device 600 in accordance with an embodiment of the present disclosure.
- the display device 600 includes a display panel 610 including a plurality of pixel units 611.
- Each of the pixel units 611 includes a light emitting device and a switching transistor having a gate and configured to allow a driving current to flow through the light emitting device depending on a voltage applied to the gate.
- each of the pixel units 611 may include, for example, a pixel circuit as shown in FIG. 1.
- the pixel circuit includes a driving transistor Td, a switching transistor T2, and a light emitting device OLED connected in series. In the example of FIG. 6, the remaining components within pixel unit 611 are not shown for simplicity.
- Display device 600 also includes scan drive circuit 500 as described in the above embodiments.
- the first signal output terminal OUTPUT1 of each of the shift register units SR1, SR2, ..., SRn-1, SRn in the scan driving circuit 500 is connected to the gate of the switching transistor T2 in the corresponding row of pixel cells.
- the first signal output terminal OUTPUT1 of the first stage shift register unit SR1 is connected to the gate of the switching transistor T2 in the first row of pixel cells through the control line EM1, and the second stage shift register unit SR2
- the first signal output terminal OUTPUT1 is connected to the gate of the switching transistor T2 in the second row of pixel cells through the control line EM2, and so on.
- examples of the display device include any display device based on an organic light emitting diode, such as a television, a digital photo frame, a mobile phone, or a tablet.
- FIG. 7 is a flow diagram of a method 700 of driving a shift register unit, which may be the shift register unit 200 described above in connection with FIGS. 2-4, in accordance with an embodiment of the present disclosure.
- a signal synchronized with the second clock signal is output to the second signal output in response to the first control signal, the second control signal, the first clock signal, the second clock signal, and the first voltage And generating a first internal control signal.
- the first voltage is output to the first signal output in response to the first internal control signal.
- a second internal control signal is generated in response to the second control signal, the first clock signal, the second clock signal, the first voltage, and the first internal control signal.
- a second voltage is output to the first signal output in response to the second internal control signal.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
Description
Claims (12)
- 一种移位寄存器单元,包括:第一控制信号端,用于接收第一控制信号;第二控制信号端,用于接收第二控制信号;第一时钟信号端,用于接收第一时钟信号;第二时钟信号端,用于接收第二时钟信号;第一电压端,用于接收第一电压;第二电压端,用于接收第二电压;第一信号输出端和第二信号输出端;第一控制模块,可操作用于响应于所述第一控制信号、所述第二控制信号、所述第一时钟信号、所述第二时钟信号以及所述第一电压而a)在一持续时间期间向所述第二信号输出端输出与所述第二时钟信号同步的信号,并且b)在第一节点处生成第一内部控制信号;第一输出模块,可操作用于响应于所述第一内部控制信号而在所述持续时间内将所述第一电压输出至所述第一信号输出端;第二控制模块,可操作用于响应于所述第二控制信号、所述第一时钟信号、所述第二时钟信号、所述第一电压以及所述第一内部控制信号而在第二节点处生成第二内部控制信号;以及第二输出模块,可操作用于响应于所述第二内部控制信号而在所述持续时间结束时将所述第二电压输出至所述第一信号输出端。
- 根据权利要求1所述的移位寄存器单元,其中所述第一控制模块被配置成根据其中所述第一控制信号和所述第二控制信号为有效的时间段的长度来调节该持续时间。
- 根据权利要求1所述的移位寄存器单元,其中所述第一输出模块包括第一晶体管,其具有连接到所述第一节点的栅极、连接到所述第一电压端的第一极、以及连接到所述第一信号输出端的第二极。
- 根据权利要求1所述的移位寄存器单元,其中所述第二输出模块包括第二晶体管,其具有连接到所述第二节点的栅极、连接到所述第二电压端的第一极、以及连接到所述第一信号输出端的第二极。
- 根据权利要求1所述的移位寄存器单元,其中所述第一控制模块包括:第三晶体管,具有连接到所述第一时钟信号端的栅极、连接到所述第一控制信号端的第一极、以及连接到第三节点的第二极;第五晶体管,具有连接到所述第三节点的栅极、连接到所述第一电压端的第一极、以及连接到第四节点的第二极;第六晶体管,具有连接到所述第一时钟信号端的栅极、连接到所述第二控制信号端的第一极、以及连接到所述第四节点的第二极;第七晶体管,具有连接到所述第四节点的栅极、连接到所述第一电压端的第一极、以及连接到所述第二信号输出端的第二极;第八晶体管,具有连接到所述第三节点的栅极、连接到所述第二时钟信号端的第一极、以及连接到所述第二信号输出端的第二极;第九晶体管,具有连接到所述第二时钟信号端的栅极、连接到所述第二信号输出端的第一极、以及连接到所述第一节点的第二极;第三电容,具有连接到所述第三节点的一端和连接到所述第二信号输出端的另一端;第四电容,具有连接到所述第一电压端的一端和连接到所述第四节点的另一端;以及第一电容,具有连接到所述第一电压端的一端和连接到所述第一节点的另一端。
- 根据权利要求1所述的移位寄存器单元,其中所述第二控制模块包括:第四晶体管,具有连接到所述第一时钟信号端的栅极、连接到所述第二控制信号端的第一极、以及连接到所述第二节点的第二极;第十晶体管,具有连接到所述第一节点的栅极、连接到所述第一电压端第一极、以及连接到所述第二节点的第二极;以及第二电容,具有连接到所述第二时钟信号端的一端和连接到所述第二节点的另一端。
- 一种扫描驱动电路,包括多级如权利要求1-6任一项所述的移位寄存器单元,其中:第一级移位寄存器单元的第一控制信号端被配置用于接收第一起始信号,并且第一级移位寄存器单元的第二控制信号端被配置用于接收第二起始信号;除所述第一级移位寄存器单元以外的每一级移位寄存器单元的第一控制信号端连接上一级移位寄存器单元的第二信号输出端;并且除所述第一级移位寄存器单元以外的每一级移位寄存器单元的第二控制信号端连接上一级移位寄存器单元的第一信号输出端。
- 一种显示装置,包括:显示面板,包括布置在阵列中的多个像素单元,所述像素单元中的每个包括像素电路,所述像素电路包括发光器件和开关晶体管,所述开关晶体管具有栅极并且被配置成取决于施加到栅极的电压而允许驱动电流流过该发光器件;以及如权利要求6所述的扫描驱动电路,其中,所述扫描驱动电路中的每一级移位寄存器单元的第一信号输出端与所述阵列中的相应一行像素单元中的开关晶体管的栅极相连接。
- 一种驱动移位寄存器单元的方法,所述移位寄存器单元包括第一信号输出端和第二信号输出端,所述方法包括:响应于第一控制信号、第二控制信号、第一时钟信号、第二时钟信号以及第一电压,向所述第二信号输出端输出与所述第二时钟信号同步的信号并且生成第一内部控制信号;响应于所述第一内部控制信号而将所述第一电压输出至所述第一信号输出端;响应于所述第二控制信号、所述第一时钟信号、所述第二时钟信号、所述第一电压以及所述第一内部控制信号而生成第二内部控制信号;以及响应于所述第二内部控制信号而将第二电压输出至所述第一信号输出端。
- 根据权利要求9所述的方法,其中向所述第二信号输出端输出与所述第二时钟信号同步的信号以及将所述第一电压输出至所述第一信号输出端是同时启动和终止的。
- 根据权利要求10所述的方法,其中与所述第二时钟信号同步的信号向所述第二信号输出端的输出以及所述第一电压输出至所述第一信号输出端的输出被维持一持续时间。
- 根据权利要求11所述的方法,还包括通过改变其中所述第一控制信号和所述第二控制信号为有效的时间段的长度来调节该持续时间。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/520,789 US10109238B2 (en) | 2016-01-04 | 2016-09-19 | Shift register unit, driving method thereof, scan driving circuit and display apparatus |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610006590.8A CN105679248B (zh) | 2016-01-04 | 2016-01-04 | 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置 |
CN201610006590.8 | 2016-01-04 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2017118092A1 true WO2017118092A1 (zh) | 2017-07-13 |
Family
ID=56299038
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2016/099287 WO2017118092A1 (zh) | 2016-01-04 | 2016-09-19 | 移位寄存器单元及其驱动方法、扫描驱动电路、显示装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10109238B2 (zh) |
CN (1) | CN105679248B (zh) |
WO (1) | WO2017118092A1 (zh) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105304057B (zh) * | 2015-12-09 | 2018-11-30 | 京东方科技集团股份有限公司 | 一种移位寄存器及其驱动方法、栅极驱动电路 |
CN105679248B (zh) * | 2016-01-04 | 2017-12-08 | 京东方科技集团股份有限公司 | 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置 |
CN105513531B (zh) | 2016-03-02 | 2018-04-10 | 京东方科技集团股份有限公司 | 移位寄存器单元、驱动方法、栅极驱动电路及显示装置 |
CN106157893B (zh) * | 2016-09-09 | 2018-12-11 | 京东方科技集团股份有限公司 | 移位寄存器单元及其驱动方法、驱动电路和显示装置 |
KR20180062282A (ko) * | 2016-11-30 | 2018-06-08 | 엘지디스플레이 주식회사 | 표시 장치용 발광 제어부 및 이를 적용한 유기 발광 표시 장치 |
CN106448567B (zh) * | 2016-12-08 | 2020-06-05 | 合肥鑫晟光电科技有限公司 | 像素驱动电路、驱动方法、像素单元和显示装置 |
KR20180096843A (ko) * | 2017-02-20 | 2018-08-30 | 삼성디스플레이 주식회사 | 스테이지 회로 및 이를 이용한 주사 구동부 |
CN107316599B (zh) * | 2017-07-07 | 2020-09-22 | 上海天马有机发光显示技术有限公司 | 移位寄存单元、其驱动方法及显示面板 |
CN107358914B (zh) * | 2017-07-12 | 2019-08-06 | 上海天马有机发光显示技术有限公司 | 一种发光控制电路、其驱动方法、显示面板及显示装置 |
CN108172169B (zh) * | 2018-03-26 | 2019-09-27 | 上海天马有机发光显示技术有限公司 | 移位寄存器及其驱动方法、发射驱动电路和显示装置 |
CN108447437B (zh) * | 2018-04-02 | 2021-09-07 | 上海天马有机发光显示技术有限公司 | 发射控制电路及其驱动方法、发射控制器、显示装置 |
CN109036282B (zh) * | 2018-08-24 | 2020-05-22 | 合肥鑫晟光电科技有限公司 | 栅极驱动输出级电路、栅极驱动单元及驱动方法 |
CN111312136B (zh) * | 2018-12-12 | 2022-01-14 | 京东方科技集团股份有限公司 | 移位寄存器单元、扫描驱动电路、驱动方法和显示装置 |
WO2020142923A1 (zh) * | 2019-01-09 | 2020-07-16 | 京东方科技集团股份有限公司 | 移位寄存器及其驱动方法、栅极驱动电路和显示装置 |
CN109860259B (zh) * | 2019-02-28 | 2020-10-16 | 武汉华星光电半导体显示技术有限公司 | 一种oled阵列基板及oled显示装置 |
CN111785207B (zh) * | 2019-04-03 | 2022-05-06 | 北京小米移动软件有限公司 | 调节oled显示屏亮度的方法、装置及电子设备 |
CN110121038B (zh) * | 2019-06-19 | 2022-04-19 | 京东方科技集团股份有限公司 | 图像传感器及其驱动方法 |
CN112447141B (zh) * | 2019-08-30 | 2022-04-08 | 京东方科技集团股份有限公司 | 移位寄存器及其驱动方法、栅极驱动电路、显示面板 |
CN113554986A (zh) * | 2020-04-26 | 2021-10-26 | 华为技术有限公司 | 移位寄存器及驱动方法、发光控制电路、阵列基板及终端 |
CN111524486A (zh) * | 2020-06-04 | 2020-08-11 | 京东方科技集团股份有限公司 | 复位控制信号生成电路、方法、模组和显示装置 |
CN111681700B (zh) * | 2020-06-24 | 2022-08-19 | 厦门天马微电子有限公司 | 一种移位寄存器、栅极驱动电路、显示面板以及驱动方法 |
CN114842812B (zh) * | 2022-05-20 | 2023-08-15 | 深圳创维-Rgb电子有限公司 | 显示面板及其控制方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110234565A1 (en) * | 2008-12-12 | 2011-09-29 | Sharp Kabushiki Kaisha | Shift register circuit, display device, and method for driving shift register circuit |
CN103295522A (zh) * | 2012-02-29 | 2013-09-11 | 三星显示有限公司 | 发光驱动单元、发光驱动部及有机发光显示装置 |
CN104715734A (zh) * | 2015-04-14 | 2015-06-17 | 京东方科技集团股份有限公司 | 移位寄存器、栅极驱动电路及显示装置 |
CN105047124A (zh) * | 2015-09-18 | 2015-11-11 | 京东方科技集团股份有限公司 | 一种移位寄存器、栅极驱动电路及显示装置 |
CN105185287A (zh) * | 2015-08-27 | 2015-12-23 | 京东方科技集团股份有限公司 | 一种移位寄存器、栅极驱动电路和相关显示装置 |
CN105679248A (zh) * | 2016-01-04 | 2016-06-15 | 京东方科技集团股份有限公司 | 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7319452B2 (en) * | 2003-03-25 | 2008-01-15 | Samsung Electronics Co., Ltd. | Shift register and display device having the same |
TWI380275B (en) * | 2008-07-11 | 2012-12-21 | Wintek Corp | Shift register |
WO2011162057A1 (ja) * | 2010-06-25 | 2011-12-29 | シャープ株式会社 | 走査信号線駆動回路およびそれを備えた表示装置 |
WO2012157545A1 (ja) * | 2011-05-18 | 2012-11-22 | シャープ株式会社 | 走査信号線駆動回路、それを備えた表示装置、および走査信号線の駆動方法 |
CN103918024B (zh) * | 2011-08-02 | 2016-08-17 | 夏普株式会社 | 液晶显示装置和辅助电容线的驱动方法 |
TWI451383B (zh) * | 2011-12-05 | 2014-09-01 | Au Optronics Corp | 平面顯示器、位移暫存器及其控制方法 |
KR102024116B1 (ko) * | 2012-03-22 | 2019-11-15 | 삼성디스플레이 주식회사 | 게이트 구동 회로 및 이를 이용한 표시 장치 |
JP2014041344A (ja) * | 2012-07-27 | 2014-03-06 | Semiconductor Energy Lab Co Ltd | 液晶表示装置の駆動方法 |
WO2014054518A1 (ja) * | 2012-10-05 | 2014-04-10 | シャープ株式会社 | シフトレジスタ |
KR20140052454A (ko) * | 2012-10-24 | 2014-05-07 | 삼성디스플레이 주식회사 | 주사 구동 장치 및 이를 포함하는 표시 장치 |
CN102945651B (zh) * | 2012-10-31 | 2015-02-25 | 京东方科技集团股份有限公司 | 一种移位寄存器、栅极驱动电路和显示装置 |
CN104240631B (zh) * | 2014-08-18 | 2016-09-28 | 京东方科技集团股份有限公司 | Goa电路及其驱动方法、显示装置 |
US9626928B2 (en) * | 2014-12-31 | 2017-04-18 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Liquid crystal display device comprising gate driver on array circuit |
CN104537980B (zh) * | 2015-02-03 | 2017-03-29 | 京东方科技集团股份有限公司 | 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置 |
US10019923B2 (en) | 2015-02-03 | 2018-07-10 | Boe Technology Group Co., Ltd. | Shift register and driving method thereof, gate driving circuit, display apparatus |
CN104637462A (zh) * | 2015-03-17 | 2015-05-20 | 合肥京东方光电科技有限公司 | 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置 |
CN104732950B (zh) * | 2015-04-20 | 2017-03-29 | 京东方科技集团股份有限公司 | 移位寄存器单元及驱动方法、栅极驱动电路和显示装置 |
CN104851383B (zh) * | 2015-06-01 | 2017-08-11 | 京东方科技集团股份有限公司 | 移位寄存器、栅极驱动电路和显示装置 |
CN104867472B (zh) * | 2015-06-15 | 2017-10-17 | 合肥京东方光电科技有限公司 | 一种移位寄存器单元、栅极驱动电路和显示装置 |
CN105185411B (zh) * | 2015-06-30 | 2019-03-26 | 上海天马有机发光显示技术有限公司 | 一种移位寄存器及其驱动方法 |
CN104900211B (zh) * | 2015-06-30 | 2017-04-05 | 京东方科技集团股份有限公司 | 一种栅极驱动电路及其驱动方法、显示装置 |
-
2016
- 2016-01-04 CN CN201610006590.8A patent/CN105679248B/zh active Active
- 2016-09-19 WO PCT/CN2016/099287 patent/WO2017118092A1/zh active Application Filing
- 2016-09-19 US US15/520,789 patent/US10109238B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110234565A1 (en) * | 2008-12-12 | 2011-09-29 | Sharp Kabushiki Kaisha | Shift register circuit, display device, and method for driving shift register circuit |
CN103295522A (zh) * | 2012-02-29 | 2013-09-11 | 三星显示有限公司 | 发光驱动单元、发光驱动部及有机发光显示装置 |
CN104715734A (zh) * | 2015-04-14 | 2015-06-17 | 京东方科技集团股份有限公司 | 移位寄存器、栅极驱动电路及显示装置 |
CN105185287A (zh) * | 2015-08-27 | 2015-12-23 | 京东方科技集团股份有限公司 | 一种移位寄存器、栅极驱动电路和相关显示装置 |
CN105047124A (zh) * | 2015-09-18 | 2015-11-11 | 京东方科技集团股份有限公司 | 一种移位寄存器、栅极驱动电路及显示装置 |
CN105679248A (zh) * | 2016-01-04 | 2016-06-15 | 京东方科技集团股份有限公司 | 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置 |
Also Published As
Publication number | Publication date |
---|---|
CN105679248A (zh) | 2016-06-15 |
CN105679248B (zh) | 2017-12-08 |
US20180090072A1 (en) | 2018-03-29 |
US10109238B2 (en) | 2018-10-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2017118092A1 (zh) | 移位寄存器单元及其驱动方法、扫描驱动电路、显示装置 | |
EP3455858B1 (en) | Display apparatus and driving method | |
US10490133B2 (en) | Shift register module and display driving circuit thereof | |
KR101944465B1 (ko) | 발광 제어선 구동부 및 이를 이용한 유기전계발광 표시장치 | |
US8542225B2 (en) | Emission control line drivers, organic light emitting display devices using the same and methods of controlling a width of an emission control signal | |
KR100986887B1 (ko) | 발광제어선 구동부 및 이를 이용한 유기전계발광 표시장치 | |
KR101778701B1 (ko) | 구동 장치 및 이를 포함하는 표시 장치 | |
US9111490B2 (en) | Gate driving circuit and organic electroluminescent display apparatus using the same | |
KR20130143318A (ko) | 스테이지 회로 및 이를 이용한 유기전계발광 표시장치 | |
TWI485684B (zh) | 像素驅動器 | |
KR20150025539A (ko) | 스테이지 회로 및 이를 이용한 유기전계발광 표시장치 | |
US11295827B2 (en) | Shift register and method for driving the same, gate driving circuit and display apparatus | |
KR20130137860A (ko) | 스테이지 회로 및 이를 이용한 발광제어선 구동부 | |
US20140355733A1 (en) | Stage circuit and scan driver using the same | |
KR20130003252A (ko) | 스테이지 회로 및 이를 이용한 주사 구동부 | |
KR20170126567A (ko) | 표시 패널 구동부 및 이를 포함하는 표시 장치 | |
KR101813215B1 (ko) | 스테이지 회로 및 이를 이용한 주사 구동부 | |
US11398178B2 (en) | Pixel driving circuit, method, and display apparatus | |
KR20120082660A (ko) | 주사 구동 장치 및 그 구동 방법 | |
US11798482B2 (en) | Gate driver and organic light emitting display device including the same | |
JP6505445B2 (ja) | マルチプレクサ及び表示装置 | |
KR20170019022A (ko) | 발광제어 구동부 및 이를 포함하는 유기전계발광 표시장치 | |
WO2017045389A1 (zh) | 驱动电路及其驱动方法、触控显示面板和触控显示装置 | |
US11295646B2 (en) | Shift-register unit, a gate-driving circuit and driving method, and a display apparatus | |
WO2019140946A1 (zh) | 一种发光控制电路、发光控制驱动器以及显示装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 15520789 Country of ref document: US |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 16883222 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 16883222 Country of ref document: EP Kind code of ref document: A1 |
|
32PN | Ep: public notification in the ep bulletin as address of the adressee cannot be established |
Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 28.06.2019) |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 16883222 Country of ref document: EP Kind code of ref document: A1 |