WO2017117901A1 - 一种显示基板及其制作方法和显示装置 - Google Patents

一种显示基板及其制作方法和显示装置 Download PDF

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WO2017117901A1
WO2017117901A1 PCT/CN2016/082986 CN2016082986W WO2017117901A1 WO 2017117901 A1 WO2017117901 A1 WO 2017117901A1 CN 2016082986 W CN2016082986 W CN 2016082986W WO 2017117901 A1 WO2017117901 A1 WO 2017117901A1
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active layer
layer
amorphous silicon
silicon material
forming
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PCT/CN2016/082986
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English (en)
French (fr)
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陈善韬
张慧娟
郭易东
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京东方科技集团股份有限公司
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Priority to US15/322,547 priority Critical patent/US20180217421A1/en
Publication of WO2017117901A1 publication Critical patent/WO2017117901A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133371—Cells with varying thickness of the liquid crystal layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes

Definitions

  • the present disclosure relates to the field of liquid crystal display technologies, and in particular, to a display substrate, a manufacturing method thereof, and a display device.
  • An active matrix type display device is a display device that uses a thin film transistor (TFT) for pixel display driving, and has many advantages such as lightness, low power consumption, low radiation, low cost, etc.
  • the active matrix type display devices each include a TFT array substrate, and the TFT array substrate can be classified into amorphous silicon (a-Si:H) and low temperature polycrystalline silicon (Low Temperature Poly-Silicon) depending on the material forming the active layer of the TFT. , referred to as LTPS), high temperature poly-Silicon (HTPS), oxide semiconductor and other types.
  • Low temperature polysilicon (LTPS) film can form a higher driving current due to its atomic arrangement and high carrier mobility, which is beneficial to accelerate the reaction time of liquid crystal molecules, reduce the volume of thin film transistors, and increase the transparency of pixel cells.
  • the over-area allows the display device to have higher brightness, resolution, and aperture ratio, and thus is widely used in the fabrication process of thin film transistors.
  • the amorphous silicon structure is unstable, it is necessary to crystallize the amorphous silicon material in the preparation of the thin film transistor.
  • the shortcoming of the conventional crystallization technique is that the crystal grain size is limited after crystallization, and the uniformity of the performance of the product is poor.
  • the embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device, which are used to solve the problem that the size of the crystal grains formed in the prior art is limited and the uniformity of the product is poor.
  • Embodiments of the present disclosure provide a method of fabricating a display substrate, the method comprising:
  • the amorphous silicon material in the active layer is crystallized into a polysilicon material.
  • the active layer formed using the amorphous silicon material includes at least one step region, and the film thickness of the step region is greater than other regions of the active layer The film thickness of the domain.
  • the difference in energy density between regions of different thicknesses is used to make the amorphous silicon material in the high film thickness region in an incompletely molten state during the crystallization process, while the amorphous silicon material in the other active layer region is in a completely molten state.
  • the active layer is crystallized with the amorphous silicon portion which is not completely melted as the nucleation center of the crystallization process. In the subsequent crystallization process, due to the presence of crystal nuclei, it is possible to form crystal particles of a larger size, providing uniformity of the product.
  • an amorphous silicon material is used to form a pattern including an active layer on a substrate, the active layer including at least one step region, including:
  • a pattern including an active layer including a plurality of regularly arranged step regions is formed on the base substrate using a halftone mask.
  • the hydrogen in the amorphous silicon material is removed by an annealing process to reduce the hydrogen content in the amorphous silicon material, thereby preventing the occurrence of hydrogen explosion.
  • regular crystal nucleations may be formed, which is advantageous for further improving product uniformity.
  • crystallizing the amorphous silicon material in the active layer into a polysilicon material includes:
  • the active layer is irradiated with a laser to crystallize the amorphous silicon material in the active layer into a polysilicon material.
  • the illuminating the active layer with a laser to crystallize the amorphous silicon material in the active layer into a polysilicon material comprises:
  • the active layer is irradiated with an excimer laser to crystallize the amorphous silicon material in the active layer into a polysilicon material.
  • the exposing the active layer by using an excimer laser to crystallize the amorphous silicon material in the active layer into a polysilicon material including :
  • the amorphous silicon material is a polycrystalline material of a crystal nucleus.
  • the size of the crystallized polycrystalline silicon crystal grain can be effectively increased due to the presence of the crystal nucleus.
  • the method before forming a pattern including an active layer on a substrate, the method further includes: forming a buffer layer on the substrate; The buffer layer is located between the base substrate and the active layer.
  • the buffer layer can block the diffusion of impurities contained in the substrate in the subsequent process into the active layer of the thin film transistor, preventing the threshold voltage of the thin film transistor and Characteristics such as leakage current have an effect.
  • the active layer is made of a low-temperature polysilicon material, and the low-temperature polysilicon is usually crystallized by excimer laser annealing, the buffer layer can also prevent the diffusion of impurities caused by excimer laser annealing. It is advantageous to further improve the quality of the thin film transistor formed by low temperature polysilicon.
  • the method further includes: forming a source/drain doping region in the active layer by using ion implantation.
  • the carrier concentration in the active layer is increased, thereby contributing to an improvement in characteristics of the thin film transistor.
  • the method before performing ion implantation on the active layer, the method further includes:
  • a pattern including a gate electrode is formed on the substrate including the gate insulating layer.
  • the method further includes:
  • the active layer is irradiated with a laser from a side of the base substrate facing away from the active layer to activate ions of the source/drain doping region.
  • the method further includes:
  • a gate is formed over the gate insulating layer.
  • the active layer may be irradiated with a laser to activate ions of the source/drain doping region to improve the characteristics of the thin film transistor.
  • a gate insulating layer and a gate are then sequentially formed over the active layer for constructing a complete thin film transistor structure.
  • the laser is an excimer laser.
  • the method further includes:
  • a pixel electrode is formed over the planar layer, and the pixel electrode is electrically connected to the drain through the third via.
  • the method further includes forming an alignment film layer above the pixel electrode.
  • liquid crystal molecules corresponding thereto are formed in a certain orientation, thereby controlling the passage of light.
  • a difference in thickness between a step region of the active layer and other regions of the active layer is
  • an embodiment of the present disclosure further provides a display substrate, which is fabricated by the above method.
  • an embodiment of the present disclosure further provides a display device including the display substrate as described above.
  • FIG. 1 is a flowchart of a method for fabricating a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a flowchart of a method for manufacturing a display substrate according to an embodiment of the present disclosure
  • 3-14 are schematic diagrams showing steps of a method of fabricating a display substrate provided by an implementation of the present disclosure.
  • the embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device, which are used to solve the problem that the crystal grain size formed in the prior art using laser crystallization is limited and the product uniformity is poor.
  • Embodiments of the present disclosure provide a method for fabricating a display of a display substrate. Referring to FIG. 1, the method includes:
  • a pattern including an active layer is formed on a base substrate using an amorphous silicon material, the active layer including at least one stepped region, the film thickness of the stepped region being greater than other regions of the active layer Film thickness.
  • step 102 the amorphous silicon material in the active layer is crystallized into a polysilicon material.
  • the active layer formed using the amorphous silicon material includes at least one step region, and the film thickness of the step region is greater than the film thickness of other regions of the active layer.
  • the difference in energy density between regions of different thicknesses is used to make the amorphous silicon material in the high film thickness region in an incompletely molten state during the crystallization process, while the amorphous silicon material in the other active layer region is in a completely molten state.
  • the active layer is crystallized with the amorphous silicon portion which is not completely melted as the nucleation center of the crystallization process. In the subsequent crystallization process, due to the presence of crystal nuclei, it is possible to form crystal particles of a larger size, providing uniformity of the product.
  • the amorphous silicon material is used to form a pattern including an active layer on a substrate, the active layer including at least one step region, including:
  • a pattern including an active layer including a plurality of regularly arranged step regions is formed on the base substrate using a halftone mask.
  • the amorphous silicon material is dehydrogenated by an annealing process to reduce the hydrogen content in the amorphous silicon material to less than 2%, thereby preventing Stop the hydrogen explosion phenomenon.
  • regular crystal nucleations may be formed, which is advantageous for further improving product uniformity.
  • crystallizing the amorphous silicon material in the active layer into a polysilicon material comprises: irradiating the active layer with a laser to crystallize the amorphous silicon material in the active layer into a polysilicon material. It is of course also possible to crystallize the active layer by other means such as solid phase crystallization and metal induced crystallization.
  • the active layer when the active layer is irradiated with a laser to crystallize the amorphous silicon material in the active layer into a polysilicon material, specifically, the active layer may be irradiated with an excimer laser.
  • the amorphous silicon material in the active layer is crystallized into a polysilicon material.
  • the active layer is irradiated with an excimer laser such that the amorphous silicon material of the stepped region of the active layer is in an incompletely molten state, and the amorphous silicon material of the region other than the stepped region is completely In a molten state, after crystallization, a polycrystalline material in which an amorphous silicon material in an incompletely molten state of the step region is a crystal nucleus is formed.
  • the size of the crystal grain can be effectively increased due to the presence of the crystal nucleus.
  • the difference between the thickness of the film layer in the step region and the thickness of other regions of the active layer does not affect the grain size of the crystal, but it affects the realization of the process effect, and the greater the difference in thickness, the process The effect of the effect is also greater. Therefore, the reference range of the thickness difference is Moreover, the process parameters of laser crystallization are also related to the difference in thickness, for example, the difference in thickness is When the corresponding energy density is 400 mJ/cm2, the parameter is slightly lower than the normal process parameters when no step area is set.
  • the thickness of the film layer in the step region is generally Left and right, the thickness of other areas is generally Specifically, the step region is generally a circular protrusion region having a diameter of 500 to 1000 nm and a distribution pitch of 1000 nm to 2000 nm.
  • the method further includes: forming a buffer layer on the base substrate, the buffer layer being located on the base substrate and the active layer between.
  • the buffer layer can block the diffusion of impurities contained in the substrate in the subsequent process into the active layer of the thin film transistor, preventing the threshold voltage of the thin film transistor and Characteristics such as leakage current have an effect.
  • the active layer is made of a low-temperature polysilicon material, and the low-temperature polysilicon is usually crystallized by excimer laser annealing, the buffer layer can also prevent excimer laser annealing. The effect of the diffusion of the impurities is beneficial to further improve the quality of the thin film transistor formed by the low temperature polysilicon.
  • the method further includes forming a source/drain doping region in the active layer by means of ion implantation.
  • the carrier concentration in the active layer is increased, thereby contributing to an improvement in characteristics of the thin film transistor.
  • the method further includes:
  • a pattern including a gate electrode is formed on the substrate including the gate insulating layer.
  • a gate insulating layer is formed on a substrate on which an active layer is formed by a chemical vapor deposition method.
  • the deposition temperature is generally controlled below 500 ° C; the thickness of the gate insulating layer can be It is also possible to select a suitable thickness depending on the specific process needs.
  • the gate insulating layer is a single layer of silicon oxide, silicon nitride, or a combination of the two. When a single layer of silicon oxide is used, the thickness of the gate insulating layer is generally When a single layer of silicon nitride is used, the thickness of the gate insulating layer is generally
  • the gate is used as a mask for ion implantation.
  • the specific process may further illuminate the active layer with a laser to activate ions of the source/drain doping region to improve the characteristics of the thin film transistor; and then sequentially form a gate insulating layer and a gate electrode above the active layer.
  • the specific steps include:
  • the active layer is irradiated with a laser from a side of the base substrate facing away from the active layer to activate ions of the source/drain doping region.
  • the active layer may be irradiated with an excimer laser.
  • the substrate should further include a source, a drain, a pixel electrode, a passivation layer for insulating the gate from the source and drain, and a source drain and a pixel. a flat layer between the electrodes; the steps of forming these structures in the practice of the present disclosure include:
  • the first via is electrically connected to the active layer, and the drain and the second via are electrically connected to the active layer;
  • a pixel electrode is formed over the planar layer, and the pixel electrode is electrically connected to the drain through the third via.
  • an alignment film layer is further disposed in the display substrate, and the method for manufacturing the display substrate further includes: forming an alignment film above the pixel electrode Floor.
  • the method includes:
  • a silicon dioxide or silicon nitride layer is deposited on the base substrate 30 by plasma enhanced chemical vapor deposition to form a buffer layer 31.
  • the buffer layer 31 is used to block diffusion of impurities contained in the substrate into the active layer of the thin film transistor in a subsequent process, thereby preventing influence on characteristics such as threshold voltage and leakage current of the thin film transistor.
  • the active layer is made of a low-temperature polysilicon material, and the low-temperature polysilicon is usually processed by an excimer laser annealing method
  • the buffer layer 31 is provided to prevent diffusion of impurities caused by excimer laser annealing, and to improve low-temperature polysilicon. The quality of the formed thin film transistor.
  • step 202 an active layer 32 is formed on the buffer layer 31.
  • This step specifically includes:
  • a layer of amorphous silicon material 40 is formed on the substrate including the buffer layer 31;
  • the annealing process is used to remove hydrogen in the amorphous silicon material, and the hydrogen content in the amorphous silicon material is reduced to less than 2% to prevent hydrogen explosion;
  • a pattern comprising an active layer is formed on a substrate, the active layer comprising a plurality of regularly arranged step regions 41;
  • the active layer is irradiated with an excimer laser to crystallize the amorphous silicon material in the active layer into a polysilicon material to form an active layer 32 having a flat surface.
  • step 203 referring to FIG. 7, a gate insulating layer 33 is formed over the active layer.
  • This step specifically includes:
  • a gate insulating layer is formed on the substrate on which the active layer is formed by a chemical vapor deposition method. Controlling the deposition temperature below 500 ° C, depositing a transparent insulating material over the active layer to form a gate insulating layer, the thickness of the gate insulating layer is generally It is also possible to select a suitable thickness depending on the specific process needs.
  • the gate insulating layer is a single layer of silicon oxide, silicon nitride, or a combination of the two. Wherein, when a single layer of silicon oxide is used, the thickness of the gate insulating layer is generally When a single layer of silicon nitride is used, the thickness of the gate insulating layer is generally
  • step 204 referring to FIG. 8, a metal film is deposited over the gate insulating layer 33, and then a gate electrode 34 is formed by a patterning process.
  • This step specifically includes:
  • a metal film for forming a gate electrode is formed (eg, sputtered or coated, etc.) on the gate insulating layer.
  • a layer of photoresist is applied over the metal film.
  • the photoresist is exposed with a mask provided with a pattern including a gate.
  • the pattern of the gate is formed after development and etching.
  • the preparation process of the film layer formed by the patterning process is the same as that of the present invention, and will not be described in detail hereinafter.
  • a source-drain doping region 35 is formed in the active layer 32 by ion implantation.
  • the ions in the ion implantation process may be one or more of the following: B ion, P ion, As ion, PHx ion.
  • the ion implantation may be performed by ion implantation with a mass analyzer, ion cloud implantation without a mass analyzer, plasma implantation, or solid state diffusion implantation, and may be performed according to actual needs.
  • the active layer is irradiated with an excimer laser from a side of the base substrate facing away from the active layer to activate ions of the source/drain doping region.
  • a passivation layer 36 is formed over the gate electrode 34, and a first via hole 361 and a second via hole 362 penetrating the gate insulating layer and the passivation layer.
  • a source 37 and a drain 38 are formed over the passivation layer 36.
  • the first via 361 and the second via 362 are filled with a conductive material forming the source 37 and the drain 38; wherein the source passes through the first via 361 and the active layer Electrically connected, the drain and the second via 362 are electrically connected to the active layer.
  • the first and second via holes may be formed by wet etching or dry etching, and the source electrode 37 and the drain electrode 38 may be composed of a conductive material such as a metal or a metal alloy. .
  • a planarization layer 39 is formed over the source electrode 37 and the drain electrode 38, and a third via hole 363 is formed in the planarization layer.
  • a pixel electrode 310 is formed over the planar layer 39.
  • the step specifically includes: depositing a layer of indium tin oxide ITO transparent conductive film on the flat layer 39 by using a magnetron sputtering method, and then coating the photoresist and exposing and developing the film, and then performing wet etching and stripping to form the pixel electrode 310.
  • the third via hole 363 is filled with a conductive material for forming the pixel electrode, and the pixel electrode 310 is electrically connected to the drain through the third via hole 363.
  • an alignment film layer 311 is formed over the pixel electrode 310.
  • the alignment film layer 311 can be formed by transfer printing using an alignment film printing plate, or can be formed by inkjet printing. Those skilled in the art can select a specific process according to needs in practice.
  • the gate is used as a mask for ion implantation.
  • the specific process may further activate the ions of the source/drain doping region by laser irradiation of the active layer to improve the characteristics of the thin film transistor; then sequentially forming a gate insulating layer and a gate over the active layer for Construct a complete thin film transistor structure.
  • an embodiment of the present disclosure further provides a display substrate, which is fabricated by the above method.
  • an embodiment of the present disclosure further provides a display device including the display substrate as described above.

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Abstract

一种显示基板及其制作方法和显示装置，用以解决现有技术中使用激光晶化时形成的晶粒尺寸受限、产品均匀性差得问题。显示基板的制作方法包括：采用非晶硅材料在衬底基板（30）上形成包括有源层（32）的图形，有源层包括至少一个台阶区域（41），台阶区域的膜层厚度大于有源层其它区域的膜层厚度；使有源层中的非晶硅材料晶化成多晶硅材料。

Description

一种显示基板及其制作方法和显示装置 技术领域
本公开涉及液晶显示技术领域，尤其涉及一种显示基板及其制作方法和显示装置。
背景技术
有源矩阵(Active Matrix)型显示装置是利用薄膜晶体管(Thin Film Transistor，简称TFT)进行像素显示驱动的一种显示装置，具有轻薄、低功耗、低辐射、低成本等诸多优点，是目前最为主流的显示技术。有源矩阵型显示装置均包含有TFT阵列基板，并且根据TFT有源层的形成材料的不同，TFT阵列基板可分为非晶硅(a-Si:H)、低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)、高温多晶硅(High Temperature Poly-Silicon，简称HTPS)、氧化物半导体等多种类型。
低温多晶硅(简称LTPS)薄膜由于其原子排列规则、载流子迁移率高等特性，可形成较高的驱动电流，有利于加快液晶分子的反应时间，缩小薄膜晶体管的体积，增加像素单元中的透过面积，使显示装置具有更高的亮度、分辨率和开口率，因此，在薄膜晶体管的制作工艺中得到广泛采用。但由于非晶硅结构具有不稳定性，因此在制备薄膜晶体管时需要将非晶硅材料晶化。传统的晶化技术的不足之处在于晶化后晶粒尺寸受限，其产品性能的均匀性较差。
发明内容
本公开实施例提供了一种显示基板及其制作方法和显示装置，用以解决现有技术中形成的晶粒尺寸受限、产品均匀性差的问题。
本公开实施例提供了一种显示基板的制作方法，所述方法包括：
采用非晶硅材料在衬底基板上形成包括有源层的图形，所述有源层包括至少一个台阶区域，所述台阶区域的膜层厚度大于所述有源层其它区域的膜层厚度；
使所述有源层中的非晶硅材料晶化成多晶硅材料。
本公开实施例提供的方法中，利用非晶硅材料形成的有源层包括至少一个台阶区域，所述台阶区域的膜层厚度大于所述有源层其它区 域的膜层厚度。利用不同厚度膜厚区域的能量密度差异，在晶化的过程中使高膜厚区域的非晶硅材料处于不完全熔融状态，而其它有源层层区域的非晶硅材料则处于完全熔融状态，然后再以未完全熔融的非晶硅部分作为晶化过程的形核中心对有源层进行晶化。在后续晶化的过程中，由于晶核存在，能够形成尺寸较大的晶体颗粒，提供产品的均匀性。
在一种可能的实现方式中，本公开实施例提供的上述方法中，采用非晶硅材料在衬底基板上形成包括有源层的图形，所述有源层包括至少一个台阶区域，包括：
在所述衬底基板上形成非晶硅材料层；
利用退火工艺，去除非晶硅材料中的氢；
利用半色调掩膜板，在衬底基板上形成包括有源层的图形，所述有源层包括多个规则排列的台阶区域。
在所述衬底基板上形成非晶硅材料层后，通过退火工艺去除非晶硅材料中的氢，使非晶硅材料中的氢含量下降，防止氢爆现象的产生。而在所述有源层中的多个台阶区域规则排列时，则可以形成规则排列的晶核，有利于进一步提高产品的均匀性。
在一种可能的实现方式中，本公开实施例提供的上述方法中，使所述有源层中的非晶硅材料晶化成多晶硅材料，包括：
利用激光照射所述有源层，使所述有源层中的非晶硅材料晶化成多晶硅材料。
在一种可能的实现方式中，本公开实施例提供的上述方法中，所述利用激光照射所述有源层，使所述有源层中的非晶硅材料晶化成多晶硅材料，包括：
利用准分子激光照射所述有源层，使所述有源层中的非晶硅材料晶化成多晶硅材料。
在一种可能的实现方式中，本公开实施例提供的上述方法中，所述利用准分子激光照射所述有源层，使所述有源层中的非晶硅材料晶化成多晶硅材料，包括：
利用准分子激光照射所述有源层，使所述有源层的台阶区域的非晶硅材料呈不完全熔融状态，除所述台阶区域以外的其它区域的非晶硅材料呈完全熔融状态，晶化后形成以所述台阶区域的不完全熔融状 态的非晶硅材料为晶核的多晶体材料。
通过利用未完全熔融的台阶区域材料作为晶核对有源层进行晶化，由于晶核的存在，可有效增大晶化成的多晶硅晶粒的尺寸。
在一种可能的实现方式中，本公开实施例提供的上述方法中，在衬底基板上形成包括有源层的图形之前，所述方法还包括：在所述衬底基板上形成缓冲层，所述缓冲层位于所述衬底基板与所述有源层之间。
通过在衬底基板与有源层之间设置缓冲层，可通过该缓冲层阻挡在后续工艺中衬底基板中所含的杂质扩散进入薄膜晶体管的有源层，防止对薄膜晶体管的阈值电压和漏电流等特性产生影响。同时，由于所述有源层采用低温多晶硅材料，而低温多晶硅通常是用准分子激光退火的方法进行晶化，因此该缓冲层还能够起到防止准分子激光退火造成的杂质的扩散的作用，有利于进一步提高低温多晶硅形成的薄膜晶体管的质量。
在一种可能的实现方式中，本公开实施例提供的上述方法中，还包括：采用离子注入的方式，在所述有源层中形成源漏掺杂区。
通过在有源层中注入离子，有源层中的载流子浓度提高，从而有利于提高薄膜晶体管的特性。
在一种可能的实现方式中，本公开实施例提供的上述方法中，在对所述有源层进行离子注入之前，所述方法还包括：
在包括所述有源层的基板上形成栅绝缘层；
在包括所述栅绝缘层的基板上形成包括栅极的图形。
在一种可能的实现方式中，本公开实施例提供的上述方法中，所述方法还包括：
从所述衬底基板背向有源层的一侧采用激光对所述有源层进行照射，使所述源漏掺杂区的离子活化。
通过采用激光对所述有源层进行照射，使所述源漏掺杂区的离子活化，有利于提高薄膜晶体管的特性。
在一种可能的实现方式中，本公开实施例提供的上述方法中，所述方法还包括：
采用激光对所述有源层进行照射，使所述源漏掺杂区的离子活化；
在所述有源层的上方形成栅绝缘层；
在所述栅绝缘层的上方形成栅极。
该方法中还可以利用激光照射有源层来使所述源漏掺杂区的离子活化，提高薄膜晶体管的特征。然后在所述有源层的上方依次形成栅绝缘层和栅极，用于构建完整的薄膜晶体管结构。
在一种可能的实现方式中，本公开实施例提供的上述方法中，所述激光为准分子激光。
在一种可能的实现方式中，本公开实施例提供的上述方法中，所述方法还包括：
在所述栅极的上方形成钝化层，以及贯穿所述栅绝缘层和钝化层的第一过孔和第二过孔；
在所述钝化层的上方形成源极和漏极；其中，所述源极通过所述第一过孔与所述有源层电连接，所述漏极与所述第二过孔与所述有源层电连接；
在所述源极和漏极的上方形成平坦层，以及贯穿所述平坦层的第三过孔；
在所述平坦层的上方形成像素电极，且使得所述像素电极通过所述第三过孔与所述漏极电连接。
在一种可能的实现方式中，本公开实施例提供的上述方法中，所述方法还包括在所述像素电极的上方形成配向膜层。
通过在所述像素电极上形成配向膜层，使得与之对应的液晶分子形成一定的取向，从而控制光的通过。
在一种可能的实现方式中，本公开实施例提供的上述方法中，所述有源层的台阶区域与所述有源层其它区域之间的厚度差为
Figure PCTCN2016082986-appb-000001
基于同一发明构思，本公开实施例还提供了一种显示基板，所述显示基板采用上述方法制作。
基于同一发明构思，本公开实施例还提供了一种显示装置，所述显示装置包括如上所述的显示基板。
附图说明
图1为本公开实施例提供的一种显示基板的制作方法的流程图；
图2为本公开实施例提供的一种制作显示基板的方法的流程图；
图3-14为示出本公开实施提供的显示基板的制作方法的各步骤的示意图。
具体实施方式
本公开实施例提供了一种显示基板及其制作方法和显示装置，用以解决现有技术中使用激光晶化时形成的晶粒尺寸受限、产品均匀性差的问题。
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。
本公开实施例提供了一种显示基板显示的制作方法，参见图1，所述方法包括：
在步骤101中，采用非晶硅材料在衬底基板上形成包括有源层的图形，所述有源层包括至少一个台阶区域，所述台阶区域的膜层厚度大于所述有源层其它区域的膜层厚度。
在步骤102中，使所述有源层中的非晶硅材料晶化成多晶硅材料。
本公开实施例提供的方法中，利用非晶硅材料形成的有源层包括至少一个台阶区域，所述台阶区域的膜层厚度大于所述有源层其它区域的膜层厚度。利用不同厚度膜厚区域的能量密度差异，在晶化的过程中使高膜厚区域的非晶硅材料处于不完全熔融状态，而其它有源层层区域的非晶硅材料则处于完全熔融状态，然后再以未完全熔融的非晶硅部分作为晶化过程的形核中心对有源层进行晶化。在后续晶化的过程中，由于晶核存在，能够形成尺寸较大的晶体颗粒，提供产品的均匀性。
在制作所述显示基板的工艺中，所述采用非晶硅材料在衬底基板上形成包括有源层的图形，所述有源层包括至少一个台阶区域，包括：
在所述衬底基板上形成非晶硅材料层；
利用退火工艺，去除非晶硅材料中的氢；
利用半色调掩膜板，在衬底基板上形成包括有源层的图形，所述有源层包括多个规则排列的台阶区域。
在所述衬底基板上形成非晶硅材料层后，通过退火工艺对非晶硅材料进行去氢处理，使非晶硅材料中的氢含量下降至2％以下，从而防 止氢爆现象的产生。而在所述有源层中的多个台阶区域规则排列时，则可以形成规则排列的晶核，有利于进一步提高产品的均匀性。
进一步的，使所述有源层中的非晶硅材料晶化成多晶硅材料，包括：利用激光照射所述有源层，使所述有源层中的非晶硅材料晶化成多晶硅材料。当然还可以通过诸如固相结晶和金属诱导结晶等其他方式对有源层进行晶化。
进一步地，利用激光照射所述有源层，使所述有源层中的非晶硅材料晶化成多晶硅材料时，具体可以采用下述方式：利用准分子激光照射所述有源层，使所述有源层中的非晶硅材料晶化成多晶硅材料。
进一步地，利用准分子激光照射所述有源层，使所述有源层的台阶区域的非晶硅材料呈不完全熔融状态，除所述台阶区域以外的其它区域的非晶硅材料呈完全熔融状态，晶化后形成以所述台阶区域的不完全熔融状态的非晶硅材料为晶核的多晶体材料。
通过利用未完全熔融的台阶区域材料作为晶核对有源层进行晶化时，由于晶核的存在，可有效增大晶粒的尺寸。
具体地，通过实验可知，台阶区域的膜层厚度与有源层其它区域的厚度之差不会影响结晶的晶粒尺寸，但是会影响到工艺效果的实现，并且，厚度差越大，对工艺效果的影响也越大。因此，厚度差的参考范围为
Figure PCTCN2016082986-appb-000002
并且，激光晶化的工艺参数与该厚度差也有关系，例如在厚度差为
Figure PCTCN2016082986-appb-000003
时，对应能量密度为400mJ/cm2，该参数会略低于没有设置台阶区域时的正常工艺参数。
并且，台阶区域的膜层厚度一般在
Figure PCTCN2016082986-appb-000004
左右，其它区域的厚度一般在
Figure PCTCN2016082986-appb-000005
具体地，台阶区域一般为圆形突起区域，其直径为500-1000nm，分布间距为1000nm-2000nm。
进一步的，在衬底基板上形成包括有源层的图形之前，所述方法还包括：在所述衬底基板上形成缓冲层，所述缓冲层位于所述衬底基板与所述有源层之间。
通过在衬底基板与有源层之间设置缓冲层，可通过该缓冲层阻挡在后续工艺中衬底基板中所含的杂质扩散进入薄膜晶体管的有源层，防止对薄膜晶体管的阈值电压和漏电流等特性产生影响。同时，由于所述有源层采用低温多晶硅材料，而低温多晶硅通常是用准分子激光退火的方法进行晶化，因此该缓冲层还能够起到防止准分子激光退火 造成的杂质的扩散的作用，有利于进一步提高低温多晶硅形成的薄膜晶体管的质量。
进一步的，所述方法还包括：采用离子注入的方式，在所述有源层中形成源漏掺杂区。
通过在有源层中注入离子，有源层中的载流子浓度提高，从而有利于提高薄膜晶体管的特性。
进一步的，在对所述有源层进行离子注入之前，所述方法还包括：
在包括所述有源层的基板上形成栅绝缘层；
在包括所述栅绝缘层的基板上形成包括栅极的图形。
例如，采用化学气相沉积方法，在形成了有源层的基板上形成栅极绝缘层。沉积温度一般控制在500℃以下；栅极绝缘层的厚度可为
Figure PCTCN2016082986-appb-000006
也可根据具体工艺需要选择合适的厚度。又如，栅极绝缘层采用单层的氧化硅、氮化硅，或者二者的叠层。当采用单层氧化硅时，所述栅绝缘层厚度一般为
Figure PCTCN2016082986-appb-000007
当采用单层氮化硅时，所述栅绝缘层厚度一般为
Figure PCTCN2016082986-appb-000008
在上述步骤中，在形成栅绝缘层和栅极以后，以栅极为掩膜板进行离子注入的。具体工艺还可以先利用激光照射有源层，使所述源漏掺杂区的离子活化，以提高薄膜晶体管的特征；然后再在所述有源层的上方依次形成栅绝缘层和栅极，用于构建完整的薄膜晶体管结构，具体步骤包括：
从所述衬底基板背向有源层的一侧采用激光对所述有源层进行照射，使所述源漏掺杂区的离子活化。具体地，可以采用准分子激光对有源层进行照射。
通过采用激光对所述有源层进行照射，使所述源漏掺杂区的离子活化，有利于提高薄膜晶体管的特性。
进一步的，为构建完整的显示基板，所述基板还应包括源极、漏极、像素电极、用于将所述栅极与源漏极绝缘的钝化层、以及设置在源漏极与像素电极之间的平坦层；本公开实施中形成这些结构的步骤包括：
在所述栅极的上方形成钝化层，以及贯穿所述栅绝缘层和钝化层的第一过孔和第二过孔；
在所述钝化层的上方形成源极和漏极；其中，所述源极通过所述 第一过孔与所述有源层电连接，所述漏极与所述第二过孔与所述有源层电连接；
在所述源极和漏极的上方形成平坦层，以及贯穿所述平坦层的第三过孔；
在所述平坦层的上方形成像素电极，且使得所述像素电极通过所述第三过孔与所述漏极电连接。
进一步的，为了使与该显示基板对应的液晶分子形成一定的取向，所述显示基板中还设置有配向膜层，所述显示基板的制作方法还包括：在所述像素电极的上方形成配向膜层。
为了使本公开的目的、技术方案和优点更加清楚，下面结合附图及具体实施例进行逐步详细描述。参见图2，所述方法包括：
在步骤201中，参见图3，在衬底基板30上通过等离子体增强化学气相沉积法沉积二氧化硅或氮化硅层，形成缓冲层31。
本实施例中，所述缓冲层31用于阻挡在后续工艺中衬底基板中所含的杂质扩散进入薄膜晶体管的有源层，防止对薄膜晶体管的阈值电压和漏电流等特性产生影响。同时，由于所述有源层采用低温多晶硅材料，而低温多晶硅通常是用准分子激光退火的方法进行处理，因此，设置该缓冲层31还可以防止准分子激光退火造成的杂质扩散，提高低温多晶硅形成的薄膜晶体管的质量。
在步骤202中，在所述缓冲层31上形成有源层32。该步骤具体包括：
参见图4，在包括缓冲层31的所述衬底基板上形成非晶硅材料层40；
利用退火工艺，去除非晶硅材料中的氢，使非晶硅材料中的氢含量下降至2％以下，防止氢爆现象的产生；
参见图5，利用半色调掩膜板，在衬底基板上形成包括有源层的图形，所述有源层包括多个规则排列的台阶区域41；
参见图6，利用准分子激光照射所述有源层，使所述有源层中的非晶硅材料晶化成多晶硅材料，形成表面平坦的有源层32。
在步骤203中，参见图7，在所述有源层的上方形成栅绝缘层33。该步骤具体包括：
采用化学气相沉积方法，在形成了有源层的基板上形成栅极绝缘 层。控制沉积温度在500℃以下，在所述有源层的上方沉积透明绝缘材料以形成栅绝缘层，该栅极绝缘层的厚度一般为
Figure PCTCN2016082986-appb-000009
也可根据具体工艺需要选择合适的厚度。栅极绝缘层采用单层的氧化硅、氮化硅，或者二者的叠层。其中，当采用单层氧化硅时，所述栅绝缘层厚度一般为
Figure PCTCN2016082986-appb-000010
当采用单层氮化硅时，所述栅绝缘层厚度一般为
Figure PCTCN2016082986-appb-000011
在步骤204中，参见图8，在所述栅绝缘层33的上方沉积金属膜，然后通过构图工艺形成栅极34。该步骤具体包括：
在所述栅绝缘层上形成(如溅射或涂覆等)用于形成栅极的金属膜。接着，在金属膜上涂覆一层光刻胶。然后，用设置有包括栅极的图形的掩模板对光刻胶进行曝光。最后经显影、刻蚀后形成栅极的图形。本实施例阵列基板的制备方法中，涉及到通过构图工艺形成的膜层的制备工艺与此相同，此后不再详细赘述。
在步骤205中，参见图9，用离子注入的方式，在所述有源层32中形成源漏掺杂区35。
本实施例中，离子注入程序中的离子可为下述的一种或多种：B离子、P离子、As离子、PHx离子。具体的，离子注入可采用具有质量分析仪的离子注入、不具有质量分析仪的离子云式注入、等离子注入或者固态扩散式注入等方法，并且可根据实际需要进行注入。
在步骤206中，从所述衬底基板背向有源层的一侧采用准分子激光对所述有源层进行照射，使所述源漏掺杂区的离子活化。
在步骤207中，参见图10，在所述栅极34的上方形成钝化层36，以及贯穿所述栅绝缘层和钝化层的第一过孔361和第二过孔362。
在步骤208中，参见图11，在所述钝化层36的上方形成源极37和漏极38。所述第一过孔361和第二过孔362中填充有形成所述源极37和漏极38的导电材料；其中，所述源极通过所述第一过孔361与所述有源层电连接，所述漏极与所述第二过孔362与所述有源层电连接。
在通过构图工艺形成源极和漏极时，可采用湿法刻蚀或者干法刻蚀形成第一和第二过孔，并且源极37和漏极38可以由金属、金属合金等导电材料构成。
在步骤209中，参见图12，在所述源极37和漏极38的上方形成平坦层39，并在所述平坦层中形成第三过孔363。
在步骤210中，参见图13，在所述平坦层39的上方形成像素电极310。该步骤具体包括：使用磁控溅射法在平坦层39上沉积一层氧化铟锡ITO透明导电薄膜，然后经涂覆光刻胶并曝光显影，再进行湿刻、剥离后，形成像素电极310的图形。所述第三过孔363中填充有用于形成所述像素电极的导电材料，所述像素电极310通过所述第三过孔363与漏极电连接。
在步骤211中，参见图14，在所述像素电极310的上方形成配向膜层311。所述配向膜层311可采用配向膜印刷版进行转印的方式形成，也可以采用喷墨式印刷方式形成，本领域技术人员在实践中可以根据需要选择具体的工艺。
在上述步骤中，在形成栅绝缘层和栅极以后，以栅极为掩膜板进行离子注入的。具体工艺还可以先利用激光照射有源层使所述源漏掺杂区的离子活化，提高薄膜晶体管的特征；然后再在所述有源层的上方依次形成栅绝缘层和栅极，用于构建完整的薄膜晶体管结构。此外，还可以在对非晶硅进行晶化之前在预定的源漏掺杂区域进行掺杂，然后通过一次准分子激光照射，实现有源层的非晶硅晶化以及源漏掺杂区的离子活化，从而减少工艺流程，降低生产成本。
基于同一发明构思，本公开实施例还提供了一种显示基板，所述显示基板采用上述方法制作。
基于同一发明构思，本公开实施例还提供了一种显示装置，所述显示装置包括如上所述的显示基板。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (16)

  1. 一种显示基板的制作方法，包括：
    采用非晶硅材料在衬底基板上形成包括有源层的图形，所述有源层包括至少一个台阶区域，所述台阶区域的膜层厚度大于所述有源层其它区域的膜层厚度；
    使所述有源层中的非晶硅材料晶化成多晶硅材料。
  2. 如权利要求1所述的方法，其中，采用非晶硅材料在衬底基板上形成包括有源层的图形，所述有源层包括至少一个台阶区域，包括：
    在所述衬底基板上形成非晶硅材料层；
    利用退火工艺，去除非晶硅材料中的氢；
    利用半色调掩膜板，在衬底基板上形成包括有源层的图形，所述有源层包括多个规则排列的台阶区域。
  3. 如权利要求1所述的方法，其中，使所述有源层中的非晶硅材料晶化成多晶硅材料，包括：
    利用激光照射所述有源层，使所述有源层中的非晶硅材料晶化成多晶硅材料。
  4. 如权利要求3所述的方法，其中，所述利用激光照射所述有源层，使所述有源层中的非晶硅材料晶化成多晶硅材料，包括：
    利用准分子激光照射所述有源层，使所述有源层中的非晶硅材料晶化成多晶硅材料。
  5. 如权利要求4所述的方法，其中，利用准分子激光照射所述有源层，使所述有源层中的非晶硅材料晶化成多晶硅材料，包括：
    利用准分子激光照射所述有源层，使所述有源层的台阶区域的非晶硅材料呈不完全熔融状态，除所述台阶区域以外的其它区域的非晶硅材料呈完全熔融状态，晶化后形成以所述台阶区域的不完全熔融状态的非晶硅材料为晶核的多晶体材料。
  6. 如权利要求1所述的方法，其中，在衬底基板上形成包括有源层的图形之前，所述方法还包括：在所述衬底基板上形成缓冲层，所述缓冲层位于所述衬底基板与所述有源层之间。
  7. 如权利要求1所述的方法，还包括：采用离子注入的方式，在所述有源层中形成源漏掺杂区。
  8. 如权利要求7所述的方法，其中，在对所述有源层进行离子注入之前，所述方法还包括：
    在包括所述有源层的基板上形成栅绝缘层；
    在包括所述栅绝缘层的基板上形成包括栅极的图形。
  9. 如权利要求8所述的方法，还包括：
    从所述衬底基板背向有源层的一侧采用激光对所述有源层进行照射，使所述源漏掺杂区的离子活化。
  10. 如权利要求7所述的方法，还包括：
    采用激光对所述有源层进行照射，使所述源漏掺杂区的离子活化；
    在所述有源层的上方形成栅绝缘层；
    在所述栅绝缘层的上方形成栅极。
  11. 如权利要求9或10所述的方法，其中，所述激光为准分子激光。
  12. 如权利要求9或10所述的方法，还包括：
    在所述栅极的上方形成钝化层，以及贯穿所述栅绝缘层和钝化层的第一过孔和第二过孔；
    在所述钝化层的上方形成源极和漏极；其中，所述源极通过所述第一过孔与所述有源层电连接，所述漏极与所述第二过孔与所述有源层电连接；
    在所述源极和漏极的上方形成平坦层，以及贯穿所述平坦层的第三过孔；
    在所述平坦层的上方形成像素电极，且使得所述像素电极通过所述第三过孔与所述漏极电连接。
  13. 如权利要求12所述的方法，还包括在所述像素电极的上方形成配向膜层。
  14. 如权利要求1所述的方法，其中，所述有源层的台阶区域与所述有源层其它区域之间的厚度差为
    Figure PCTCN2016082986-appb-100001
  15. 一种显示基板，采用如权利要求1～14任一权项所述的方法制作。
  16. 一种显示装置，包括如权利要求15所述的显示基板。
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