WO2017045380A1 - 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置 - Google Patents
移位寄存器单元及其驱动方法、栅极驱动电路和显示装置 Download PDFInfo
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- WO2017045380A1 WO2017045380A1 PCT/CN2016/075976 CN2016075976W WO2017045380A1 WO 2017045380 A1 WO2017045380 A1 WO 2017045380A1 CN 2016075976 W CN2016075976 W CN 2016075976W WO 2017045380 A1 WO2017045380 A1 WO 2017045380A1
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- 238000000034 method Methods 0.000 title claims abstract description 15
- 239000003990 capacitor Substances 0.000 claims description 39
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
- G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
- G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2230/00—Details of flat display driving waveforms
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Definitions
- the present disclosure relates to the field of display technologies, and in particular, to a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
- Existing GOA circuits typically include a plurality of cascaded shift register units.
- a general shift register unit the input end of the output unit is connected to a clock signal, and the width of the high-level shift pulse outputted by the output unit is consistent with the width of a high-level pulse in the clock signal.
- the width of the shift pulse required by the display device is large, it is impossible to drive with the gate drive circuit obtained by cascading such shift register units.
- the present disclosure provides a shift register unit, including: an input unit, an output unit, a reset unit, a first control unit, and a second control unit, and has a first node, a second node, and a third node.
- the input unit is connected to the first input end, the second input end, and the second node, and is adapted to be when the level of the first input end is an input unit active level
- the level of the second node is set to the level input by the second input
- the first control unit is connected to the third input, the first node and the second node, and the level suitable for the second node is Turning on at a low level, setting the level of the first node to a level input by the third input terminal, and being adapted to maintain a level of the first node when the first node is floating
- the second control unit includes a first control module and a second control module; the first control module is connected to the fourth input terminal, the fifth input terminal, the first node, and the third node a point adapted to be turned on when a level of the third node is a low level and a level of the fourth input terminal is an active level of the first control module, and setting a level of the first node
- first input end and the sixth input end are the same input end, and the input unit active level is a low level.
- the third input end and the eight input end are the same input end.
- the fifth input end and the seventh input end are the same input end.
- the ninth input end is the same input end as the fifth input end or the seventh input end.
- the fifth, seventh and ninth input terminals are the same input end.
- the first control unit includes a first transistor and a first capacitor, the first transistor is a P-type transistor, a source thereof is connected to the third input terminal, and a drain is connected to the first node, a gate Connecting the second node, the first end of the first capacitor is connected to the first node.
- the second end of the first capacitor is connected to the third input end or the eighth input end.
- the first control module includes a second transistor and a third transistor; the second transistor is a P-type transistor, a gate thereof is connected to the third node, and a drain is connected to the fifth input terminal, a source Connecting a drain of the third transistor; a gate of the third transistor is connected to the fourth input, and a source is connected to the first node.
- the third transistor is a P-type transistor.
- the second control module includes a fourth transistor and a fifth transistor that are both P-type transistors, and a second capacitor, a gate of the fourth transistor is connected to the sixth input terminal, and a drain is connected to the first a third node, the source is connected to the seventh input; the gate of the fifth transistor is connected to the second node, the drain is connected to the third node, and the source is connected to the sixth input; the first end of the second capacitor Connecting the third node.
- the second end of the second capacitor is connected to the fourth input end.
- the input unit includes a P-type sixth transistor, a gate of the sixth transistor is connected to the first input end, a source is connected to the second input end, and a drain is connected to the second node.
- the output unit includes a P-type seventh transistor, a gate of the seventh transistor is connected to the first node, a source is connected to the eighth input end, and a drain is connected to the shift signal output end.
- the reset unit includes a P-type eighth transistor and a third capacitor, a gate of the eighth transistor is connected to the second node, a source is connected to the shift signal output end, and a drain is connected to the drain And a ninth input end, the first end of the third capacitor is connected to the second node.
- the second end of the third capacitor is connected to the shift signal output end.
- the present disclosure provides a method of driving the shift register unit of any of the above, comprising: inputting a low level at the fifth input, the seventh input, and the ninth input, in the third Inputting a high level at the input end and the eighth input end; inputting a clock signal on the first input end, the sixth input end, and the fourth input end; and when the clock signal input at the first input end is an input unit active level, The clock signal input by the fourth input terminal is an invalid level of the first control module, and the clock signal input at the sixth input terminal is a low level; when the clock signal input by the fourth input terminal is an active level of the first control module The clock signal input at the first input terminal is an input unit invalid level, and the clock signal input at the sixth input terminal is a high level; the input unit active level and the sixth input terminal of the clock signal input by the first input terminal The input clock signal is synchronized at a low level, and does not overlap or overlap with the first control module active level in the clock signal input at the fourth input terminal; the clock input clock signal is synchron
- the input unit active level is a low level
- the first control module active level is a low level
- the present disclosure provides a gate driving circuit including a plurality of cascaded shift register units, wherein a shift signal input terminal is included in any one of the first stage and the first stage of the shift register unit Connected to the shift signal output end of the shift register unit of the previous stage, and the shift signal output end is connected to the shift signal input end of the shift register unit of the next stage, and the shift signal output end is also connected to the upper stage.
- the reset control signal input terminal of the shift register unit is connected, and the shift signal input end of the first stage shift register unit is connected to a start signal.
- the present disclosure provides a display device including the gate drive circuit described above.
- the width of the shift pulse outputted by the shift register unit can be adjusted by the shift pulse input to the shift register unit, and the output shift pulse signal and the input shift pulse signal are The width is the same.
- the width of the pulse signal outputted by each stage of the shift register unit in the gate drive circuit cascaded by such a shift register unit can be adjusted according to the width of the start signal input to the first stage shift register unit.
- the display device having a large width of the required shift pulse is driven.
- FIG. 1 is a schematic structural diagram of a shift register unit according to some embodiments of the present disclosure
- FIG. 2 is a schematic circuit diagram of a shift register unit according to some embodiments of the present disclosure
- Fig. 3 is a timing chart showing signals and node potentials when the shift register unit of Fig. 2 is driven.
- the present disclosure provides a shift register unit.
- the shift register unit includes:
- the input unit 110 is connected to the first input terminal S1, the second input terminal S2 and the second node N2, and the level suitable at the first input terminal S1 is an effective level corresponding to the input unit 110 (so that the connected transistor is turned on) Leveling, for example, low level, setting the level of the second node N2 to the level input by the second input terminal S2;
- the first control unit 140 is connected to the third input terminal S3, the first node N1 and the second node N2, and is adapted to be turned on when the level of the second node N2 is low, and set the level of the first node N1 to the third.
- the level of the input terminal S3 is adapted to maintain the level of the first node N1 when the first node N1 is floating;
- the second control unit 150 includes a first control module 151 and a second control module 152;
- the first control module 151 is connected to the fourth input terminal S4, the fifth input terminal S5, the first node N1 and the third node N3, and is adapted to be at a low level of the third node N3 and the power of the fourth input terminal S4.
- the level of the first node N1 is set to a level at which the fifth input terminal S5 is connected;
- the second control module 152 is connected to the sixth input terminal S6, the seventh input terminal S7, the second node N2, and the third node N3 for inputting the level of the second node N2 to the low level and inputting the sixth input terminal S6.
- the level of the third node N3 is set to a high level; when the level of the sixth input terminal S6 is low, the level of the third node N3 is set to the seventh input end.
- Level of S7 and adapted to maintain the level of the third node N3 when the third node N3 is floating;
- the output unit 120 is connected to the shift signal output terminal OUTPUT and the eighth input terminal S8 for turning on when the level of the first node N1 is low, and setting the level of the shift signal output terminal OUTPUT to the eighth input terminal S8. Input level
- the reset unit 130 is connected to the second node N2, the shift signal output terminal OUTPUT and the ninth input terminal S9 is adapted to set the level of the shift signal output terminal OUTPUT to the level of the ninth input terminal S9 when the second node N2 is at a low level, and is adapted to maintain the second state when the second node N2 is floating.
- the width of the shift pulse outputted by the shift register unit can be adjusted by the shift pulse input to the shift register unit, and the output shift pulse signal and the input shift pulse signal are The width is the same.
- the width of the pulse signal outputted by each stage of the shift register unit in the gate drive circuit cascaded by such a shift register unit can be adjusted according to the width of the start signal input to the first stage shift register unit.
- the display device having a large width of the required shift pulse is driven.
- the floating connection here refers to a state in which the corresponding node is not connected to the current loop, causing the node's charge to not be lost through the current loop.
- the present disclosure provides a method of driving a shift register unit as described above, the method comprising:
- the clock signal is input to the terminal S6 and the fourth input terminal S4; and when the clock signal input by the first input terminal S1 is the active level of the input unit, the clock signal input at the fourth input terminal S4 is the invalid level of the first control module.
- the clock signal input at the sixth input terminal S6 is a low level; when the clock signal input at the fourth input terminal S4 is the active level of the first control module, the clock signal input at the first input terminal S1 is an input unit invalid level.
- the clock signal input at the sixth input terminal S6 is at a high level; the active level of the input unit in the clock signal input by the first input terminal S1 is synchronized with the low level of the clock signal input by the sixth input terminal S6, and The first control module active level in the clock signal input at the fourth input terminal S4 does not overlap in time, and is not connected;
- the shift pulse signal of the high level is input at the second input terminal S2; the clock signal input at the first input terminal is at the beginning of the input shift pulse.
- the subsequent N+1th input unit is inactive, the input of the high level shift pulse signal is stopped at the second input terminal S2; wherein N is an arbitrary integer greater than or equal to 1.
- the width of the output shift pulse can be adjusted by adjusting the size of N.
- the fifth input terminal S5, the seventh input terminal S7 and the ninth input terminal S9 are always input with a low level.
- any two input terminals or three input terminals may be used.
- the first input terminal S5 and the seventh input terminal S7 may be the same input terminal, or may be the same input terminal as the ninth input terminal S9, or the seventh input terminal S7 and the ninth input terminal S9 may be combined.
- the fifth input terminal S5, the seventh input terminal S7 and the ninth input terminal S9 are all the same input terminal. This can reduce the number of signal lines used in the corresponding gate drive circuit.
- the third input terminal S3 and the eighth input terminal S8 can also be the same input terminal.
- the active level of the input unit 110 may be a low level
- the first input terminal S1 and the sixth input terminal S6 herein may be the same input terminal. These can save the number of signal lines used.
- the first control unit 140 includes a first transistor and a first capacitor, the first transistor is a P-type transistor, the source is connected to the third input terminal S3, the drain is connected to the first node N1, and the gate is connected.
- the second node N2, the first end of the first capacitor is connected to the first node N1. Further, the second end of the first capacitor may be connected to the third input terminal S3 or the eighth input terminal S8.
- the third input terminal S3 and the eighth input terminal S8 generally continue to input a high level, connecting the second end of the first capacitor to the third input terminal S3 or the eighth input terminal S8 can ensure the first The voltage at the second end of a capacitor does not change, thereby avoiding a change in the voltage at the first end of the first capacitor.
- the first control module 151 can include a second transistor and a third transistor
- the second transistor is a P-type transistor having a gate connected to the third node N3, a drain connected to the fifth input terminal S5, and a source connected to the drain of the third transistor;
- the gate of the third transistor is connected to the fourth input terminal S4, and the source is connected to the first node N1.
- the third transistor may be a P-type transistor.
- the second control module 152 may include a fourth transistor and a fifth transistor, both of which are P-type transistors, and a second capacitor.
- the gate of the fourth transistor is connected to the sixth input terminal S6 (which may be coupled to the first input terminal S1).
- the same input terminal) the drain is connected to the third node N3, and the source is connected to the seventh input terminal S7 (which can be the same input terminal as the fifth input terminal S5);
- the fifth transistor has a gate connected to the second node N2, a drain connected to the third node N3, and a source connected to the sixth input terminal S6 (which can be the same input end as the first input terminal S1); the first end of the second capacitor is connected The third node N3.
- the second end of the second capacitor may be connected to the fourth input terminal S4, so that when the fourth input terminal S4 is input with a high level, the voltage of the third node N3 can be advanced. The one step rises to ensure that the third node N3 is maintained at a high level, so that the first control module 151 can be turned off.
- the input unit 110 may include a P-type sixth transistor, the gate of the sixth transistor is connected to the first input terminal S1, the source is connected to the second input terminal S2, and the drain is connected to the second node N2.
- the output unit 120 may include a P-type seventh transistor, the gate of the seventh transistor is connected to the first node N1, and the source is connected to the eighth input terminal S8 (which may be the same input as the third input terminal S3). End), the drain is connected to the shift signal output terminal OUTPUT.
- the reset unit 130 may include a P-type eighth transistor and a third capacitor, the gate of the eighth transistor is connected to the second node N2, the source is connected to the shift signal output terminal OUTPUT, and the drain connection is
- the ninth input terminal S9 (which may be the same input terminal as the fifth input terminal S5)
- the first end of the third capacitor is connected to the second node N2.
- the second end of the third capacitor can be connected to the shift signal output terminal OUTPUT, so that when the shift signal output terminal OUTPUT is at a high level, the level of the second node N2 can be further raised to ensure the second node N2. Maintain high level to avoid affecting the shift signal output terminal OUTPUT output high level.
- the source and drain described above may be interchanged in some transistors.
- the above various units are not limited to the above structure, and in some cases, the specific structure of some units may be different, for example, in some applications, the input unit may include a plurality of transistors.
- the specific structure of each unit does not actually affect the implementation of the present disclosure, and the corresponding should fall within the protection scope of the present disclosure.
- the source and the drain of each of the above transistors are only for convenience of description.
- the connection relationship between the source and the drain of the same transistor can be interchanged.
- the electrode connected to the second input terminal S2 may also be a drain
- the corresponding electrode connected to the second node N2 may be a source.
- the manner in which the connection relationship between the source and the drain of each transistor in the present disclosure is interchanged should understand the equivalent replacement of the corresponding technical features in the technical solutions provided by the present disclosure, and the corresponding technical solutions should also fall within the protection scope of the present disclosure. .
- a shift register unit and a driving method thereof provided by the present disclosure are described in detail below in conjunction with a specific circuit diagram and a potential timing diagram of a key signal and a node when the shift register unit is driven, assuming that the first input is in the shift register unit.
- the terminal S1 and the sixth input terminal S6 are located at the same input terminal (hereinafter referred to as S1), and the third input terminal S3 and the eighth input terminal S8 are located at the same input terminal (hereinafter referred to as S3), the fifth input terminal S5, the seventh input terminal S7 and the ninth input terminal S9 are in the same input terminal (hereinafter referred to as S5); referring to FIG.
- the shift register unit includes: M1-M8, a total of 8 P Type transistor and three capacitors C1, C2 and C3, and having a first input terminal S1, a second input terminal S2, a third input terminal S3, a fourth input terminal S4, a fifth input terminal S5, and a shift signal input terminal OUTPUT and three nodes N1, N2 and N3; wherein the drain of the first transistor M1, the source of the third transistor M3, the gate of the seventh transistor M7, and the first end of the first capacitor C1 are connected to the first node N1
- the gate of the first transistor M1, the gate of the eighth transistor M8, the gate of the fifth transistor M5, the drain of the sixth transistor M6, and the first end of the third capacitor C3 are all connected to the second node N2;
- the drain of the transistor M4, the drain of the fifth transistor M5, the gate of the second transistor M2, and the first end of the second capacitor C2 are connected to the node N3; the second end of the capacitor C1 and the source and the first of the first transistor M
- the shift register unit in the figure can adjust the width of the shift pulse signal of the output by adjusting the width of the shift pulse signal input thereto, and the driving method of the shift register unit in FIG. 2 will be described below with reference to FIG.
- a first clock signal is applied at the first input terminal S1
- a high level is applied at the third input terminal S3
- a second clock signal is applied at the fourth input terminal S4, fifth.
- the input terminal S5 applies a low level; and when the first clock signal is at a low level, the second clock signal is at a high level; when the second clock signal is at a low level, the first clock signal is at a high level; and the two clocks
- the low level of the signal does not overlap or continue in time;
- the shift pulse signal of the high level is input at the second input terminal S2; and the first clock is started after the input of the shift pulse signal is started.
- the signal is in the second high-level shift pulse signal, input a low level at the second input terminal, that is, stop inputting a high-level shift pulse signal at the second input terminal; thus, the output shift pulse can be made.
- the width of the signal coincides with the width of the input shift pulse signal, thereby ensuring that the shift drive pulse signals of the high level are stably outputted by the stages of the gate drive circuit cascaded by the shift register unit described above, specifically:
- the first clock signal applied on the first input terminal S1 is at a low level, and the second clock signal applied at the fourth input terminal S4 is at a high level; the first input terminal S1 is at a low level
- the sixth transistor M6 is turned on, and since the level applied on the second input terminal S2 is a low level, the second node N2 is set to a low level at this time, causing the first transistor M1 to be turned on, thereby making the first
- the node N1 is connected to the third input terminal S3. Since S3 is always at a high level, the level of the first node N1 is at a high level, ensuring that the seventh transistor M7 is not turned on; and the second clock signal is at a high level. Resulting that the third transistor M3 does not turn on, and does not pull down the level of the first node N1;
- stage b since the first clock signal applied on the first input terminal S1 is at a high level; at this time, the sixth transistor M6 is turned off, causing the first node N2 to float, and the third capacitor C3 is maintained at the second node N2.
- the level is low, at which time the first transistor M1 continues to conduct, ensuring that the level of the first node N1 is high, and the fifth transistor M5 is also turned on, resulting in the level of the third node N3 and the first input.
- the terminals S1 are identical and are both high level, so that the second transistor M2 is not turned on; thus, although the low level input by the fourth input terminal S4 causes the transistor M3 to be turned on, the first node N1 is not connected to the fifth input. Terminal S5, will not be set low;
- a shift pulse signal of a high level is applied to the second input terminal S2, and the first clock signal applied at the first input terminal S1 is at a low level, and the sixth transistor M6 and the fourth transistor are M4 is both turned on, such that the voltage at the second node N2 connected to the second input terminal S2 rises, thereby causing the first transistor M1 and the fifth transistor M5 to be turned off, and the first clock applied on the first input terminal S1
- the signal is at a low level such that the fourth transistor M4 is turned on. Since S5 is always at a low level, the third node N3 is set to a low level; a high level applied at the fourth input terminal S4 causes the third transistor M3 to be turned off. At this time, the voltage of N1 of the first node is still high because it is maintained by the first capacitor C1. At this time, the seventh transistor M7 is not turned on, and does not output a high level;
- the first clock signal applied on the first input terminal S1 is at a high level, and the high-level shift pulse signal is continuously applied at the second input terminal S2; at this time, the sixth transistor M6 continues to be turned off,
- the level of the two nodes N2 continues to be maintained at a high level, so that the fifth transistor M5 and the first transistor M1 are both turned off; and the first input terminal S1 is at a high level such that the fourth transistor M4 is turned off, such that the third node N3
- the level does not change, is maintained at a low level by the capacitor C2, so that the second transistor M2 is turned on; the low level applied by the fourth input terminal S4 causes the third transistor M3 to also be turned on, thereby turning the first node N1
- the level is set low, which will cause the seventh transistor M7 to turn on and start outputting high.
- the first clock signal applied on the first input terminal S1 is at a low level
- the second clock signal applied at the fourth input terminal S4 is at a high level
- the second input terminal S2 continues to apply a high voltage.
- the flat shift pulse signal at this time, the sixth transistor M6 is turned on, and the second node N2 is still at a high level, so that the first transistor M1 is turned off, ensuring that the level of the first node N1 is not pulled high
- the third transistor M3 is turned off; at this time, the seventh transistor M7 continues to be turned on, and outputs a high-level shift pulse signal;
- the first clock signal applied on the first input terminal S1 is at a high level
- the second input terminal S2 stops applying a high-level shift pulse signal, that is, a low level is applied
- M6 is turned off, the level of the second node N2 is still maintained at a high level, and the first transistor M1 is still not turned on, so that the level of the first node N1 is not pulled high, and the seventh transistor M7 is at this time.
- a high-level shift pulse signal that is, a low level is applied
- the first clock signal applied on the first input terminal S1 is at a low level
- the second clock signal applied at the fourth input terminal S4 is at a high level
- a low level is applied at the second input terminal S2.
- the first input terminal S1 is at a low level such that the sixth transistor M6 is turned on, and since the level applied on the second input terminal S2 is a low level, the second node N2 is set to a low level, resulting in the a transistor M1 is turned on, so that the first node N1 is connected to the third input terminal S3, the level of the first node N1 is at a high level, so that the seventh transistor M7 is no longer turned on; and the fourth input terminal S4 is The input second clock signal is at a high level, causing the third transistor M3 not to be turned on, and the level of the first node N1 is not pulled low;
- the h phase it can be divided into two phases, and the first clock signal applied on the first input terminal S1 in the first phase h1 and the second clock signal applied on the fourth input terminal S4 are both high level signals, At this time, the sixth transistor M6 is turned off, so that the second node N2 is still maintained at a low level, causing the fifth transistor M5 to be turned on, and since the clock signal applied on the first input terminal S1 is at a high level at this time, At this time, the level of the third node N3 is at a high level; the second transistor M2 is turned off; the first clock signal applied at the first input terminal S1 in the second phase h2 is at a high level, at the fourth input terminal.
- the second clock signal applied on S4 is at a low level; at this time, the fourth transistor M4 is turned off, and the fifth transistor M5 is turned on, so that the third node N3 continues to communicate to the first input terminal S1, the third node N3 continues to be high, causing the second transistor M2 to be turned off; thus even if the fourth input terminal S4 is input low level
- the three transistors M3 are turned on, and the first node N1 is not connected to the fifth input terminal S5, so that the level of the first node N1 is not pulled low, and the seventh transistor M7 is no longer turned on.
- the start time and the end time of the high level output by the seventh transistor M7 correspond to a half clock later than the level input to the second input terminal S2 (one clock includes a high level)
- the pulse and a low-level pulse are such that the high-level shift pulse signal outputted by the shift register unit is exactly the same as the width of the high-level shift pulse signal input to the second input terminal S2.
- the level of the second node N2 is not pulled low, and the corresponding first transistor T1 does not turn on the level of the first node N1. Pull high so that the seventh transistor M7 can output a high level.
- all the transistors are P-type transistors, which can be fabricated by the same process, which is beneficial to reduce the manufacturing difficulty.
- the present disclosure further provides a gate driving circuit, the gate driving circuit comprising a plurality of cascaded shift register units, wherein the shift register unit is the shift register unit according to any one of the above . It is not difficult to understand that, in the specific implementation, in the above shift register unit, in addition to the last stage and the first stage of any one of the shift register units, the shift signal input terminal and the shift register unit of the previous stage are shifted.
- the bit signal output end is connected to receive the shift signal outputted by the output unit of the previous stage, and the shift signal output end is connected to the shift signal input end of the shift register unit of the next stage for shifting the register signal
- the output is output to the next stage shift register unit, and the shift signal output terminal is further connected to the reset control signal input end of the shift register unit of the previous stage for resetting the shift register unit of the previous stage.
- the shift signal input of the first stage shift register unit is connected to a start signal.
- the other inputs are connected to the corresponding signal lines.
- the present disclosure also provides a display device including the above-described gate driving circuit.
- the display device here can be: electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator and the like with any display product or component.
- the display device provided by the present disclosure may be a liquid crystal display device or other types of display devices.
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Abstract
Description
Claims (20)
- 一种移位寄存器单元,包括:输入单元、输出单元、重置单元、第一控制单元和第二控制单元,并具有第一节点、第二节点、第三节点、移位信号输出端和若干输入端;其中,所述输入单元连接第一输入端、第二输入端和第二节点,适于在第一输入端的电平为输入单元有效电平时,将所述第二节点的电平置为第二输入端输入的电平;所述第一控制单元连接第三输入端、第一节点和第二节点,适于在所述第二节点的电平为低电平时开启,将所述第一节点的电平置为第三输入端输入的电平,并适于在所述第一节点浮接时维持所述第一节点的电平;所述第二控制单元包括第一控制模块和第二控制模块;所述第一控制模块连接第四输入端、第五输入端、第一节点和第三节点,适于在所述第三节点的电平为低电平且所述第四输入端的电平为第一控制模块有效电平时开启,将所述第一节点的电平置为所述第五输入端输入的电平;所述第二控制模块,连接第六输入端、第七输入端、第二节点和第三节点,用于在所述第二节点的电平为低电平且所述第六输入端输入的电平为高电平时,将所述第三节点的电平置为高电平;在所述第六输入端输入的电平为低电平时,将所述第三节点的电平置为第七输入端输入的电平;并适于在所述第三节点浮接时,维持所述第三节点的电平;所述输出单元连接移位信号输出端和第八输入端,用于在所述第一节点的电平为低电平时开启,将所述移位信号输出端的电平置为所述第八输入端输入的电平;所述重置单元连接第二节点、移位信号输出端和第九输入端,适于在所述第二节点为低电平时,将所述移位信号输出端的电平置为所述第九输入端输入的电平,并适于在所述第二节点浮接时,维持所述第二节点的电平。
- 如权利要求1所述的移位寄存器单元,其中,所述第一输入端和所述第六输入端为同一输入端,所述输入单元有效电平为低电平。
- 如权利要求1或2的所述的移位寄存器单元,其中,所述第三输入端 和所述八输入端为同一输入端。
- 如权利要求1-3中任一项所述的移位寄存器单元,其中,所述第五输入端和所述第七输入端为同一输入端。
- 如权利要求1-3中任一项所述的移位寄存器单元,其中,所述第九输入端与所述第五输入端或所述第七输入端为同一输入端。
- 如权利要求1-3中任一项所述的移位寄存器单元,其中,所述第五、第七和第九输入端为同一输入端。
- 如权利要求1所述的移位寄存器单元,其中,所述第一控制单元包括第一晶体管和第一电容,所述第一晶体管为P型晶体管,其源极连接所述第三输入端,漏极连接所述第一节点,栅极连接所述第二节点,所述第一电容的第一端连接所述第一节点。
- 如权利要求7所述的移位寄存器单元,其中,所述第一电容的第二端连接所述第三输入端或者所述第八输入端。
- 如权利要求1所述的移位寄存器单元,其中,所述第一控制模块包括第二晶体管和第三晶体管;所述第二晶体管为P型晶体管,其栅极连接所述第三节点,漏极连接所述第五输入端,源极连接第三晶体管的漏极;所述第三晶体管的栅极连接第四输入端,源极连接所述第一节点。
- 如权利要求9所述的移位寄存器单元,其中,所述第三晶体管为P型晶体管。
- 如权利要求1或6所述的移位寄存器单元,其中,所述第二控制模块包括均为P型晶体管的第四晶体管和第五晶体管以及第二电容,所述第四晶体管的栅极连接所述第六输入端,漏极连接所述第三节点,源极连接第七输入端;第五晶体管的栅极连接所述第二节点,漏极连接所述第三节点,源极连接第六输入端;所述第二电容的第一端连接所述第三节点。
- 如权利要求11所述的移位寄存器单元,其中,所述第二电容的第二端连接所述第四输入端。
- 如权利要求1所述的移位寄存器单元,其中,所述输入单元包括P型的第六晶体管,所述第六晶体管的栅极连接第一输入端,源极连接第二输入端, 漏极连接第二节点。
- 如权利要求1或6所述的移位寄存器单元,其中,所述输出单元包括P型的第七晶体管,所述第七晶体管的栅极连接第一节点,源极连接第八输入端,漏极连接所述移位信号输出端。
- 如权利要求1或6所述的移位寄存器单元,其中,所述重置单元包括一个P型的第八晶体管和第三电容,所述第八晶体管的栅极连接第二节点,源极连接所述移位信号输出端,漏极连接所述第九输入端,所述第三电容的第一端连接所述第二节点。
- 如权利要求15所述的移位寄存器单元,其中,所述第三电容的第二端连接所述移位信号输出输入端。
- 一种驱动如权利要求1-16中任一项所述的移位寄存器单元的方法,包括:在第五输入端、第七输入端和第九输入端输入低电平,在第三输入端和第八输入端输入高电平;在第一输入端、第六输入端、第四输入端均输入时钟信号;且在第一输入端输入的时钟信号为输入单元有效电平时,在所述第四输入端输入的时钟信号为第一控制模块无效电平,在第六输入端输入的时钟信号为低电平;在第四输入端输入的时钟信号为第一控制模块有效电平时,在第一输入端输入的时钟信号为输入单元无效电平,在第六输入端输入的时钟信号为高电平;第一输入端输入的时钟信号中输入单元有效电平与第六输入端输入的时钟信号的低电平同步,且与在第四输入端输入的时钟信号中的第一控制模块有效电平在时间上不重叠也不接续;在第一输入端输入的时钟信号为输入单元有效电平时,开始在第二输入端输入高电平的移位脉冲信号;在开始输入高电平的移位脉冲之后在第一输入端输入的时钟信号处于第N+1个输入单元无效电平时,停止在第二输入端输入高电平的移位脉冲信号;其中N为大于等于1的任意整数。
- 根据权利要求17所述的方法,其中输入单元有效电平为低电平,第一控制模块有效电平为低电平。
- 一种栅极驱动电路,包括多个级联的如权利要求1-16任一项所述的移位寄存器单元,其中,除了最后一级和第一级的任意一级移位寄存器单元,移位信号输入端与上一级移位寄存器单元的移位信号输出端相连,而移位信号输 出端则与下一级移位寄存器单元的移位信号输入端相连,且移位信号输出端还与上一级移位寄存器单元的复位控制信号输入端相连,第一级移位寄存器单元的移位信号输入端连接一起始信号。
- 一种显示装置,包括如权利要求19所述的栅极驱动电路。
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CN105632564B (zh) * | 2016-01-08 | 2019-06-21 | 京东方科技集团股份有限公司 | 一种移位寄存器、栅极集成驱动电路及显示装置 |
TWI625718B (zh) * | 2016-10-04 | 2018-06-01 | 創王光電股份有限公司 | 高穩定性的脈衝寬度可調式移位暫存器 |
CN107657918B (zh) * | 2017-09-29 | 2019-10-01 | 上海天马微电子有限公司 | 发光控制信号生成电路、其驱动方法及装置 |
CN110197697B (zh) * | 2018-02-24 | 2021-02-26 | 京东方科技集团股份有限公司 | 移位寄存器、栅极驱动电路以及显示设备 |
CN109616056A (zh) | 2018-08-24 | 2019-04-12 | 京东方科技集团股份有限公司 | 移位寄存器及其驱动方法、栅极驱动电路和显示装置 |
CN108877662B (zh) * | 2018-09-13 | 2020-03-31 | 合肥鑫晟光电科技有限公司 | 栅极驱动电路及其控制方法、显示装置 |
CN113823640A (zh) | 2020-05-11 | 2021-12-21 | 京东方科技集团股份有限公司 | 显示基板和显示装置 |
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