WO2017012254A1 - 阵列基板行驱动电路单元、驱动电路和显示面板 - Google Patents
阵列基板行驱动电路单元、驱动电路和显示面板 Download PDFInfo
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- WO2017012254A1 WO2017012254A1 PCT/CN2015/097114 CN2015097114W WO2017012254A1 WO 2017012254 A1 WO2017012254 A1 WO 2017012254A1 CN 2015097114 W CN2015097114 W CN 2015097114W WO 2017012254 A1 WO2017012254 A1 WO 2017012254A1
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- 230000005284 excitation Effects 0.000 claims description 90
- 239000000758 substrate Substances 0.000 claims description 75
- 230000005540 biological transmission Effects 0.000 claims description 24
- 239000000872 buffer Substances 0.000 claims description 13
- 230000002441 reversible effect Effects 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 7
- 230000003139 buffering effect Effects 0.000 claims description 5
- 230000000295 complement effect Effects 0.000 claims description 4
- 230000003111 delayed effect Effects 0.000 claims description 3
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 10
- 230000006870 function Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0283—Arrangement of drivers for different directions of scanning
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
Definitions
- the present invention relates to the field of display technologies, and in particular, to an array substrate row driving circuit unit. Further, the present invention relates to a driving circuit including the array substrate row driving circuit unit. Still further, the present invention relates to a display panel including the drive circuit.
- the manufacture of the existing display usually adopts a design of a Gate Driver on Array (GOA) in which a gate switching circuit of a Thin Film Transistor (TFT) is integrated on an array substrate of a display panel.
- GAA Gate Driver on Array
- TFT Thin Film Transistor
- CK and CKB are clock signals that are inverted with respect to each other
- CN and CNB are complementary DC levels for controlling the direction of positive and negative sweep
- STV_N-1 and STV_N+1 are inputs for positive and negative sweep, respectively.
- the signal, STV_N is the generated intermediate scan signal
- OUT_1 and OUT_2 are gate drive pulses supplied to different rows of pixels.
- An object of the present invention is to provide an array substrate row driving circuit unit capable of outputting gate driving pulses for two rows of pixels, thereby reducing the number of required GOA cells, and thus reducing the frame area to be occupied. Further, another object of the present invention is to provide a driving circuit including the array substrate row driving circuit unit. Further, it is still another object of the present invention to provide a display panel including the driving circuit.
- an array substrate row driving circuit unit comprising: a first input terminal for receiving an excitation pulse of a current stage; a second input terminal for receiving a first additional clock signal; Receiving a third input of the second additional clock signal, the second additional clock signal being an inverted version of the first additional clock signal; a fourth input for receiving the first clock signal; for receiving the second a fifth input terminal of the clock signal, the second clock signal being an inverted version of the first clock signal; a first output terminal for outputting a secondary excitation pulse; and a first output signal for outputting a first gate line driving pulse a first stage output terminal; a second local stage output terminal for outputting a second gate line driving pulse; an array substrate row driving register module having a shift register unit; and an array substrate row driving output module having a digital logic circuit Wherein the first stage excitation pulse, the first additional clock signal and the first clock signal are synchronized, and the width of the current stage excitation pulse is equal to the first additional clock One period of the number
- the digital logic circuit can include: an AND gate, one of its two inputs being provided with the current stage excitation pulse, and the other input being provided with the second additional clock signal; a NAND gate having one input connected to the output of the AND gate, and the other input being provided with the first clock signal; the first NOT gate, the input An input terminal is connected to the output of the first NAND gate; a second NAND gate, one input terminal is connected to the output end of the AND gate, and the other input terminal is provided with the second clock signal; a second NOT gate having an input coupled to the output of the second NAND gate; wherein an output signal of the first NOT gate is routed to the first local output as the first gate Driving a pulse, and the output signal of the second NOT gate is routed to the second local stage output as the second gate line driving pulse.
- the digital logic circuit may further include: a first buffer circuit for buffering the first gate line drive pulse before routing it to the first stage output for output And a second buffer circuit for buffering the second gate line drive pulse before routing it to the second stage output for output.
- the first buffer circuit may include an even number of NOT gates connected in series with each other
- the second buffer circuit may include an even number of NOT gates connected in series with each other.
- the shift register unit may include: a third NOT gate whose input terminal is provided with the first additional clock signal; a first tri-state NOT gate whose input terminal is provided with the current-level excitation a pulse having a first control terminal coupled to the input of the third NOT gate and a second control terminal coupled to the output of the third NOT gate; a second tri-state NOT gate having an output coupled to the output An output of the first three-state gate, a first control end of which is coupled to an output of the third NOT gate, and a second control end of which is coupled to an input of the third NOT gate; and a fourth non- a gate having an input coupled to the output of the second tri-state NOT gate, an output coupled to the input of the second tri-state NOT gate, and an output signal thereof routed to the first output as The secondary excitation pulse.
- the array substrate row driving circuit unit may further include a scanning direction control module, wherein the scanning direction control module may include: a sixth input end for receiving a positive sweep excitation pulse; a seventh input end of the sweep excitation pulse; a first scan direction control end to which the first DC level is applied; a second scan direction control end to which the second DC level is applied, the second DC level and the first DC level Complementary; a second output coupled to the first input; and an analog switch that, under control of the first DC level and the second DC level, the positive sweep excitation pulse and the One of the anti-sweep excitation pulses is selectively routed to the second output as the current stage excitation pulse.
- the scanning direction control module may include: a sixth input end for receiving a positive sweep excitation pulse; a seventh input end of the sweep excitation pulse; a first scan direction control end to which the first DC level is applied; a second scan direction control end to which the second DC level is applied, the second DC level and the first DC level Complementary; a second output coupled to
- the analog switch may include a first transmission gate and a second transmission gate, the positive sweep excitation pulse being provided to an input end of the first transmission gate, the first a DC level is applied to the first control terminal of the first transmission gate, the second DC level is applied to a second control terminal of the first transmission gate, and an output signal of the first transmission gate is routed To the second output terminal as the current stage excitation pulse, the reverse sweep excitation pulse is supplied to an input end of the second transmission gate, and the second DC level is applied to the second transmission gate a first control terminal, the first DC level is applied to a second control end of the second transmission gate, and an output signal of the second transmission gate is routed to the second output terminal as the current level excitation pulse.
- the array substrate row driver circuit unit may be fabricated based on a CMOS or NMOS process.
- an array substrate row driving circuit comprising at least two cascaded array substrate row driving circuit units as described in the first aspect of the invention, wherein the array substrate
- the row driving circuit unit does not include the scanning direction control module, the first output end of each array substrate row driving circuit unit is connected to the next-level array substrate row except for the last-stage array substrate row driving circuit unit.
- each of the array substrate rows except the first-level array substrate row driving circuit unit includes the scanning direction control module, each of the array substrate rows except the first-level array substrate row driving circuit unit
- the sixth input end of the driving circuit unit is connected to the first output end of the row driving circuit unit of the upper array substrate, and the seventh row driving circuit unit of each array substrate except the last one array substrate driving circuit unit
- the input terminal is connected to the first output end of the row driving circuit unit of the next-stage array substrate.
- a display panel comprising the array substrate row driving circuit according to the second aspect of the invention.
- the present invention is based on the idea of providing a GOA circuit that occupies a smaller area than the prior art.
- Two sets of clock signals having different frequencies and corresponding logic circuits are introduced, wherein a low frequency clock is used to drive the GOA shift register unit, and a high frequency clock is used to drive the GOA output circuit so that a single GOA unit can output for two
- the gate drive pulses of the row pixels reduce the number of GOA circuit cells required.
- Figure 1 illustrates a conventional GOA circuit schematic
- FIG. 2 schematically illustrates a block diagram of a GOA circuit unit in accordance with one embodiment of the present invention
- FIG. 3 shows a timing diagram for a GOA circuit unit in accordance with an embodiment of the present invention
- FIG. 4 schematically illustrates a GOA circuit constructed by cascading GOA circuit elements as shown in Figure 2;
- Figure 5 illustrates a schematic diagram of an implementation of a GOA circuit in accordance with an embodiment of the invention
- Figure 6 schematically illustrates a block diagram of a GOA circuit unit in accordance with another embodiment of the present invention.
- FIG. 7 schematically illustrates a GOA circuit constructed by cascading the GOA circuit unit 200 as shown in FIG. 5;
- Figure 8 illustrates a schematic diagram of an implementation of a GOA circuit in accordance with another embodiment of the invention.
- FIG. 2 schematically illustrates a block diagram of a GOA circuit unit 100 in accordance with one embodiment of the present invention.
- the GOA circuit unit 100 operates under the driving of the current stage excitation pulse inxtpls, the first additional clock signal CKK, the second additional clock signal CKKB, the first clock signal CK, and the second clock signal CKB, which is the same as the conventional one shown in FIG.
- the GOA circuit unit is similar except that the GOA circuit unit 100 does not have a reverse scan function, and thus the scan direction control circuit and the corresponding DC control levels CN, CNB are not provided.
- the GOA circuit unit 100 includes a first input for receiving the excitation pulse inxtpls of the current stage, a second input for receiving the first additional clock signal CKK, and a third for receiving the second additional clock signal CKKB.
- the second additional clock signal CKKB is an inverted version of the first additional clock signal CKK
- the second clock signal CKB is an inverted version of the first clock signal CK.
- FIG. 3 shows a timing diagram for the GOA circuit unit 100 in accordance with an embodiment of the present invention.
- two sets are introduced that are different The frequency clock signals CKK/CKKB and CK/CKB, wherein the frequency of CCK/CKKB is half of the frequency of CK/CKB; in other words, the period of CKK/CKKB is twice the period of CK/CKB.
- the current excitation pulse inxtpls, the additional clock signal CKK/CKKB and the clock signal CK/CKB are synchronized, the width of the excitation pulse inxtpls of the current stage is equal to one cycle of the first additional clock signal CKK, and the first gate line driving pulse The widths of the OUT_1 and second gate line driving pulses OUT_2 are both equal to half of the period of the first clock signal CK.
- the hardware description language HDL
- the electronic design automation (EDA) tool can then be used to convert to a modular combination of actual circuits represented by a gate-level circuit netlist. Then, the netlist can be converted into a specific circuit structure by using an application specific integrated circuit ASIC or a field programmable gate array FPGA automatic place and route tool.
- the GOA circuit unit 100 may include an array substrate row drive registration module 110 and an array substrate row drive output module 120.
- the array substrate row drive registration module 110 may have a shift register unit, wherein the current stage excitation pulse inxtpls and the first additional clock signal CKK are supplied to the shift register unit such that the secondary excitation pulse STV_N is output at the first output terminal .
- the secondary excitation pulse STV_N is a delayed version of the half cycle of the shifted first additional clock signal CKK of the current stage excitation pulse inxtpls.
- the array substrate row driving output module 120 may have a digital logic circuit, wherein the current stage excitation pulse inxtpls, the second additional clock signal CKKB, the first clock signal CK, and the second clock signal CKB are supplied to the digital logic circuit such that only The first gate line driving pulse OUT_1 is outputted at the first local stage output terminal and the second gate line driving pulse OUT_2 is outputted at the second local stage output terminal during the first half pulse width of the current stage excitation pulse inxtpls.
- the first gate line driving pulse OUT_1 corresponds in time to the first half cycle of the first clock signal CK
- the second gate line driving pulse OUT_2 corresponds in time to the second half cycle of the second clock signal CKB.
- gate drive pulses OUT_1 and OUT_2 for adjacent two pixel rows can be provided by one GOA circuit unit 100.
- Fig. 4 schematically illustrates a GOA circuit constructed by cascading the GOA circuit unit 100 as shown in Fig. 2, in which only two GOA circuit units 100 are shown, and the two GOA units 100 are output in addition to the present stage.
- the first output of the first stage GOA circuit unit 100 (which outputs the secondary excitation pulse STV_N) is coupled to the second stage GOA
- the first input of the way unit 100 (which receives the STV_N from the first stage as the present stage excitation pulse inxtpls), and so on.
- the first output of each GOA circuit unit 100 is connected to the first input of the next stage array substrate row driver circuit unit.
- the corresponding gate drive pulses OUT_1, OUT_2, OUT_3, OUT_4, ..., OUT_n can be sequentially supplied to the respective pixel rows.
- FIG. 5 illustrates a schematic diagram of an implementation of a GOA circuit in which only two cascaded GOA circuit units are shown, in accordance with an embodiment of the invention.
- one GOA circuit unit includes an array substrate row drive register module 110 and an array substrate row drive output module 120.
- the array substrate row drive output module 120 includes digital logic circuitry for generating two gate drive pulses in accordance with the timing relationships previously described with reference to FIG.
- the digital logic circuit includes an AND gate A1, a first NAND gate AN1, a first NOT gate N1, a second NAND gate AN2, and a second NOT gate N2.
- One of the two inputs of the AND gate A1 is supplied with the own stage excitation pulse inxtpls, and the other is supplied with the second additional clock signal CKKB.
- One input of the first NAND gate AN1 is connected to the output of the AND gate A1, and the other input is supplied with the first clock signal CK.
- the input of the first NOT gate N1 is connected to the output of the first NAND gate AN1.
- One input of the second NAND gate AN2 is connected to the output of the AND gate A1, and the other input is supplied with the second clock signal CKB.
- the input of the second NOT gate N2 is connected to the output of the second NAND gate AN2.
- the output signal of the first NOT gate N1 may be routed to the first local stage output as the first gate line driving pulse OUT_1, and the output signal of the second NOT gate N2 may be routed to the second local stage output as the second gate The line drives the pulse OUT_2.
- the digital logic circuit may further include a first buffer circuit for buffering the first gate line driving pulse before routing it to the first local stage output for output, and for A second buffer circuit that buffers the second gate line drive pulse before routing it to the second stage output for output.
- the first buffer circuit includes an even number of NOT gates connected in series with each other
- the second buffer circuit includes an even number of NOT gates connected in series with each other.
- the array substrate row drive registration module 110 includes a shift register unit for generating a secondary excitation pulse in accordance with the timing relationship previously described with reference to FIG.
- the shift register unit includes a third NOT gate N3, a first tri-state NOT gate TN1, a second tri-state NOT gate TN2, and a fourth NOT gate N4.
- the input of the third NOT gate N3 is provided with the first additional clock letter No. CKK.
- the input end of the first tri-state NOT gate TN1 is supplied with the excitation pulse inxtpls of the current stage, the first control terminal thereof is connected to the input terminal of the third NOT gate N3, and the second control terminal thereof is connected to the output terminal of the third NOT gate N3. .
- the output of the second tri-state NOT gate TN2 is connected to the output of the first tri-state NOT gate TN1, the first control terminal thereof is connected to the output terminal of the third NOT gate N3, and the second control terminal thereof is connected to the third non-gate The input of the door N3.
- the input end of the fourth NOT gate N4 is connected to the output end of the second tri-state NOT gate TN2, the output end thereof is connected to the input end of the second tri-state NOT gate TN2, and the output signal thereof is routed to the array substrate row drive registration module.
- the first output of 110 acts as a secondary excitation pulse STV_N.
- the first three-state NOT gate TN1 of the shift register unit is turned off, so that inxtpls cannot enter the bistable circuit composed of the second three-state NOT gate TN2 and the fourth NOT gate N4, but is directly input to the AND gate together with the CKKB.
- the output of the AND gate A1 is a high level, and the high level is respectively input to one input terminal of each of the two NAND gates AN1, AN2, and the other input terminals of the two NAND gates AN1, AN2 CK and CKB are provided separately.
- CK is high and CKB is low, making OUT_1 high and OUT_2 low.
- CK is low and CKB is high, making OUT_1 low and OUT_1 high.
- inxtpls remains high, CCK is high, and CKKB is low.
- the first three-state NOT gate TN1 of the shift register unit is turned on, and the second three-state NOT gate TN2 is turned off, so that the bistable circuit does not operate.
- the second half of the inxtpls pulse is routed through the first three-state NOT gate TN1 and the fourth NOT gate N4 to the first output, and the output is input to the high level signal of the next-stage GOA unit (ie, the STV_N pulse
- the first half of the cycle will enable the next stage GOA unit to generate two gate drive pulses OUT_3/OUT_4).
- CKKB since CKKB is low, the output of the AND gate A1 is low, so that OUT_1/OUT_2 is kept low regardless of whether CK/CKB is high.
- inxtpls goes low, CCK is low, and CKKB is high.
- the first three-state NOT gate TN1 of the shift register unit is turned off, and the bistable circuit operates to latch the high level of the previous time therein as the second half of the STV_N pulse.
- OUT_1/OUT_2 is low regardless of the CK/CKB signal.
- inxtpls is still low, CCK is high, and CKKB is low.
- the first three-state NOT gate TN1 of the shift register unit is turned on, and the second three-state NOT gate TN2 is turned off, so that the bistable circuit does not operate.
- the low level signal of inxtpls pulls STV_N low to low level via the first three-state NOT gate TN1 and the fourth NOT gate N4. At this time, the OUT_1/OUT_2 output remains low regardless of the CK/CKB signal.
- STV_N and OUT_1/OUT_2 remain at a low level.
- Each level of GOA operates in accordance with the above process to complete the shift of the scan excitation pulse and the output of the drive pulse of the stage.
- FIG. 6 schematically illustrates a block diagram of a GOA circuit unit 200 in accordance with another embodiment of the present invention.
- the GOA circuit unit 200 may further include a scan direction control module 130 in addition to the array substrate row drive register module 110 and the array substrate row drive output module 120.
- the scan direction control module 130 includes a sixth input for receiving the positive sweep excitation pulse STV_N-1, a seventh input for receiving the reverse sweep excitation pulse STV_N+1, and a first applied first DC level CN
- the second DC level CNB is complementary to the first DC level CN.
- the analog switch selectively routes one of the positive sweep excitation pulse STV_N-1 and the reverse sweep excitation pulse STV_N+1 to the second output terminal as the current stage excitation under the control of the first DC level CN and the second DC level CNB.
- Pulse inxtpls For example, when CN is high and CNB is low, the analog switch routes the positive sweep excitation pulse STV_N-1 to the second output as the current excitation pulse inxtpls to perform forward scanning; otherwise, when CN is low When the CNB is high, the analog switch routes the anti-sweep excitation pulse STV_N+1 to the second output terminal as the current excitation pulse inxtpls to perform reverse scanning.
- Fig. 7 schematically illustrates a GOA circuit constructed by cascading the GOA circuit unit 200 as shown in Fig. 6, in which only two GOA circuit units 200 are shown, and the two GOA units 200 are output in addition to the present stage.
- the first output of the first stage GOA circuit unit 200 which outputs the secondary excitation pulse STV_N in the case of forward scanning
- the sixth input of the second stage GOA circuit unit 200 which is In the case of forward scanning, STV_N from the first stage is received as the current stage excitation pulse inxtpls
- the first output of the second stage GOA circuit unit 200 which outputs the secondary excitation pulse STV_N in the case of reverse scanning
- Connected to a seventh input of the first stage GOA circuit unit 200 its In the case of reverse scanning, STV_N from the second stage is received as the current excitation pulse inxtpls
- each array substrate row driver circuit unit in addition to the first-stage array substrate row driver circuit unit, the sixth input terminal of each array substrate row driver circuit unit is connected to the first output terminal of the upper-order array substrate row driver circuit unit, and except for the last stage In addition to the array substrate row driving circuit unit, the seventh input terminal of each array substrate row driving circuit unit is connected to the first output terminal of the next-stage array substrate row driving circuit unit.
- FIG. 8 illustrates a schematic diagram of an implementation of a GOA circuit in which only two cascaded GOA circuit units are shown, in accordance with another embodiment of the invention.
- one GOA circuit unit includes an array substrate row drive registration module 110, an array substrate row drive output module 120, and an optional scan direction control module 130.
- the array substrate row drive registration module 110 and the array substrate row drive output module 120 illustrated in FIG. 8 are the same as those previously described, and will not be described in detail herein.
- the optional scan direction control module 130 includes means for selecting one of the positive sweep excitation pulse STV_N-1 and the reverse sweep excitation pulse STV_N+1 under the control of the first DC level CN and the second DC level CNB.
- the analog switch is routed to the second output.
- the analog switch includes a first transmission gate TG1 and a second transmission gate TG2.
- the positive sweep excitation pulse STV_N-1 is supplied to the input terminal of the first transfer gate TG1, the first DC level CN is applied to the first control terminal of the first transfer gate TG1, and the second DC level CNB is applied to the first transfer gate
- the second control terminal of TG1 and the output signal of the first transmission gate TG1 is routed to the second output of the scanning direction control module 130 as the current excitation pulse inxtpls.
- the reverse sweep excitation pulse STV_N+1 is supplied to the input terminal of the second transfer gate TG2, the second DC level CNB is applied to the first control terminal of the second transfer gate TG2, and the first DC level CN is applied to the second transfer gate At the second control end of TG2, the output signal of the second transmission gate TG2 is routed to the second output of the scanning direction control module 130 as the current excitation pulse inxtpls.
- the GOA circuit of FIG. 8 will be described in detail below in conjunction with the signal timing shown in FIG. operating. Assuming that the first DC level CN is at a high level, the second DC level CNB is at a low level, that is, the GOA circuit operates in a forward scan mode.
- CK is high and CKB is low, making OUT_1 high and OUT_2 low.
- CK is low and CKB is high, making OUT_1 low and OUT_1 high.
- STV_N-1 remains at a high level, CCK is at a high level, and CKKB is at a low level.
- the first three-state NOT gate TN1 of the shift register unit is turned on, and the second three-state NOT gate TN2 is turned off, so that the bistable circuit does not operate.
- the second half of the STV_N-1 pulse is routed through the first three-state NOT gate TN1 and the fourth NOT gate N4 to the first output, and the output is input to the high-level signal of the next-stage GOA unit (ie, STV_N The first half of the pulse, which will enable the next stage of the GOA unit to generate two gate drive pulses OUT_3/OUT_4).
- STV_N the output of the AND gate A1 is low, so that OUT_1/OUT_2 is kept low regardless of whether CK/CKB is high.
- STV_N-1 is still low, CCK is high, and CKKB is low.
- the first three-state NOT gate TN1 of the shift register unit is turned on, and the second three-state NOT gate TN2 is turned off, so that the bistable circuit does not operate.
- the low level signal of STV_N-1 pulls STV_N low to the low level via the first three-state NOT gate TN1 and the fourth NOT gate N4. At this time, the OUT_1/OUT_2 output remains low regardless of the CK/CKB signal.
- STV_N and OUT_1/OUT_2 remain at a low level.
- Each level of GOA operates in accordance with the above process to complete the shift of the scan excitation pulse and the output of the drive pulse of the stage.
- circuit configurations shown in Figures 5 and 8 are merely exemplary.
- different gate structures can be obtained based on Boolean algebraic formulas.
- the functions of the digital logic circuit of the array substrate row drive output module 120 illustrated in FIGS. 5 and 8 can be expressed as:
- each Boolean algebra expression can represent a specific gate structure. Therefore, instead of the gate circuit structure as illustrated in FIGS. 5 and 8, it is also possible to generate the first gate line drive pulse OUT_1 using, for example, a digital logic circuit composed of a NAND gate, a NOT gate, and a NOR gate. which is, Such variations are known to those skilled in the art and will not be described in detail herein.
- the previously described GOA circuit units 100, 200 may be fabricated based on a CMOS process. In an alternate embodiment, the previously described GOA circuit units 100, 200 may be fabricated based on an NMOS process. In the latter case, the number of transistors can be further reduced, resulting in a further reduced GOA footprint.
- a display panel comprising the GOA circuit described above, the GOA circuit comprising a plurality of cascaded GOA circuit units 100 or 200.
- the display panel can be applied to any product or component having a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, a tablet computer, or the like.
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Abstract
Description
Claims (10)
- 一种阵列基板行驱动电路单元,包括:用于接收本级激励脉冲的第一输入端;用于接收第一附加时钟信号的第二输入端;用于接收第二附加时钟信号的第三输入端,所述第二附加时钟信号是所述第一附加时钟信号的反相版本;用于接收第一时钟信号的第四输入端;用于接收第二时钟信号的第五输入端,所述第二时钟信号是所述第一时钟信号的反相版本;用于输出次级激励脉冲的第一输出端;用于输出第一栅线驱动脉冲的第一本级输出端;用于输出第二栅线驱动脉冲的第二本级输出端;阵列基板行驱动寄存模块,其具有移位寄存器单元;以及阵列基板行驱动输出模块,其具有数字逻辑电路;其中,所述本级激励脉冲、所述第一附加时钟信号和所述第一时钟信号是同步的,所述本级激励脉冲的宽度等于所述第一附加时钟信号的一个周期,所述第一附加时钟信号的周期是所述第一时钟信号的周期的两倍,并且,所述第一栅线驱动脉冲和所述第二栅线驱动脉冲的宽度均等于所述第一时钟信号的周期的一半;其中,所述本级激励脉冲和所述第一附加时钟信号被提供给所述移位寄存器单元,使得在所述第一输出端输出所述次级激励脉冲,所述次级激励脉冲是所述本级激励脉冲的被移位所述第一附加时钟信号的半个周期的延迟版本;并且其中,所述本级激励脉冲、所述第二附加时钟信号、所述第一时钟信号和所述第二时钟信号被提供给所述数字逻辑电路,使得仅在所述本级激励脉冲的前半个脉宽期间在所述第一本级输出端输出与所述第一时钟信号的前半个周期时序上对应的所述第一栅线驱动脉冲,并且在所述第二本级输出端输出与所述第二时钟信号的后半个周期时序上对应的所述第二栅线驱动脉冲。
- 根据权利要求1所述的阵列基板行驱动电路单元,其中,所述数字逻辑电路包括:与门,其两个输入端之一被提供所述本级激励脉冲,并且另一个输入端被提供所述第二附加时钟信号;第一与非门,其一个输入端连接到所述与门的输出端,并且另一个输入端被提供所述第一时钟信号;第一非门,其输入端连接到所述第一与非门的输出端;第二与非门,其一个输入端连接到所述与门的输出端,并且另一个输入端被提供所述第二时钟信号;以及第二非门,其输入端连接到所述第二与非门的输出端;其中,所述第一非门的输出信号被路由到所述第一本级输出端作为所述第一栅线驱动脉冲,并且所述第二非门的输出信号被路由到所述第二本级输出端作为所述第二栅线驱动脉冲。
- 根据权利要求1所述的阵列基板行驱动电路单元,其中,所述数字逻辑电路还包括:第一缓冲电路,用于在将所述第一栅线驱动脉冲路由到所述第一本级输出端以供输出之前对其进行缓冲;以及第二缓冲电路,用于在将所述第二栅线驱动脉冲路由到所述第二本级输出端以供输出之前对其进行缓冲。
- 根据权利要求3所述的阵列基板行驱动电路单元,其中,所述第一缓冲电路包括相互串联的偶数个非门,并且所述第二缓冲电路包括相互串联的偶数个非门。
- 根据权利要求1所述的阵列基板行驱动电路单元,其中,所述移位寄存器单元包括:第三非门,其输入端被提供所述第一附加时钟信号;第一三态非门,其输入端被提供所述本级激励脉冲,其第一控制端连接到所述第三非门的输入端,并且其第二控制端连接到所述第三非门的输出端;第二三态非门,其输出端连接到所述第一三态非门的输出端,其第一控制端连接到所述第三非门的输出端,并且其第二控制端连接到所述第三非门的输入端;以及第四非门,其输入端连接到所述第二三态非门的输出端,其输出端连接到所述第二三态非门的输入端,并且其输出信号被路由到所述第一输出端作为所述次级激励脉冲。
- 根据权利要求1所述的阵列基板行驱动电路单元,还包括扫描方向控制模块,其中,所述扫描方向控制模块包括:用于接收正扫激励脉冲的第六输入端;用于接收反扫激励脉冲的第七输入端;被施加第一直流电平的第一扫描方向控制端;被施加第二直流电平的第二扫描方向控制端,所述第二直流电平与所述第一直流电平是互补的;被连接到所述第一输入端的第二输出端;以及模拟开关,其在所述第一直流电平和所述第二直流电平的控制下,将所述正扫激励脉冲和所述反扫激励脉冲中的一个选择性地路由到所述第二输出端作为所述本级激励脉冲。
- 根据权利要求6所述的阵列基板行驱动电路单元,其中,所述模拟开关包括第一传输门和第二传输门,所述正扫激励脉冲被提供给所述第一传输门的输入端,所述第一直流电平被施加到所述第一传输门的第一控制端,所述第二直流电平被施加到所述第一传输门的第二控制端,所述第一传输门的输出信号被路由到所述第二输出端作为所述本级激励脉冲,所述反扫激励脉冲被提供给所述第二传输门的输入端,所述第二直流电平被施加到所述第二传输门的第一控制端,所述第一直流电平被施加到所述第二传输门的第二控制端,所述第二传输门的输出信号被路由到所述第二输出端作为所述本级激励脉冲。
- 根据权利要求1所述的阵列基板行驱动电路单元,其中,所述阵列基板行驱动电路单元是基于CMOS或NMOS工艺制造的。
- 一种阵列基板行驱动电路,包括至少两个级联的根据权利要求1-7中任一项所述的阵列基板行驱动电路单元,其中,在所述阵列基板行驱动电路单元不包括所述扫描方向控制模块的情况下,除最后一级阵列基板行驱动电路单元之外,每一个阵列基板行驱动电路单元的第一输出端连接到下一级阵列基板行驱动电路单元的第一输入端;并且其中,在所述阵列基板行驱动电路单元包括所述扫描方向控制模块的情况下,除第一级阵列基板行驱动电路单元之外,每一个阵列基板行驱动电路单元的第六输入端连接到上一级阵列基板行驱动电路单元的第一输出端,并且除最后一级阵列基板行驱动电路单元之外, 每一个阵列基板行驱动电路单元的第七输入端连接到下一级阵列基板行驱动电路单元的第一输出端。
- 一种显示面板,包括根据权利要求9所述的阵列基板行驱动电路。
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CN112799465A (zh) * | 2019-10-28 | 2021-05-14 | 京东方科技集团股份有限公司 | 控制信号发生器及其驱动方法 |
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CN105609077B (zh) * | 2016-01-28 | 2018-03-30 | 深圳市华星光电技术有限公司 | 像素驱动电路 |
CN106847223B (zh) * | 2017-03-29 | 2019-03-22 | 武汉华星光电技术有限公司 | 扫描驱动电路及液晶显示面板 |
CN109427307B (zh) | 2017-08-21 | 2020-06-30 | 京东方科技集团股份有限公司 | 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置 |
CN107424582B (zh) * | 2017-09-27 | 2019-08-30 | 武汉华星光电技术有限公司 | 扫描驱动电路及显示装置 |
CN107767809B (zh) * | 2017-11-15 | 2019-11-26 | 鄂尔多斯市源盛光电有限责任公司 | 栅极驱动单元、驱动方法和栅极驱动电路 |
CN109872673B (zh) * | 2019-04-09 | 2022-05-20 | 京东方科技集团股份有限公司 | 栅极驱动单元、栅极驱动方法、栅极驱动电路和显示装置 |
CN113160733B (zh) * | 2020-01-22 | 2023-05-30 | 群创光电股份有限公司 | 电子装置 |
CN113763818B (zh) * | 2021-09-07 | 2023-06-02 | 武汉华星光电技术有限公司 | 显示装置 |
CN117116212B (zh) * | 2023-02-09 | 2024-07-09 | 荣耀终端有限公司 | 阵列栅驱动单元、电路,显示屏和电子设备 |
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US20170200408A1 (en) | 2017-07-13 |
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