WO2016203505A1 - 半導体装置及び診断テスト方法 - Google Patents
半導体装置及び診断テスト方法 Download PDFInfo
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- WO2016203505A1 WO2016203505A1 PCT/JP2015/003047 JP2015003047W WO2016203505A1 WO 2016203505 A1 WO2016203505 A1 WO 2016203505A1 JP 2015003047 W JP2015003047 W JP 2015003047W WO 2016203505 A1 WO2016203505 A1 WO 2016203505A1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3177—Testing of logic operation, e.g. by logic analysers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318555—Control logic
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318544—Scanning methods, algorithms and patterns
- G01R31/318547—Data generators or compressors
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318566—Comparators; Diagnosing the device under test
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318569—Error indication, logging circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318594—Timing aspects
Definitions
- the present invention relates to a semiconductor device and a diagnostic test method, and more particularly to a technique for performing a scan test of a circuit under test.
- a safety mechanism that can detect a single point fault (hereinafter referred to as SPF) that is a failure due to a single failure or a latency fault (hereinafter referred to as LF) that is a failure due to simultaneous occurrence of a plurality of failures, Mounting on a semiconductor device is recognized as one of the countermeasures.
- SPF single point fault
- LF latency fault
- Mounting on a semiconductor device is recognized as one of the countermeasures.
- Patent Document 1 two processors perform the same calculation process, and the calculation results are compared by a comparator to determine whether the calculation results match or not, thereby determining whether the processor is normal.
- a control device for diagnosing this is disclosed.
- this control device further improves the reliability by diagnosing the comparator by BIST (Built-In-Self-Test).
- BIST Busilt-In-Self-Test
- this control device does not disclose a technique that can detect both SPF and LF without requiring a plurality of circuits to be tested, as will be described later.
- the semiconductor device performs the first scan test on the first test control device. It is designed to instruct implementation.
- a semiconductor device with improved reliability can be provided.
- FIG. 1 is a block diagram showing a schematic configuration of a semiconductor device according to an embodiment.
- 1 is a block diagram showing a configuration of a semiconductor device according to a first embodiment.
- FIG. 3 is a block diagram showing an operation of the semiconductor device according to the first embodiment.
- 7 is a block diagram showing a configuration of a semiconductor device according to a modification of the first embodiment.
- FIG. FIG. 6 is a block diagram showing a configuration of a semiconductor device according to a second embodiment.
- FIG. 6 is a block diagram showing a configuration of a semiconductor device according to a third embodiment.
- FIG. 6 is a block diagram showing an operation of a semiconductor device according to a third embodiment.
- FIG. 10 is a block diagram showing a configuration of a semiconductor device according to a fourth embodiment.
- FIG. 10 is a block diagram showing a configuration of a semiconductor device according to a fourth embodiment.
- FIG. 10 is a block diagram showing an operation of a semiconductor device according to a fourth embodiment.
- FIG. 10 is a block diagram showing a configuration of a semiconductor device according to a fifth embodiment.
- FIG. 10 is a block diagram showing a configuration of a semiconductor device according to a sixth embodiment.
- FIG. 10 is a block diagram showing a configuration of a semiconductor device according to a seventh embodiment.
- FIG. 20 is a block diagram showing an operation in the first half of a semiconductor device according to a seventh embodiment.
- FIG. 23 is a block diagram showing the latter half of the operation of the semiconductor device according to the seventh embodiment.
- FIG. 10 is a block diagram showing a configuration of a semiconductor device according to an eighth embodiment.
- FIG. 23 is a block diagram showing an operation in the first half of a semiconductor device according to an eighth embodiment.
- FIG. 24 is a block diagram showing the latter half of the operation of the semiconductor device according to the eighth embodiment.
- FIG. 1 is a block diagram illustrating a semiconductor device that is an outline of a semiconductor device according to an embodiment described later.
- the semiconductor device (1) includes a circuit under test (2), a first test control device (3), a second test control device (4), and a common result determination device (5).
- the circuit under test (2) has a scan chain.
- Each of the first test control device (3) and the second test control device (4) performs a scan test of the circuit under test (2) using the scan chain of the circuit under test (2).
- the common result determination device (5) obtains the test result of the circuit under test (2) obtained by the scan test performed by each of the first test control device (3) and the second test control device (4). judge.
- the second test control device (4) scans the test pattern into the scan chain of the circuit under test (2), operates the circuit under test (2) with the test pattern, and scan chain of the circuit under test (2). Scan out test results from.
- the second test control device (4) outputs the test result to the common result determination device (5).
- the common result determination device (5) determines whether or not a failure has occurred in the circuit under test (2) based on the test result output from the second test control device (4).
- the second test control device (4) performs a scan test of the circuit under test (2).
- the circuit under test (2) instructs the first test control device (3) to perform the scan test after the second test control device (4) performs the scan test of the circuit under test (2).
- the first test control device (3) performs a scan test of the circuit under test (2) in response to a scan test instruction from the circuit under test (2).
- a failure that is, SPF
- a failure that is, LF
- both SPF and LF can be detected, and the reliability of the semiconductor device (1) can be further improved.
- FIG. 2 is a block diagram showing a configuration of the semiconductor device (1A) according to the first embodiment.
- the semiconductor device (1A) includes, as elements for realizing its functions, a CPU (10), a built-in memory (11), an external I / F (interface) (12), a system bus ( 13) and a system control circuit (15).
- the CPU (10), the built-in memory (11), and the external I / F (12) are connected to each other via the system bus (13). Therefore, necessary data is transferred among the CPU (10), the built-in memory (11), and the external I / F (12).
- CPU (10) executes an application program for operating the semiconductor device (1A). Therefore, this application program includes a plurality of instructions for causing the CPU (10) to execute various processes for realizing the functions in the semiconductor device (1A).
- the CPU (10) is an arithmetic circuit that comprehensively controls the semiconductor device (1A) by executing this application program.
- the CPU (10) is described as being a circuit under test (circuit to be tested).
- the CPU (10) has a plurality of scan chains.
- the CPU (10) can make a diagnosis by a scan test using the plurality of scan chains.
- the built-in memory (11) is a storage circuit that stores data used for the CPU (10) to execute the various processes described above. Accordingly, the various data includes, for example, the application program described above.
- the CPU (10) reads data stored in the built-in memory (11) and executes processing based on the read data. Further, the CPU (10) writes the data generated in accordance with the execution of the processing into the built-in memory (11).
- the built-in memory (11) is a volatile memory such as a RAM (Random Access Memory).
- the external I / F (12) is also connected to an external memory (14) disposed outside the semiconductor device (1A).
- the external I / F (12) is a circuit that transmits and receives data between the external memory 14 and a circuit (CPU (10) or the like) connected to the system bus (13). Therefore, the CPU (10) reads data stored in the external memory (14) and writes data to the external memory (14) via the system bus (13) and the external I / F (12). I do.
- External memory (14) is a storage circuit for storing arbitrary data. Data used for the CPU (10) to execute the various processes described above may also be stored in the external memory (14). For example, the application program described above may be stored in advance in the external memory (14). Then, the CPU (10) may be executed after loading the application program stored in the external memory (14) into the built-in memory (11). In other words, the CPU (10) may read data stored in the external memory (14) and execute processing based on the read data. Further, the CPU (10) may write data generated in accordance with the execution of the processing into the external memory (14).
- the external memory (14) is a non-volatile memory such as a ROM (Read Only Memory) or a FLASH memory.
- a plurality of test patterns used for execution of the scan test of the CPU (10) are stored in advance in the internal memory (11) or the external memory (14).
- the system control circuit (15) performs overall control such as activation of the semiconductor device (1A).
- the system control circuit (15) is connected to the CPU (10), the built-in memory (11), and the external I / F (12) via the system bus (13) or a signal line directly connected thereto. Various controls such as reset control are performed.
- the system control circuit (15) is connected to the CPU (10), the built-in memory (11), and the external I / F (12) via a clock signal line (not shown) directly connected. Supply.
- the semiconductor device (1A) includes, as a first test control device (3), a first test control circuit (100), a pattern input circuit (101), a first result compression circuit (206), Expected value storage circuit (103).
- the semiconductor device (1A) includes, as a second test control device (4), a second test control circuit (200), a pattern generation circuit (201), a second result compression circuit (207), A second expected value storage circuit (203) is included.
- the semiconductor device (1A) includes a recursive compression circuit (208), a comparison circuit (209), and a timer (205) as a common result determination device (5).
- the components of the first test control device (3) are as described in the description of the overall configuration.
- the first test control circuit (100) is connected to the CPU (10) via the system bus (13).
- the first test control circuit (100) executes a scan test of the CPU (10) in accordance with a request from the CPU (10).
- the pattern input circuit (101) is connected to the first test control circuit (100) and the system bus (13).
- the pattern input circuit (101) receives a plurality of test patterns from the built-in memory (11) or the external memory (14) via the system bus (13) according to a request from the first test control circuit (100). Read. For example, when this test pattern is stored in the external memory (14) in advance, the CPU (10) transfers from the external memory (14) to the built-in memory (11) after the start of the semiconductor device (1A). May be.
- the pattern input circuit (101) may read the test pattern transferred to the built-in memory (11).
- the pattern input circuit (101) is connected to the CPU (10) via the selection circuit (300).
- the pattern input circuit (101) sequentially supplies the plurality of read test patterns to the plurality of scan chains of the CPU (10) via the selection circuit (300).
- one test pattern is data having the same number of bits as the number of scan chains of the CPU (10).
- One test pattern is input to a plurality of scan chains every one shift cycle (one clock).
- the input circuit (101) expands the test pattern into data having the same number of bits as the number of scan chains of the CPU (10) and inputs the data to the scan chain.
- the first result compression circuit (206) compresses the multi-bit test results output from the plurality of scan chains of the CPU (10) in the spatial axis direction.
- the test result means multi-bit data output from a plurality of scan chains per shift cycle. Therefore, the test result is multi-bit data (for example, several tens to several hundred bits) having the same number of bits as the number of scan chains of the CPU (10).
- the first result compression circuit (206) compresses the multi-bit test result into a 1-bit code by using, for example, a compression circuit in which XOR is configured in a tree shape.
- the first test control device (3) assumes a compression scan test technique.
- the first result compression circuit (206) is connected to the recursive compression circuit (208) via the selection circuit (301).
- the first result compression circuit (206) outputs the test result (the above sign) after compression to the recursive compression circuit (208) via the selection circuit (301).
- the first expected value storage circuit (103) is a first expected value that is an expected value of the code after the test result output from the first result compression circuit (206) is compressed by the recursive compression circuit (208). Is stored.
- first expected values corresponding to a plurality of test patterns stored in the external memory 14 or the built-in memory 11 may be stored in advance. Further, it is stored in advance in the external memory 14 or the built-in memory 11 together with a plurality of test patterns, and after the system control circuit (15) completes the start of the semiconductor device (1A), the first expectation is received from the external memory 14 or the built-in memory 11. The value may be read and written to the first expected value storage circuit (103).
- the first expected value storage circuit (103) is connected to the comparison circuit (209) via the selection circuit (302).
- the first expected value storage circuit (103) outputs the first expected value to the comparison circuit (209) via the selection circuit (302).
- the components of the second test control device (4) are as described in the description of the overall configuration.
- the second test control circuit (200) is connected to the system control circuit (15).
- the second test control circuit (200) executes a scan test of the CPU (10) in accordance with a request from the system control circuit (15).
- the pattern generation circuit (201) is connected to the second test control circuit (200).
- the pattern generation circuit (201) generates (generates) a plurality of test patterns with pseudorandom numbers in accordance with the request of the second test control circuit (200).
- the pattern generation circuit (201) is connected to the CPU (10) via the selection circuit (300).
- the pattern generation circuit (201) sequentially supplies the generated plurality of test patterns to the plurality of scan chains of the CPU (10) via the selection circuit (300).
- the second result compression circuit (207) compresses a plurality of multi-bit test results output from the plurality of scan chains of the CPU (10) in the time axis direction.
- the second result compression circuit (207) compresses all the test results into one multi-bit code by, for example, MISR (Multiple Input signature Register). That is, this code is multi-bit data having the same number of bits as the number of scan chains.
- MISR Multiple Input signature Register
- a test result compressed in the spatial direction by a compression circuit in which the XOR is configured in a tree shape may be used as the input of the MISR. That is, the number of bits of the code may be smaller than the number of scan chains.
- the second test control device (4) assumes the LogicBIST technology.
- the second result compression circuit (207) is connected to the recursive compression circuit (208) via the selection circuit (301).
- the second result compression circuit (207) outputs the test result (the above sign) after compression to the recursive compression circuit (208) via the selection circuit (301).
- the second expected value storage circuit (203) is a second expected value that is an expected value of the code after the test result output from the second result compression circuit (207) is compressed by the recursive compression circuit (208). Is stored.
- the second expected value is generated, for example, according to the test pattern generated by itself by the pattern generation circuit (201), and is stored in the second expected value storage circuit (203).
- the second expected value storage circuit (203) is connected to the comparison circuit (209) via the selection circuit (302).
- the second expected value storage circuit (203) outputs the second expected value to the comparison circuit (209) via the selection circuit (302).
- the memory circuits included in the semiconductor device (1A), such as the first expected value memory circuit (103) and the second expected value memory circuit (203), are determined in advance using a power source and a ground, for example. It is a circuit, a register, a memory, or the like that fixedly indicates the obtained value.
- the memory is, for example, a RAM, a ROM (for example, including a fuse ROM), a FLASH memory, or the like. The same applies to the following description.
- the components of the common result determination device (5) are as described in the description of the overall configuration.
- the recursive compression circuit (208) compresses the test result after compression in the time axis direction.
- the recursive compression circuit (208) performs an XOR operation between the input data and the data stored in itself while circulating the data stored in the recursive compression circuit (208), such as SISR (Single Input signature Register).
- SISR Single Input signature Register
- the operation result is composed of a multi-bit register for storing the result of the calculation.
- the recursive compression circuit (208) is connected to the comparison circuit (209).
- the recursive compression circuit (208) outputs the test result after compression to the comparison circuit (209).
- the comparison circuit (209) is connected to the first expected value storage circuit (103) and the second expected value storage circuit (203) via the selection circuit (302).
- the comparison circuit (209) is also connected to the system control circuit (15).
- the comparison circuit (209) outputs the test result after compression output from the recursive compression circuit (208) and the first expected value storage circuit (103) or the second expected value storage circuit (203). Compare the output with the expected value.
- the comparison circuit (209) notifies an error to the system control circuit (15) when the test result and the expected value do not match. On the other hand, when the test result matches the expected value, the comparison circuit (209) notifies the system control circuit (15) of normality.
- the timer (205) is a circuit that monitors the scan test execution time of each of the first test control circuit (100) and the second test control circuit (200). That is, the timer (205) is a so-called watchdog timer.
- the timer (205) is configured to wait until a predetermined time elapses from the time when the start of the scan test is notified from the first test control circuit (100) or the second test control circuit (200). When the end of the scan test is not notified from the first test control circuit (100) or the second test control circuit (200), an error is notified to the system control circuit (15). According to this, it is possible to detect an abnormality in which the scan test by the first test control circuit (100) and the second test control circuit (200) does not end normally.
- the timer (205) starts from the time when the start of the scan test is notified from the first test control circuit (100) or the second test control circuit (200) until a predetermined time elapses.
- the end of the scan test is notified from the first test control circuit (100) or the second test control circuit (200)
- no error is notified to the system control circuit (15).
- the selection circuit (300) selectively outputs the test pattern output from either the pattern input circuit (101) or the pattern generation circuit (201) to the CPU (10).
- the selection circuit (301) outputs the test result output from one of the first result compression circuit (206) and the second result compression circuit (207) to the recursive compression circuit (208).
- the selection circuit (302) outputs the expected value output from one of the first expected value storage circuit (103) and the second expected value storage circuit (203) to the comparison circuit (209).
- FIG. 3 is a flowchart showing the operation during self-diagnosis of the semiconductor device (1A) according to the first embodiment.
- FIG. 3 shows that each operation event (each processing block) is connected by an arrow, and the operation event is performed in time series according to the direction of the arrow.
- the diamond-shaped operation event represents a conditional branch.
- the downward arrow indicates the branch destination when a normal judgment is made with respect to the action event condition
- the horizontal arrow shows an abnormal judgment with respect to the action event condition. This shows the branching destination when The operation of the semiconductor device (1A) according to the first embodiment will be described by comparing the example of the semiconductor device (1A) shown in FIG. 2 with the operation flow shown in FIG.
- the semiconductor device (1A) periodically performs a diagnosis to detect the SPF by interrupting the processing during normal operation.
- this diagnosis is also referred to as “in-operation diagnosis”.
- the first test control device (3) and the common result determination device (5) are used for the diagnosis during operation. If SPF is not detected, the semiconductor device (1A) resumes normal operation.
- the common result determination device (5) notifies the system control circuit (15) of an error.
- the system control circuit When the start-up diagnosis is started, the system control circuit (15) asserts a diagnosis start signal for instructing the CPU (10) to start diagnosis, and outputs the signal to the second test control circuit (200).
- the second test control circuit (200) starts diagnosis of the CPU (10) in response to the assertion of the diagnosis start signal (S101).
- the second test control circuit (200) selects the second test control device (4) side ("2" side in FIG. 2) side when starting diagnosis, so that the selection circuit (300, 301, 302).
- the selection circuit (300, 301, 302) may be controlled before the system control circuit (15) asserts the diagnosis start signal.
- the second test control circuit (200) when starting the diagnosis, the second test control circuit (200) outputs a start notification signal for notifying the start of the scan test to be performed to the CPU (10) to the timer (205).
- the timer (205) starts measuring the elapsed time from when the start notification signal is notified (S102).
- the timer (205) operates in parallel with the scan test executed by the second test control circuit (200).
- the timer (205) notifies the end of the scan test from the second test control circuit (200)).
- a notification signal for notifying the system control circuit (15) of an error is output (S102: timeout).
- the output of the end notification signal to the timer (205) may be performed when the system control circuit (15) receives a notification signal from the comparison circuit (209) described later.
- a threshold value is stored in advance in a memory circuit (not shown) included in the semiconductor device (1A), and the timer (205) refers to the threshold value stored in the memory circuit.
- the system control circuit (15) may directly control the timer (205).
- the second test control circuit (200) outputs an instruction signal for causing the pattern generation circuit (201) to generate a test pattern in order to start diagnosis of the CPU (10).
- the pattern generation circuit (201) generates a test pattern in response to an instruction signal from the second test control circuit (200).
- a PRPG Pseudo Random Pattern Generator
- LFSR Linear Feedback Backshift Register
- the reason for generating the test pattern in this way is that, in the state where the semiconductor device (1A) is being activated, many modules including the system bus (13) in the semiconductor device (1A) are suspended for the diagnosis. This is because the test pattern cannot be read from the internal memory (11) or the external memory (14) via the system bus (13). For this reason, when the method of holding the test pattern in the memory circuit is adopted, it is necessary to prepare a dedicated memory circuit (for example, a FLASH memory or a ROM) that can be accessed without using the system bus (13). Means are limited.
- a dedicated memory circuit for example, a FLASH memory or a ROM
- the test pattern is read from the built-in memory (11) or the external memory (14) via the system bus (13). There is no need to provide a circuit.
- this method makes it impossible to start the startup diagnosis of the CPU (10) until the diagnosis of the system bus (13) is completed. This is not preferable because the semiconductor device often has a limited time until startup is complete (for example, within 50 msec).
- the startup diagnosis of the CPU (10) can be executed in parallel with the diagnosis of the system bus (13). It is possible to shorten the start-up time of the semiconductor device (1A) and complete the start-up of the semiconductor device (1A) within the time limit.
- the pattern generation circuit (201) sequentially supplies the generated plurality of test patterns to the scan chain of the CPU (10), and executes the scan test of the CPU (10). That is, the CPU (10) performs an operation (capture) based on the test pattern supplied to the scan chain. As a result of this operation, the test results stored in the scan chain are sequentially acquired by the second result compression circuit (207), and all the test results are compressed into one code.
- the second result compression circuit (207) The plurality of test results (codes) are serially output bit by bit to the recursive compression circuit (208).
- the recursive compression circuit (208) recompresses the compressed test result output from the second result compression circuit (207).
- the test result of the size of (number of bits of the multi-bit test result after compression by the second result compression circuit (207) ⁇ 1) is the SISR. It is compressed to the size of the number of stages.
- the recursive compression circuit (208) outputs the test result after compression to the comparison circuit (209).
- the comparison circuit (209) determines that the CPU (10) is normal when the comparison results match (S103: normal). In this case, the comparison circuit (209) outputs a notification signal notifying normality to the system control circuit (15).
- the comparison circuit (209) determines that the CPU (10) is abnormal when the comparison result is inconsistent (S103: abnormal). That is, in this case, LF is detected. In this case, the comparison circuit (209) outputs a notification signal notifying an error to the system control circuit (15).
- the system control circuit (15) When a notification signal for notifying an error is output from the timer (205) or the comparison circuit (209), the system control circuit (15) quickly performs a process of stopping the system in the semiconductor device (1A), and the semiconductor device ( The system in 1A) is stopped (S111). That is, the system control circuit (15) suppresses activation of the semiconductor device (1A).
- the second test control circuit (200) outputs an end notification signal for notifying the end of the scan test to the timer (205) when the scan test ends.
- the first test control circuit (100) starts diagnosis of the CPU (10) in response to the assertion of the diagnosis start signal (S108). Further, the first test control circuit (100) controls the selection circuits (300, 301, 302) so as to select the first test control device (3) side, “1” side in FIG. .
- the selection circuit (300, 301, 302) may be controlled before the CPU (10) asserts the diagnosis start signal.
- the first test control circuit (100) when starting the diagnosis, the first test control circuit (100) outputs a start notification signal for notifying the start of the scan test to be performed to the CPU (10) to the timer (205).
- the timer (205) starts measuring the elapsed time from when the start notification signal is notified (S109).
- the timer (205) operates in parallel with the scan test executed by the first test control circuit (100).
- the scan test test is not completed before the elapsed time to be measured reaches a predetermined threshold value (that is, the timer (205) terminates the end of the scan test from the first test control circuit (100)).
- the timer (205) refers to the threshold value stored in the memory circuit included in the semiconductor device (1A). Further, the threshold value used in the diagnostic during operation may be different from the threshold value used in the startup diagnosis.
- the first test control circuit (100) outputs an instruction signal for instructing input of the test pattern to the pattern input circuit (101) via the system bus (13) in order to start diagnosis of the CPU (10). To do.
- the pattern input circuit (101) acquires a test pattern from the built-in memory (11) or the external memory (14) in response to an instruction signal from the first test control circuit (100).
- test pattern composed of arbitrary values is used in order to achieve a high failure detection rate in a short test time. Since an arbitrary value is used, the amount of data tends to increase. However, when the test pattern is stored in the external memory (14), the area cost of the semiconductor device (1A) can be kept low.
- the pattern input circuit (101) supplies the acquired plurality of test patterns to the scan chain of the CPU (10) and executes a scan test of the CPU (10). That is, the CPU (10) performs an operation (capture) based on the test pattern supplied to the scan chain. As a result of this operation, the test results stored in the scan chain are sequentially acquired by the first result compression circuit (206) and compressed into a 1-bit code.
- the first result compression circuit (206) serially outputs the test result (sign) after compression to the recursive compression circuit (208) bit by bit.
- the recursive compression circuit (208) recompresses the compressed test result (code) output from the first result compression circuit (206).
- the test result of the size of (1 bit test result after compression by the first result compression circuit (206) ⁇ the number thereof) is the number of stages of the SISR. Compressed to the size of The recursive compression circuit (208) outputs the test result after compression to the comparison circuit (209).
- the comparison circuit (209) outputs a notification signal for notifying normality to the system control circuit (15) when the comparison results match.
- a notification signal notifying normality is output from the comparison circuit (209), the system control circuit (15) determines that the CPU (10) is normal (S110: normal).
- the system control circuit (15) When it is determined that the CPU (10) is normal (S110: normal), the system control circuit (15) resets and restarts the CPU (10) (S104). After completing the restart, the CPU (10) resumes the process that was stopped in step S107 described above (S105). Then, after a predetermined time has elapsed (S106: Yes), the CPU (10) executes a process for performing a self-diagnosis again (S107).
- the comparison circuit (209) outputs a notification signal for notifying an error to the system control circuit (15).
- the system control circuit (15) determines that the CPU (10) is abnormal (S110: abnormal). That is, in this case, SPF is detected.
- the system control circuit (15) When it is determined that the CPU (10) is abnormal (S110: abnormal), the system control circuit (15) promptly stops the system in the semiconductor device (1A), and the system in the semiconductor device (1A). Is stopped (S111).
- SPF is a failure due to a single failure, and in the first embodiment, a failure caused by a failure of the CPU (10) corresponds.
- the failure of the CPU (10) is detected by a scan test periodically performed by the first test control device (3) and a result determination by the common result determination device (5). It can be said that the safety (reliability) of the semiconductor device (1A) with respect to the SPF is improved.
- LF is a failure caused by multiple failures occurring at the same time. For example, it is a failure in which an SPF that should be detected by the safety mechanism cannot be detected due to a failure that has occurred in the safety mechanism.
- a failure that occurs due to a failure of the CPU (10) and the common result determination device (5) is applicable. More specifically, the CPU (10) is a module that starts an operation for detecting SPF (hereinafter referred to as in-operation diagnosis), but a failure has occurred in the mechanism that activates the in-operation diagnosis of the CPU (10). If the in-operation diagnosis cannot be started, the failure of the CPU (10) occurring at the same time is overlooked. As a result, improvement in safety is hindered.
- the failure of the CPU (10) is detected by a scan test performed when the semiconductor device (1A) is started up by the second test control device (4) and the common result determination device (5).
- the failure of the common result determination device (5) is functionally diagnosed by an operation for detecting LF (hereinafter referred to as startup diagnosis).
- startup diagnosis an operation for detecting LF
- the recursive compression circuit (208) included in the common result determination device (5) has a multi-bit register that XORs the input data and the own data and also circulates the own value. Therefore, 1-bit inversion greatly changes the result. For this reason, not only the test result output from the second test control device (4) but also the recursive compression circuit (208), when the operation differs from the expected value, the test result appears as a value different from the expected value. Because.
- the erroneous determination of the comparison circuit (209) can be realized by adding a diagnosis of the comparison circuit (209) described later in the startup diagnosis.
- the first test control device (3) is not hindered from improving safety no matter where it fails. For example, even if a failure occurs simultaneously in the pattern input circuit (101) and the CPU (10), the failure is embodied as a mismatch between the final test result generated by the recursive compression circuit (208) and the expected value. Turn into. As a result, an error is notified to the system control circuit (15), and control for shifting the system to a safe state can be performed. That is, if the diagnosis during operation by the CPU (10) is normally performed and the evaluation by the common result determination device (5) is correct, it does not hinder the improvement of safety regardless of the operation during the diagnosis.
- the safety of the semiconductor device (1A) against LF is improved. That is, according to the first embodiment, both SPF and LF can be detected, and the reliability of the semiconductor device (1A) can be further improved.
- the common result determination device (5) having the recursive compression circuit (208) and the comparison circuit (209) detects the SPF of the CPU (10).
- the first embodiment uses the first test control device (3) using a scan test (compression scan) to detect SPF, and also uses the scan test (Logic BIST) to detect LF.
- a second test control device (4) is used.
- a highly safe semiconductor device capable of detecting both SPF and LF can be realized at low cost.
- the scan test of the CPU (10) is performed by the first test control device (3), thereby detecting the SPF without duplicating the CPU (10). Therefore, the cost and cost can be reduced by reducing the area and power consumption required for duplicating the CPU (10).
- a scan test of the CPU (10) is performed by the second test control device (4), and the recursive compression circuit (208) used in common for SPF detection and By making a determination using the result in the comparison circuit (209), the LF of the CPU (10) is detected by a scan test, and the LFs of the recursive compression circuit (208) and the comparison circuit (209) are detected. , Can increase safety.
- circuit under test circuit to be diagnosed
- circuit under test circuit to be diagnosed
- the circuit under test is not limited to the CPU. It can be applied to various processing modules in a semiconductor device that requires high safety.
- FIG. 4 is a flowchart showing an operation during self-diagnosis of the semiconductor device (1A) according to the modification of the first embodiment.
- an operation for diagnosing whether or not the comparison circuit (209) has failed may be added in the startup diagnosis.
- step S112 is added between steps S101 and S102 and step S103 as compared with the operation illustrated in FIG. 3.
- the system control circuit (15) Before instructing the CPU (10) to start diagnosis, the system control circuit (15) asserts a diagnosis start signal for instructing the comparison circuit (209) to start diagnosis, and the second test control circuit (200). Output to.
- the second test control circuit (200) starts diagnosis of the comparison circuit (209) in response to the assertion of the diagnosis start signal (S112).
- step S112 the scan test of the CPU (10) is performed as in step S103, but the second expected value stored in the second expected value storage circuit (203) by the second test control circuit (200). Is a value that intentionally generates an error.
- step S112 when a notification signal for notifying an error is output from the comparison circuit (209), the system control circuit (15) determines that the comparison circuit (209) is normal (S112: normal). In this case, the operation of the semiconductor device (1A) proceeds to step S103.
- the system control circuit (15) determines that the CPU (10) is abnormal (S112: abnormal). In this case, the system control circuit (15) quickly stops the system in the semiconductor device (1A), and stops the system in the semiconductor device (1A) (S111). That is, the system control circuit (15) suppresses activation of the semiconductor device (1A).
- the diagnosis of the comparison circuit (209) is not limited to the scan test as described above.
- the system control circuit (15) sets the second expected value different from the initial value output from the recursive compression circuit (208) to the comparison circuit (209) when the semiconductor device (1A) is started.
- the comparison circuit (209) may be diagnosed by causing the comparison circuit (209) to execute only the corresponding notification.
- the comparison circuit (209) compares different values and determines that they match, the semiconductor device (1A) ) Is stopped. According to this, it is possible to detect a failure of the comparison circuit (209) and prevent the test result from being determined by the failed comparison circuit (209).
- FIG. 5 is a block diagram showing a configuration of the semiconductor device (1B) according to the second embodiment.
- the semiconductor device (1B) includes a plurality of circuits under test (40, 50, 60) and a system control circuit (15) as elements constituting the function.
- FIG. 5 shows an example in which the number of circuits under test is three, the number of circuits under test is not limited to this.
- each of the circuits under test (40, 50, 60) is the same as the circuit under test (2). Therefore, each of the circuits under test (40, 50, 60) is, for example, a CPU (10).
- the semiconductor device (1B) includes a plurality of first test control devices (41, 51, 61), a plurality of second test control devices (42, 52, 62), and a plurality of common result determination devices ( 43, 53, 63).
- each of the plurality of first test control devices (41, 51, 61) is the same as the first test control device (3). Therefore, each of the plurality of first test control devices (41, 51, 61) includes a first test control circuit (100), a pattern input circuit (101), and a first result compression circuit (206). And a first expected value storage circuit (103) (not shown).
- each of the second test control devices (42, 52, 62) is the same as the second test control device (4). Therefore, each of the second test control devices (42, 52, 62) includes a second test control circuit (200), a pattern generation circuit (201), a second result compression circuit (207), 2 expected value storage circuits (203) (not shown).
- each of the common result determination devices (43, 53, 63) is the same as the common result determination device (5). Therefore, each of the common result determination devices (43, 53, 63) includes a recursive compression circuit (208), a comparison circuit (209), and a timer (205).
- each of the first test control devices (41, 51, 61) and each of the common result determination devices (43, 52, 62) perform diagnosis during operation of each of the circuits under test (40, 50, 60). It corresponds to the device to be implemented.
- Each of the second test control devices (42, 52, 62) and each of the common result determination devices (43, 53, 63) perform diagnosis at startup of each of the circuits under test (40, 50, 60). It corresponds to a device.
- the semiconductor device (1B) includes an AND gate (44, 54, 64) and a test target setting circuit (70).
- the AND gate (44) is inserted into a signal line through which a diagnosis start signal for the second test control device (42) is transmitted from the system control circuit (15).
- the AND gate (54) is inserted into a signal line through which a diagnosis start signal is transmitted from the system control circuit (15) to the second test control device (52).
- the AND gate (64) is inserted into a signal line through which a diagnosis start signal is transmitted from the system control circuit (15) to the second test control device (62).
- the AND gate (44) receives the diagnosis start signal output from the system control circuit (15) and the inverted value of the test target setting signal output from the test target setting circuit (70).
- the AND gate (54) receives the diagnosis start signal output from the system control circuit (15) and the inverted value of the test target setting signal output from the test target setting circuit (70).
- the AND gate (64) receives the diagnosis start signal output from the system control circuit (15) and the inverted value of the test target setting signal output from the test target setting circuit (70).
- Each of the AND gates (44, 54, 64) performs an AND operation on the inverted value of the test target setting signal output from the test target setting circuit (70) and the diagnosis start signal output from the system control circuit (15). Then, a signal as a result of the calculation is output to the second test control device (42).
- the memory circuit (not shown) included in the test target setting circuit (70) is a target at the time of start-up diagnosis of the semiconductor device (1B) for each of the circuits under test (40, 50, 60). A value indicating whether or not is stored.
- This memory circuit is, for example, a memory whose value can be arbitrarily changed in the steps after the completion of the manufacture of the semiconductor device (1B). This memory is, for example, a FLASH memory or a fuse ROM.
- the test target setting circuit (70) outputs a value for each of the circuits under test (40, 50, 60) to each of the AND gates (44, 54, 64) as a test target setting signal.
- a low-level test target setting signal is output, and the startup diagnosis at the time of startup of the semiconductor device (1B) is performed. If it is not a target, a high level test target setting signal is output.
- the AND gate (44) directly uses the diagnosis start signal output from the system control circuit (15) as the second test control. Output to the device (42). That is, the high-level diagnosis start signal (asserted diagnosis start signal) output from the system control circuit (15) can be output to the second test control device (42) as it is. Therefore, it is possible to start the startup diagnosis by the second test control device (42) by the system control circuit (15).
- the AND gate (44) is independent of the value of the diagnosis start signal output from the system control circuit (15).
- a low level signal (a negated signal) is always output to the second test control device (42) as a diagnosis start signal. That is, it becomes impossible for the system control circuit (15) to start the startup diagnosis by the second test control device (42).
- the test target setting circuit (70) includes a plurality of test target circuits (40, 50, 60) at the time of starting the semiconductor device (1B).
- a value indicating whether or not the second test control device (42, 52, 62) is a target of a scan test is stored.
- Each of the plurality of second test control devices (42, 52, 62) performs a scan test when the semiconductor device (1B) is started according to the value. Therefore, it is possible to invalidate the startup diagnosis itself of any circuit under test and reduce the number of startup diagnosis targets. That is, the startup time of the semiconductor device (1B) can be shortened by not performing the startup diagnosis for any circuit under test. According to this, since the setting can be changed before shipping the semiconductor product, it is possible to respond to a plurality of customer needs, such as when priority is given to improving safety and priority is given to startup speed. it can.
- FIG. 6 is a block diagram showing a configuration of the semiconductor device (1C) according to the third embodiment.
- the semiconductor device (1C) further includes a plurality of OR gates (45, 55, 65) as compared with the semiconductor device (1B) according to the second embodiment.
- the system bus (13) is clearly shown.
- the OR gate (45) is inserted into a signal line through which a diagnosis start signal is transmitted from the AND gate (44) to the second test control device (42).
- the OR gate (55) is inserted into a signal line through which a diagnosis start signal for the second test controller (52) is transmitted from the AND gate (54).
- the OR gate (65) is inserted into a signal line through which a diagnosis start signal for the second test control device (62) is transmitted from the AND gate (64).
- each of the OR gates (45, 55, 65) is connected to each output terminal of the AND gate (44, 54, 64), and the OR gate (45, 55, 65). ) Is connected to the system bus (13).
- Each of the OR gates (45, 55, 65) performs an OR operation on the diagnosis start signal output from each of the AND gates (44, 54, 64) and the diagnosis start signal output from the system bus (13). Then, a signal that is a calculation result is output to the second test control device (42).
- the OR gate (45) directly outputs the diagnosis start signal output from the AND gate (44) to the second test control device (42). Output. That is, the test target circuit (40) is set as the test target in the test target setting circuit (70), and the test target setting signal output from the test target setting circuit (70) to the AND gate (44) is at the Low level. In some cases, the start-up diagnosis by the second test control device (42) can be started by the system control circuit (15).
- the OR gate (45) is always at the high level regardless of the value of the diagnosis start signal output from the AND gate (44). Is output as a diagnosis start signal to the second test control device (42). That is, in the test target setting circuit (70), the circuit under test (40) is not set as the test target, and the test target setting signal output from the test target setting circuit (70) to the AND gate (44) is High. Even when the level is the level, when the diagnosis start signal output from the system bus (13) is asserted (when the level is changed from the Low level to the High level), the second test control device (42) It is possible to start diagnostics at startup.
- FIG. 7 is a flowchart showing an operation during self-diagnosis of the semiconductor device (1C) according to the third embodiment.
- FIG. 7 shows that each operation event is connected by an arrow, and events are performed in time series according to the direction of the arrow.
- the point where the arrow branches indicates that the processes are executed in parallel.
- a diamond event represents a branch.
- the diamond-shaped event basically indicates the next processing when the downward arrow is in a normal state with respect to the content of the event.
- test target setting circuit (70) among the circuits under test (40, 50, 60), only the circuit under test (40) is set as the target of the start-up diagnosis when the semiconductor device (1C) is started. It is assumed that When the power of the semiconductor device (1C) is turned on and the reset of the second test control device (42, 52, 62) and the common result determination device (43, 53, 63) is released, the startup diagnosis is performed. Start. When the start-up diagnosis is started, the system control circuit (15) starts diagnosis of the circuit under test (40) by the second test control device (42) (S201).
- the common result determination device (43) When it is determined that the test result does not match the expected value (S202: Abnormal), the common result determination device (43) notifies the system control circuit (15) that the circuit under test (40) is abnormal. To do. The same applies when a timeout is detected by the timer (205). On the other hand, when it is determined that the circuit under test (40) is normal (S202: normal), the common result determination device (43) notifies the system control circuit (15) that it is normal. In response to this notification, the system control circuit (15) activates the circuit under test (40) (S203). As a result, the circuit under test (40) enters a normal operation state and starts processing according to its function (S204).
- steps S201 and S202 are the same as the operation in steps S101 to S103 in FIG.
- the circuit under test (40) starts normal operation, the system of the semiconductor device (1C) starts up (that is, the start-up of the semiconductor device (1C) is completed). After the semiconductor device (1C) is activated, the circuit under test (40) performs a process corresponding to the function of the second test control device (52) and the second test control device via the system bus (13). Each of (62) is requested to start diagnosis of each of the circuit under test (50) and the circuit under test (60). That is, the circuit under test (40) asserts the diagnosis start signal output to each of the OR gates (55, 65) via the system bus (13) (changes the diagnosis start signal from low level to high level). To do). Thereby, each of the second test control device (52) and the second test control device (62) starts diagnosis of the circuit under test (50) and the circuit under test (60) (S205, S209).
- the circuit under test (40) refers to the value stored in the test target setting circuit (70) via, for example, the system bus (13), and indicates that the value is not the target of diagnosis at startup.
- a diagnosis start signal for start-up diagnosis is asserted to the second test control device (52) and the second test control device (62) corresponding to the test circuits (50, 60).
- the circuit under test (40) does not have to perform the start-up diagnosis for all of the circuits under test (50, 60) that are indicated not to be the target of start-up diagnosis.
- the circuit under test (40) performs the start-up diagnosis on only a part of the circuits under test (50, 60) indicated not to be the start-up diagnosis target. Also good.
- the circuit under test to be subjected to the start-up diagnosis may be indicated by a value stored separately from the value indicating the start-up diagnosis target in the test target setting circuit (70).
- 40) may be defined as the processing of the application program to be executed, or may be indicated by a value stored in the external memory (14).
- the common result determination device (53) When it is determined that the test result does not match the expected value (S206: Abnormal), the common result determination device (53) notifies the system control circuit (15) of an error, assuming that the circuit under test (50) is abnormal. To do. The same applies when a timeout is detected by the timer (205). On the other hand, when it is determined that the circuit under test (50) is normal (S206: normal), the common result determination device (53) notifies the system control circuit (15) that it is normal. In response to this notification, the system control circuit (15) activates the circuit under test (50) (S207). As a result, the circuit under test (50) enters a normal operation state and starts processing according to its function (S208).
- the common result determination device (63) When it is determined that the test result does not match the expected value (S210: Abnormal), the common result determination device (63) notifies the system control circuit (15) that the circuit under test (60) is abnormal. To do. The same applies when a timeout is detected by the timer (205). On the other hand, when it is determined that the circuit under test (60) is normal (S210: normal), the common result determination device (63) notifies the system control circuit (15) that it is normal. In response to this notification, the system control circuit (15) activates the circuit under test (60) (S211). As a result, the circuit under test (60) enters a normal operation state and starts processing according to its function (S212).
- the system control circuit (15) promptly stops the system in the semiconductor device (1C) when the error is notified, and stops the system in the semiconductor device (1C) (S213).
- the activation of the circuit under test (60) may be suppressed to continue the operation of the system.
- Each of the circuits under test (40, 50, 60) periodically starts its own start-up diagnosis in the normal operation process, and this operation is the same as that described in the first embodiment. Therefore, the description thereof is omitted.
- a plurality of paths for instructing the start of diagnosis are provided for each of a plurality of startup diagnosis targets.
- the diagnosis is started from the system control circuit (15) after the reset is released immediately after the power is turned on, and the system bus (13) is connected after the system startup of the semiconductor device (1C) is completed.
- the circuit under test (40) indicating that the value stored in the test target setting circuit (70) is the target of the scan test by the second test control device is stored in the test target setting circuit (70).
- the test controller (52, 62) is instructed to perform a startup diagnosis (scan test). According to this, the startup time of the system can be shortened while ensuring high safety.
- the reason is that not all of the circuits under test (40, 50, 60) in the semiconductor device (1C) start operation immediately after the start-up, so that priority can be given also in the self-diagnosis.
- the circuit under test is a communication module that communicates with an external network, it is necessary to start up immediately, and the self-diagnosis must be performed immediately after starting up.
- the circuit under test is expected to operate later than the communication module, such as a module that performs image processing, the circuit under test slowly after the start of the semiconductor device (1C) is completed.
- a self-diagnosis may be performed. This is because a failure that occurs before the operation is expected can be regarded as not corresponding to LF.
- FIG. 8 is a block diagram showing a configuration of the semiconductor device (1D) according to the fourth embodiment.
- the semiconductor device (1D) includes a first result compression circuit (206), a second result compression circuit (207), and a semiconductor device (1A) according to the first embodiment.
- the common result determination device (5) timer (205), recursive compression circuit (208) and comparison circuit (209)
- the first result determination circuit (102), the first timer (104), the first 2 and the second timer (204) are different from the point that the circuit further includes a cutoff circuit (16, 17).
- the first result determination circuit (102) includes a first result compression circuit (206), a recursive compression circuit (208), and a comparison circuit (209) (not shown).
- the second result determination circuit (202) includes a second result compression circuit (207), a recursive compression circuit (208), and a comparison circuit (209) (not shown).
- the semiconductor device (1A) according to the first embodiment has the common result determination device (5) shared by the startup diagnosis and the in-operation diagnosis as a circuit for determining the test result.
- the semiconductor device (1D) according to the fourth embodiment includes circuits that are separately used for the startup diagnosis and the in-operation diagnosis as a circuit for determining the test result.
- the semiconductor device (1D) includes a first result determination circuit (102) and a first timer (104) as a circuit used for diagnosis during operation, and a second circuit as a circuit used for startup diagnosis. Result determination circuit (202) and second timer (204).
- the first test control circuit (100), the pattern input circuit (101), a part of the first result determination circuit (102) (first result compression circuit (206)), The first expected value storage circuit (103) functions as the first test control device (3).
- the second test control circuit (200), the pattern generation circuit (201), a part of the second result determination circuit (202) (second result compression circuit (207)), and the second expected value functions as the second test control device (4).
- the first result determination circuit (102) acquires the test result output from the scan chain of the CPU (10), and uses the acquired test result as the first result compression circuit (206) and the recursive compression circuit (208). Compress by.
- the first result determination circuit (102) compares the test result after compression with the first expected value output from the first expected value storage circuit (103) by the comparison circuit (209). Note that the specific test result compression method and the contents of notification to the system control circuit (15) according to the comparison result are the same as those in the first embodiment, and the description thereof will be omitted.
- the semiconductor device (1D) includes a first test control circuit (100), a pattern input circuit (101), a first result determination circuit (102), a first expected value storage circuit (103), and An operating diagnostic device (20) including a first timer (104).
- the operating diagnostic device (20) has a plurality of scan chains for performing a scan test on itself. Of the scan chain of the operating diagnostic device (20), the portion of the CPU (10) may be shared with the scan chain of the CPU (10) used by the first test control device (3). .
- the second test control device (4) includes not only the CPU (10) but also the CPU (10) as an object of the scan test.
- the pattern generation circuit (201) inputs the test pattern to the scan chain of the operating diagnostic device (20), not the scan chain of only the CPU (10). To do.
- the second result determination circuit (202) acquires the test result output from the scan chain of the operating diagnostic device (20), and uses the acquired test result as the second result compression circuit (207) and the recursive compression circuit. Compress by (208).
- the second result determination circuit (202) compares the test result after compression with the second expected value output from the second expected value storage circuit (203) by the comparison circuit (209). Note that the specific test result compression method and the contents of notification to the system control circuit (15) according to the comparison result are the same as those in the first embodiment, and the description thereof will be omitted.
- the operations of the first timer (104) and the second timer (204) are the same as the operations of the timer (205), description thereof will be omitted.
- the first timer (104) does not monitor the scan test execution time by the second test control circuit (200), but monitors the scan test execution time by the first test control circuit (100).
- the second timer (204) does not monitor the scan test execution time by the first test control circuit (100), but monitors the scan test execution time by the second test control circuit (200).
- the first test control circuit (100) when starting the scan test, the first test control circuit (100) outputs a start notification signal for notifying the start of the scan test to the first timer (104).
- the first test control circuit (100) outputs an end notification signal for notifying the end of the scan test to the first timer (104) when the scan test is ended.
- the second test control circuit (200) outputs a start notification signal for notifying the start of the scan test to the second timer (204) when starting the scan test.
- the second test control circuit (200) outputs an end notification signal for notifying the end of the scan test to the second timer (204).
- the cutoff circuit (16) cuts off a signal output from the system bus (13) to the operating diagnostic device (20) during the scan test in the startup diagnosis.
- This signal is, for example, a signal output from the system bus (13) to each of the CPU (10), the pattern input circuit (101), and the first test control circuit (100).
- the shut-off circuit (16) shuts off a signal output from the operating diagnostic device (20) to the system bus (13) during the scan test in the startup diagnosis.
- This signal is, for example, a signal output to the system bus (13) from each of the CPU (10), the pattern input circuit (101), and the first test control circuit (100).
- the operating diagnostic device (20) malfunctions due to the signal output from the system bus (13) to the operating diagnostic device (20) during the startup diagnosis, and the operating diagnostic device (20) It can be prevented that a test result different from the second expected value is obtained even though there is no failure. Further, a circuit (built-in memory (11) and external I / O connected to the system bus (13) by an unintentionally output signal from the operating diagnostic device (20) to the system bus (13) during the startup diagnosis. F (12) etc.) can be prevented from malfunctioning.
- the cutoff circuit (17) cuts off a signal output from the operating diagnostic device (20) to the system control circuit (15) during the scan test in the startup diagnosis.
- This signal is, for example, a notification signal output from the first result determination circuit (102) (comparison circuit (209)) and a notification signal output from the first timer (104). According to this, it is possible to prevent an error from being erroneously detected by a notification signal that is unintentionally output from the operating diagnostic device (20) to the system control circuit (15) during the dynamic diagnosis.
- the selection circuits (300, 301, 302) are It is considered unnecessary. That is, unlike the semiconductor device (1A) according to the first embodiment, the semiconductor device (1D) according to the fourth embodiment does not have the selection circuit (300, 301, 302).
- FIG. 9 is a flowchart showing an operation during self-diagnosis of the semiconductor device (1D) according to the fourth embodiment.
- FIG. 9 shows that each operation event is connected by an arrow, and events are performed in time series according to the direction of the arrow.
- a diamond event represents a branch.
- the diamond-shaped event basically indicates the next processing when the downward arrow is in a normal state with respect to the content of the event.
- the semiconductor device (1D) starts its startup diagnosis when the power is turned on and the reset of the circuits (200 to 204) for executing the startup diagnosis is released.
- the system control circuit (15) asserts a diagnosis start signal instructing the start of the diagnosis of the operating diagnostic device (20) and outputs it to the second test control circuit (200).
- the second test control circuit (200) starts diagnosis of the operating diagnostic device (20) in response to the assertion of the diagnosis start signal (S301).
- the second test control circuit (200) When the diagnosis is started (before the scan test of the operating diagnostic device (20) is started), the second test control circuit (200) is connected between the system bus (13) and the operating diagnostic device (20). The cutoff circuit (16) is controlled so as to cut off the signal transmitted between them. The second test control circuit (200) controls the cutoff circuit (17) so as to cut off a signal transmitted between the system bus (13) and the operating diagnostic device (20). As a result, the system bus (13) and the system control circuit (15) are prevented from malfunctioning during diagnosis as described above.
- the second test control circuit (200) When the diagnosis is started, the second test control circuit (200) outputs a start notification signal for notifying the CPU (10) of the start of the scan test to the second timer (204). Since the specific determination content and operation (S302) according to the determination result of the second timer (204) are the same as those of the timer (205) (same as step S102 of FIG. 1), the description thereof is omitted. .
- the control of the second timer (204) is not limited to the second test control circuit (200) as described above, and may be performed by the system control circuit (15).
- the second test control circuit (200) instructs the pattern generation circuit (201) to generate a test pattern in order to start diagnosis of the operating diagnostic device (20), and performs a scan test of the operating diagnostic device (20). To implement.
- the operation in the scan test is the same as in the first embodiment except that the target is not only the CPU (10) but the operating diagnostic device (20) including the CPU (10). Description is omitted.
- the second result determination circuit (202) compresses the test result acquired from the operating diagnostic device (20), and stores the test result after compression and the second expected value storage circuit (203). It is determined whether or not the expected value matches (S303).
- the second result determination circuit (202) outputs a notification signal for notifying normality to the system control circuit (15) when the comparison results match ( (S303: normal), if the comparison result does not match, a notification signal for notifying an error is output to the system control circuit (15) (S303: abnormal).
- the second test control circuit (200) after completing the scan test (after all the test results are output from the scan chain), is connected to the system bus (13) and the operating diagnostic device (20).
- the cutoff circuit (16) is controlled so as not to cut off signals transmitted between them.
- the second test control circuit (200) controls the cutoff circuit (17) so as not to cut off a signal transmitted between the system bus (13) and the operating diagnostic device (20).
- the test control circuit (105) is the CPU (10) as in steps S104 and S105 of FIG. 1 described in the first embodiment. Is started (S304), and the CPU (10) executes the process (S305). As with steps S106 and S107 of FIG. 1 described in the first embodiment, the CPU (10) performs CPU to the first test control circuit (100) every time a predetermined time elapses (S306: Yes). The diagnosis of (10) is instructed and the processing is stopped (S307). The first test control circuit (100) starts diagnosis of the CPU (10) in response to an instruction from the CPU (10), similarly to step S108 of FIG. 1 described in the first embodiment (S308). .
- the first test control circuit (100) When the diagnosis is started, the first test control circuit (100) outputs to the first timer (104) a start notification signal that notifies the CPU (10) of the start of the scan test. Since the specific determination contents and the operation according to the determination result (S309) of the first timer (104) are the same as the timer (205) (same as step S109 in FIG. 1), the description thereof is omitted. .
- the control of the first timer (104) is not limited to the first test control circuit (100) as described above, but may be controlled by the system control circuit (15).
- the first test control circuit (100) instructs the pattern input circuit (101) to input a test pattern via the system bus (13), and the CPU (10 ) Perform a scan test.
- the operation in the scan test is the same as that in the first embodiment, and a description thereof will be omitted.
- the first result determination circuit (102) compresses the test result acquired from the CPU (10), the test result after compression, and the first expected value stored in the first expected value storage circuit (103). Whether or not coincides with each other (S310).
- the first result determination circuit (102) outputs a notification signal notifying normality to the system control circuit (15) when the comparison results match ( (S310: Normal), if the comparison result does not match, a notification signal for notifying an error is output to the system control circuit (15) (S310: Abnormal).
- the system control circuit 15) As in step S111 of FIG. 1 described in the first embodiment, the system in the semiconductor device (1D) is immediately stopped to stop the system in the semiconductor device (1D) (S311).
- the entire operating diagnostic device (20) including the CPU (10) is targeted for diagnosis.
- the scan test of the first test control device (3) is performed together with the CPU (10).
- FIG. 10 is a block diagram showing a configuration of the semiconductor device (1E) according to the fifth embodiment.
- the semiconductor device (1E) is different from the semiconductor device (1E) according to the fourth embodiment in the cutoff circuits (16), (17), the second test control circuit (200), The difference is that the pattern generation circuit (201), the second result determination circuit (202), the second expected value storage circuit (203), and the second timer (204) are not provided.
- the semiconductor device (1E) is compared with the semiconductor device (1E) according to the fourth embodiment in the first test control circuit (100), the pattern input circuit (101), and the first result determination circuit (102).
- the semiconductor device (1E) is different from the semiconductor device (1E) according to the fourth embodiment in that it further includes a ROM (400) and a selection circuit (401).
- the test control circuit (600), the pattern input circuit (601), the result determination circuit (602), the expected value storage circuit (603), and the timer (604) are used to diagnose and operate at startup. Perform both diagnoses. That is, in the fifth embodiment, the result determination circuit (602) includes the first result compression circuit (206), the second result compression circuit (207), the recursive compression circuit (208), and the comparison circuit. (209) (not shown).
- a part of the test control circuit (600), the pattern input circuit (601), and the result determination circuit (602) (the first result compression circuit (206) and the second result compression circuit ( 207)), the expected value storage circuit (603), and the timer (604) function as a first test control device (3) and a second test control device (4).
- the expected value storage circuit (603) stores in advance both a first expected value used in the diagnostic during operation and a second expected value used in the startup diagnosis.
- the test control circuit (600) differs from the first test control circuit (100) according to the fourth embodiment in that it also performs a scan test of the CPU (10) in the startup diagnosis. That is, the test control circuit (600) executes a scan test of the CPU (10) in the startup diagnosis according to a request from the system control circuit (15) at the startup of the semiconductor device (1E).
- the pattern input circuit (601) is connected to the system bus (13) and the ROM (400) via the selection circuit (401).
- the ROM (400) stores in advance a plurality of test patterns used for startup diagnosis.
- the selection circuit (401) selectively outputs the test pattern output from either the system bus (13) or the ROM (400) to the pattern input circuit (601).
- the selection circuit (401) is a test control circuit (600) or system control circuit so that the ROM (400) side is selected as a connection destination with the pattern input circuit (601) when starting diagnosis at startup Controlled by (15).
- the test control circuit (600) may control in response to the assertion of the diagnosis start signal from the system control circuit (15), and may be controlled before the system control circuit (15) asserts the diagnosis start signal. Also good.
- the pattern input circuit (101) reads the test pattern from the ROM (400) and supplies it to the scan chain of the CPU (10) in accordance with a request from the first test control circuit (100) in the startup diagnosis.
- the result determination circuit (602) acquires the test result output from the scan chain of the CPU (10), and the acquired test result is the first result.
- the result is compressed by the result compression circuit (207) and the recursive compression circuit (208).
- the result determination circuit (602) compares the test result after compression with the second expected value output from the expected value storage circuit (603) by the comparison circuit (209). That is, unlike the second result determination circuit (202), the result determination circuit (602) diagnoses the CPU (10), not the operating diagnostic device (20). Note that the specific test result compression method and the contents of notification to the system control circuit (15) according to the comparison result are the same as those of the second result determination circuit (202) according to the fourth embodiment. Therefore, the description is omitted.
- the timer (604) Since the operation of the timer (604) is the same as the operation of the timer (205) according to the first embodiment, the description thereof is omitted. However, unlike the timer (205) according to the first embodiment, the timer (604) does not monitor the scan test execution time by the test control circuit (100, 200) that is different between the startup diagnosis and the in-operation diagnosis. The difference is that the scan test execution time by the test control circuit (600) is monitored both in the startup diagnosis and the in-operation diagnosis.
- the operations of the test control circuit (600), the pattern input circuit (601), the result determination circuit (602), and the timer (604) in the operation diagnosis are the first test control circuit (100) according to the fourth embodiment.
- the operations of the pattern input circuit (101), the first result determination circuit (102), and the first timer (104) are the same as those of the pattern input circuit (101).
- the selection circuit (401) performs test control so that the system bus (13) side is selected as a connection destination with the pattern input circuit (601) when the diagnosis during operation is started. It is controlled by the circuit (600) or the CPU (10).
- the test control circuit (600) may control in response to the assertion of the diagnosis start signal from the CPU (10), or may be controlled before the CPU (10) asserts the diagnosis start signal.
- the operation of the semiconductor device (1E) according to the fifth embodiment is the same as the operation of the semiconductor device (1D) according to the fourth embodiment (the operation shown in FIG. 9), description thereof is omitted.
- the operation of the semiconductor device (1E) is compared with the operation of the semiconductor device (1D), and both the startup diagnosis and the in-operation diagnosis are performed in the test control circuit (600) and the pattern input circuit (601).
- the result determination circuit (602) and the timer (604) are implemented, the selection circuit (401) is controlled at the start of the start-up diagnosis and the in-operation diagnosis, and a test pattern for the start-up diagnosis is generated. Instead, it is obtained from the ROM (400).
- a circuit for performing the startup diagnosis and the startup diagnosis is shared.
- many modules including the system bus (13) are in a dormant state for diagnosis. Therefore, it is difficult to acquire the test pattern via the system bus (13).
- the dedicated ROM (400) has test data to be used in the startup diagnosis. That is, when the system bus (13) is being initialized, a test pattern is acquired from the ROM (400), and the acquired test pattern is input to the scan chain of the CPU (10) to perform a scan test in the startup diagnosis. To do.
- FIG. 11 is a block diagram showing a configuration of the semiconductor device (1F) according to the sixth embodiment.
- the semiconductor device (1F) further includes an external I / F (18) and a selection circuit (402) as compared with the semiconductor device (1E) according to the fifth embodiment shown in FIG. ).
- the semiconductor device (1F) is different from the semiconductor device (1E) according to the fifth embodiment in that it does not have a ROM (400).
- both the test pattern used in the startup diagnosis and the test pattern used in the operating diagnosis are stored in the external memory (14).
- an external I / F (18) is connected to the selection circuit (401) instead of the ROM (400).
- the external memory (14) is connected to the external I / F (12) and the external I / F (18) via the selection circuit (402).
- the external I / F (18) is a circuit that transmits and receives data between the external memory 14 and the selection circuit (401) via the selection circuit (402).
- the selection circuit (401) selectively selects a test pattern input from either the system bus (13) or the external I / F (18) as a pattern input circuit (601). ).
- the selection circuit (402) selectively outputs the test pattern input from the external memory (14) to one of the external I / F (12) and the external I / F (18).
- the selection circuit (401) selects the external I / F (18) side as the connection destination with the pattern input circuit (601) when starting the diagnosis at the time of startup. It is controlled by the test control circuit (600) or the system control circuit (15).
- the selection circuit (402) is configured so that the external I / F (18) side is selected as a connection destination with the external memory (14) when starting diagnosis at the time of starting, Controlled by the system control circuit (15).
- the test control circuit (600) may control in response to the assertion of the diagnosis start signal from the system control circuit (15), and may be controlled before the system control circuit (15) asserts the diagnosis start signal. Also good.
- the pattern input circuit (601) follows the request from the first test control circuit (100), not via the system bus (13) but via the external I / F (18).
- the test pattern is read from the external memory (14) and supplied to the scan chain of the CPU (10).
- the test control circuit (600) when the selection circuit (401) starts diagnosis during operation, the test control circuit (600), or so that the system bus (13) side is selected as a connection destination with the pattern input circuit (601) It is controlled by the CPU (10).
- the selection circuit (402) is configured so that the external I / F (12) side is selected as a connection destination with the external memory (14) when starting diagnosis during operation. , Controlled by the CPU (10).
- the test control circuit (600) may control in response to the assertion of the diagnosis start signal from the CPU (10), or may be controlled before the CPU (10) asserts the diagnosis start signal.
- the operation of the semiconductor device (1F) according to the sixth embodiment is the same as the operation of the semiconductor device (1E) according to the fifth embodiment, the description thereof is omitted.
- the operation of the semiconductor device (1F) is more controlled than the operation of the semiconductor device (1E) in that the selection circuit (402) is further controlled at the start of the startup diagnosis and the in-operation diagnosis, and the test pattern in the startup diagnosis. Is obtained not from the ROM (400) but from the external memory (14).
- the sixth embodiment shares a circuit that performs the startup diagnosis and the startup diagnosis. That is, in the sixth embodiment, when the system bus (13) is initialized, a test pattern is acquired from the external memory (14) via the external I / F (18), and the acquired test pattern is stored in the CPU. Input to the scan chain of (10) and execute the scan test in the startup diagnosis. Then, after initialization of the system bus (13), a test pattern is acquired from the external memory (14) via the system bus (13), and the acquired test pattern is input to the scan chain of the CPU (10). A scan test for diagnosis is performed.
- the scan test is performed during operation on a single CPU (10), thereby reducing the cost compared to duplicating the CPU. As well as ensuring the safety, the safety of the diagnostic device used for the diagnosis during operation is also ensured. Further, since the semiconductor device (1F) does not need to have the ROM (400), the cost can be further reduced.
- FIG. 12 is a block diagram showing a configuration of the semiconductor device (1G) according to the seventh embodiment.
- the semiconductor device (1G) has a plurality of CPUs (10A to 10D) instead of one CPU (10) as compared with the semiconductor device (1A) according to the first embodiment. Is different.
- the semiconductor device (1G) is different from the semiconductor device (1A) according to Embodiment 1 in that it further includes a selection circuit (501).
- each of the CPUs (10A to 10D) is the same as the CPU (10) according to the first embodiment, the description thereof is omitted. That is, the semiconductor device (1G) employs a multiprocessor configuration in which a plurality of CPUs having the same configuration are mounted.
- the first test control circuit (100) is connected to each of the CPUs (10A to 10D) via the system bus (13).
- the first test control circuit (100) executes a scan test of the CPU (10A) according to a request from the CPU (10A), and executes a scan test of the CPU (10B) according to a request from the CPU (10B).
- the CPU (10C) scan test is executed according to the request from the CPU (10C), and the CPU (10D) scan test is executed according to the request from the CPU (10D).
- All the CPUs (10A to 10D) are connected to the pattern input circuit (101) and the pattern generation circuit (201) via the selection circuit (300). That is, the test patterns output from the pattern input circuit (101) and the pattern generation circuit (201) are input to all the CPUs (10A to 10D) via the selection circuit (300).
- the first test control circuit (100) when performing a scan test, out of the scan enable signals output to the CPUs (10A to 10D), the scan enable signal output to the test target CPU. And the scan enable signal output to each of the other CPUs remains negated.
- Each of the CPUs (10A to 10D) performs a scan shift operation while the asserted scan enable signal is being input, so that each of the CPUs (10A to 10D) has a test pattern input via the selection circuit (300). While scanning in, the test results stored in the scan chain are scanned out. On the other hand, each of the CPUs (10A to 10D) does not perform the scan shift operation while the negated scan enable signal is input, and has a test pattern input via the selection circuit (300). The scan chain is not scanned in, and the data stored in the scan chain is not scanned out.
- the scan test is performed only on the CPU to be tested, and the CPU not to be tested can continue the normal operation.
- the second test control circuit (200) executes each scan test of the CPU (10A to 10D) in accordance with a request from the system control circuit (15). To do.
- the system control circuit (15) designates the CPU to be tested for the second test control circuit (200).
- the second test control circuit (200) performs a CPU scan test designated by the system control circuit (15).
- the second test control circuit (200) also performs a scan test on the test target CPU by asserting a scan enable signal for the test target CPU. . Since the specific operation is the same as described above, the description thereof is omitted.
- the first result compression circuit (206) and the second result compression circuit (207) are connected to each of the CPUs (10A to 10D) via the selection circuit (501).
- the selection circuit (501) selectively selects a test result output from any one of the CPUs (10A to 10D) of the first result compression circuit (206) and the second result compression circuit (207). Output to each.
- the selection circuit (501) selects the CPU to be tested as a connection destination of the first result compression circuit (206) and the second result compression circuit (207) when starting diagnosis at the time of startup. , Controlled by the second test control circuit (200) or the system control circuit (15).
- each of the second test control circuits (200A to 200D) may control in response to the assertion of the diagnosis start signal from the system control circuit (15), and the system control circuit (15) outputs the diagnosis start signal. You may control before asserting.
- the selection circuit (501) selects the CPU to be tested as the connection destination of the first result compression circuit (206) and the second result compression circuit (207) when starting the diagnosis during operation.
- the control is performed by the first test control circuit (100) or the CPU to be tested.
- the first test control circuit (100) may be controlled in response to the assertion of the diagnosis start signal from the test target CPU, or may be controlled before the test target CPU asserts the diagnosis start signal. Good.
- the first result compression circuit (206) and the second result compression circuit (207) can acquire and compress the test result from the CPU on which the scan test is performed.
- the operation of the common result determination apparatus (5) is the same as that of the first embodiment, and thus the description thereof is omitted.
- FIGS. 13 and 14 are flowcharts showing operations during self-diagnosis of the semiconductor device (1G) according to the seventh embodiment.
- each operation event is connected by an arrow, and it is represented that events are performed in time series according to the direction of the arrow.
- the point where the arrow branches indicates that the processes are executed in parallel.
- a diamond event represents a branch. The diamond event basically points to the next process when the downward arrow is normal for the event content, and the right arrow is abnormal for the event content. Refers to the next process.
- the operation in the seventh embodiment will be described while comparing the example of the semiconductor device (1G) shown in FIG. 12 with the operation flows shown in FIGS.
- the semiconductor device (1G) periodically interrupts the processing of any one of the CPUs (10A to 10D) during normal operation, and detects the SPF of the CPU that interrupted the processing. Perform diagnostics during operation. If no SPF is detected here, the semiconductor device (1G) restarts normal operation of the CPU that performed the startup diagnosis.
- the diagnostic operation for SPF detection is performed in a predetermined order for each of the CPUs (10A to 10D), for example, and not performed simultaneously for two or more CPUs.
- step S401 is the same as the operation in step S112 in FIG. 4 described in the modification of the first embodiment, and thus the description thereof is omitted.
- step S402 the system control circuit (15) asserts a diagnosis start signal instructing the CPU (10A) to start diagnosis and outputs the asserted signal to the second test control circuit (200).
- the second test control circuit (200) starts diagnosis of the CPU (10A) in response to the assertion of the diagnosis start signal instructing the CPU (10A) to start diagnosis (S402).
- the specific operation in step S402 is the same as that in step S101 in FIG. 3 in the first embodiment, and a description thereof will be omitted. The same applies to the operations for CPUs (10B to 10D) described later.
- the second test control circuit (200) or the system control circuit (15) performs the test before starting the startup diagnosis of the CPU (10A).
- the difference is that the selection circuit (501) is controlled so that the target CPU (10A) is selected.
- the second test control circuit (200) starts the timer (205) in the same manner as step S102 of FIG. 3 in the first embodiment before starting diagnosis of the first CPU (10A) ( S403).
- the details of the determination by the timer (205) and the notification content according to the determination result are the same as in step S102 of FIG.
- the timer (205) monitors the time from the start of diagnosis of the first CPU (10A) to the end of diagnosis of the last CPU (10D) described later.
- step S404 determines the test result obtained by the scan test (S404).
- the specific operation in step S404 is the same as that in step S104 in FIG. 3 in the first embodiment, and a description thereof will be omitted. The same applies to the operations for CPUs (10B to 10D) described later.
- the system control circuit (15) When an error is notified as a diagnosis result of the CPU (10A) from the comparison circuit (209) (S404: Abnormal), the system control circuit (15) performs a process of quickly stopping the system and stops the system (S423). ). That is, the system control circuit (15) suppresses activation of the semiconductor device (1G). The same applies to the operations for CPUs (10B to 10D) described later.
- the system control circuit (15) When a notification signal for notifying normality is output from the comparison circuit (209) as a diagnosis result of the CPU (10A) (S404: normal), the system control circuit (15) performs a diagnosis for instructing the CPU (10B) to start diagnosis.
- the start signal is asserted and output to the second test control circuit (200).
- the second test control circuit (200) starts diagnosis of the CPU (10B) in response to the assertion of the diagnosis start signal instructing the CPU (10B) to start diagnosis (S405).
- the second test control circuit (200) or the system control circuit (15) is configured so that the test target CPU (10B) is selected before starting the startup diagnosis of the CPU (10B). 501) is controlled.
- the comparison circuit (209) determines the test result obtained by the scan test (S406).
- the system control circuit (15) performs a diagnosis for instructing the CPU (10C) to start diagnosis.
- the start signal is asserted and output to the second test control circuit (200).
- the second test control circuit (200) starts diagnosis of the CPU (10C) in response to the assertion of the diagnosis start signal instructing the CPU (10C) to start diagnosis (S407).
- the second test control circuit (200) or the system control circuit (15) selects the selection circuit (10C) so that the test target CPU (10C) is selected before starting the startup diagnosis of the CPU (10C). 501) is controlled.
- the comparison circuit (209) determines the test result obtained by the scan test (S408).
- the system control circuit (15) performs diagnosis for instructing the CPU (10D) to start diagnosis
- the start signal is asserted and output to the second test control circuit (200).
- the second test control circuit (200) starts the diagnosis of the CPU (10D) in response to the assertion of the diagnosis start signal instructing the CPU (10D) to start the diagnosis (S409).
- the second test control circuit (200) or the system control circuit (15) selects the selection circuit (10D) so that the test target CPU (10D) is selected before starting the startup diagnosis of the CPU (10D). 501) is controlled.
- the comparison circuit (209) determines the test result obtained by the scan test (S410).
- the second test control circuit (200) outputs a notification signal notifying the end of the scan test to the timer (205) when the scan test of the last CPU (10D) is completed.
- the timer (205) ends the elapsed time measurement in response to the notification signal from the second test control circuit (200).
- the monitoring by the timer (205) may be performed in units of performing diagnosis at startup of each of the CPUs (10A to 10D).
- the second test control circuit (200) outputs a start notification signal to the timer (205) when starting the execution of each scan test of the CPU (10A to 10D), and the CPU (10A to 10D)
- An end notification signal may be output to the timer (205) when the execution of each scan test is ended.
- This process includes a process of performing a self-diagnosis periodically as in the first embodiment.
- control is performed by the system control circuit (15) or by cooperative operation between the CPUs (10A to 10D) so that a plurality of CPUs do not enter the self-diagnosis state at the same time.
- self-diagnosis is executed in the order of CPU (10A), CPU (10B), CPU (10C), and CPU (10D) will be described.
- Step S10 includes the operations of Steps S414 to S417, but their specific operations are the same as those of Steps S107 to S110 of Embodiment 1 (FIG. 3). Omitted.
- the first test control circuit (100) or the CPU (10A) selects the test target CPU (10A) so that the CPU (10A) to be tested is selected before the CPU (10A) starts diagnosis during operation. To control.
- Step S416: Abnormal or S417: Abnormal, S427) when the diagnosis result is abnormal is the same as the operation of Step S109: Abnormal or S110: Abnormal, S111 in the first embodiment (FIG. 3). Therefore, the description is omitted.
- the CPU (10B) executes a self-diagnosis (S11). That is, the starting time for measuring the elapsed time for the CPU (10B) is later than the starting time for measuring the elapsed time for the CPU (10A). Since the operation of step S11 is the same as that of step S10, the description thereof is omitted.
- the first test control circuit (100) or the CPU (10B) selects the test target CPU (10B) so that the CPU (10B) to be tested is selected before the CPU (10B) starts diagnosis during operation. To control. When the diagnosis result of the CPU (10B) is normal, the system control circuit (15) restarts the CPU (10B) (S418). After restarting, the CPU (10B) resumes the stopped processing (S419).
- the CPU (10C) executes a self-diagnosis (S12). That is, the starting time for measuring the elapsed time for the CPU (10C) is later than the starting time for measuring the elapsed time for the CPU (10B). Since the operation of step S12 is the same as that of step S10, the description thereof is omitted.
- the first test control circuit (100) or the CPU (10C) selects the test target CPU (10C) so that the CPU (10C) to be tested is selected before starting the diagnosis during the operation of the CPU (10C). To control.
- the system control circuit (15) restarts the CPU (10C) (S421). After restarting, the CPU (10C) resumes the stopped processing (S422).
- the CPU (10D) executes a self-diagnosis (S13). That is, the starting time for measuring the elapsed time for the CPU (10D) is later than the starting time for measuring the elapsed time for the CPU (10C). Since the operation in step S13 is the same as that in step S10, the description thereof is omitted.
- the first test control circuit (100) or the CPU (10D) selects the test target CPU (10D) so that the CPU (10D) to be tested is selected before starting the diagnosis during the operation of the CPU (10D). To control.
- the system control circuit (15) restarts the CPU (10D) (S424). After restarting, the CPU (10D) resumes the stopped processing (S425).
- the system control circuit (15) promptly stops the system and stops the system (S427).
- any method may be adopted as a method of periodically executing the self-diagnosis (diagnosis during activation) of the CPUs (10A to 10D) described above at a timing that does not overlap.
- the CPU (10A) may be periodically notified of an interrupt from a timer, and the CPU (10A) may execute a self-diagnosis in response to the interrupt from the timer.
- each of the CPUs (10A to 10C) notifies the CPU interrupts to the CPUs (10B to 10D) that execute the self-diagnosis next time when the operation is resumed after the restart. Accordingly, each of the CPUs (10B to 10D) may execute a self-diagnosis.
- the CPUs (10A to 10D) are notified of interrupts periodically from the plurality of timers corresponding to the CPUs (10A to 10D) at a timing at which the self-diagnosis (diagnosis during activation) does not overlap.
- each of the CPUs (10A to 10D) may execute self-diagnosis in response to an interrupt from the timer.
- the seventh embodiment shows a configuration for detecting LF and SPF in a semiconductor device (1G) equipped with a multi CPU.
- the common result determination device (5) is shared by a plurality of CPUs. That is, the first test control device (3) and the second test control device (4) perform the scan tests of the plurality of CPUs (10A to 10D) in a predetermined order. According to this, the circuit area can be reduced.
- the features and effects of the first embodiment are combined and the number of CPUs for diagnosis does not increase in proportion to the number of CPUs to be mounted, the area and power according to the seventh embodiment increase as the number of CPUs increases. The reduction effect is significant.
- FIG. 15 is a block diagram showing a configuration of a semiconductor device (1H) according to the eighth embodiment.
- the semiconductor device (1G) includes a plurality of CPUs (10A, 10B, 10C, 10D) and a plurality of second tests as compared with the semiconductor device (1A) according to the first embodiment. The difference is that it includes a control circuit (200A to 200D), a plurality of pattern generation circuits (201A to 201D), a plurality of result compression circuits (207A to 207D), and a plurality of selection circuits (300A to 300D).
- the semiconductor device (1G) further includes an AND gate (500), a selection circuit (501), a selection circuit (502), and an AND gate, as compared with the semiconductor device (1A) according to the first embodiment. (503).
- each of the CPUs (10A to 10D) is the same as the CPU (10) according to the first embodiment, the description thereof is omitted. That is, the semiconductor device (1H) adopts a multiprocessor configuration in which a plurality of CPUs having the same configuration are mounted.
- each of the second test control circuits (200A to 200D) is the same as the second test control circuit (200) according to the first embodiment, the description thereof is omitted. That is, the semiconductor device (1H) adopts a multiprocessor configuration in which a plurality of CPUs having the same configuration are mounted.
- each of the pattern generation circuits (201A to 201D) is the same as the pattern generation circuit (201) according to the first embodiment, description thereof is omitted.
- each of the second result compression circuits (207A to 207D) is the same as the second result compression circuit (207) according to the first embodiment, description thereof is omitted.
- each of the selection circuits (300A to 300D) is the same as the selection circuit (300) according to Embodiment 1, the description thereof is omitted.
- the AND gate 500 performs an AND operation on the start notification signal output from each of the plurality of second test control circuits (200A to 200D), and outputs a signal as a calculation result to the timer (205) as a start notification signal.
- the AND gate 504 performs an AND operation on the end notification signal output from each of the plurality of second test control circuits (200A to 200D), and outputs a signal as a calculation result to the timer (205) as an end notification signal. To do.
- the test result output from each of the CPUs (10A to 10D) is transmitted through the second result compression circuit (207A to 207D) without going through the selection circuit (501). ). Therefore, the selection circuit (501) according to the eighth embodiment outputs test results to the second result compression circuits (207A to 207D) as compared with the selection circuit (501) according to the seventh embodiment. Without output to the first result compression circuit (206). Further, this makes it unnecessary to control the selection circuit (501) when starting diagnosis at startup.
- the selection circuit (502) selectively outputs the test result output from any one of the plurality of result compression circuits (207A to 207D) to the selection circuit (301).
- the first test control circuit (100) is connected to each of the CPUs (10A to 10D) via the system bus (13).
- the first test control circuit (100) executes a scan test of the CPU (10A) according to a request from the CPU (10A), and executes a scan test of the CPU (10B) according to a request from the CPU (10B).
- the CPU (10C) scan test is executed according to the request from the CPU (10C), and the CPU (10D) scan test is executed according to the request from the CPU (10D).
- Each of the CPUs (10A to 10D) is connected to a pattern input circuit (101) and a pattern generation circuit (201A to 201D) via a selection circuit (300A to 300D). That is, the test pattern output from each of the pattern generation circuits (201A to 201D) is input to each of the CPUs (10A to 10D) via each of the selection circuits (300A to 300D).
- the pattern input circuit (101) outputs a test pattern to each of all the selection circuits (300A to 300D).
- the test pattern output from the pattern input circuit (101) is input to all the CPUs (10A to 10D) via the selection circuits (300A to 300D).
- the first test control circuit (100) when performing a scan test, out of the scan enable signals output to the CPUs (10A to 10D), the scan enable signal output to the test target CPU. And the scan enable signal output to each of the other CPUs remains negated.
- the scan test is performed only on the test target CPU, and the non-test target CPU can continue the normal operation.
- Each of the second test control circuits (200A to 200D) is connected to the system control circuit (15).
- the second test control circuit (200A) executes a scan test of the CPU (10A) in accordance with a request from the system control circuit (15).
- the second test control circuit (200B) executes a scan test of the CPU (10B) in accordance with a request from the system control circuit (15).
- the second test control circuit (200C) executes a scan test of the CPU (10C) in accordance with a request from the system control circuit (15).
- the second test control circuit (200D) executes a scan test of the CPU (10D) in accordance with a request from the system control circuit (15).
- Each of the second result compression circuits (207A to 207D) is connected to each of the CPUs (10A to 10D). Similar to the second result compression circuit (207) of the first embodiment, the second result compression circuit (207A) compresses the test result output from the scan chain of the CPU (10A). Similar to the second result compression circuit (207) of the first embodiment, the second result compression circuit (207B) compresses the test result output from the scan chain of the CPU (10B). Similar to the second result compression circuit (207) of the first embodiment, the second result compression circuit (207C) compresses the test result output from the scan chain of the CPU (10C). Similar to the second result compression circuit (207) of the first embodiment, the second result compression circuit (207D) compresses the test result output from the scan chain of the CPU (10D).
- the AND gate (500) performs an AND operation on the start notification signal output from each of the second test control circuits (200A to 200D), and outputs a start notification signal as a calculation result to the timer (205). That is, the timer (205) starts measuring the elapsed time from the time when all the second test control circuits (200A to 200D) output the start notification signal.
- the AND gate (503) performs an AND operation on the end notification signals output from the second test control circuits (200A to 200D), and outputs an end notification signal as a calculation result to the timer (205). That is, the timer (205) ends the measurement of the elapsed time when all the second test control circuits (200A to 200D) output the end notification signal.
- FIGS. 16 and 17 are flowcharts showing operations during self-diagnosis of the semiconductor device (1H) according to the eighth embodiment.
- each operation event is connected by an arrow, and it is represented that events are performed in time series according to the direction of the arrow.
- the point where the arrow branches indicates that the processes are executed in parallel.
- a diamond event represents a branch. The diamond event basically points to the next process when the downward arrow is normal for the event content, and the right arrow is abnormal for the event content. Refers to the next process.
- the operation in the eighth embodiment will be described while comparing the example of the semiconductor device (1H) shown in FIG. 15 with the operation flows shown in FIGS.
- the semiconductor device (1H) periodically interrupts the processing of any one of the CPUs (10A to 10D) during normal operation, and detects the SPF of the CPU that has suspended the processing. Perform diagnostics during operation. If the SPF is not detected here, the CPU that has performed the startup diagnosis resumes normal operation of the semiconductor device (1H).
- the diagnostic operation for SPF detection is performed in a predetermined order for each of the CPUs (10A to 10D), for example, and not performed simultaneously for two or more CPUs.
- step S501 the system control circuit (15) performs the diagnosis of the comparison circuit (209) (S501).
- the system control circuit (15) asserts a diagnosis start signal that instructs the comparison circuit (209) to start diagnosis and outputs the asserted signal to the second test control circuits (200A to 200D).
- the second test control circuits (200A to 200D) perform the diagnosis of the comparison circuit (209) in response to the assertion of the diagnosis start signal instructing the comparison circuit (209) to start diagnosis.
- the operation in step S501 is the same as the operation in step S112 of FIG. 4 described in the modification of the first embodiment, and thus the description thereof is omitted.
- the system control circuit (15) outputs a diagnosis start signal asserted to any one of the second test control circuits (200A to 200D), and the CPU (10A to 10D) out of the first
- the comparison circuit (209) may be diagnosed by performing a CPU scan test corresponding to the second test control circuit. Further, as described in the modification of the first embodiment, the system control circuit (15) may cause the comparison circuit (209) to compare only different values without performing the scan test.
- the system control circuit (15) asserts a diagnosis start signal instructing the start of diagnosis of each of the CPUs (10A to 10D) and outputs it to each of the second test control circuits (200A to 200D).
- Each of the second test control circuits (200A to 200D) starts diagnosis of each of the CPUs (10A to 10D) in response to assertion of a diagnosis start signal instructing the CPU (10A to 10D) to start diagnosis.
- S502, S503, S504, S505 Note that the specific operations of steps S502, S503, S504, and S505 are the same as those in step S101 of FIG. 3 in the first embodiment, and a description thereof will be omitted.
- each of the plurality of pattern generation circuits (201A to 201D) inputs a test pattern in parallel to each of the plurality of CPUs (10A to 10D).
- Each of the plurality of second result compression circuits (207A to 207D) acquires the test results from the respective scan chains of the plurality of CPUs (10A to 10D) and compresses them.
- each of the second test control circuits (200A to 200D) starts a timer (as in step S102 of FIG. 3 in the first embodiment) before starting diagnosis of each of the CPUs (10A to 10D). 205) is started (S506).
- the details of the determination by the timer (205) and the notification content according to the determination result are the same as in step S102 of FIG.
- the timer (205) receives the start notification signal from all of the second test control circuits (200A to 200D). Then, the measurement of elapsed time is started.
- test results are determined in the order of CPU (10A), CPU (10B), CPU (10C), and CPU (10D).
- the second test control circuit (200A) or the second result compression circuit (207A) controls the selection circuit (502) so that the second result compression circuit (207A) is selected.
- the second result compression circuit (207A) corresponding to the CPU (10A) serially outputs the test result after compression to the recursive compression circuit (208) bit by bit via the selection circuit (502).
- the other second result compression circuits (207B to 207D) corresponding to the CPUs (10B to 10D) that have not determined the test results stop while holding the test results after compression.
- the recursive compression circuit (208) recompresses the test result of the CPU (10A) from the second result compression circuit (207A).
- the comparison circuit (209) determines the test result after compression by the recursive compression circuit (208) (S507).
- the specific operation in step S507 is the same as that in step S104 in FIG. 3 in the first embodiment, and a description thereof will be omitted. The same applies to the operations for CPUs (10B to 10D) described later
- the system control circuit (15) When an error is notified from the comparison circuit (209) as a diagnosis result of the CPU (10A) (S507: Abnormal), the system control circuit (15) performs a process of quickly stopping the system and stops the system (S527). ). That is, the system control circuit (15) suppresses activation of the semiconductor device (1H). The same applies to the operations for CPUs (10B to 10D) described later.
- the second test control circuit (200B) or the second result compression circuit (207B) controls the selection circuit (502) so that the second result compression circuit (207B) is selected.
- the second result compression circuit (207B) corresponding to the CPU (10B) serially outputs the test result after compression to the recursive compression circuit (208) bit by bit via the selection circuit (502).
- the other second result compression circuit (207C, 207D) corresponding to the CPU (10C, 10D) that has not determined the test result stops while holding the test result after compression.
- the recursive compression circuit (208) recompresses the test result of the CPU (10B) from the second result compression circuit (207B).
- the comparison circuit (209) determines the test result after compression by the recursive compression circuit (208) (S508).
- the second test control circuit (200C) or the second result compression circuit (207C) controls the selection circuit (502) so that the second result compression circuit (207C) is selected.
- the second result compression circuit (207C) corresponding to the CPU (10C) serially outputs the test result after compression to the recursive compression circuit (208) bit by bit via the selection circuit (502).
- the other second result compression circuit (207D) corresponding to the CPU (10D) that has not determined the test result stops while holding the test result after compression.
- the recursive compression circuit (208) recompresses the test result of the CPU (10C) from the second result compression circuit (207C).
- the comparison circuit (209) determines the test result after compression by the recursive compression circuit (208) (S509).
- the second test control circuit (200D) or the second result compression circuit (207D) controls the selection circuit (502) so that the second result compression circuit (207D) is selected.
- the second result compression circuit (207D) corresponding to the CPU (10D) outputs the test result after compression to the recursive compression circuit (208) serially bit by bit through the selection circuit (502).
- the recursive compression circuit (208) recompresses the test result of the CPU (10D) from the second result compression circuit (207D).
- the comparison circuit (209) determines the test result after compression by the recursive compression circuit (208) (S510).
- the eighth embodiment is different from the seventh embodiment in that a device (second test control device (4)) for performing a scan test for detecting LF is provided for each CPU. That is, each of the plurality of second test control devices performs the scan test in the startup diagnosis in parallel with each other. Thereby, since the LF detection of a plurality of CPUs can be performed at the same time, the time required for the startup diagnosis can be shortened.
- examples of a plurality of CPUs in a multiprocessor have been described as a plurality of circuits to be tested.
- the present invention is not limited to this.
- a plurality of cores in a multi-core may be targeted. That is, various arithmetic circuits can be targeted as the circuit under test.
- the in-startup diagnosis may be performed on two or more CPUs simultaneously (for example, two or three). However, preferably, as described above, it is possible to reduce deterioration in system performance during the startup diagnosis by not performing the startup diagnosis on two or more CPUs at the same time.
- the startup diagnosis may be performed on the circuit under test (40) for which the startup diagnosis is performed during the startup of the semiconductor device (1C) after the startup of the semiconductor device (1C) is completed.
- the system control circuit negates the diagnosis start signal for the second test control device (52) after completing the startup diagnosis of the circuit under test (40).
- a diagnosis start signal asserted via the system bus (13) may be output to each of them.
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Abstract
Description
図1を参照して、後述の実施の形態に係る半導体装置の概略構成について説明する。図1は、後述の実施の形態に係る半導体装置の概略となる半導体装置を示すブロック図である。
[全体構成]
続いて、実施の形態1について説明する。図2を参照して、実施の形態1に係る半導体装置(1A)の構成について説明する。図2は、実施の形態1に係る半導体装置(1A)の構成を示すブロック図である。
第1のテスト制御装置(3)の構成要素は、全体構成の説明で述べた通りである。第1のテスト制御回路(100)は、システムバス(13)を介して、CPU(10)と接続されている。第1のテスト制御回路(100)は、CPU(10)からの要求に従い、CPU(10)のスキャンテストを実行する。
第2のテスト制御装置(4)の構成要素は、全体構成の説明で述べた通りである。第2のテスト制御回路(200)は、システム制御回路(15)と接続されている。第2のテスト制御回路(200)は、システム制御回路(15)からの要求に従い、CPU(10)のスキャンテストを実行する。
共通結果判定装置(5)の構成要素は、全体構成の説明で述べた通りである。再帰型圧縮回路(208)は、圧縮後のテスト結果を時間軸方向に圧縮する。再帰型圧縮回路(208)は、例えば、SISR(Single Input signature Register)のように、自身に格納されるデータを循環させながら、入力されたデータと自身に格納されるデータとのXOR演算をし、その演算結果を自身に格納する複数ビットのレジスタで構成されている。再帰型圧縮回路(208)は、比較回路(209)と接続されている。再帰型圧縮回路(208)は、圧縮後のテスト結果を比較回路(209)に出力する。
半導体装置(1A)は、その電源が投入され、第2のテスト制御装置(4)及び共通結果判定装置(5)のリセットが解除されると、最初に、LFを検出するための診断を行う。以下、この診断を「起動時診断」とも言う。起動時診断には、第2のテスト制御装置(4)と共通結果判定装置(5)が用いられる。ここで、LFが検出されなければ、半導体装置(1A)は、通常動作を開始する。
起動時診断が開始されると、システム制御回路(15)は、CPU(10)の診断の開始を指示する診断開始信号をアサートして第2のテスト制御回路(200)に出力する。第2のテスト制御回路(200)は、診断開始信号のアサートに応じて、CPU(10)の診断を開始する(S101)。また、第2のテスト制御回路(200)は、診断を開始するときに、第2のテスト制御装置(4)側(図2では「2」側)を選択するように、選択回路(300、301、302)を制御する。なお、この選択回路(300、301、302)の制御は、システム制御回路(15)が診断開始信号をアサートする前に実施してもよい。
CPU(10)のLFの診断結果が正常である場合(S103:正常)、システム制御回路(15)は、CPU(10)の起動を開始する(S104)。CPU(10)は、その起動完了後、アプリケーションプログラムの処理を実行する(S105)。また、CPU(10)は、このアプリケーションプログラムの処理において、定期的(所定時間経過する毎)に自己診断を行う処理も実行する。所定時間が経過して自己診断を行う処理に入ると(S106:Yes)、CPU(10)は、システムバス(13)を介して、CPU(10)の診断の開始を指示する診断開始信号をアサートして第1のテスト制御回路(100)に出力し、自身は処理を停止した状態(例えば、スリープ状態)に遷移する(S107)。
本実施の形態1の構成および動作において、SPFとLFの両方の検出が実施できており、機能安全が有効とされている理由を、以下に説明する。
続いて、実施の形態1の変形例について説明する。図4を参照して、実施の形態1の変形例に係る半導体装置(1A)の自己診断時の動作について説明する。図4は、実施の形態1の変形例に係る半導体装置(1A)の自己診断時の動作を示すフロー図である。図3に示した動作において、起動時診断において、比較回路(209)が故障していないかどうかを診断する動作を追加してもよい。図4では、その動作について説明する。図4に示す動作は、図3に示した動作と比較して、ステップS101及びS102と、ステップS103との間に、ステップS112が追加されている。
続いて、実施の形態2について説明する。以下の実施の形態2の説明では、上述した実施の形態1と同様の内容については、同一の符号を付す等して、適宜、その説明を省略する。図5を参照して、実施の形態2に係る半導体装置(1B)の構成について説明する。図5は、実施の形態2に係る半導体装置(1B)の構成を示すブロック図である。
続いて、実施の形態3について説明する。以下の実施の形態3の説明では、上述した実施の形態2と同様の内容については、同一の符号を付す等して、適宜、その説明を省略する。
図6を参照して、実施の形態3に係る半導体装置(1C)の構成について説明する。図6は、実施の形態3に係る半導体装置(1C)の構成を示すブロック図である。図3に示すように、半導体装置(1C)は、実施の形態2に係る半導体装置(1B)と比較して、さらに、複数のORゲート(45、55、65)を有する。また、図6では、システムバス(13)を明示している。
システムバス(13)から出力される診断開始信号がLowレベルである場合、ORゲート(45)は、ANDゲート(44)から出力される診断開始信号をそのまま第2のテスト制御装置(42)に出力する。つまり、テスト対象設定回路(70)において被テスト回路(40)がテスト対象として設定されており、テスト対象設定回路(70)からANDゲート(44)に出力されるテスト対象設定信号がLowレベルである場合、システム制御回路(15)によって、第2のテスト制御装置(42)による起動時診断を開始することが可能である。
ここでは、テスト対象設定回路(70)において、被テスト回路(40、50、60)のうち、被テスト回路(40)のみが、半導体装置(1C)の起動時における起動時診断の対象として定められているものとする。半導体装置(1C)は、その電源が投入され、第2のテスト制御装置(42、52、62)及び共通結果判定装置(43、53、63)のリセットが解除されると、起動時診断を開始する。起動時診断が開始されると、システム制御回路(15)は、第2のテスト制御装置(42)によって被テスト回路(40)の診断を開始する(S201)。
以上に説明した本実施の形態3では、複数の起動時診断の対象のそれぞれに対して、診断の開始を指示する経路を複数有している。本実施の形態3では、電源投入直後のリセット解除後にシステム制御回路(15)から診断が起動される経路と、半導体装置(1C)のシステムの立ち上げが完了した後にシステムバス(13)を介して診断が起動される経路と、の2つの経路を有している。言い換えると、テスト対象設定回路(70)に格納された値が、第2のテスト制御装置によるスキャンテストの対象であると示す被テスト回路(40)は、テスト対象設定回路(70)に格納された値が、第2のテスト制御装置によるスキャンテストの対象でないと示す被テスト回路(50、60)のうち、所定の被テスト回路(全部又は一部の被テスト回路)に対応する第2のテスト制御装置(52、62)に対して、起動時診断(スキャンテスト)の実施を指示するようにしている。これによれば、高い安全性を担保しながらもシステムの立ち上げ時間を短縮できる。
続いて、実施の形態4について説明する。以下の実施の形態4の説明では、上述した実施の形態1と同様の内容については、同一の符号を付す等して、適宜、その説明を省略する。
図8を参照して、実施の形態4に係る半導体装置(1D)の構成について説明する。図8は、実施の形態4に係る半導体装置(1D)の構成を示すブロック図である。図8に示すように、半導体装置(1D)は、実施の形態1に係る半導体装置(1A)と比較して、第1の結果圧縮回路(206)、第2の結果圧縮回路(207)及び共通結果判定装置(5)(タイマー(205)、再帰型圧縮回路(208)及び比較回路(209))に代えて、第1の結果判定回路(102)、第1のタイマー(104)、第2の結果判定回路(202)及び第2のタイマー(204)を有する点と、さらに遮断回路(16、17)を有する点が異なる。
続いて、図9を参照して、実施の形態4に係る半導体装置(1D)の自己診断時の動作について説明する。図9は、実施の形態4に係る半導体装置(1D)の自己診断時の動作を示すフロー図である。
半導体装置(1D)は、その電源が投入され、起動時診断を実施する回路(200~204)のリセットが解除されると、その起動時診断を開始する。起動時診断が開始されると、システム制御回路(15)は、動作中診断装置(20)の診断の開始を指示する診断開始信号をアサートして第2のテスト制御回路(200)に出力する。第2のテスト制御回路(200)は、診断開始信号のアサートに応じて、動作中診断装置(20)の診断を開始する(S301)。
実施の形態4では、LFを検出するための起動時診断として、CPU(10)を含む動作中診断装置(20)全体を、診断の対象としている。言い換えると、CPU(10)とともに第1のテスト制御装置(3)のスキャンテストも実施するようにしている。本構成により、単一のCPU(10)に対して動作中にスキャンテストを実施することで、CPUを二重化するよりも低コストでその安全性を担保すると同時に、動作中診断に用いられる回路(10、100~104)の安全性についても担保する。
続いて、実施の形態5について説明する。以下の実施の形態5の説明では、上述した実施の形態4と同様の内容については、同一の符号を付す等して、適宜、その説明を省略する。
図10を参照して、実施の形態5に係る半導体装置(1E)の構成について説明する。図10は、実施の形態5に係る半導体装置(1E)の構成を示すブロック図である。図10に示すように、半導体装置(1E)は、実施の形態4に係る半導体装置(1E)と比較して、遮断回路(16)、(17)、第2のテスト制御回路(200)、パタン発生回路(201)、第2の結果判定回路(202)、第2の期待値記憶回路(203)、及び、第2のタイマー(204)を有さない点が異なる。また、半導体装置(1E)は、実施の形態4に係る半導体装置(1E)と比較して、第1のテスト制御回路(100)、パタン入力回路(101)、第1の結果判定回路(102)、第1の期待値記憶回路(103)、及び、第1のタイマー(104)に代えて、テスト制御回路(600)、パタン入力回路(601)、結果判定回路(602)、期待値記憶回路(603)、及び、タイマー(604)を有する点が異なる。また、半導体装置(1E)は、実施の形態4に係る半導体装置(1E)と比較して、さらに、ROM(400)と、選択回路(401)とを有する点が異なる。
本実施の形態5に係る半導体装置(1E)の動作については、実施の形態4に係る半導体装置(1D)の動作(図9に示した動作)と同様であるため、その説明を省略する。ただし、上述したように、半導体装置(1E)の動作は、半導体装置(1D)の動作と比較し、起動時診断と動作中診断の両方をテスト制御回路(600)、パタン入力回路(601)、結果判定回路(602)、及び、タイマー(604)が実施する点と、起動時診断と動作中診断の開始時に選択回路(401)を制御する点と、起動時診断におけるテストパタンを発生するのではなく、ROM(400)から取得する点が異なる。
本実施の形態5では、起動時診断と起動中診断を実施する回路を共用している。ここで、起動時は、システムバス(13)を含む多くのモジュールは診断のために休止状態である。そのため、テストパタンを、システムバス(13)を介して、取得することは困難である。その課題に対して、本実施の形態5では、起動時診断で利用するテストデータを専用のROM(400)に有するようにしている。すなわち、システムバス(13)を初期化しているときに、ROM(400)からテストパタンを取得し、取得したテストパタンをCPU(10)のスキャンチェーンに入力して起動時診断におけるスキャンテストを実施する。そして、システムバス(13)の初期化後に、システムバス(13)を介して外部メモリ(14)からテストパタンを取得し、取得したテストパタンをCPU(10)のスキャンチェーンに入力して動作中診断におけるスキャンテストを実施するようにしている。本構成により、起動時診断と起動中診断を実施する回路を共用しつつも、単一のCPU(10)に対して動作中にスキャンテストを実施することで、CPUを二重化するよりも低コストでその安全性を担保すると同時に、動作中診断に用いられる診断装置の安全性についても担保することができる。
続いて、実施の形態6について説明する。以下の実施の形態6の説明では、上述した実施の形態5と同様の内容については、同一の符号を付す等して、適宜、その説明を省略する。
図11を参照して、実施の形態6に係る半導体装置(1F)の構成について説明する。図11は、実施の形態6に係る半導体装置(1F)の構成を示すブロック図である。図11に示すように、半導体装置(1F)は、図10に示した実施の形態5に係る半導体装置(1E)と比較して、さらに、外部I/F(18)と、選択回路(402)とを有する点が異なる。また、半導体装置(1F)は、実施の形態5に係る半導体装置(1E)と比較して、ROM(400)を有さない点が異なる。
本実施の形態6に係る半導体装置(1F)の動作については、実施の形態5に係る半導体装置(1E)の動作と同様であるため、その説明を省略する。ただし、半導体装置(1F)の動作は、半導体装置(1E)の動作と比較し、起動時診断と動作中診断の開始時にさらに選択回路(402)を制御する点と、起動時診断におけるテストパタンをROM(400)ではなく、外部メモリ(14)から取得する点が異なる。
本実施の形態6は、実施の形態5と同様に、起動時診断と起動中診断を実施する回路を共用している。すなわち、本実施の形態6では、システムバス(13)を初期化しているときに、外部I/F(18)を介して外部メモリ(14)からテストパタンを取得し、取得したテストパタンをCPU(10)のスキャンチェーンに入力して起動時診断におけるスキャンテストを実施する。そして、システムバス(13)の初期化後に、システムバス(13)を介して外部メモリ(14)からテストパタンを取得し、取得したテストパタンをCPU(10)のスキャンチェーンに入力して動作中診断におけるスキャンテストを実施するようにしている。本構成により、起動時診断と起動中診断を実施する回路を共用しつつも、単一のCPU(10)に対して動作中にスキャンテストを実施することで、CPUを二重化するよりも低コストでその安全性を担保すると同時に、動作中診断に用いられる診断装置の安全性についても担保する。また、半導体装置(1F)がROM(400)を有する必要がないため、より低コストとすることができる。
続いて、実施の形態7について説明する。以下の実施の形態7の説明では、上述した実施の形態1と同様の内容については、同一の符号を付す等して、適宜、その説明を省略する。
[全体構成]
図12を参照して、実施の形態7に係る半導体装置(1G)の構成について説明する。図12は、実施の形態7に係る半導体装置(1G)の構成を示すブロック図である。図12に示すように、半導体装置(1G)は、実施の形態1に係る半導体装置(1A)と比較して、1つのCPU(10)ではなく、複数のCPU(10A~10D)を有する点が異なる。また、半導体装置(1G)は、実施の形態1に係る半導体装置(1A)と比較して、さらに、選択回路(501)を有する点が異なる。
第1のテスト制御回路(100)は、システムバス(13)を介して、CPU(10A~10D)のそれぞれと接続されている。第1のテスト制御回路(100)は、CPU(10A)からの要求に従い、CPU(10A)のスキャンテストを実行し、CPU(10B)からの要求に従い、CPU(10B)のスキャンテストを実行し、CPU(10C)からの要求に従い、CPU(10C)のスキャンテストを実行し、CPU(10D)からの要求に従い、CPU(10D)のスキャンテストを実行する。
本実施の形態7では、実施の形態1と同様に、第2のテスト制御回路(200)は、システム制御回路(15)からの要求に従い、CPU(10A~10D)のそれぞれのスキャンテストを実行する。ただし、本実施の形態7では、実施の形態1と異なり、その要求において、システム制御回路(15)が第2のテスト制御回路(200)に対してテスト対象とするCPUを指定する。第2のテスト制御回路(200)は、システム制御回路(15)から指定されたCPUのスキャンテストを実施する。
第1の結果圧縮回路(206)及び第2の結果圧縮回路(207)は、選択回路(501)を介して、CPU(10A~10D)のそれぞれと接続されている。選択回路(501)は、CPU(10A~10D)のうち、いずれか1つから出力されたテスト結果を選択的に第1の結果圧縮回路(206)及び第2の結果圧縮回路(207)のそれぞれに出力する。選択回路(501)は、起動時診断を開始するときに、第1の結果圧縮回路(206)及び第2の結果圧縮回路(207)との接続先としてテスト対象のCPUが選択されるように、第2のテスト制御回路(200)、若しくは、システム制御回路(15)によって制御される。例えば、第2のテスト制御回路(200A~200D)のそれぞれが、システム制御回路(15)からの診断開始信号のアサートに応じて制御してもよく、システム制御回路(15)が診断開始信号をアサートする前に制御してもよい。
続いて、図13及び図14を参照して、実施の形態7に係る半導体装置(1G)の自己診断時の動作について説明する。図13及び図14は、実施の形態7に係る半導体装置(1G)の自己診断時の動作を示すフロー図である。
半導体装置(1G)は、その電源が投入され、第2のテスト制御装置(4)及び共通結果判定装置(5)のリセットが解除されると、最初に、LFを検出するための起動時診断を行う。CPU(10A~10D)のそれぞれに対して所定の順序で起動時診断を実施する。ここでLFが検出されなければ、半導体装置(1G)は、通常動作を開始する。
起動時診断の診断動作が開始されると、システム制御回路(15)は、比較回路(209)の診断を実施する(S401)。システム制御回路(15)は、比較回路(209)の診断開始を指示する診断開始信号をアサートして第2のテスト制御回路(200)に出力する。第2のテスト制御回路(200)は、比較回路(209)の診断開始を指示する診断開始信号のアサートに応じて、比較回路(209)の診断を実施する。なお、このステップS401における動作は、実施の形態1の変形例で説明した図4のステップS112の動作と同様であるため、その説明は省略する。
全てのCPU(10A~10D)の診断結果が正常である場合、システム制御回路(15)は、実施の形態1で説明した図1のステップS104、105と同様に、全てのCPU(10A~10D)の起動を開始し(S411、S418、S421、S424)、CPU(10A~10D)のそれぞれが処理を実行する(S412、S419、S422、S425)。
実施の形態7は、マルチCPUを搭載した半導体装置(1G)においてLF及びSPFを検出する構成を示したもので、第1のテスト制御装置(3)と第2のテスト制御装置(4)と共通結果判定装置(5)を複数のCPUで共有化している。すなわち、第1のテスト制御装置(3)及び第2のテスト制御装置(4)は、複数のCPU(10A~10D)のそれぞれのスキャンテストを所定の順序で実施する。これによれば、回路面積を削減することができる。また、実施の形態1における特徴と効果も併せ持っており、搭載するCPUの数に比例して診断用のCPUが増えることが無いため、CPU数が増えるほど、本実施の形態7による面積、電力削減効果は大きなものとなる。
続いて、実施の形態8について説明する。以下の実施の形態8の説明では、上述した実施の形態1と同様の内容については、同一の符号を付す等して、適宜、その説明を省略する。
[全体構成]
図15を参照して、実施の形態8に係る半導体装置(1H)の構成について説明する。図15は、実施の形態8に係る半導体装置(1H)の構成を示すブロック図である。図15に示すように、半導体装置(1G)は、実施の形態1に係る半導体装置(1A)と比較して、複数のCPU(10A、10B、10C、10D)と、複数の第2のテスト制御回路(200A~200D)と、複数のパタン発生回路(201A~201D)と、複数の結果圧縮回路(207A~207D)と、複数の選択回路(300A~300D)とを有する点が異なる。また、半導体装置(1G)は、実施の形態1に係る半導体装置(1A)と比較して、さらに、ANDゲート(500)と、選択回路(501)と、選択回路(502)と、ANDゲート(503)とを有する点が異なる。
第1のテスト制御回路(100)は、システムバス(13)を介して、CPU(10A~10D)のそれぞれと接続されている。第1のテスト制御回路(100)は、CPU(10A)からの要求に従い、CPU(10A)のスキャンテストを実行し、CPU(10B)からの要求に従い、CPU(10B)のスキャンテストを実行し、CPU(10C)からの要求に従い、CPU(10C)のスキャンテストを実行し、CPU(10D)からの要求に従い、CPU(10D)のスキャンテストを実行する。
第2のテスト制御回路(200A~200D)のそれぞれは、システム制御回路(15)と接続されている。第2のテスト制御回路(200A)は、システム制御回路(15)からの要求に従い、CPU(10A)のスキャンテストを実行する。第2のテスト制御回路(200B)は、システム制御回路(15)からの要求に従い、CPU(10B)のスキャンテストを実行する。第2のテスト制御回路(200C)は、システム制御回路(15)からの要求に従い、CPU(10C)のスキャンテストを実行する。第2のテスト制御回路(200D)は、システム制御回路(15)からの要求に従い、CPU(10D)のスキャンテストを実行する。
ANDゲート(500)は、第2のテスト制御回路(200A~200D)のそれぞれから出力された開始通知信号をAND演算し、演算結果となる開始通知信号をタイマー(205)に出力する。すなわち、タイマー(205)は、第2のテスト制御回路(200A~200D)の全てが開始通知信号を出力した時点からの経過時間の計測を開始する。
続いて、図16及び図17を参照して、実施の形態8に係る半導体装置(1H)の自己診断時の動作について説明する。図16及び図17は、実施の形態8に係る半導体装置(1H)の自己診断時の動作を示すフロー図である。
半導体装置(1H)は、その電源が投入され、複数の第2のテスト制御装置(4)及び共通結果判定装置(5)のリセットが解除されると、最初に、LFを検出するための診断動作を行う。LFの検出には、複数の第2のテスト制御装置(4)と共通結果判定装置(5)が用いられ、CPU(10A~10D)のそれぞれの起動時診断は、そのテスト結果の判定を除き、同時並列に実施される。ここでLFが検出されなければ、半導体装置(1H)は、通常動作を開始する。
起動時診断の診断動作が開始されると、システム制御回路(15)は、比較回路(209)の診断を実施する(S501)。システム制御回路(15)は、比較回路(209)の診断開始を指示する診断開始信号をアサートして第2のテスト制御回路(200A~200D)に出力する。第2のテスト制御回路(200A~200D)は、比較回路(209)の診断開始を指示する診断開始信号のアサートに応じて、比較回路(209)の診断を実施する。なお、このステップS501における動作は、実施の形態1の変形例で説明した図4のステップS112の動作と同様であるため、その説明は省略する。
全てのCPU(10A~10D)の診断結果が正常である場合、システム制御回路(15)は、ステップS511~S527、S20~S23の動作を行う。なお、ステップS511~S527、S20~S23の動作は、実施の形態7におけるステップS411~427、S10~13の動作と同様であるため、それらの説明は省略する。
実施の形態8は、実施の形態7に対して、LFを検出するためのスキャンテストを実施する装置(第2のテスト制御装置(4))をCPU毎に設けたものである。すなわち、複数の第2のテスト制御装置のそれぞれが、相互に並行して起動時診断におけるスキャンテストのそれぞれの実施するようにしている。これにより、複数のCPUのLF検出が同時に実施できるため、起動時診断にかかる時間を短縮することができる。
2、40、50、60 被テスト回路
3、41、51、61 第1のテスト制御装置
4、42、52、62 第2のテスト制御装置
5、43、53、63 共通結果判定装置
10、10A、10B、10C、10D CPU
11 内蔵メモリ
12 外部I/F
13 システムバス
14 外部メモリ
15 システム制御回路
16、17 遮断回路
20 動作中診断装置
44、54、64、500 ANDゲート
45、55、65 ORゲート
70 テスト対象設定回路
100 第1のテスト制御回路
101 パタン入力回路
102 第1の結果判定回路
103 第1の期待値記憶回路
104 第1のタイマー
200、200A、200B、200C、200D 第2のテスト制御回路
201、201A、201B、201C、201D パタン発生回路
202 第2の結果判定回路
203 第2の期待値記憶回路
204 第2のタイマー
205 タイマー
206 第1の結果圧縮回路
207、207A、207B、207C、207D 第2の結果圧縮回路
208 再帰型圧縮回路
209 比較回路
203 第2の期待値記憶回路
300、300A、300B、300C、300D、301、302、401、402、501、502 選択回路
400 ROM
600 テスト制御回路
601 パタン入力回路
602 結果判定回路
603 期待値記憶回路
Claims (13)
- スキャンチェーンを有する被テスト回路と、
前記スキャンチェーンを用いて前記被テスト回路のスキャンテストを実施する第1のテスト制御装置及び第2のテスト制御装置と、を備え、
前記第2のテスト制御装置は、前記被テスト回路に対し第2のスキャンテストを実施し、
前記被テスト回路が、前記第2のスキャンテストが実施された後に、前記第1のテスト制御装置に第1のスキャンテストの実施を指示し、
前記第1のテスト制御装置は、前記被テスト回路からの指示に応じて、前記被テスト回路に対し第1のスキャンテストを実施する、
を備えた半導体装置。 - 前記第2のテスト制御装置は、前記半導体装置の起動時に、テストパタンを生成して前記スキャンチェーンに入力することで、前記第2のスキャンテストを実施するものであり、
前記第1のテスト制御装置は、前記半導体装置の起動完了後に、前記半導体装置に接続された外部記憶回路からテストパタンを取得し、前記スキャンチェーンに入力することで、前記第1のスキャンテストを実施するものである、
請求項1に記載の半導体装置。 - 前記半導体装置は、前記第1のスキャンテスト及び前記第2のスキャンテストのそれぞれによって前記被テスト回路から取得したテスト結果を判定する結果判定装置を更に備えた、
請求項2に記載の半導体装置。 - 前記半導体装置は、前記スキャンテストの実施時間を計測し、計測した実施時間が所定の閾値を超えた場合に、エラーを通知するタイマーをさらに備え、
前記第1のテスト制御装置及び前記第2のテスト制御装置のそれぞれは、前記被テスト回路のスキャンテストを開始するときに、前記実施時間の計測開始を前記タイマーに指示し、前記被テスト回路のスキャンテストを終了したときに、前記実施時間の計測終了を前記タイマーに指示する、
請求項1に記載の半導体装置。 - 前記半導体装置は、前記第2のスキャンテストによって前記被テスト回路から取得したテスト結果の期待値である第2の期待値が格納される第2の期待値記憶部と、
前記第2のスキャンテストによって前記被テスト回路から取得した第2のテスト結果と、前記第2の期待値記憶部に格納された第2の期待値とを比較し、一致する場合には正常であると判定し、一致しない場合にはエラーであると判定する結果判定装置と、
前記結果判定装置の判定結果に応じて、前記半導体装置を制御するシステム制御回路と、をさらに備え、
前記システム制御回路は、前記第2のスキャンテストを実施する前に、前記結果判定装置に異なる値を比較させて、一致すると判定された場合に、前記半導体装置の動作を停止させる、
請求項1に記載の半導体装置。 - 前記半導体装置は、
複数の前記被テスト回路と、
前記複数の被テスト回路のそれぞれのスキャンテストを実行する複数の前記第2のテスト制御装置と、を備え、
前記複数の第2のテスト制御装置のそれぞれは、前記半導体装置の起動時に、前記第2のスキャンテストを実施するものであり、
前記第1のテスト制御装置は、前記半導体装置の起動後に、前記第1のスキャンテストを実施するものであり、
前記半導体装置は、前記複数の被テスト回路のそれぞれについて、前記半導体装置の起動時における、前記第2のスキャンテストの対象であるか否かを示すテスト対象値が格納されるテスト対象設定回路をさらに備え、
前記複数の第2のテスト制御装置のそれぞれは、前記テスト対象値に従って、前記第2のスキャンテストを実施する、
請求項1に記載の半導体装置。 - 前記複数の被テスト回路のそれぞれは、前記第2のスキャンテストが実施された後に起動されて、前記第1のスキャンテストの指示を含む処理を実行し、
前記テスト対象値が前記第2のスキャンテストの対象であると示す被テスト回路は、前記処理において、前記半導体装置の起動後に、前記テスト対象値が前記第2のスキャンテストの対象でないと示す被テスト回路のうち、所定の被テスト回路に対応する第2のテスト制御装置に対して、前記第2のスキャンテストの実施を指示する、
請求項6に記載の半導体装置。 - 前記第2のテスト制御装置は、前記被テスト回路とともに前記第1のテスト制御装置のスキャンテストも実施する、
請求項1に記載の半導体装置。 - 前記第1のテスト制御装置及び前記第2のテスト制御装置は、同一のテスト制御装置であり、
前記半導体装置は、
前記テスト制御装置が前記半導体装置に接続された外部記憶回路から前記第1のスキャンテストで前記スキャンチェーンに入力するテストパタンを取得する際に使用されるシステムバスと、
前記第2のスキャンテストで前記スキャンチェーンに入力するテストパタンが格納された内部記憶回路と、をさらに備え、
前記テスト制御装置は、
前記システムバスを初期化しているときに、前記内部記憶回路から前記テストパタンを取得し、取得したテストパタンを前記スキャンチェーンに入力して前記第2のスキャンテストを実施し、
前記システムバスの初期化後に、前記システムバスを介して前記外部記憶回路から前記テストパタンを取得し、取得したテストパタンを前記スキャンチェーンに入力して前記第1のスキャンテストを実施する、
請求項1に記載の半導体装置。 - 前記第1のテスト制御装置及び前記第2のテスト制御装置は、同一のテスト制御装置であり、
前記半導体装置は、
前記テスト制御装置が前記半導体装置に接続された外部記憶回路から前記第1のスキャンテスト及び前記第2のスキャンテストで前記スキャンチェーンに入力するテストパタンを取得する際に使用されるシステムバスと、
前記テスト制御装置が前記外部記憶回路から前記システムバスを介さずに前記テストパタンを取得する際に使用される外部インターフェース回路と、をさらに備え、
前記テスト制御装置は、
前記システムバスを初期化しているときに、前記外部インターフェース回路を介して前記外部記憶回路から前記テストパタンを取得し、取得したテストパタンを前記スキャンチェーンに入力して前記第2のスキャンテストを実施し、
前記システムバスの初期化後に、前記システムバスを介して前記外部記憶回路から前記テストパタンを取得し、取得したテストパタンを前記スキャンチェーンに入力して前記第1のスキャンテストを実施する、
請求項1に記載の半導体装置。 - 前記半導体装置は、複数の前記被テスト回路を備え、
前記第1のテスト制御装置及び前記第2のテスト制御装置は、前記複数の被テスト回路のそれぞれのスキャンテストを所定の順序で実施する、
請求項1に記載の半導体装置。 - 前記半導体装置は、
複数の前記被テスト回路と、
前記複数の被テスト回路のそれぞれのスキャンテストを実行する複数の前記第2のテスト制御装置と、を備え、
前記複数の第2のテスト制御装置のそれぞれは、前記半導体装置の起動時に、前記第2のスキャンテストを実施するものであり、
前記第1のテスト制御装置は、前記半導体装置の起動後に、前記第1のスキャンテストを実施するものであり、
前記複数の第2のテスト制御装置のそれぞれは、相互に並行して前記第2のスキャンテストのそれぞれの実施する、
請求項1に記載の半導体装置。 - 第2のテスト制御装置が、被テスト回路が有するスキャンチェーンを用いて前記被テスト回路に対しスキャンテストを実施し、
前記被テスト回路が、前記第2のテスト制御装置によるスキャンテストが実施された後に、第1のテスト制御装置にスキャンテストの実施を指示し、
前記第1のテスト制御装置が、前記被テスト回路からの指示に応じて、前記被テスト回路が有するスキャンチェーンを用いて前記被テスト回路に対し第1のスキャンテストを実施する、
診断テスト方法。
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