WO2016165291A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

Info

Publication number
WO2016165291A1
WO2016165291A1 PCT/CN2015/091005 CN2015091005W WO2016165291A1 WO 2016165291 A1 WO2016165291 A1 WO 2016165291A1 CN 2015091005 W CN2015091005 W CN 2015091005W WO 2016165291 A1 WO2016165291 A1 WO 2016165291A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
spacer
film transistor
thin film
array substrate
Prior art date
Application number
PCT/CN2015/091005
Other languages
English (en)
French (fr)
Inventor
朱亚文
莫再隆
樊浩原
胡伟
周全国
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2016165291A1 publication Critical patent/WO2016165291A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13398—Spacer materials; Spacer properties

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a display device.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the thin film transistor included in the thin film transistor liquid crystal display is a semiconductor element, and its performance is easily affected by light, thereby generating a light leakage phenomenon, resulting in picture defects such as crosstalk and flicker.
  • the present disclosure provides an array substrate, a display panel, and a display device for solving the problem that light reflected by the color filter substrate affects the performance of the thin film transistor.
  • an array substrate including a thin film transistor disposed on a substrate and a spacer disposed on the thin film transistor.
  • the projection of the thin film transistor on the substrate substrate completely falls into the projection of the spacer on the substrate.
  • the spacer wraps the thin film transistor.
  • the spacer is made of an opaque material.
  • a display panel further includes an array substrate and a color filter substrate disposed opposite to each other, and a spacer between the array substrate and the color filter substrate.
  • the array substrate includes a thin film transistor disposed on a base substrate, and a projection of the thin film transistor on the base substrate completely falls into a projection of the spacer on the base substrate such that the The spacer is capable of blocking light reflected by the color filter substrate from being incident on the thin film transistor.
  • the spacer surrounds the thin film transistor.
  • the spacer is disposed on the array substrate, The spacer is disposed on the color filter substrate.
  • a black matrix is disposed on the color filter substrate, and a projection of the spacer on the color filter substrate is completely covered by the black matrix.
  • the spacer is made of an opaque material.
  • the spacer has a trapezoidal shape in a longitudinal section.
  • a display device including the display panel as described above is also provided in the embodiment of the present disclosure.
  • the liquid crystal panel includes an array substrate and a color filter substrate of the pair of boxes, and a spacer between the array substrate and the color filter substrate.
  • the array substrate includes a thin film transistor disposed on a base substrate.
  • FIG. 1 is a schematic structural view of a liquid crystal panel in the related art
  • FIG. 2 is a schematic structural view 1 of an array substrate in an embodiment of the present disclosure
  • FIG. 3 is a schematic structural view 2 of an array substrate in an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural view 1 of a liquid crystal panel in an embodiment of the present disclosure.
  • FIG. 5 is a second structural diagram of a liquid crystal panel according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural view 3 of a liquid crystal panel according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic view showing the structure of a liquid crystal panel according to an embodiment of the present disclosure.
  • the main structure of the liquid crystal display is a liquid crystal panel.
  • the liquid crystal panel includes an array substrate 10 and a color filter substrate 20 provided to the cartridge, and a liquid crystal layer 40 filled between the array substrate 10 and the color filter substrate 20.
  • the cell thickness of the liquid crystal panel is mainly controlled by a spacer (Post Spacer, PS) 30' formed between the array substrate 10 and the color filter substrate 20.
  • the array substrate 10 is formed with data lines and gate lines (not shown) for defining a plurality of pixel units, each of which includes a thin film transistor 1 and a pixel electrode 6.
  • the pixel voltage transmitted on the data line is transmitted to the pixel electrode 6 through the thin film transistor 1 for forming an electric field for driving the deflection of the liquid crystal molecules to realize display.
  • the thin film transistor 1 is a semiconductor element whose performance is easily affected by light. Materials in the prior art inevitably have a reflective effect on light. Therefore, in the TFT-LCD, the light reflected by the material film on the color filter substrate 20 is irradiated onto the thin film transistor 1 on the array substrate 10, causing a light leakage phenomenon, affecting the performance of the thin film transistor 1, resulting in poor picture such as crosstalk and flicker. .
  • the present disclosure provides a liquid crystal panel including a color film substrate and an array substrate disposed opposite to each other, and a spacer between the color film substrate and the array substrate, wherein the spacer is used to support the panel and The cell thickness is determined, and liquid crystal molecules are filled in a sealed space between the color filter substrate and the array substrate.
  • the array substrate includes a thin film transistor disposed on a substrate, and the projection of the thin film transistor on the substrate is completely dropped into a projection of the spacer on the substrate, so that the spacer
  • the light that can block the reflection of the color filter substrate is irradiated to the thin film transistor, which can improve the performance of the thin film transistor and improve the picture display quality of the display device.
  • the spacer may be disposed on the color filter substrate or on the array substrate.
  • the longitudinal section of the spacer is set to be trapezoidal in the actual manufacturing process (as shown in FIG. 1-7), that is, the bottom of the spacer is large and small at the top.
  • the end of the spacer in fixed contact with the color filter substrate is the bottom, and the opposite end is the top.
  • the end of the spacer in fixed contact with the array substrate is the bottom, and the opposite end is the top.
  • an array substrate 10 specifically a thin film transistor array substrate, is provided in the embodiment of the present disclosure.
  • the array substrate 10 includes a first base substrate 100, a thin film transistor 1 disposed on the first base substrate 100, and a spacer 30 disposed on the thin film transistor 1, and the thin film transistor 1 is on the first base substrate 100.
  • the projection completely falls into the projection of the spacer 30 on the first base substrate 100, so that the spacer 30 can block the light incident from the display side from being incident on the thin film transistor 1, preventing the thin film transistor 1 from generating light leakage, and improving Characteristics of the thin film transistor 1.
  • the spacer 30 encloses the thin film transistor 1 so that the spacer 30 blocks the light incident from the display side to illuminate the thin film transistor 1 better, as shown in FIG.
  • the spacer 30 may be disposed on the thin film transistor 1 with the thin film transistor 1 wrapped at the bottom.
  • the projection of the thin film transistor on the array substrate on the substrate substrate completely falls into the projection of the spacer on the substrate, so that the spacer can block the light incident from the display side.
  • the thin film transistor prevents the thin film transistor from generating light leakage and improves the characteristics of the thin film transistor.
  • the spacer 30 is preferably made of an opaque material and has an absorption effect on light.
  • the barrier efficiency against light can be further improved with respect to the spacer 30 made of a light-transmitting material.
  • a protective layer 102 is usually disposed between the thin film transistor 1 and the spacer 30, that is, the spacer 30 is disposed on the protective layer 102.
  • the protective layer 102 is an insulating material such as silicon nitride, silicon oxide or silicon oxynitride, and may have a single layer, a double layer or a multilayer structure. Specifically, the material of the protective layer 102 may be SiNx, SiOx or Si(ON)x.
  • the protective layer 102 is provided to have a thin thickness and only serves to protect the thin film transistor 1.
  • the spacer 30 is disposed on the protective layer 102, and the spacer 30 wraps the film Transistor 1, as shown in Figure 3.
  • the protective layer 102 is provided to be thicker, not only to protect the thin film transistor 1, but also to provide a flat surface.
  • the spacer 30 is disposed on the protective layer 102, and the projection of the thin film transistor 1 on the first substrate 100 completely falls into the projection of the spacer 30 on the first substrate 100 as shown in FIG. Since the protective layer 102 is thicker, the height of the spacer 30 can be reduced in a case of a certain thickness, as shown in FIGS. 2 and 3.
  • the spacer 30 is provided of an opaque material.
  • the longitudinal cross-sectional shape of the spacer 30 is trapezoidal, that is, the bottom of the spacer 30 is large at the top.
  • the bottom substrate type thin film transistor array substrate is taken as an example, and the array substrate in the embodiment of the present disclosure specifically includes:
  • the first base substrate 100 is a transparent substrate such as a glass substrate, a quartz substrate, or an organic resin substrate;
  • a plurality of gate lines and a plurality of data lines (not shown) disposed on the first base substrate 100 for defining a plurality of pixel regions;
  • Each pixel area includes:
  • the thin film transistor 1 disposed on the first base substrate 100, the thin film transistor 1 including a gate electrode 2, an active layer 3, a source electrode 4, and a drain electrode 5, and a gate insulating layer is disposed between the gate electrode 2 and the active layer 3.
  • the material of the gate insulating layer 101 may be an oxide, a nitride or an oxynitride, and may be a single layer, a double layer or a multilayer structure.
  • the material of the gate insulating layer 101 may be SiNx, SiOx or Si(ON)x.
  • the source electrode 4 and the drain electrode 5 are overlapped on the active layer 3;
  • a pixel electrode 6 one end of the pixel electrode 6 is located between the active layer 3 and the drain electrode 5;
  • the thickness of the protective layer 102 is thin;
  • the common electrode 7 disposed on the protective layer 102 has a position corresponding to the position of the pixel electrode 6, and the common electrode 7 has a plurality of slits for cooperating with the pixel electrode 6 to form a driving electric field.
  • the array substrate 10 may not include the common electrode 7 , and the pixel electrode 6 is disposed on the protective layer 102 and is in electrical contact with the drain electrode 5 through the via hole in the protective layer 102 .
  • the thin film transistor 1 in the embodiment of the present disclosure is not limited to the bottom gate type thin film transistor, and may also be It is a top gate thin film transistor or a coplanar thin film transistor.
  • a display panel including an opposite array substrate 10 and a color filter substrate 20 and between the array substrate 10 and the color filter substrate 20 is further provided in the embodiment of the present disclosure.
  • the spacer 30 has a liquid crystal molecular layer 40 filled in a sealed space between the array substrate 10 and the color filter substrate 20.
  • the color film substrate 20 is located on one side of the display screen.
  • the array substrate 10 includes the thin film transistor 1 disposed on the first substrate 100, and the projection of the thin film transistor 1 on the first substrate 100 completely falls into the projection of the spacer 30 on the first substrate 100. Therefore, the spacer 30 can block the light reflected by the color filter substrate 20 from being incident on the thin film transistor 1, preventing the thin film transistor 1 from generating a light leakage phenomenon, and improving the characteristics of the thin film transistor 1.
  • a black matrix 8 is disposed on the color filter substrate 20, and the projection of the spacer 30 on the color filter substrate 20 is completely covered by the black matrix.
  • the light reflected by the color filter substrate 20 is specifically the second substrate 200 of the color filter substrate 20, and the light reflected by the black matrix 8, the filter layer 9, and the flat layer 201 formed on the second substrate 200.
  • the projection of the thin film transistor on the array substrate completely falls into the projection of the spacer on the array substrate, so that the spacer can block the light reflected by the color filter substrate from being irradiated to the thin film transistor, thereby preventing the thin film transistor from being generated.
  • the light leakage phenomenon improves the characteristics of the thin film transistor and improves the display quality of the picture.
  • the spacer 30 encloses the thin film transistor 1 so that the spacer 30 blocks the light reflected by the color filter substrate 20 from illuminating the thin film transistor 1 better, as shown in FIGS. 4 and 5.
  • the bottom of the spacer 30 encloses the thin film transistor 1, as shown in FIG. 4, wherein the bottom of the spacer 30 is the spacer 30 and the array substrate. 10 fixed contact ends.
  • the top of the spacer 30 encloses the thin film transistor 1, as shown in FIG. 5, wherein the top of the spacer 30 is the spacer 30 away from the color filter substrate 20. The end.
  • the spacer 30 is preferably made of an opaque material and has an absorption effect on light.
  • the barrier efficiency against light is improved relative to the spacer 30 made of a light transmissive material.
  • a protective layer 102 is usually disposed between the thin film transistor 1 and the spacer 30, that is, the spacer 30 is disposed on the protective layer 102.
  • the protective layer 102 is an insulating material such as nitrogen. Silicon, silicon oxide or silicon oxynitride may be a single layer, a double layer or a multilayer structure. Specifically, the material of the protective layer 102 may be SiNx, SiOx or Si(ON)x.
  • the protective layer 102 is provided to have a thin thickness and only serves to protect the thin film transistor 1.
  • the spacer 30 is made of an opaque material, is disposed on the protective layer 102 of the array substrate 10, and the bottom of the spacer 30 encloses the thin film transistor 1, as shown in FIG.
  • the spacer 30 may also be disposed on the color filter substrate 20, and the top of the spacer 30 encloses the thin film transistor 1, as shown in FIG.
  • the protective layer 102 is provided to be thicker, not only to protect the thin film transistor 1, but also to provide a flat surface.
  • the spacer 30 is made of an opaque material and is disposed on the protective layer 102 of the array substrate 10. The projection of the thin film transistor 1 on the first substrate 100 completely falls into the spacer 30 on the first substrate 100. In the above projection, as shown in Figure 6. Since the thickness of the protective layer 102 is thick, the height of the spacer 30 can be reduced with a certain thickness of the case, as shown in Fig. 4 and Fig. 6.
  • the spacers 30 may also be disposed on the color filter substrate 20, and the projection of the thin film transistor 1 on the first substrate substrate 100 completely falls on the spacers 30 on the first substrate substrate 100.
  • the projection as shown in Figure 7.
  • a person skilled in the art can make a meaningless introduction.
  • the spacer 30 blocks the light reflected by the color filter substrate 20 from being incident on the thin film transistor 1, it is necessary to provide the thin film transistor 1 on the first base substrate 100.
  • the projection completely falls into the projection of the spacer 30 away from the top of the color filter substrate 20 on the first base substrate 100, as shown in FIG.
  • the top of the spacer 30 may be flattened to simplify the manufacturing process of the spacer 30.
  • the spacer 30 is disposed on the array substrate 10, and the bottom of the spacer 30 is disposed to wrap the thin film transistor. Since the surface of the color filter substrate 20 is flat, the supporting force of the spacer 30 can be effectively improved, the stability of the panel thickness can be improved, the unevenness of the screen unevenness can be reduced, and the display quality of the screen can be improved. At the same time, since the bottom of the spacer 30 is the largest, it is possible to better protect the thin film transistor 1 from being irradiated by the light reflected by the color filter substrate 20.
  • the display panel in the embodiment of the present disclosure specifically includes:
  • the array substrate 10 includes:
  • the first base substrate 100 is a transparent substrate such as a glass substrate, a quartz substrate, or an organic resin substrate;
  • a plurality of gate lines and a plurality of data lines (not shown) disposed on the first base substrate 100 to define a plurality of pixel regions;
  • Each pixel area includes:
  • the thin film transistor 1 disposed on the first base substrate 100, the thin film transistor 1 including a gate electrode 2, an active layer 3, a source electrode 4, and a drain electrode 5, and a gate insulating layer is disposed between the gate electrode 2 and the active layer 3.
  • the material of the gate insulating layer 101 may be an oxide, a nitride or an oxynitride, and may be a single layer, a double layer or a multilayer structure.
  • the material of the gate insulating layer 101 may be SiNx, SiOx or Si(ON)x.
  • the source electrode 4 and the drain electrode 5 are overlapped on the active layer 3;
  • a pixel electrode 6 one end of the pixel electrode 6 is located between the active layer 3 and the drain electrode 5;
  • the thickness of the protective layer 102 is thin;
  • the spacer 30 disposed on the protective layer 102 is located between the array substrate 10 and the color filter substrate 20, the bottom of the spacer 30 wraps the thin film transistor 1;
  • the common electrode 7 disposed on the protective layer 102 corresponds to the position of the pixel electrode 6, and the common electrode 7 has a plurality of slits for cooperating with the pixel electrode 6 to form a driving electric field;
  • the color filter substrate 20 includes:
  • the second base substrate 200 is a transparent substrate such as a glass substrate, a quartz substrate, or an organic resin substrate;
  • the black matrix 8 disposed on the second substrate 200 corresponds to the gate lines and the data line positions on the array substrate 10 for defining a plurality of pixel regions;
  • a filter layer 9 located in the pixel region such as a red filter layer, a green filter layer or a blue filter layer;
  • the flat layer 201 covering the black matrix 8 and the filter layer 9 is covered.
  • the common electrode 6 may also be disposed on the color film substrate 20, and may be specifically disposed on the flat layer 201.
  • the pixel electrode 6 is disposed on the protective layer 102, and is electrically contacted with the drain electrode 5 through the via hole in the protective layer 102.
  • a display device including a display panel in an embodiment of the present disclosure, is further provided in an embodiment of the present disclosure. Thereby improving the quality of the product and the quality of the picture display.
  • the display device further includes a backlight.
  • the display panel includes an array substrate and a color filter substrate.
  • the backlight is disposed on a side of the array substrate opposite to the color filter substrate, and the color filter substrate is located on one side of the display screen.
  • the display device may be any product or component having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the liquid crystal panel includes an array substrate and a color filter substrate disposed opposite to each other, and a spacer between the array substrate and the color filter substrate, and the array substrate includes a thin film transistor disposed on the base substrate.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

提供了一种阵列基板（10）、显示面板及显示装置。显示面板包括对盒的阵列基板（10）和彩膜基板（20），以及位于阵列基板（10）和彩膜基板（20）之间的隔垫物（30），阵列基板（10）包括设置在衬底基板（100）上的薄膜晶体管（1），通过设置薄膜晶体管（1）在衬底基板（100）上的投影完全落入隔垫物（30）在衬底基板（100）上的投影中，使得隔垫物（30）能够保护薄膜晶体管（1）不被彩膜基板（20）反射的光线照射。

Description

阵列基板、显示面板及显示装置
相关申请的交叉引用
本申请主张在2015年4月17日在中国提交的中国专利申请号No.201510184911.9的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，特别是涉及一种阵列基板、显示面板及显示装置。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，简称TFT-LCD)具有体积小，功耗低，无辐射等特点，近年来得到迅速发展，在当前的平板显示器市场中占据主导地位。
但薄膜晶体管液晶显示器中包括的薄膜晶体管为半导体元件，其性能容易受到光线的影响，进而产生光漏电现象，导致串扰、闪烁等画面不良。
发明内容
本公开提供一种阵列基板、显示面板及显示装置，用以解决彩膜基板反射的光线会影响薄膜晶体管的性能的问题。
为解决上述技术问题，本公开实施例中提供一种阵列基板，包括设置在衬底基板上的薄膜晶体管以及设置在薄膜晶体管上的隔垫物。所述薄膜晶体管在所述衬底基板上的投影完全落入所述隔垫物在所述衬底基板上的投影中。
如上所述的阵列基板，可选的是，所述隔垫物包裹住所述薄膜晶体管。
如上所述的阵列基板，可选的是，所述隔垫物由不透光材料制成。
本公开实施例中还提供一种显示面板，包括相对设置的阵列基板和彩膜基板，以及位于所述阵列基板和彩膜基板之间的隔垫物。所述阵列基板包括设置在衬底基板上的薄膜晶体管，所述薄膜晶体管在所述衬底基板上的投影完全落入所述隔垫物在所述衬底基板上的投影中，使得所述隔垫物能够阻挡所述彩膜基板反射的光线照射到所述薄膜晶体管。
如上所述的显示面板，可选的是，所述隔垫物包裹住所述薄膜晶体管。
如上所述的显示面板，可选的是，所述隔垫物设置在阵列基板上，所述 隔垫物设置在彩膜基板上。
如上所述的显示面板，可选的是，所述彩膜基板上设置有黑矩阵，所述隔垫物在所述彩膜基板上的投影完全被所述黑矩阵覆盖。
如上所述的显示面板，可选的是，所述隔垫物由不透光材料制成。
如上所述的显示面板，可选的是，所述隔垫物的纵截面形状为梯形。
本公开实施例中还提供一种显示装置，包括如上所述的显示面板。
本公开的上述技术方案的有益效果如下：
上述技术方案中，液晶面板包括对盒的阵列基板和彩膜基板，以及位于所述阵列基板和彩膜基板之间的隔垫物。所述阵列基板包括设置在衬底基板上的薄膜晶体管。通过设置所述薄膜晶体管在所述衬底基板上的投影完全落入隔垫物在所述衬底基板上的投影中，使得隔垫物能够保护薄膜晶体管不被彩膜基板反射的光线照射，进而改善薄膜晶体管的性能，提高显示器件的画面显示品质。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1表示相关技术中液晶面板的结构示意图；
图2表示本公开实施例中阵列基板的结构示意图一；
图3表示本公开实施例中阵列基板的结构示意图二；
图4表示本公开实施例中液晶面板的结构示意图一；
图5表示本公开实施例中液晶面板的结构示意图二；
图6表示本公开实施例中液晶面板的结构示意图三；
图7表示本公开实施例中液晶面板的结构示意图四。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描 述的本公开的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
液晶显示器的主体结构为液晶面板。如图1所示，液晶面板包括对盒设置的阵列基板10和彩膜基板20，以及填充在阵列基板10和彩膜基板20之间的液晶层40。液晶面板的盒厚主要通过形成在阵列基板10和彩膜基板20之间的隔垫物(Post Spacer，PS)30′来控制。其中，阵列基板10上形成有数据线和栅线(图中未示出)，用于限定多个像素单元，每个像素单元包括薄膜晶体管1和像素电极6。数据线上传输的像素电压通过薄膜晶体管1传输至像素电极6，用于形成驱动液晶分子偏转的电场，实现显示。
薄膜晶体管1为半导体元件，其性能容易受到光线的影响。现有技术中的材料不可避免的会对光线具有反射作用。因此，在TFT-LCD中，彩膜基板20上的材料薄膜反射的光线会照射到阵列基板10上的薄膜晶体管1，产生光漏电现象，影响薄膜晶体管1的性能，导致串扰、闪烁等画面不良。
本公开提供一种液晶面板，所述液晶面板包括相对设置的彩膜基板和阵列基板，以及位于所述彩膜基板和阵列基板之间的隔垫物，所述隔垫物用于支持面板并确定盒厚，液晶分子填充在所述彩膜基板和阵列基板之间的密封空间内。
所述阵列基板包括设置在衬底基板上的薄膜晶体管，通过设置所述薄膜晶体管在所述衬底基板上的投影完全落入隔垫物在所述衬底基板上的投影中，使得隔垫物能够阻挡彩膜基板反射的光线照射到所述薄膜晶体管，能够改善薄膜晶体管的性能，提高显示器件的画面显示品质。
所述隔垫物可以设置在彩膜基板上，也可以设置在阵列基板上。
为了提高隔垫物的支撑力，实际制作工艺中会设置隔垫物的纵截面形状为梯形(如图1-7所示)，即隔垫物的底部大顶部小。当隔垫物设置在彩膜基板上时，隔垫物与彩膜基板固定接触的端部为底部，相对的另一端部为顶部。当隔垫物设置在阵列基板上时，隔垫物与阵列基板固定接触的端部为底部，相对的另一端部为顶部。
下面将结合附图和实施例，对本公开的具体实施方式作进一步详细描述。以下实施例用于说明本公开，但不用来限制本公开的范围。
结合图2和图3所示，本公开实施例中提供一种阵列基板10，具体为薄膜晶体管阵列基板。阵列基板10包括第一衬底基板100、设置在第一衬底基板100上的薄膜晶体管1和设置在薄膜晶体管1上的隔垫物30，且薄膜晶体管1在第一衬底基板100上的投影完全落入隔垫物30在第一衬底基板100上的投影中，从而隔垫物30能够阻挡从显示侧射入的光线照射到薄膜晶体管1，防止薄膜晶体管1产生光漏电现象，改善薄膜晶体管1的特性。
可选地，隔垫物30包裹住薄膜晶体管1，使得隔垫物30阻挡从显示侧射入的光线照射薄膜晶体管1的效果更好，如图3所示。具体地，隔垫物30可以设置在薄膜晶体管1上，其底部包裹住薄膜晶体管1。
上述技术方案中，通过设置阵列基板上的薄膜晶体管在衬底基板上的投影完全落入隔垫物在衬底基板上的投影中，使得隔垫物能够阻挡从显示侧射入的光线照射到薄膜晶体管，从而防止薄膜晶体管产生光漏电现象，改善薄膜晶体管的特性。
其中，隔垫物30最好由不透光材料制成，对光线具有吸收作用。相对于由透光材料制成的隔垫物30，能够进一步提高了对光线的阻挡效率。
为了保护薄膜晶体管1，通常会在薄膜晶体管1和隔垫物30之间设置保护层102，即隔垫物30设置在保护层102上。保护层102为绝缘材料，如氮化硅、氧化硅或氮氧化硅，可以为单层、双层或多层结构。具体地，保护层102的材料可以是SiNx，SiOx或Si(ON)x。
在一个具体的实施方式中，设置保护层102厚度较薄，仅起到保护薄膜晶体管1的作用。隔垫物30设置在保护层102上，且隔垫物30包裹住薄膜 晶体管1，如图3所示。
在另一个具体的实施方式中，设置保护层102厚度较厚，不仅到保护薄膜晶体管1的作用，还用于提供平坦表面。隔垫物30设置在保护层102上，薄膜晶体管1在第一衬底基板100上的投影完全落入隔垫物30在第一衬底基板100上的投影中，如图2所示。由于保护层102厚度较厚，在一定盒厚的情况下，可以减小隔垫物30的高度，对比如图2和图3所示。
在上述两个实施方式中，设置隔垫物30由不透光材料制成。
本公开实施例中，隔垫物30的纵截面形状为梯形，即隔垫物30的底部大顶部小。
如图3所示，以底栅型薄膜晶体管阵列基板为例，本公开实施例中的阵列基板具体包括：
第一衬底基板100，为透明基板，如：玻璃基板、石英基板、有机树脂基板；
设置在第一衬底基板100上的多条栅线和多条数据线(图中未示出)，用于限定多个像素区域；
每个像素区域包括：
设置在第一衬底基板100上的薄膜晶体管1，薄膜晶体管1包括栅电极2、有源层3、源电极4和漏电极5，在栅电极2和有源层3之间设置有栅绝缘层101，栅绝缘层101的材料可以选用氧化物、氮化物或者氮氧化物，可以为单层、双层或多层结构。具体地，栅绝缘层101的材料可以是SiNx，SiOx或Si(ON)x。源电极4和漏电极5搭接在有源层3上；
像素电极6，像素电极6的一端位于有源层3和漏电极5之间；
覆盖薄膜晶体管1和像素电极6的保护层102，保护层102的厚度较薄；
设置在保护层102上的隔垫物30，隔垫物30的底部包裹住薄膜晶体管1；
设置在保护层102上的公共电极7，其位置与像素电极6的位置对应，公共电极7上具有多个狭缝，用于与像素电极6配合形成驱动电场。
当然，阵列基板10也可以不包括公共电极7，并设置像素电极6位于保护层102上，并通过保护层102中的过孔与漏电极5电性接触。
本公开实施例中的薄膜晶体管1并不局限于底栅型薄膜晶体管，也可以 为顶栅型薄膜晶体管或共面型薄膜晶体管。
基于同一发明构思，结合图4-图7所示，本公开实施例中还提供一种显示面板，包括相对的阵列基板10和彩膜基板20，以及位于阵列基板10和彩膜基板20之间的隔垫物30，在阵列基板10和彩膜基板20之间的密封空间填充有液晶分子层40。其中，彩膜基板20位于显示画面的一侧。
阵列基板10包括设置在第一衬底基板100上的薄膜晶体管1，且薄膜晶体管1在第一衬底基板100上的投影完全落入隔垫物30在第一衬底基板100上的投影中，从而隔垫物30能够阻挡彩膜基板20反射的光线照射到薄膜晶体管1，防止薄膜晶体管1产生光漏电现象，改善薄膜晶体管1的特性。
彩膜基板20上设置有黑矩阵8，所述隔垫物30在所述彩膜基板20上的投影完全被所述黑矩阵覆盖。
其中，彩膜基板20反射的光线具体为彩膜基板20的第二衬底基板200，以及形成在第二衬底基板200上的黑矩阵8、滤光层9和平坦层201反射的光线。
上述技术方案中，通过设置薄膜晶体管在阵列基板上的投影完全落入隔垫物在阵列基板上的投影中，从而隔垫物能够阻挡彩膜基板反射的光线照射到薄膜晶体管，防止薄膜晶体管产生光漏电现象，改善薄膜晶体管的特性，提高画面的显示品质。
可选地，隔垫物30包裹住薄膜晶体管1，使得隔垫物30阻挡彩膜基板20反射的光线照射薄膜晶体管1的效果更好，结合图4和图5所示。具体的，当隔垫物30设置在阵列基板10上时，隔垫物30的底部包裹住薄膜晶体管1，如图4所示，其中，隔垫物30的底部为隔垫物30与阵列基板10固定接触的端部。当隔垫物30设置在彩膜基板20上时，隔垫物30的顶部包裹住薄膜晶体管1，如图5所示，其中，隔垫物30的顶部为隔垫物30远离彩膜基板20的端部。
其中，隔垫物30最好由不透光材料制成，对光线具有吸收作用。相对于由透光材料制成的隔垫物30，提高了对光线的阻挡效率。
为了保护薄膜晶体管1，通常会在薄膜晶体管1和隔垫物30之间设置保护层102，即隔垫物30设置在保护层102上。保护层102为绝缘材料，如氮 化硅、氧化硅或氮氧化硅，可以为单层、双层或多层结构。具体地，保护层102的材料可以是SiNx，SiOx或Si(ON)x。
在一个具体的实施方式中，设置保护层102厚度较薄，仅起到保护薄膜晶体管1的作用。隔垫物30由不透光材料制成，设置在阵列基板10的保护层102上，且隔垫物30的底部包裹住薄膜晶体管1，如图4所示。
在该实施方式中，还可以将隔垫物30设置在彩膜基板20上，且隔垫物30的顶部包裹住薄膜晶体管1，如图5所示。
在另一个具体的实施方式中，设置保护层102厚度较厚，不仅起到保护薄膜晶体管1的作用，还用于提供平坦表面。隔垫物30由不透光材料制成，设置在阵列基板10的保护层102上，薄膜晶体管1在第一衬底基板100上的投影完全落入隔垫物30在第一衬底基板100上的投影中，如图6所示。由于保护层102厚度较厚，在一定盒厚的情况下，可以减小隔垫物30的高度，对比图4和图6所示。
在该实施方式中，隔垫物30还可以设置在彩膜基板20上，且薄膜晶体管1在第一衬底基板100上的投影完全落入隔垫物30在第一衬底基板100上的投影中，如图7所示。本领域技术人员可以毫无意义推出，此时，为了更好得实现隔垫物30阻挡彩膜基板20反射的光线照射到薄膜晶体管1，需要设置薄膜晶体管1在第一衬底基板100上的投影完全落入隔垫物30远离彩膜基板20的顶部在第一衬底基板100上的投影中，如图7所示。
由于保护层102提供了平坦表面，则可以设置隔垫物30的顶部平坦，以简化隔垫物30的制作工艺。
可选地，如图4所示，隔垫物30设置在阵列基板10上，并设置隔垫物30的底部包裹住薄膜晶体管。由于彩膜基板20的表面平坦，可以有效提高隔垫物30的支撑力，提高面板盒厚的稳定性，减轻画面不均的不良现象，提高画面的显示品质。同时由于隔垫物30的底部最大，可以更好得保护薄膜晶体管1不被彩膜基板20反射的光线照射。
如图4所示，本公开实施例中的显示面板具体包括：
相对设置的阵列基板10和彩膜基板20，在阵列基板10和彩膜基板20之间的密封空间填充有液晶分子层40；
阵列基板10，包括：
第一衬底基板100，为透明基板，如：玻璃基板、石英基板、有机树脂基板；
设置在第一衬底基板100上多条栅线和多条数据线(图中未示出)，限定多个像素区域；
每个像素区域包括：
设置在第一衬底基板100上的薄膜晶体管1，薄膜晶体管1包括栅电极2、有源层3、源电极4和漏电极5，在栅电极2和有源层3之间设置有栅绝缘层101，栅绝缘层101的材料可以选用氧化物、氮化物或者氮氧化物，可以为单层、双层或多层结构。具体地，栅绝缘层101的材料可以是SiNx，SiOx或Si(ON)x。源电极4和漏电极5搭接在有源层3上；
像素电极6，像素电极6的一端位于有源层3和漏电极5之间；
覆盖薄膜晶体管1和像素电极6的保护层102，保护层102的厚度较薄；
设置在保护层102上的隔垫物30，位于阵列基板10和彩膜基板20之间，隔垫物30的底部包裹住薄膜晶体管1；
设置在保护层102上的公共电极7，与像素电极6的位置对应，公共电极7上具有多个狭缝，用于与像素电极6配合形成驱动电场；
彩膜基板20包括：
第二衬底基板200，为透明基板，如：玻璃基板、石英基板、有机树脂基板；
设置在第二衬底基板200上的黑矩阵8，与阵列基板10上的栅线和数据线位置对应，用于限定多个像素区域；
位于像素区域的滤光层9，例如：红色滤光层、绿色滤光层或蓝色滤光层；
覆盖黑矩阵8和滤光层9的平坦层201。
其中，公共电极6还可以设置在彩膜基板20上，具体可以设置在平坦层201上。并设置像素电极6位于保护层102上，通过保护层102中的过孔与漏电极5电性接触。
本公开实施例中还提供一种显示装置，包括本公开实施例中的显示面板， 从而提高了产品的质量和画面显示品质。
所述显示装置还包括背光源，所述显示面板包括阵列基板和彩膜基板，所述背光源设置在阵列基板与彩膜基板相对的一侧，彩膜基板位于显示画面的一侧。
所述显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
上述技术方案中，液晶面板包括相对设置的阵列基板和彩膜基板，以及位于所述阵列基板和彩膜基板之间的隔垫物，所述阵列基板包括设置在衬底基板上的薄膜晶体管。通过设置所述薄膜晶体管在所述衬底基板上的投影完全落入隔垫物在所述衬底基板上的投影中，使得隔垫物能够保护薄膜晶体管不被彩膜基板反射的光线照射，改善薄膜晶体管的性能，提高显示器件的画面显示品质。
以上所述仅是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开技术原理的前提下，还可以做出若干改进和替换，这些改进和替换也应视为本公开的保护范围。

Claims (10)

  1. 一种阵列基板，包括
    设置在衬底基板上的薄膜晶体管，以及
    设置在薄膜晶体管上的隔垫物，
    其中，所述薄膜晶体管在所述衬底基板上的投影完全落入所述隔垫物在所述衬底基板上的投影中。
  2. 根据权利要求1所述的阵列基板，其中，所述隔垫物包裹住所述薄膜晶体管。
  3. 根据权利要求1或2所述的阵列基板，其中，所述隔垫物由不透光材料制成。
  4. 一种显示面板，包括
    相对设置的阵列基板和彩膜基板，以及
    位于所述阵列基板和彩膜基板之间的隔垫物，
    其中，所述阵列基板包括设置在衬底基板上的薄膜晶体管，所述薄膜晶体管在所述衬底基板上的投影完全落入所述隔垫物在所述衬底基板上的投影中，使得所述隔垫物能够阻挡所述彩膜基板反射的光线照射到所述薄膜晶体管。
  5. 根据权利要求4所述的显示面板，其中，所述隔垫物包裹住所述薄膜晶体管。
  6. 根据权利要求5所述的显示面板，其中，所述隔垫物设置在阵列基板或彩膜基板上。
  7. 根据权利要求4所述的显示面板，其中，所述彩膜基板上设置有黑矩阵，所述隔垫物在所述彩膜基板上的投影完全被所述黑矩阵覆盖。
  8. 根据权利要求4-7任一项所述的显示面板，其中，所述隔垫物由不透光材料制成。
  9. 根据权利要求4-7任一项所述的显示面板，其中，所述隔垫物的纵截面形状为梯形。
  10. 一种显示装置，包括权利要求4-9任一项所述的显示面板。
PCT/CN2015/091005 2015-04-17 2015-09-29 阵列基板、显示面板及显示装置 WO2016165291A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510184911.9 2015-04-17
CN201510184911.9A CN104730779A (zh) 2015-04-17 2015-04-17 阵列基板、显示面板及显示装置

Publications (1)

Publication Number Publication Date
WO2016165291A1 true WO2016165291A1 (zh) 2016-10-20

Family

ID=53454826

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/091005 WO2016165291A1 (zh) 2015-04-17 2015-09-29 阵列基板、显示面板及显示装置

Country Status (2)

Country Link
CN (1) CN104730779A (zh)
WO (1) WO2016165291A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110991400A (zh) * 2019-12-18 2020-04-10 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104730779A (zh) * 2015-04-17 2015-06-24 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置
CN105700219B (zh) * 2015-12-18 2019-09-13 厦门天马微电子有限公司 一种彩色滤光片及其制造方法、一种显示面板
CN106292102A (zh) * 2016-08-12 2017-01-04 京东方科技集团股份有限公司 一种显示面板及显示器
CN106773241A (zh) * 2016-12-20 2017-05-31 武汉华星光电技术有限公司 液晶面板及液晶显示器
CN112447761B (zh) * 2019-08-28 2024-02-13 京东方科技集团股份有限公司 阵列基板、led显示面板及其制作方法、显示装置
CN113156697A (zh) * 2021-04-27 2021-07-23 深圳市华星光电半导体显示技术有限公司 一种显示面板及显示装置
CN117311041A (zh) * 2023-10-18 2023-12-29 京东方科技集团股份有限公司 一种显示面板及其制造方法、显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08234212A (ja) * 1995-02-28 1996-09-13 Casio Comput Co Ltd 液晶表示素子
JP2002023170A (ja) * 2000-07-04 2002-01-23 Toppan Printing Co Ltd 液晶表示装置
KR20070076740A (ko) * 2006-01-19 2007-07-25 삼성전자주식회사 차광 컬럼 스페이서를 포함하는 액정 패널의 형성 방법 및그에 의해 형성된 액정 패널을 포함하는 표시 장치
CN202025170U (zh) * 2011-04-22 2011-11-02 京东方科技集团股份有限公司 一种显示屏及显示装置
CN103091897A (zh) * 2013-02-01 2013-05-08 信利半导体有限公司 一种液晶显示装置
CN103293802A (zh) * 2012-02-27 2013-09-11 乐金显示有限公司 液晶显示器件及其制造方法
CN104730779A (zh) * 2015-04-17 2015-06-24 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08234212A (ja) * 1995-02-28 1996-09-13 Casio Comput Co Ltd 液晶表示素子
JP2002023170A (ja) * 2000-07-04 2002-01-23 Toppan Printing Co Ltd 液晶表示装置
KR20070076740A (ko) * 2006-01-19 2007-07-25 삼성전자주식회사 차광 컬럼 스페이서를 포함하는 액정 패널의 형성 방법 및그에 의해 형성된 액정 패널을 포함하는 표시 장치
CN202025170U (zh) * 2011-04-22 2011-11-02 京东方科技集团股份有限公司 一种显示屏及显示装置
CN103293802A (zh) * 2012-02-27 2013-09-11 乐金显示有限公司 液晶显示器件及其制造方法
CN103091897A (zh) * 2013-02-01 2013-05-08 信利半导体有限公司 一种液晶显示装置
CN104730779A (zh) * 2015-04-17 2015-06-24 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110991400A (zh) * 2019-12-18 2020-04-10 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置
CN110991400B (zh) * 2019-12-18 2023-08-18 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置

Also Published As

Publication number Publication date
CN104730779A (zh) 2015-06-24

Similar Documents

Publication Publication Date Title
WO2016165291A1 (zh) 阵列基板、显示面板及显示装置
KR102033263B1 (ko) Va형 coa 액정 디스플레이 패널
US8064013B2 (en) Liquid crystal display panel having an ornamental reflector deployed around the periphery of a display region
US10096800B2 (en) Display device including reflecting layer
WO2017101204A1 (zh) 液晶显示装置
US9581871B2 (en) Display panel comprising a wire disposed and sandwiched in between a sealant and a planarization layer and method for manufacturing the same
KR102007905B1 (ko) 표시판 및 이를 포함하는 액정 표시 장치
KR20180107442A (ko) 표시 장치 및 이의 제조 방법
US9885909B2 (en) Liquid crystal display and manufacturing method thereof
US9575371B2 (en) Liquid crystal device and electronic apparatus
WO2018171079A1 (zh) 主动开关阵列基板及其制造方法与显示面板
WO2017063240A1 (zh) 一种ltps阵列基板以及液晶显示面板
WO2021184506A1 (zh) 液晶显示面板
JP2014212191A (ja) 半導体装置、電気光学装置、半導体装置の製造方法、電気光学装置の製造方法、及び電子機器
JP2008020772A (ja) 液晶表示パネル
US10288923B2 (en) COA array substrate and liquid crystal display panel
JP2012208178A (ja) 電気光学装置用基板、電気光学装置、電気光学装置の製造方法、及び電子機器
WO2018113061A1 (zh) 阵列基板、彩膜基板及液晶面板
US9568777B2 (en) Display substrate, preparing method thereof, and display device
US9664942B2 (en) Liquid crystal display
US20210286221A1 (en) Liquid crystal display panel
JP2007322766A (ja) 液晶表示装置及び電子機器
JP2020129617A (ja) 半導体装置および半導体装置の製造方法
US11221528B2 (en) Electro-optical device and electronic apparatus
US11614664B2 (en) Electro-optical device, manufacturing method of electro-optical device, and electronic apparatus

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15888988

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15888988

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 23/04/2018)

122 Ep: pct application non-entry in european phase

Ref document number: 15888988

Country of ref document: EP

Kind code of ref document: A1