WO2015096581A1 - 用于功率半导体装置的场板结构及其制造方法 - Google Patents

用于功率半导体装置的场板结构及其制造方法 Download PDF

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WO2015096581A1
WO2015096581A1 PCT/CN2014/092250 CN2014092250W WO2015096581A1 WO 2015096581 A1 WO2015096581 A1 WO 2015096581A1 CN 2014092250 W CN2014092250 W CN 2014092250W WO 2015096581 A1 WO2015096581 A1 WO 2015096581A1
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semi
field plate
plate structure
insulating
implemented
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PCT/CN2014/092250
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French (fr)
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伍震威
艾哈迈德⋅伊夫蒂哈尔
单建安
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伍震威
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Priority to CN201480002396.1A priority Critical patent/CN104737293B/zh
Priority to US14/771,095 priority patent/US10593767B2/en
Publication of WO2015096581A1 publication Critical patent/WO2015096581A1/zh

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Definitions

  • the present invention relates generally to the construction and fabrication of power semiconductor devices, and in particular to the construction and fabrication of semi-insulating field plates.
  • MOSFETs metal oxide semiconductor field effect transistors
  • BJT bipolar junction transistors
  • IGBT Insulated gate bipolar transistor
  • Semi-insulated field plates have been widely used in power semiconductor device structures.
  • the basic function of the semi-insulating field plate is to provide a uniform electric field distribution under the plate in the off state of the device, which helps to increase the breakdown voltage of the power semiconductor device.
  • semi-insulating field plates typically require patterning, which requires an additional etching step that increases manufacturing costs [1].
  • the etching step can be skipped by depositing an amorphous silicon layer as a semi-insulating field plate before metallization or after metallization [2].
  • deposition after metallization may cause contamination of the electric furnace, while deposition prior to metallization may cause degradation of electrical performance due to increased contact resistance between metal and silicon. Accordingly, it is an object of the present invention to provide a cost effective semi-insulating field plate structure and method of manufacture therefor without causing process compatibility or degradation of electrical performance.
  • the semi-insulating field plate is a semi-insulating polysilicon (SIPOS) layer (32) over the silicon oxide layer (31).
  • SIPOS semi-insulating polysilicon
  • the SIPOS layer (32) is fabricated by deposition prior to metallization. In the off state of the device, current flows from the cathode (22) to the anode (21) through the SIOS layer (32), producing a linear voltage drop that is higher than the resistance of the SIPOS (32). The linear voltage drop causes a uniform electric field distribution at the surface of the n - drift region (12).
  • a uniform electric field distribution eliminates or reduces the peak electric field near the p-anode (11) and/or n + cathode (13), which helps to increase the breakdown voltage of the diode.
  • the manufacturing process of the structure requires etching the SIPOS to cut the contact holes of the metal electrodes (21, 22) at the surface, and the etching process may cause additional manufacturing costs.
  • the semi-insulating field plate is a high resistivity amorphous silicon layer (33) over both the silicon oxide layer (31) and the metal electrodes (21, 23).
  • the high resistivity amorphous silicon layer (33) is fabricated by deposition after metallization. In the off state of the device, current flows from the outer metal (23) to the anode metal (21) at the junction terminal through the amorphous silicon layer (33), thereby causing a linear voltage higher than the resistance of the amorphous silicon (33). drop.
  • the linear voltage drop causes a uniform electric field distribution at the surface of the n - drift region (12) between the p anode (11) and the p-guard (14), which helps to improve the breakdown of the diode at the junction termination. Voltage.
  • the fabrication of the amorphous silicon layer (33) requires a deposition step. The metal may cause contamination of the electric furnace during the deposition process.
  • the semi-insulating field plate is a high resistivity amorphous silicon layer (33) above the silicon oxide layer (31) and under the metal electrodes (21, 23).
  • the high resistivity amorphous silicon layer (33) is fabricated by deposition prior to metallization. In the off state of the device, current flows from the outer metal (23) to the anode metal (21) at the junction terminal through the amorphous silicon layer (33), thereby causing a linear voltage higher than the resistance of the amorphous silicon (33). drop.
  • the linear voltage drop causes a uniform electric field distribution at the surface of the n - drift region (12) between the p anode (11) and the p-guard (14), which helps to improve the breakdown of the diode at the junction termination. Voltage.
  • the amorphous silicon (33) located between the anode electrode (21) and the p anode (11) can cause an increased contact resistance here, which degrades electrical performance. For example, increased contact resistance will cause an increased on-state voltage drop.
  • the increased contact resistance will result in increased on-resistance.
  • the present invention provides a novel semi-insulating field plate structure comprising a metal electrode (21, 22/23) located at the surface of the power semiconductor device. Thin semi-insulating layer (34).
  • the semi-insulating layer (34) comprises any high resistivity material, including but not limited to, titanium nitride, polysilicon, and amorphous silicon.
  • the semi-insulating layer (34) is contacted by the metal electrodes (21, 22/23) at the side walls.
  • the semi-insulating field plate structure is implemented in an LDMOS.
  • the semi-insulating field plate structure is implemented in an LIGBT.
  • the semi-insulating field plate structure is implemented in a vertical power MOSFET.
  • the semi-insulating field plate structure is implemented in a power BJT.
  • the semi-insulating field plate structure is implemented in an IGBT.
  • the semi-insulating field plate structure is implemented in a thyristor.
  • a manufacturing method for fabricating a semi-insulating field plate structure comprising
  • the contact hole (41) is formed by patterning silicon oxide (31) covering the silicon surface of the device wafer,
  • Annealing is performed to pass the metal electrode (21, 22/23) through the thin semi-insulating layer (34).
  • the semi-insulating layer (34) comprises any high resistivity material, including but not limited to, titanium nitride, polysilicon, and amorphous silicon.
  • the deposition method comprises chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition or sputtering.
  • FIG. 1 is a cross-sectional view of a prior art SIPOS field plate structure implemented in a lateral power diode.
  • FIG. 2 is a cross-sectional view of a prior art amorphous silicon field plate implemented in a vertical power diode.
  • FIG 3 is a cross-sectional view of another prior art amorphous silicon field plate implemented in a vertical power diode.
  • FIG. 4 is a cross-sectional view of the invention implemented in a lateral power diode.
  • Figure 5 is a cross-sectional view of the invention implemented in a lateral double diffused MOSFET (LDMOS).
  • LDMOS lateral double diffused MOSFET
  • Figure 6 is a cross-sectional view of the invention implemented in a vertical power diode.
  • Figure 7 is a cross-sectional view of the invention implemented in a vertical power MOSFET.
  • Figure 8 is a cross-sectional view of the invention implemented in a vertical power BJT.
  • 9A to 9D show key manufacturing processes of the embodiment of the present invention previously shown in Fig. 6.
  • the diode includes a p anode (11), an n - drift region (12), and an n + cathode (13) on the p substrate (16).
  • the p anode (11) and the n + cathode (13) are respectively contacted by the anode electrode (21) and the cathode electrode (22).
  • the surface of the n - drift region (12) is covered by a silicon oxide layer (31).
  • the silicon oxide layer (31) is covered by the SIPOS layer (32).
  • the SIPOS layer portion is covered by metal electrodes (21, 22).
  • the manufacturing process of the SIPOS field plate (32) comprises: (1) depositing high-resistivity polysilicon doped with silicon oxide or silicon nitride on the silicon oxide (31); (2) patterning the plasma by photolithography and etching (32) and silicon oxide (31); and (3) metal electrodes (21, 22) by deposition and patterning.
  • the diode includes a p anode (11), an n - drift region (12), an n + cathode (13), and a plurality of p-guard rings (14) at the junction termination.
  • the n + cathode (13) (22) contacted by the cathode electrode at the bottom of the wafer, and the p anode (11) and a p-guard ring (14) are in contact with an anode electrode (21) and an external metal (23) at the wafer surface.
  • the surface of the n - drift region (12) and the p-guard ring (14) is covered by a silicon oxide layer (31).
  • the silicon oxide layer (31) is partially covered by metal electrodes (21, 23). Both the silicon oxide layer (31) and the metal electrodes (21, 23) are covered by high-resistivity amorphous silicon (33).
  • the fabrication process of the high resistivity amorphous silicon field plate (33) involves depositing a thin layer of amorphous silicon after forming the metal electrodes (21, 23).
  • FIG. 3 is a cross-sectional view of another prior art amorphous silicon field plate implemented in a vertical power diode.
  • the diode includes a p anode (11), an n - drift region (12), an n + cathode (13), and a plurality of p-guard rings (14) at the junction termination.
  • the n + cathode (13) is connected to the cathode electrode (22) through high-resistivity amorphous silicon (33), and the p anode (11) and the p-guard ring (14) are respectively connected to the high-resistivity amorphous silicon (33)
  • the surface of the n - drift region (12) and the p-guard ring (14) is covered by a silicon oxide layer (31), and the silicon oxide (31) is covered by high-resistivity amorphous silicon (33).
  • the fabrication process of the high resistivity amorphous silicon field plate (33) involves depositing a thin layer of amorphous silicon prior to forming the metal electrodes (21, 23).
  • the diode includes a p anode (11), an n - drift region (12), and an n + cathode (13).
  • the p anode (11) and the n + cathode (13) are respectively contacted by the anode electrode (21) and the cathode electrode (22).
  • the surface of the n - drift region (12) is covered by a silicon oxide layer (31).
  • the silicon oxide layer (31) is covered by a thin semi-insulating layer (34).
  • the silicon oxide layer (31) is also partially covered by the metal electrodes (21, 22).
  • a semi-insulating layer (34) is located between the metal electrodes (21, 22) and is in contact with those electrodes at the side walls.
  • the semi-insulating layer (34) may comprise any high resistivity material including, but not limited to, titanium nitride, polysilicon, and amorphous silicon.
  • the semi-insulating layer (34) has a thickness of about 5 nm to 100 nm and a resistivity of about 100 ohm-cm to 10,000 ohm-cm.
  • LDMOS lateral double diffused MOSFETs
  • LIGBTs lateral IGBTs
  • Figure 6 is a cross-sectional view of the invention implemented in a vertical power diode.
  • P diodes by the anode (11), n - drift region (12), n + cathode (13) and a plurality of p grommet (14) at a junction terminal composition.
  • the n + cathode (13) is contacted by a cathode electrode (22) at the bottom of the wafer, and the p anode (11) and the p guard ring (14) are respectively contacted by an anode electrode (21) at the surface of the wafer and an external metal (23).
  • the surface of the n - drift region (12) and the p-guard ring (14) is covered by a silicon oxide layer (31).
  • the silicon oxide layer (31) is covered by a thin semi-insulating layer (34).
  • the silicon oxide layer (31) is also partially covered by the metal electrodes (21, 23).
  • a semi-insulating layer (34) is located between the metal electrodes (21, 23) and is in contact with those electrodes at the side walls.
  • the semi-insulating layer (34) may comprise any high resistivity material including, but not limited to, titanium nitride, polysilicon, and amorphous silicon.
  • the semi-insulating layer (34) has a thickness of about 5 nm to 100 nm and a resistivity of about 100 ohm-cm to 10,000 ohm-cm.
  • FIG. 7 shows a cross-sectional view of the invention implemented in a vertical power MOSFET.
  • Figure 8 shows a cross-sectional view of the invention implemented in a vertical power BJT.
  • the manufacturing process of the structure includes: (1) forming a contact hole (41) by patterning silicon oxide (31) on the silicon surface of the cover device wafer, as shown in FIG. 9A; (2) thin semi-insulating layer (34) Deposited on the entire surface of the wafer, as shown in Figure 9B; (3) depositing and patterning the metal electrodes (21, 23) on the thin semi-insulating layer (34), as shown in Figure 9C; and (4) annealing The metal electrodes (21, 23) are passed through the thin semi-insulating layer (34) as shown in Fig. 9D.
  • Fig. 9A shows the formation of a contact hole (41).
  • Contact holes (41) are typically formed by optical lithography and etching.
  • Figure 9B shows a thin semi-insulating layer (34) deposited on silicon oxide (31).
  • the semi-insulating layer (34) is also deposited at the same time In the contact hole (41).
  • the semi-insulating layer (34) covers the sidewall of the silicon oxide (31) and the surface of the silicon.
  • the deposition may be chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, or sputtering.
  • the semi-insulating layer (34) may comprise any high resistivity material including, but not limited to, titanium nitride, polysilicon, and amorphous silicon.
  • the semi-insulating layer (34) has a thickness of about 5 nm to 100 nm and a resistivity of about 100 ohm-cm to 10,000 ohm-cm.
  • Fig. 9C shows the formation of the metal electrodes (21, 23).
  • the metal electrodes (21, 23) are typically formed by deposition, optical lithography, and etching.
  • Figure 9D shows the penetration of the metal electrodes (21, 23). Penetration is performed by annealing the device wafer.
  • the temperature, duration and environment of the annealing depend on the thickness of the semi-insulating layer (34) as well as the material, and also on the material of the metal electrodes (21, 23). For example, in the case of a SIPOS-type semi-insulating layer (34) having about 10 nm and an aluminum electrode (21, 23), annealing takes about 30 minutes at 450 ° C in an H 2 environment.
  • FIGS. 9A to 9D are also applicable to the structure illustrated in FIG. 4.
  • the same fabrication process is also applicable to other embodiments, for example, the invention is implemented in other power semiconductor device structures such as MOSFETs, BJTs, IGBTs, and thyristors.

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Abstract

提供一种功率半导体装置的结构和制造方法。提供位于在功率半导体装置的表面处的金属电极（21、22、23）之间的薄半绝缘场板（32、33、34）结构。所述薄半绝缘场板（32、33、34）通过在金属化之前进行沉积并且在所述金属化之后进行退火而形成。可用于横向功率半导体装置和垂直功率半导体装置中。

Description

用于功率半导体装置的场板结构及其制造方法 技术领域
本发明大体上涉及功率半导体装置的结构和制造，且具体而言涉及半绝缘场板的结构和制造。
背景技术
将在功率二极管结构中说明本发明，但在以下说明中应理解，本发明同等适用于其它功率半导体装置结构，例如，金属氧化物半导体场效应晶体管(MOSFET)、双极结晶体管(BJT)、绝缘栅双极晶体管(IGBT)以及闸流晶体管。
半绝缘场板已广泛用于功率半导体装置结构。半绝缘场板的基本功能是在装置的断开状态下在板下方提供均匀的电场分布，这有助于提高功率半导体装置的击穿电压。然而，半绝缘场板通常需要进行图案化，这需要增加制造成本的额外蚀刻步骤[1]。所述蚀刻步骤可以通过在金属化之前或在金属化之后沉积非晶硅层作为半绝缘场板而被跳过[2]。然而，在金属化之后的沉积可能引起对电炉的污染，而在金属化之前的沉积可能由于金属与硅之间的增加的接触电阻而引起电气性能降级。因此，本发明的目标是提供一种有成本效益的半绝缘场板结构以及为此的制造方法，而不会产生过程兼容性或电气性能降级问题。
现有技术
图1中示出实施于横向功率二极管结构中的现有技术半绝缘场板。如图所示，半绝缘场板是氧化硅层(31)上方的半绝缘多晶硅(SIPOS)层(32)。SIPOS层(32)通过在金属化之前进行沉积而制造。在装置的断开状态下，电流从阴极(22)到阳极(21)流过SIPOS层(32)，从而产生高于SIPOS(32)的电阻的线性电压降。线性电压降会在n-漂移区(12)的表面处引起均匀的电场分布。均匀的电场分布消除或减少了p阳极(11)和/或n+阴极(13)附近的峰值电场，这有助于提高二极管的击穿电压。然而，结构的制造过程需要蚀刻SIPOS以在表面处切开金属电极(21、22)的接触孔，并且蚀刻工艺可以引起额外的制造成本。
图2中示出实施于垂直功率二极管结构中的另一现有技术半绝缘场板。如图所示，半绝缘场板是氧化硅层(31)以及金属电极(21、23)两者上方的高电阻率非晶硅层(33)。高电阻率非晶硅层(33)通过在金属化之后进行沉积而制造。在装置的断开状态下，电流从外部金属(23)到结终端处的阳极金属(21)流过非晶硅层(33)，从而引起高于非晶硅(33)的电阻的线性电压降。线性电压降会在位于p阳极(11)与p护环(14)之间的n-漂移区(12)的表面处引起均匀的电场分布，这有助于提高结终端处的二极管的击穿电压。然而，在装置晶片的表面处存在金属之后，非晶硅层(33)的制造需要沉积步骤。在沉积过程中所述金属 可能引起对电炉的污染。
图3中示出实施于垂直功率二极管结构中的再另一现有技术半绝缘场板。如图所示，半绝缘场板是氧化硅层(31)上方以及金属电极(21、23)下方的高电阻率非晶硅层(33)。高电阻率非晶硅层(33)通过在金属化之前进行沉积而制造。在装置的断开状态下，电流从外部金属(23)到结终端处的阳极金属(21)流过非晶硅层(33)，从而引起高于非晶硅(33)的电阻的线性电压降。线性电压降会在位于p阳极(11)与p护环(14)之间的n-漂移区(12)的表面处引起均匀的电场分布，这有助于提高结终端处的二极管的击穿电压。然而，位于阳极电极(21)与p阳极(11)之间的非晶硅(33)可以在此处引起增加的接触电阻，这会使电气性能降级。例如，增加的接触电阻将引起增加的开态电压降。对于另一实例，如果相同结构实施于功率MOSFET中，那么增加的接触电阻将会引起增加的导通电阻。
发明内容
因此，本发明的目标是提供一种有成本效益的半绝缘场板结构以及为此的制造方法，而不会产生过程可兼容或电气性能降级的问题。
为了实现此目标以及其它目标，本发明提供一种新的半绝缘场板结构，所述半绝缘场板结构包括位于在功率半导体装置的表面处的金属电极(21、22/23)之间的薄半绝缘层(34)。
进一步的，其中所述半绝缘层(34)包括任何高电阻率材料，包含但不限于，氮化钛、多晶硅以及非晶硅。
进一步的，其中所述半绝缘层(34)由侧壁处的所述金属电极(21、22/23)接触。
进一步的，所述的半绝缘场板结构，其实施于LDMOS中。
进一步的，所述的半绝缘场板结构，其实施于LIGBT中。
进一步的，所述的半绝缘场板结构，其实施于垂直功率MOSFET中。
进一步的，所述的半绝缘场板结构，其实施于功率BJT中。
进一步的，所述的半绝缘场板结构，其实施于IGBT中。
进一步的，所述的半绝缘场板结构，其实施于闸流晶体管中。
一种用于制造半绝缘场板结构的制造方法，所述制造方法包括
通过将覆盖装置晶片的硅表面的氧化硅(31)图案化形成接触孔(41)，
将薄半绝缘层(34)沉积在所述晶片的整个表面上，
沉积以及图案化所述薄半绝缘层(34)上的金属电极(21、22/23)以及
退火以使所述金属电极(21、22/23)穿过所述薄半绝缘层(34)。
进一步的，其中所述半绝缘层(34)包括任何高电阻率材料，包含但不限于，氮化钛、多晶硅以及非晶硅。
进一步的，其中所述沉积方法包含化学气相沉积、低压化学气相沉积、等离子体增强化学气相沉积或溅镀。
附图说明
图1是实施于横向功率二极管中的现有技术SIPOS场板结构的横截面图。
图2是实施于垂直功率二极管中的现有技术非晶硅场板的横截面图。
图3是实施于垂直功率二极管中的另一现有技术非晶硅场板的横截面图。
图4是实施于横向功率二极管中的本发明的横截面图。
图5是实施于横向双扩散MOSFET(LDMOS)中的本发明的横截面图。
图6是实施于垂直功率二极管中的本发明的横截面图。
图7是实施于垂直功率MOSFET中的本发明的横截面图。
图8是实施于垂直功率BJT中的本发明的横截面图。
图9A到图9D示出之前在图6中示出的本发明的实施例的关键制造工序。
具体实施方式
图1是实施于横向功率二极管中的现有技术SIPOS场板结构的横截面图。二极管包括p阳极(11)、n-漂移区(12)以及p衬底(16)上的n+阴极(13)。p阳极(11)以及n+阴极(13)分别由阳极电极(21)以及阴极电极(22)接触。n-漂移区(12)的表面由氧化硅层(31)覆盖。氧化硅层(31)由SIPOS层(32)覆盖。SIPOS层部分由金属电极(21、22)覆盖。SIPOS场板(32)的制造过程包含：(1)将掺杂有氧化硅或氮化硅的高电阻率多晶硅沉积在氧化硅(31)上；(2)通过光学光刻以及蚀刻图案化SIPOS(32)以及氧化硅(31)；以及(3)通过沉积以及图案化形式金属电极(21、22)。
图2是实施于垂直功率二极管中的现有技术非晶硅场板的横截面图。二极管包括p阳极(11)、n-漂移区(12)、n+阴极(13)以及结终端处的多个p护环(14)。n+阴极(13)由晶片底部处的阴极电极(22)接触，并且p阳极(11)以及p护环(14)分别由晶片表面处的阳极电极(21)以及外部金属(23)接触。n-漂移区(12)以及p护环(14)的表面由氧化硅层(31)覆盖。氧化硅层(31)部分由金属电极(21、23)覆盖。氧化硅层(31)以及金属电极(21、23)两者均由高电阻率非晶硅(33)覆盖。高电阻率非晶硅场板(33)的制造过程包含在形成金属电极(21、23)之后沉积薄的非晶硅层。
图3是实施于垂直功率二极管中的另一现有技术非晶硅场板的横截面图。二极管包括p阳极(11)、n-漂移区(12)、n+阴极(13)以及结终端处的多个p护环(14)。n+阴极(13)通过高电阻率非晶硅(33)连接到阴极电极(22)，并且p阳极(11)以及p护环(14)分别 通过高电阻率非晶硅(33)连接到阳极电极(21)以及外部金属(23)。n-漂移区(12)以及p护环(14)的表面由氧化硅层(31)覆盖，并且氧化硅(31)由高电阻率非晶硅(33)覆盖。高电阻率非晶硅场板(33)的制造过程包含在形成金属电极(21、23)之前沉积薄的非晶硅层。
图4是实施于横向功率二极管中的本发明的横截面图。二极管包括p阳极(11)、n-漂移区(12)以及n+阴极(13)。p阳极(11)以及n+阴极(13)分别由阳极电极(21)以及阴极电极(22)接触。n-漂移区(12)的表面由氧化硅层(31)覆盖。氧化硅层(31)由薄半绝缘层(34)覆盖。氧化硅层(31)还部分由金属电极(21、22)覆盖。半绝缘层(34)位于金属电极(21、22)之间并且由侧壁处的那些电极接触。半绝缘层(34)可以包括任何高电阻率材料，包含但不限于，氮化钛、多晶硅以及非晶硅。半绝缘层(34)具有约5nm到100nm的厚度以及约100ohm-cm到10000ohm-cm的电阻率。此外，值得指出的是，相同半绝缘场板结构还适用于其它横向功率半导体装置，例如，横向双扩散MOSFET(LDMOS)以及横向IGBT(LIGBT)。图5示出实施于LDMOS中的本发明的横截面图。
图6是实施于垂直功率二极管中的本发明的横截面图。二极管由p阳极(11)、n-漂移区(12)、n+阴极(13)以及结终端处的多个p护环(14)组成。n+阴极(13)由晶片底部处的阴极电极(22)接触，并且p阳极(11)以及p护环(14)分别由晶片表面处的阳极电极(21)以及外部金属(23)接触。n-漂移区(12)以及p护环(14)的表面由氧化硅层(31)覆盖。氧化硅层(31)由薄半绝缘层(34)覆盖。氧化硅层(31)还部分由金属电极(21、23)覆盖。半绝缘层(34)位于金属电极(21、23)之间并且由侧壁处的那些电极接触。半绝缘层(34)可以包括任何高电阻率材料，包含但不限于，氮化钛、多晶硅以及非晶硅。半绝缘层(34)具有约5nm到100nm的厚度以及约100ohm-cm到10000ohm-cm的电阻率。此外，值得指出的是，相同半绝缘场板结构还适用于其它垂直功率半导体装置，例如，垂直功率MOSFET、BJT、闸流晶体管以及IGBT。图7示出实施于垂直功率MOSFET中的本发明的横截面图。图8示出实施于垂直功率BJT中的本发明的横截面图。
图9A到图9D示出之前在图6中示出的本发明的实施例的关键制造工序。所述结构的制造过程包含：(1)通过对覆盖装置晶片的硅表面的氧化硅(31)图案化形成接触孔(41)，如图9A所示；(2)将薄半绝缘层(34)沉积在晶片的整个表面上，如图9B所示；(3)沉积以及图案化薄半绝缘层(34)上的金属电极(21、23)，如图9C所示；以及(4)退火以使金属电极(21、23)穿过薄半绝缘层(34)，如图9D所示。
图9A示出接触孔(41)的形成。接触孔(41)通常通过光学光刻以及蚀刻形成。
图9B示出薄半绝缘层(34)沉积在氧化硅(31)上。半绝缘层(34)同时还沉积在接 触孔(41)中。在接触孔中，半绝缘层(34)覆盖氧化硅(31)的侧壁以及硅的表面。所述沉积可以是化学气相沉积、低压化学气相沉积、等离子体增强化学气相沉积或溅镀。半绝缘层(34)可以包括任何高电阻率材料，包含但不限于，氮化钛、多晶硅以及非晶硅。半绝缘层(34)具有约5nm到100nm的厚度以及约100ohm-cm到10000ohm-cm的电阻率。
图9C示出金属电极(21、23)的形成。金属电极(21、23)通常通过沉积、光学光刻以及蚀刻形成。
图9D示出金属电极(21、23)的穿透。通过使装置晶片退火进行穿透。退火的温度、持续时间以及环境取决于半绝缘层(34)的厚度以及材料，并且还取决于金属电极(21、23)的材料。例如，在具有约10nm的SIPOS型半绝缘层(34)以及铝电极(21、23)的情况下，退火在H2环境中在450℃下需要约30分钟。
此外，从图9A到图9D示出的制造过程还适用于图4中示出的结构。此外，相同的制造过程还适用于其它实施例，例如，本发明实施于例如MOSFET、BJT、IGBT以及闸流晶体管的其它功率半导体装置结构中。

Claims (12)

  1. 一种半绝缘场板结构，其包括在氧化硅(31)上方并且在功率半导体装置的表面处的金属电极(21、22、23)之间的半绝缘层(34)。
  2. 根据权利要求1所述的半绝缘场板结构，其中所述半绝缘层(34)包括任何高电阻率材料，包含但不限于，氮化钛、多晶硅以及非晶硅。
  3. 根据权利要求1所述的半绝缘场板结构，其中所述半绝缘层(34)由侧壁处的所述金属电极(21、22/23)接触。
  4. 根据权利要求1所述的半绝缘场板结构，其实施于LDMOS中。
  5. 根据权利要求1所述的半绝缘场板结构，其实施于LIGBT中。
  6. 根据权利要求1所述的半绝缘场板结构，其实施于垂直功率MOSFET中。
  7. 根据权利要求1所述的半绝缘场板结构，其实施于功率BJT中。
  8. 根据权利要求1所述的半绝缘场板结构，其实施于IGBT中。
  9. 根据权利要求1所述的半绝缘场板结构，其实施于闸流晶体管中。
  10. 一种用于制造半绝缘场板结构的制造方法，所述制造方法包括
    通过将覆盖装置晶片的硅表面的氧化硅(31)图案化形成接触孔(41)，
    将薄半绝缘层(34)沉积在所述晶片的整个表面上，
    沉积以及图案化所述薄半绝缘层(34)上的金属电极(21、22/23)以及
    退火以使所述金属电极(21、22/23)穿过所述薄半绝缘层(34)。
  11. 根据权利要求10所述的制造方法，其中所述半绝缘层(34)包括任何高电阻率材料，包含但不限于，氮化钛、多晶硅以及非晶硅。
  12. 根据权利要求10所述的制造方法，其中所述沉积方法包含化学气相沉积、低压化学气相沉积、等离子体增强化学气相沉积或溅镀。
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