WO2015093090A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2015093090A1 WO2015093090A1 PCT/JP2014/070519 JP2014070519W WO2015093090A1 WO 2015093090 A1 WO2015093090 A1 WO 2015093090A1 JP 2014070519 W JP2014070519 W JP 2014070519W WO 2015093090 A1 WO2015093090 A1 WO 2015093090A1
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- layer
- crack
- solder
- crack starting
- semiconductor device
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Definitions
- the technique disclosed in this specification relates to a semiconductor device including a solder layer.
- Patent Document 1 Japanese Unexamined Patent Publication No. 2011-023631 discloses a technique for improving resistance to cracks generated in a semiconductor device.
- the configuration disclosed in Patent Document 1 includes a semiconductor element and an electrode layer disposed to face the semiconductor element.
- this configuration includes an intermediate bonding layer and a solder bonding layer on the surface of the semiconductor element facing the electrode layer.
- a semiconductor element protective resin is formed on the semiconductor element and at least on the outer peripheral surface area between the intermediate bonding layer and the solder bonding layer.
- an object of the present specification is to provide a semiconductor device in which cracks are unlikely to occur in an electrode layer.
- a semiconductor device disclosed in this specification includes a semiconductor layer, an electrode layer disposed on the semiconductor layer, a crack starting layer disposed on the semiconductor layer, and the electrode layer and the crack starting layer in contact with each other.
- a solder layer The joining force between the solder layer and the crack initiation layer is smaller than the joining force between the solder layer and the electrode layer.
- the crack starting layer becomes a crack starting point, and the solder layer cracks before the electrode layer. If there is no crack starting layer, there is no chance of cracking, so there is a risk of cracks entering not the solder layer but the electrode layer. Therefore, cracks can be prevented from entering the electrode layer.
- the crack starting layer may be disposed on the electrode layer, and the thickness of the crack starting layer may be smaller than the width of the crack starting layer.
- the electrode layer may be formed of a material that is easier to form an alloy with respect to the solder layer than the crack starting layer.
- the crack starting layer may be formed of any one of aluminum, aluminum silicon, carbon, or polyimide resin.
- FIG. 2 is an enlarged cross-sectional view (II-II cross-sectional view of FIG. 1) showing the main part of the semiconductor device. It is sectional drawing which expands and shows the principal part of the semiconductor device which concerns on other embodiment. Furthermore, it is sectional drawing which expands and shows the principal part of the semiconductor device which concerns on other embodiment. It is a top view of the semiconductor device concerning other embodiments. It is a top view of the semiconductor device concerning other embodiments. It is a top view of the semiconductor device concerning other embodiments. It is a top view of the semiconductor device concerning other embodiments. It is a top view of the semiconductor device concerning other embodiments. It is a top view of the semiconductor device concerning other embodiments. It is a top view of the semiconductor device concerning other embodiments.
- the semiconductor device 1 includes a semiconductor layer 2, an electrode layer 3 disposed on the semiconductor layer 2, and a crack starting layer 10 disposed on the semiconductor layer 2. And a solder layer 4 in contact with the electrode layer 3 and the crack initiation layer 10. Each layer is laminated in the vertical direction (z direction). Since the crack starting layer 10 is covered with the solder layer 4 and cannot be visually recognized in the plan view of FIG. 1, the crack starting layer 10 is indicated by a solid line in FIG.
- the semiconductor layer 2 is formed by implanting impurities into a semiconductor substrate such as silicon (Si) or silicon carbide (SiC) to form n-type or p-type regions.
- a semiconductor substrate such as silicon (Si) or silicon carbide (SiC)
- Si silicon
- SiC silicon carbide
- a diode, a transistor, or a thyristor can be used as the semiconductor layer 2.
- MOSFET Metal-Oxide-Semiconductor-Field-Effect-Transistor
- IGBT Insulated Gate-Bipolar-Transistor
- the electrode layer 3 includes a first layer 31 disposed on the surface of the semiconductor layer 2 and a second layer 32 disposed on the surface of the first layer 31.
- the first layer 31 is in contact with the semiconductor layer 2, and the second layer 32 is in contact with the solder layer 4.
- the joining force between the solder layer 4 and the electrode layer 3 (second layer 32) is larger than the joining force between the solder layer 4 and the crack starting point layer 10.
- the alloy layer is more easily formed than the crack starting layer 10.
- a material that is easier to form an alloy with respect to the material of the solder layer 4 than the material of the crack starting point layer 10. is used. More specifically, as the material of the second layer 32, for example, nickel (Ni) or copper (Cu) can be used.
- the protective layer 6 is disposed between the end of the first layer 31 and the end of the second layer 32 of the electrode layer 3.
- a material of the protective layer 6 for example, polyimide resin (PI) can be used.
- the solder layer 4 is disposed on the surface of the electrode layer 3.
- the solder layer 4 joins the member 5 to be joined to the electrode layer 3.
- the solder layer 4 is filled between the electrode layer 3 and the member 5 to be joined.
- the member 5 to be joined is not particularly limited, but is a lead frame made of metal such as copper (Cu), for example.
- the member 5 to be joined is electrically connected to the electrode layer 3 through the solder layer 4.
- a known material for soldering can be used.
- an alloy containing tin (Sn), silver (Ag), and copper (Cu) as a main component can be used.
- the thermal expansion coefficient of the solder layer 4 and the thermal expansion coefficient of the member 5 to be joined are different.
- the solder layer 4 includes a first region 41 located between the semiconductor layer 2 and the member to be joined 5 and a second region 42 located outside the first region 41.
- the first region 41 is disposed below the bonded member 5.
- the second region 42 protrudes from the bonded member 5 in the lateral direction (x direction) and is disposed above the protective layer 6.
- the crack starting point layer 10 is disposed inside the second region 42.
- the crack starting point layer 10 is disposed on the electrode layer 3 and is disposed at a boundary portion between the electrode layer 3 and the solder layer 4.
- the crack starting point layer 10 is disposed on the second layer 32 of the electrode layer 3.
- the crack starting point layer 10 is disposed at a position in contact with the end of the solder layer 4.
- the crack starting point layer 10 is entirely covered with the solder layer 4 and buried in the solder layer 4.
- the solder layer 4 surrounds the crack starting layer 10 and is joined to the electrode layer 3 around the crack starting layer 10.
- the crack starting point layer 10 extends along the surface of the electrode layer 3.
- the crack starting point layer 10 is inclined with respect to the first portion 101 extending in the direction along the surface of the semiconductor layer 2 (lateral direction: x direction) and the first portion 101, and the semiconductor layer is separated from the first portion 101. And a second portion 102 extending toward the second side.
- the first portion 101 is located on the outer side (the end portion side of the solder layer 4), and the second portion 102 is located on the inner side of the first portion 101.
- a contact surface between the solder layer 4 and the crack starting point layer 10 is bent at a boundary portion between the first portion 101 and the second portion 102.
- a plurality of crack initiation layers 10 are disposed along the end of the solder layer 4.
- a solder layer 4 is filled around each crack starting layer 10.
- the crack starting point layer 10 is arranged around the member to be bonded 5 so as to surround the member to be bonded 5 in plan view.
- the bonding force between the solder layer 4 and the crack initiation layer 10 is smaller than the bonding force between the solder layer 4 and the electrode layer 3.
- a material that is difficult to form an alloy with the material of the solder layer 4 is used as the material of the crack starting layer 10 (a material that has poor wettability with the material of the solder layer 4 is used as the material of the crack starting layer 10. ).
- aluminum (Al), aluminum silicon (AlSi), carbon (C), polyimide resin (PI), or the like can be used as the material of the crack starting point layer 10.
- the thickness t of the crack starting layer 10 is preferably smaller than the width w of the crack starting layer 10.
- the thickness t of the crack starting layer 10 is the distance between the ends of the crack starting layer 10 in the longitudinal direction (z direction), and the width w is the distance between the ends of the crack starting layer 10 in the lateral direction (x direction). It is.
- a current flows by applying a voltage to the semiconductor layer 2.
- a current flows through the semiconductor layer 2
- heat is generated, and the temperature of the semiconductor device 1 rises.
- the voltage application is stopped, the temperature of the semiconductor device 1 decreases.
- stress is applied to the inside of the semiconductor device 1 by a cycle of temperature increase and decrease.
- the crack starting point layer 10 becomes a crack starting point, and the solder layer 4 cracks. That is, if there is no crack starting layer 10, there is no chance of cracking, and therefore there is a risk that cracks may occur in the electrode layer 3 instead of the solder layer 4.
- the semiconductor device cannot be used.
- the bonding force between the solder layer 4 and the crack starting layer 10 is smaller than the bonding force between the solder layer 4 and the electrode layer 3.
- the solder layer 4 is cracked before 3. Thereby, a crack can be made difficult to enter the electrode layer 3.
- the electrical resistance in the solder layer 4 increases and the temperature rises higher than usual. Therefore, the deterioration of the semiconductor device 1 is avoided by detecting the temperature rise and issuing a warning. be able to.
- the crack generated from the crack starting layer 10 can be guided in the width direction (x direction). Thereby, it can suppress that a crack extends in the vertical direction (z direction), and can make it difficult for the crack to enter the electrode layer 3 and the semiconductor layer 2 from the solder layer 4. Moreover, since the crack starting point layer 10 is in contact with the end portion of the solder layer 4, it is possible to make a crack at the end portion of the solder layer 4, and to prevent the crack from being generated at the center portion of the solder layer 4. it can.
- the crack starting layer 10 is formed on the second layer 32 of the electrode layer 3.
- the present invention is not limited to this configuration, and the crack starting layer 10 is formed below the second layer 32. It may be formed.
- the crack starting layer 10 is disposed on the first layer 31, and the second layer 32 is disposed on the crack starting layer 10.
- an opening 35 is formed at a position where the crack starting point layer 10 is formed, and the crack starting point layer 10 is exposed from the opening 35.
- the solder layer 4 covers the opening 35 and is in contact with the exposed crack initiation layer 10.
- the crack starting layer 10 having this configuration also has a function as the protective layer 6 in the semiconductor device 1 shown in FIG. In FIG. 3, the same components as those in FIG.
- edge part of the 2nd layer 32 of the electrode layer 3 was arrange
- each crack starting layer 10 may be arranged so as to extend linearly along the end of the solder layer 4.
- Each crack starting point layer 10 is disposed so as to face the whole of each side of the bonded member 5.
- the some crack origin layer 10 may be arrange
- the plurality of crack initiation layers 10 extend in a straight line and are spaced apart from each other in the longitudinal direction.
- the some crack origin layer 10 may be arrange
- the crack starting point layer 10 in one row is disposed at a position overlapping the member to be bonded 5 in the z direction, and the crack starting point layer 10 in the other row is disposed at a position not overlapping with the member to be bonded 5 in the z direction.
- the some crack origin layer 10 may be arrange
- the crack starting point layer 10 is not disposed at a position facing the other two sides (long sides) of the member 5 to be joined.
- the some crack origin layer 10 located in a line along each side of the to-be-joined member 5 may be arrange
- a plurality of crack starting layers 10 arranged in two rows along one side in the y direction of the member to be bonded 5 are arranged so as not to overlap in the x direction by shifting in the y direction.
- 5 to 9 also causes cracks in the solder layer 4 with the crack starting point layer 10 as a trigger.
- the same components as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.
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Abstract
半導体装置1は、半導体層2と、半導体層2上に配置された電極層3と、半導体層2の上側に配置されたクラック起点層10と、電極層3およびクラック起点層10に接触するはんだ層4とを備えている。はんだ層4とクラック起点層10との接合力がはんだ層4と電極層3との接合力より小さい。
Description
本明細書に開示の技術は、はんだ層を備える半導体装置に関する。
一般的な半導体装置では、使用中に温度の上昇と下降が繰り返される温度サイクルにより、半導体装置の内部に応力が加わり、クラック(ひび割れ)が生じることがある。特許文献1(日本国特開2011-023631号公報)には、半導体装置に生じるクラックに対する耐性を向上させるための技術が開示されている。特許文献1に開示の構成は、半導体素子と、半導体素子に対向して配置された電極層とを備えている。また、この構成は、半導体素子の電極層に対向する側の面に中間接合層及びはんだ接合層を備えている。また、半導体素子上、および少なくとも中間接合層とはんだ接合層との間の外周面域に、半導体素子保護樹脂が被覆形成されている。
特許文献1の技術では、半導体素子保護樹脂を形成することにより、半導体装置の耐クラック性を向上させている。しかしながら、特許文献1の技術においても温度サイクルにより半導体装置の内部に応力が加わったときにクラックが生じる可能性がある。また、クラックが生じたときに、そのクラックが電極層に進行する可能性がある。そこで本明細書は、電極層にクラックが入りにくい半導体装置を提供することを目的とする。
本明細書に開示する半導体装置は、半導体層と、前記半導体層上に配置された電極層と、前記半導体層の上側に配置されたクラック起点層と、前記電極層および前記クラック起点層に接触するはんだ層と、を備えている。前記はんだ層と前記クラック起点層との接合力が前記はんだ層と前記電極層との接合力より小さい。
このような構成によれば、温度サイクルにより半導体装置の内部に応力が加わったときにクラック起点層がクラックの起点となり、電極層より先にはんだ層にクラックが入る。クラック起点層が存在しないと、クラックが生じるきっかけがないので、はんだ層ではなく電極層にクラックが入るおそれがあるが、上記構成によればクラック起点層をきっかけにしてはんだ層にクラックが入る。よって、電極層にクラックが入りにくくすることができる。
上記半導体装置において、前記クラック起点層が前記電極層上に配置されており、前記クラック起点層の厚みが前記クラック起点層の幅よりも小さくてもよい。
また、前記電極層が、前記クラック起点層に比べて、前記はんだ層に対して合金を形成し易い材料によって形成されていてもよい。
また、前記クラック起点層は、アルミニウム、アルミシリコン、カーボン、または、ポリイミド樹脂のいずれかにより形成されていてもよい。
以下、実施形態について添付図面を参照して説明する。実施形態に係る半導体装置1は、図1及び図2に示すように、半導体層2と、半導体層2上に配置された電極層3と、半導体層2の上側に配置されたクラック起点層10と、電極層3およびクラック起点層10に接触するはんだ層4と、を備えている。各層は縦方向(z方向)に積層されている。なお、クラック起点層10ははんだ層4に覆われているので図1の平面図において本来視認することはできないが、説明のために図1においてクラック起点層10を実線で示している。
半導体層2は、例えばシリコン(Si)や炭化ケイ素(SiC)等の半導体基板に不純物を注入することによりn型又はp型の各領域を形成したものである。この半導体層2としては、例えばダイオード、トランジスタ、又はサイリスタなどを用いることができる。より具体的には、MOSFET(Metal Oxide Semiconductor Field Effect Transistor)やIGBT(Insulated Gate Bipolar Transistor)などを用いることができる。
電極層3は、半導体層2の表面に配置された第1層31と、第1層31の表面に配置された第2層32とを備えている。第1層31は半導体層2に接触しており、第2層32ははんだ層4に接触している。はんだ層4と電極層3(第2層32)との接合力は、はんだ層4とクラック起点層10との接合力より大きい。電極層3(第2層32)について、はんだ層4との接合力を大きくするためには、クラック起点層10に比べて、はんだ層4に対して合金を形成し易い構成にする。具体的には、はんだ層4と接合する電極層3の表面側の第2層32の材料として、クラック起点層10の材料に比べて、はんだ層4の材料に対して合金を形成し易い材料を用いる。より具体的には、第2層32の材料として、例えばニッケル(Ni)や銅(Cu)を用いることができる。
電極層3の第1層31の端部と第2層32の端部との間には保護層6が配置されている。保護層6の材料としては、例えばポリイミド樹脂(PI)等を用いることができる。
はんだ層4は、電極層3の表面に配置されている。はんだ層4は、電極層3に対して被接合部材5を接合する。はんだ層4は、電極層3と被接合部材5の間に充填されている。被接合部材5は、特に限定されるものではないが、例えば銅(Cu)などの金属製のリードフレームである。被接合部材5は、はんだ層4を介して電極層3と通電する。はんだ層4の材料としては、はんだ付けを行うための公知の材料を用いることができ、例えば錫(Sn)、銀(Ag)、銅(Cu)を主成分として含む合金を用いることができる。はんだ層4の熱膨張率と被接合部材5の熱膨張率は異なっている。また、はんだ層4は、半導体層2と被接合部材5の間に位置する第1領域41と、第1領域41より外側に位置する第2領域42とを備えている。第1領域41は、被接合部材5の下方に配置されている。第2領域42は、被接合部材5から横方向(x方向)へはみ出しており、保護層6の上方に配置されている。第2領域42の内部にクラック起点層10が配置されている。
クラック起点層10は、電極層3の上に配置されており、電極層3とはんだ層4との境界部分に配置されている。クラック起点層10は、電極層3の第2層32の上に配置されている。クラック起点層10は、はんだ層4の端部と接触する位置に配置されている。クラック起点層10は、はんだ層4により全体が覆われており、はんだ層4の内部に埋没している。はんだ層4を平面視したときに、はんだ層4は、クラック起点層10を取り囲んでおり、クラック起点層10の周囲において電極層3と接合している。クラック起点層10は、電極層3の表面に沿って延びている。また、クラック起点層10は、半導体層2の表面に沿う方向(横方向:x方向)に延びる第1部分101と、第1部分101に対して傾斜しており、第1部分101から半導体層2側に向かって延びる第2部分102とを備えている。第1部分101が外側(はんだ層4の端部側)に位置し、第2部分102が第1部分101より内側に位置している。はんだ層4とクラック起点層10との接触面は、第1部分101と第2部分102の境界部分において屈曲している。また、平面視において、はんだ層4の端部に沿って複数のクラック起点層10が配置されている。各クラック起点層10の周囲にはんだ層4が充填されている。また、クラック起点層10は、平面視において、被接合部材5を取り囲むように、被接合部材5の周囲に配置されている。
はんだ層4とクラック起点層10との接合力は、はんだ層4と電極層3との接合力より小さい。クラック起点層10について、はんだ層4との接合力を小さくするためには、はんだ層4と合金を形成し難い構成にする。具体的には、クラック起点層10の材料として、はんだ層4の材料と合金を形成し難い材料を用いる(クラック起点層10の材料として、はんだ層4の材料と濡れ性が悪い材料を用いる。)。より具体的には、クラック起点層10の材料として、例えばアルミニウム(Al)、アルミシリコン(AlSi)、カーボン(C)、ポリイミド樹脂(PI)等を用いることができる。はんだ層4とクラック起点層10との接合力がはんだ層4と電極層3との接合力より小さいことから、クラック起点層10を起点にして、はんだ層4にクラックが入り易くなる。はんだ層4に横方向(x方向)にクラックを入れる観点から、クラック起点層10の厚みtは、クラック起点層10の幅wより小さいことが好ましい。クラック起点層10の厚みtは、縦方向(z方向)におけるクラック起点層10の端部間の距離であり、幅wは、横方向(x方向)におけるクラック起点層10の端部間の距離である。
上記の構成を備える半導体装置1によれば、半導体層2に電圧を印加することにより電流が流れる。半導体層2に電流が流れると熱が発生し、半導体装置1の温度が上昇する。また、電圧の印加をやめると、半導体装置1の温度が低下する。このとき、温度の上昇と低下のサイクルにより、半導体装置1の内部に応力が加わる。上記の半導体装置1によれば、内部に応力が加わったときにクラック起点層10がクラックの起点となり、はんだ層4にクラックが入る。すなわち、クラック起点層10が存在しないと、クラックが生じるきっかけがないので、はんだ層4ではなく電極層3にクラックが入るおそれがある。電極層3にクラックが入ると、半導体装置を使用できなくなる。しかしながら、上記の半導体装置1によれば、はんだ層4とクラック起点層10との接合力がはんだ層4と電極層3との接合力より小さいので、クラック起点層10をきっかけにして、電極層3より先にはんだ層4にクラックが入る。これにより、電極層3にクラックが入り難くすることができる。また、はんだ層4にクラックが入ると、はんだ層4における電気抵抗が大きくなり、通常より温度上昇が高くなるので、その温度上昇を検出して警告を出すことにより半導体装置1の劣化を回避することができる。
また、クラック起点層10の厚みtがクラック起点層10の幅wよりも小さいので、クラック起点層10を起点にして発生するクラックを幅方向(x方向)に導くことができる。これにより、クラックが縦方向(z方向)に延びることを抑制でき、クラックがはんだ層4から電極層3や半導体層2に入り難くすることができる。また、クラック起点層10がはんだ層4の端部に接触しているので、はんだ層4の端部にクラックを入れることができ、はんだ層4の中央部にクラックが発生することを防ぐことができる。
以上、一実施形態について説明したが、具体的な態様は上記実施形態に限定されるものではない。例えば、上記実施形態では電極層3の第2層32の上にクラック起点層10が形成されていたが、この構成に限定されるものではなく、第2層32の下にクラック起点層10が形成されていてもよい。他の実施形態では、図3に示すように、第1層31の上にクラック起点層10が配置されており、クラック起点層10の上に第2層32が配置されている。第2層32には、クラック起点層10が形成されている位置において、開口部35が形成されており、開口部35からクラック起点層10が露出している。はんだ層4は、開口部35を覆っており、露出したクラック起点層10に接触している。この構成のクラック起点層10は、図1に示す半導体装置1における保護層6としての機能も有している。なお、図3において、図2と同様の構成については同一の符号を付して説明を省略する。
また、上記実施形態では電極層3の第2層32の端部が保護層6の上に配置されていたが、この構成に限定されるものではなく、図4に示すように、保護層6の上に第2層32の端部が配置されていなくてもよい。なお、図4において、図2と同様の構成については同一の符号を付して説明を省略する。
また、平面視におけるクラック起点層10の配置位置は特に限定されるものではない。例えば、図5に示すように、各クラック起点層10がはんだ層4の端部に沿って直線状に延びるように配置されていてもよい。各クラック起点層10は、被接合部材5の各辺の全体にそれぞれ対向するように配置されている。また、図6に示すように、被接合部材5の一辺に対向して複数のクラック起点層10が配置されていてもよい。複数のクラック起点層10は、直線状に延び、長手方向に互いに間隔をあけて配置されている。また、図7に示すように、複数のクラック起点層10が2列に並んで配置されていてもよい。一方の列のクラック起点層10はz方向において被接合部材5と重なる位置に配置されており、他方の列のクラック起点層10はz方向において被接合部材5と重ならない位置に配置されている。また、図8に示すように、被接合部材5の2辺(短辺)に対向するように複数のクラック起点層10が配置されていてもよい。被接合部材5の他の2辺(長辺)に対向する位置には、クラック起点層10が配置されていない。また、図9に示すように、被接合部材5の各辺に沿って2列に並んだ複数のクラック起点層10が互いにずれた位置に配置されていてもよい。例えば、被接合部材5のy方向の1辺に沿って2列に並んだ複数のクラック起点層10が、互いにy方向にずれることにより、x方向において重ならないように配置されている。図5~図9に示す各構成によっても、クラック起点層10をきっかけにしてはんだ層4にクラックが入る。なお、図5~図9において、図1と同様の構成については同一の符号を付して説明を省略する。
以上、本発明の具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。
1;半導体装置
2;半導体層
3;電極層
4;はんだ層
5;被接合部材
6;保護層
10;クラック起点層
31;第1層
32;第2層
35;開口部
41;第1領域
42;第2領域
101;第1部分
102;第2部分
2;半導体層
3;電極層
4;はんだ層
5;被接合部材
6;保護層
10;クラック起点層
31;第1層
32;第2層
35;開口部
41;第1領域
42;第2領域
101;第1部分
102;第2部分
Claims (4)
- 半導体層と、
前記半導体層上に配置された電極層と、
前記半導体層の上側に配置されたクラック起点層と、
前記電極層および前記クラック起点層に接触するはんだ層と、を備え、
前記はんだ層と前記クラック起点層との接合力が前記はんだ層と前記電極層との接合力より小さい、半導体装置。 - 前記クラック起点層が前記電極層上に配置されており、
前記クラック起点層の厚みが前記クラック起点層の幅よりも小さい、請求項1に記載の半導体装置。 - 前記電極層が、前記クラック起点層に比べて、前記はんだ層に対して合金を形成し易い材料によって形成されている、請求項1又は2に記載の半導体装置。
- 前記クラック起点層は、アルミニウム、アルミシリコン、カーボン、または、ポリイミド樹脂のいずれかにより形成されている、請求項1から3のいずれか一項に記載の半導体装置。
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CN201480069435.XA CN105830203B (zh) | 2013-12-20 | 2014-08-04 | 半导体装置 |
US15/029,393 US9553067B2 (en) | 2013-12-20 | 2014-08-04 | Semiconductor device |
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JP6179538B2 (ja) * | 2015-03-04 | 2017-08-16 | トヨタ自動車株式会社 | 半導体装置 |
US11114387B2 (en) * | 2017-02-15 | 2021-09-07 | Industrial Technology Research Institute | Electronic packaging structure |
Citations (3)
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JP2008166432A (ja) * | 2006-12-27 | 2008-07-17 | Sharp Corp | クラックを生じにくい半田接合部、該半田接続部を備える回路基板などの電子部品、半導体装置、及び電子部品の製造方法 |
JP2010212294A (ja) * | 2009-03-06 | 2010-09-24 | Toyota Motor Corp | 半導体装置 |
JP2013211497A (ja) * | 2012-03-30 | 2013-10-10 | Keihin Corp | 部品接合構造 |
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US8004075B2 (en) * | 2006-04-25 | 2011-08-23 | Hitachi, Ltd. | Semiconductor power module including epoxy resin coating |
WO2010047139A1 (ja) * | 2008-10-24 | 2010-04-29 | 三菱電機株式会社 | はんだ合金および半導体装置 |
JP2011023631A (ja) | 2009-07-17 | 2011-02-03 | Panasonic Corp | 接合構造体 |
US9905524B2 (en) * | 2011-07-29 | 2018-02-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structures in semiconductor device and packaging assembly |
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JP2010212294A (ja) * | 2009-03-06 | 2010-09-24 | Toyota Motor Corp | 半導体装置 |
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DE112014005925B4 (de) | 2020-08-13 |
JP2015122349A (ja) | 2015-07-02 |
CN105830203B (zh) | 2018-05-04 |
JP6070532B2 (ja) | 2017-02-01 |
US9553067B2 (en) | 2017-01-24 |
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