WO2015085608A1 - 液晶显示设备及其像素驱动方法 - Google Patents

液晶显示设备及其像素驱动方法 Download PDF

Info

Publication number
WO2015085608A1
WO2015085608A1 PCT/CN2013/089771 CN2013089771W WO2015085608A1 WO 2015085608 A1 WO2015085608 A1 WO 2015085608A1 CN 2013089771 W CN2013089771 W CN 2013089771W WO 2015085608 A1 WO2015085608 A1 WO 2015085608A1
Authority
WO
WIPO (PCT)
Prior art keywords
pixel
transistor
pixel electrode
scan line
sub
Prior art date
Application number
PCT/CN2013/089771
Other languages
English (en)
French (fr)
Inventor
陈政鸿
许哲豪
王醉
姚晓慧
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to EA201690932A priority Critical patent/EA032519B1/ru
Priority to GB1607987.3A priority patent/GB2540453B/en
Priority to KR1020167012785A priority patent/KR101906924B1/ko
Priority to US14/234,393 priority patent/US9224354B2/en
Priority to JP2016535098A priority patent/JP2017504822A/ja
Publication of WO2015085608A1 publication Critical patent/WO2015085608A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G09G2300/0447—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/08—Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present invention relates to a pixel driving method, and more particularly to a pixel driving method of a liquid crystal display device.
  • liquid crystal display panels With the advancement of the technology of liquid crystal display panels, different manufacturers have developed different types of liquid crystal display panels, among which there are twisted nematic (Twisted) Nematic, TN), Vertical Alignment (VA), Planar Conversion (In-Plane) Switching, IPS) and polymer stabilized vertical alignment (Polymer Stabilized Vertical) Alignment, PSVA) and other types.
  • VA vertical alignment
  • VA Polymer Stabilized Vertical
  • one pixel is divided into two parts, one part is the main pixel area, and the other part is the sub-pixel area, which improves the large viewing angle distortion by controlling the voltage of the two areas, generally called low.
  • Color shift Color shift, LCS Color shift Color shift
  • the low color shift design is mainly divided into two categories. One is to control the main pixel and the sub pixel by adding data or scanning lines, and the disadvantage is that the number of driving lines is increased. The other is to design a capacitor on the array substrate to control the main pixel and sub-pixel potential inconsistency to achieve a low color shift effect. However, since the capacitance is designed on the array substrate, the aperture ratio of the pixel is affected.
  • FIG. 1 shows a schematic diagram of a pixel structure design of a conventional liquid crystal display device.
  • the two scanning lines 102 are on the same side of the main pixel area 104 and the sub-pixel area 106, and the capacitor is used for low color shift. Since the scan line 102 is on the same side of the main pixel region 104 and the sub-pixel region 106, the drain line connecting the sub-pixel region 106 passes through the main pixel region. If the drain line has metal particles in the process, the drain is caused. A short circuit occurs between the line and the main pixel area, resulting in a low color shift failure and an abnormal display.
  • An object of the present invention is to provide a pixel driving method of a liquid crystal display device, which can improve the aperture ratio of a pixel and effectively avoid the problem of short circuit.
  • Another object of the present invention is to provide a liquid crystal display device which combines two conventional scanning lines into one scanning line so that the scanning line can increase the potential of the pixels (main pixel and sub-pixel) of the current stage. It is also possible to lower the voltage difference of the sub-pixel electrode of the current level in the driving time of the next-level pixel by using the sharing capacitor to achieve low color shift.
  • the present invention constructs a pixel driving method for a liquid crystal display device, comprising a first level pixel, a second level pixel, a first transistor, a second transistor, a third transistor, a first scan line, a second scan line, and a plurality of data a line, a main pixel electrode, a sub-pixel electrode and a sharing capacitor, the pixel driving method comprising: enabling the first scan line during a first enable, and the main pixel electrode of the first level pixel Charging of the sub-pixel electrode; stopping enabling the first scan line during a second enable period to reduce a voltage of the main pixel electrode and the sub-pixel electrode of the first-level pixel; During the third enable period, enabling the second scan line and turning on the third transistor of the first-level pixel; and during the fourth enable, stopping enabling the second scan line, and During the third enabling period and the fourth enabling period, the sharing capacitor of the third transistor is used to pull down the voltage of the sub-pixel electrode of the first-level pixel
  • the second scan line is enabled to turn on the third transistor of the first-level pixel and the second-level pixel a transistor and the second transistor.
  • the pixel driving method is used for a vertical imaging type (VA) liquid crystal display device, and the second level pixel is a next level pixel of the first level pixel.
  • VA vertical imaging type
  • the voltage of the main pixel electrode and the sub-pixel electrode may be due to a feed effect (feed Through effect).
  • the first transistor and the second transistor of the second-level pixel share a scan line with the third transistor of the first-level pixel.
  • Another object of the present invention is to provide a liquid crystal display device which combines two conventional scanning lines into one scanning line so that the scanning line can increase the potential of the pixels (main pixel and sub-pixel) of the current stage. It is also possible to lower the voltage difference of the sub-pixel electrode of the current level in the driving time of the next-level pixel by using the sharing capacitor to achieve low color shift.
  • the liquid crystal display device is a vertical alignment type liquid crystal display device.
  • the scan line (G_N) is enabled to charge the main pixel electrode of the pixel of the current stage and the sub-pixel electrode.
  • the enabling of the scan line (G_N) is stopped, and the voltage of the main pixel electrode and the sub-pixel electrode may be due to a feed effect (feed Through effect).
  • the scan line (G_N+1) is enabled, and the main pixel electrode of the pixel of the next stage and the sub-pixel electrode are Charging and turning on the third transistor.
  • the enabling of the scan line (G_N+1) is stopped, and during the third enabling period and the fourth enabling period, utilizing the The shared capacitance of the three transistors pulls down the voltage of the sub-pixel electrode of the pixel of the current stage.
  • the first transistor of the pixel of the first stage and the second transistor share a scan line with the third transistor of the next stage pixel.
  • the pixel driving method of the liquid crystal display device of the present invention can increase the aperture ratio of a pixel and effectively avoid the problem of short circuit.
  • the scan line can increase the potential of the next-stage pixel (the main pixel and the sub-pixel). It is also possible to lower the sub-pixel voltage of the pixel of the current stage by using the sharing capacitance of the third transistor in the driving time of the next-stage pixel to achieve the purpose of low color shift.
  • FIG. 1 is a schematic view showing a pixel structure design of a conventional liquid crystal display device
  • FIG. 2A is a schematic diagram of a liquid crystal display device according to an embodiment of the present invention.
  • FIG. 2B is a partial view showing a liquid crystal display device according to an embodiment of the present invention.
  • FIG. 2C is an equivalent circuit diagram of the liquid crystal display device of FIG. 2B;
  • FIG. 3 is a voltage timing diagram of a liquid crystal display device according to an embodiment of the present invention.
  • FIG. 4 is a diagram showing a pixel driving method of a liquid crystal display device according to an embodiment of the present invention.
  • a plurality of scanning lines 202 are arranged along the column direction, a plurality of data lines 204 are arranged in a row direction perpendicular to the column direction, and a plurality of pixels 206 are arranged in an array.
  • One of the pixels 206 is located between two adjacent scan lines 202 and two adjacent data lines 204.
  • 2B is a schematic view partially showing a liquid crystal display device according to an embodiment of the present invention
  • FIG. 2C is an equivalent circuit diagram of the liquid crystal display device shown in FIG. 2B.
  • 2B and 2C show only two scanning lines (G_N, G_N+1) 202, a schematic diagram of two data lines (D_M, D_M+1) 204 and one pixel 206.
  • the pixel 206 includes a main pixel electrode 2061 and a sub-pixel electrode 2062, a first transistor (TFT_A) 2063, a second transistor (TFT_B) 2064, and a third transistor (TFT_C) 2065.
  • the gates of the first transistor 2063 and the second transistor 2064 are electrically connected to the scan line (G_N) 202, and the drains of the first transistor 2063 and the second transistor 2064 are electrically connected to the main pixel electrode 2061 and the sub-pixel electrode 2062, respectively.
  • the gate of the third transistor 2065 is electrically connected to the scan line (G_N+1) 202, the source of the third transistor 2065 is electrically connected to the sub-pixel electrode, and the drain of the third transistor 2065 is connected to a shared capacitor (C_share) ) 2066.
  • the scan signal (gn) enables the scan line (G_N) 202 during the first enable period to turn on the first transistor (TFT_A) 2063 and the second transistor (TFT_B) 2064
  • the image data signal is input from the data line 204 to
  • the scan line (G_N) 202 is connected to the pixel 206. Therefore, the voltages of the main pixel electrode 2061 and the sub-pixel electrode 2062 rise.
  • the scan signal (gn) stops enabling the scan line (G_N) 202 during the second enable
  • the main pixel electrode 2061 and the sub-pixel electrode 2062 may be fed due to the feed effect. Through Effect) is slightly reduced.
  • the scan signal (gn) enables the scan line (G_N+1) 202 during the third enable period
  • the image data signal is input to the pixel of the next stage, and the third transistor (TFT_C) 2065 is simultaneously turned on.
  • the scan signal (gn) stops enabling the scan line (G_N+1) 202
  • the sub-pixel electrode 2062 in the upper stage is connected to the shared capacitor (C_share) 2066 of the third transistor 2065. Its effect causes its potential to be pulled low.
  • this scan line can increase the potential of the pixels (main pixel and sub-pixel) of the current stage, and can also add the sub-pixel electrode of the stage.
  • the voltage difference is driven by the sharing capacitor at the driving time of the next stage pixel to achieve low color shift.
  • Fig. 3 is a timing chart showing the voltage of the liquid crystal display device of the embodiment of the present invention.
  • the liquid crystal display device of this embodiment includes a first level pixel, a second level pixel, a first transistor, a second transistor, a third transistor, a first scan line, a second scan line, a plurality of data lines, a main pixel electrode, Sub-pixel electrode and sharing capacitor.
  • the second-level pixel is the next-level pixel of the first-level pixel
  • the second-level scan line is the next-pole scan line of the first scan line
  • the first-level pixel and the second-level pixel both include the main pixel electrode and the sub-pixel electrode. As shown in FIG.
  • the first-level pixel is Charging of the main pixel electrode and the sub-pixel electrode.
  • the scan signal (gn) stops enabling the first scan line (G_N), and the voltage of the main pixel electrode and the sub-pixel electrode of the first-stage pixel is due to the feed effect (feed Through Effect) is slightly reduced.
  • the scan signal (gn) enables the second scan line (G_N+1) to enable the second level of pixels and turn on the third transistor.
  • the scan signal stops enabling the second scan line (G_N+1), and during the third enable period t3 and the fourth enable period t4, the shared capacitor connected by the third transistor is used to pull down
  • the voltage of the sub-pixel electrode of the first-level pixel is such that the main pixel electrode and the sub-pixel electrode of the first-level pixel have different voltages.
  • the scan line can increase the potential of the second-level pixel (the main pixel and the sub-pixel)
  • the sub-pixel electrode of the first-level pixel can also be used in the driving time of the second-level pixel, and the sub-pixel electrode voltage of the first-level pixel is pulled down by the sharing capacitor connected to the third transistor to achieve low color shift.
  • the liquid crystal display device includes a first level pixel, a second level pixel, a first transistor, a second transistor, a third transistor, a first scan line, a second scan line, a plurality of data lines, and a main pixel electrode.
  • the sub-pixel electrode and the sharing capacitor, and the pixel driving method includes the following steps.
  • step S402 during the first enabling period, the first scan line is enabled to charge the main pixel electrode and the sub-pixel electrode of the first level pixel.
  • step S404 When the scan signal (gn) enables the first scan line during the first enable, the first transistor and the second transistor are turned on to charge the main pixel electrode and the sub-pixel electrode of the first level pixel.
  • step S404 during the second enable period, the enabling of the first scan line and the reduction of the voltages of the main pixel electrode and the sub-pixel electrode are stopped.
  • the voltage of the main pixel electrode and the sub-pixel electrode will be due to the feed effect (feed Through Effect).
  • the second scan line is enabled to charge the main pixel electrode and the sub-pixel electrode of the second level pixel, and turn on the third transistor of the first level pixel.
  • step S408 during the fourth enable period, the enabling of the second scan line is stopped, and during the third enable period and the fourth enable period, the sharing capacitance of the third transistor of the first-level pixel is utilized to pull down the first The voltage of the sub-pixel electrode of the primary pixel.
  • the scan line can increase the potential of the second-level pixel (the main pixel and the sub-pixel)
  • the sub-pixel electrode of the first-level pixel can also be used to lower the color-shifting of the first-level pixel by using the sharing capacitance of the third transistor in the driving time of the second-level pixel to achieve low color shift.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)

Abstract

一种液晶显示设备的像素驱动方法，液晶显示设备包含第一级像素、第二级像素、第一晶体管、第二晶体管、第三晶体管、第一扫描线、第二扫描线、复数条资料线、主像素电极、次像素电极与分享电容。所述像素驱动方法包含：在第一致能期间，致能第一扫描线，将第一级像素的主像素电极与次像素电极的充电（S402）；在第二致能期间时，停止致能第一扫描线，以降低第一级像素的主像素电极与次像素电极的电压（S404）；在第三致能期间，致能第二扫描线，并开启第一级像素的第三晶体管（S406）；以及在第四致能期间，停止致能第二扫描线，并于第三致能期间与第四致能期间，利用第三晶体管的分享电容，拉低第一级像素的次像素电极的电压（S408）。

Description

液晶显示设备及其像素驱动方法 技术领域
本发明涉及一种像素驱动方法，特别是涉及一种液晶显示设备的像素驱动方法。
 背景技术
随着液晶显示面板的技术日益进步，不同厂商之间各自发展出不同类型的液晶显示面板，其中有扭曲向列型(Twisted Nematic，TN)、垂直配向技术(Vertical Alignment，VA)、平面转换（In-Plane Switching，IPS）以及聚合物稳定垂直配向型(Polymer Stabilized Vertical Alignment，PSVA)等种类。而以垂直配向(VA)作为液晶显示设备的一种显示模式时，由于在不同视角下观察到液晶指向不同，会导致大视角下观察到的颜色失真。为改善大视角颜色失真，在液晶像素设计时，将一个像素分成两部分，一部份为主像素区，另一部分为次像素区，通过控制两区电压来改善大视角失真，一般称为低色偏(low color shift, LCS)设计。
低色偏设计主要分为两类，一类是通过增加数据或扫描线，分别对主像素与次像素控制，其缺点是驱动线的数目增加。另一类是在阵列基板上设计电容，用来控制主像素与次像素电位不一致，以实现低色偏效果。但是，由于在阵列基板设计电容，会影响像素的开口率。
图1显示传统的液晶显示设备的像素结构设计的示意图。如图1所示，其采用两条扫描线102在主像素区104与次像素区106同侧的架构，利用电容做低色偏。由于扫描线102在主像素区104与次像素区106的同侧，连接次像素区106的漏极线会通过主像素区，若制程中漏极线有金属微粒(particle)，会导致漏极线和主像素区发生短路，进而导致低色偏的失效，而使显示异常。
因此，存在一种需求设计新型的液晶显示设备的像素驱动方法，可提高像素的开口率，且有效避免短路的问题。
 技术问题
本发明的一个目的在于提供一种液晶显示设备的像素驱动方法，可提高像素的开口率，且有效避免短路的问题。
本发明的另一个目的在于提供一种液晶显示设备，藉由将传统的两条扫描线合并成一条扫描线，使得这一条扫描线既能给本级的像素(主像素与次像素)提高电位，还可以将本级的次像素电极的电压差在下一级像素的驱动时间，利用分享电容拉低，来达到低色偏的目的。
 技术解决方案
本发明构造了一种液晶显示设备的像素驱动方法，包含第一级像素、第二级像素、第一晶体管、第二晶体管、第三晶体管、第一扫描线、第二扫描线、复数条资料线、主像素电极、次像素电极与分享电容，所述像素驱动方法包含：在第一致能期间，致能所述第一扫描线，将所述第一级像素的所述主像素电极与所述次像素电极的充电；在第二致能期间时，停止致能所述第一扫描线，以降低所述第一级像素的所述主像素电极与所述次像素电极的电压；在第三致能期间，致能所述第二扫描线，并开启所述第一级像素的所述第三晶体管；以及在第四致能期间，停止致能所述第二扫描线，并于所述第三致能期间与所述第四致能期间，利用所述第三晶体管连接的所述分享电容，拉低所述第一级像素的所述次像素电极的电压。
在本发明一实施例中，在所述第三致能期间，致能所述第二扫描线以开启所述第一级像素的所述第三晶体管以及所述第二级像素的所述第一晶体管与所述第二晶体管。
在本发明一实施例中，所述像素驱动方法用于垂直配像型(VA)液晶显示设备，且所述第二级像素为所述第一级像素的下一级像素。
在本发明一实施例中，在所述第二致能期间，所述主像素电极与所述次像素电极的电压会因为馈入效应(feed through effect)而降低。
在本发明一实施例中，所述第二级像素的所述第一晶体管与所述第二晶体管与所述第一级像素的所述第三晶体管共享一条扫描线。
本发明的另一个目的在于提供一种液晶显示设备，藉由将传统的两条扫描线合并成一条扫描线，使得这一条扫描线既能给本级的像素(主像素与次像素)提高电位，还可以将本级的次像素电极的电压差在下一级像素的驱动时间，利用分享电容拉低，来达到低色偏的目的。
为解决上述技术问题，本发明构造了一种液晶显示设备，其特征在于，所述液晶显示设备包含复数个像素{P(n, m)}，n=1, 2, …, N, N+1, …, m=1, 2, …, M, M+1, …，并以阵列的形式排列，其中n, m为正整数，其中一个所述像素位于两相邻扫描线(G_N, G_N+1)与两相邻数据线(D_M, D_M+1)之间，且所述像素包含第一晶体管，所述第一晶体管的闸极电性连接所述扫描线(G_N)，所述第一晶体管的漏极电性连接主像素电极；第二晶体管，所述第二晶体管的闸极电性连接所述扫描线(G_N)，所述第二晶体管的漏极电性连接次像素电极；以及第三晶体管，所述第三晶体管的闸极电性连接所述扫描线(G_N+1)，所述第三晶体管的漏极电性连接电容，所述第三晶体管的源极电性连接所述次像素电极；其中，所述第一晶体管与所述第二晶体管用于将本级的所述像素充电，所述第三晶体管利用所述分享电容用于将下一级的所述像素的所述次像素电极的电位拉低。
在本发明一实施例中，当所述液晶显示设备为垂直配向型液晶显示设备。
在本发明一实施例中，在第一致能期间，致能所述扫描线(G_N)，将所述本级的所述像素的所述主像素电极与所述次像素电极的充电。
在本发明一实施例中，在第二致能期间时，停止致能所述扫描线(G_N)，所述主像素电极与所述次像素电极的电压会因为馈入效应(feed through effect)而降低。
在本发明一实施例中，在第三致能期间，致能所述扫描线(G_N+1)，将所述下一级的所述像素的所述主像素电极与所述次像素电极的充电，并开启所述第三晶体管。
在本发明一实施例中，在第四致能期间，停止致能所述扫描线(G_N+1)，并于所述第三致能期间与所述第四致能期间，利用所述第三晶体管的所述分享电容，拉低所述本级的所述像素的所述次像素电极的电压。
在本发明一实施例中，所述本级像素的所述第一晶体管与所述第二晶体管与所述下一级像素的所述第三晶体管共享一条扫描线。
 有益效果
本发明的液晶显示设备的像素驱动方法，可提高像素的开口率，且有效避免短路的问题。藉由将下一级像素的第一晶体管与第二晶体管与本级像素的第三晶体管共享一条扫描线，使得这一条扫描线既能给下一级像素(主像素与次像素)提高电位，还可以在下一级像素的驱动时间，利用第三晶体管的分享电容拉低本级像素的次像素电压，来达到低色偏的目的。
 附图说明
图1为传统的液晶显示设备的像素结构设计的示意图；
图2A为根据本发明实施例的液晶显示设备的示意图；
图2B部分显示根据本发明实施例的液晶显示设备的示意图；
图2C为图2B的液晶显示设备的等效电路图；
图3为本发明实施例的液晶显示设备的电压时序图；以及
图4为本发明实施例的液晶显示设备的像素驱动方法。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
图2A显示根据本发明实施例的液晶显示设备的示意图。如图2A所示，液晶显示设备20包含复数条扫描线{G_n}202、复数条数据线{D_m}204以及复数个像素{P(n, m)} 206，其中n=1, 2, …, N, N+1, …, m=1, 2, …, M, M+1, …，n与m皆为正整数。复数条扫描线202沿着列方向排列，复数条资料线204沿着垂直于列方向的行方向排列，复数个像素206以阵列的方式排列。而其中一个像素206位于两相邻扫描线202与两相邻数据线204之间。图2B为部分显示根据本发明实施例的液晶显示设备的示意图，图2C为图2B所示的液晶显示设备的等效电路图。为了说明本发明的实施例，图2B与图2C仅显示出液晶显示设备20的两条扫描线(G_N, G_N+1)202、两条资料线(D_M, D_M+1)204与一个像素206的示意图。
依旧参阅图2B与图2C，像素206包含主像素电极2061与次像素电极2062、第一晶体管(TFT_A)2063、第二晶体管(TFT_B)2064与第三晶体管(TFT_C)2065。第一晶体管2063与第二晶体管2064的闸极电性连接至扫描线(G_N)202，第一晶体管2063与第二晶体管2064的漏极分别电性连接至主像素电极2061与次像素电极2062。第三晶体管2065的闸极电性连接至扫描线(G_N+1)202，第三晶体管2065的源极电性连接至次像素电极，而第三晶体管2065的漏极连接至一分享电容(C_share)2066。当扫描信号(gn)在第一致能期间致能扫描线(G_N)202，以开启第一晶体管(TFT_A)2063与第二晶体管(TFT_B)2064，影像数据信号会从数据线204输入至与扫描线(G_N)202连接的像素206中。因此，主像素电极2061与次像素电极2062的电压会上升。而当扫描信号(gn)在第二致能期间停止致能扫描线(G_N)202，主像素电极2061与次像素电极2062会因为馈入效应(feed through effect)而被些微地降低。接着，当扫描信号(gn)在第三致能期间致能扫描线(G_N+1)202，而将影像数据信号输入至下一级的像素中，并同时开启第三晶体管(TFT_C)2065。而在第四致能期间时，扫描信号(gn)停止致能扫描线(G_N+1)202，在上一级的次像素电极2062会因为第三晶体管2065连接的分享电容(C_share)2066的作用而使其电位被拉低。因次，藉由将传统的两条扫描线合并成一条扫描线，使得这一条扫描线既能给本级的像素(主像素与次像素)提高电位，还可以将本级的次像素电极的电压差在下一级像素的驱动时间，利用分享电容拉低，来达到低色偏的目的。
图3显示本发明实施例的液晶显示设备的电压时序图。在此实施例的液晶显示设备包含第一级像素、第二级像素、第一晶体管、第二晶体管、第三晶体管、第一扫描线、第二扫描线、复数条资料线、主像素电极、次像素电极与分享电容。而第二级像素为第一级像素的下一级像素，第二扫描线为第一扫描线的下一极扫描线，且第一级像素与第二级像素均包含主像素电极与次像素电极。如图3所示，当扫描信号(gn)在第一致能期间t1致能第一扫描线(G_N)，以开启第一级像素的第一晶体管与第二晶体管，将第一级像素的主像素电极与次像素电极的充电。在第二致能期间t2时，扫描信号(gn)停止致能第一扫描线(G_N)，第一级像素的主像素电极与次像素电极的电压会因为馈入效应(feed through effect)而被些微地降低。在第三致能期间t3时，扫描信号(gn)致能第二扫描线(G_N+1)，以致能第二级像素，并开启第三晶体管。而在第四致能期间t4，扫描信号停止致能第二扫描线(G_N+1)，在第三致能期间t3与第四致能期间t4，利用第三晶体管连接的分享电容，拉低第一级像素的次像素电极的电压，以达到在第一级像素的主像素电极与次像素电极有不同的电压。藉由将第二级像素的第一晶体管与第二晶体管和第一级像素的第三晶体管共享一条扫描线，使得这一条扫描线既能给第二级像素(主像素与次像素)提高电位，还可以将第一级像素的次像素电极在第二级像素的驱动时间，利用第三晶体管连接的分享电容拉低第一级像素的次像素电极电压，来达到低色偏的目的。
图4显示本发明实施例的液晶显示设备的像素驱动方法。如图4所示，液晶显示设备包含第一级像素、第二级像素、第一晶体管、第二晶体管、第三晶体管、第一扫描线、第二扫描线、复数条资料线、主像素电极、次像素电极与分享电容，而像素驱动方法包含下列步骤。在步骤S402中，在第一致能期间，致能第一扫描线，将第一级像素的主像素电极与次像素电极的充电。当扫描信号(gn)在第一致能期间致能第一扫描线，会将第一晶体管与第二晶体管开启，以将第一级像素的主像素电极与次像素电极的充电。在步骤S404中，在第二致能期间时，停止致能第一扫描线以及降低主像素电极与次像素电极的电压。在第二致能期间，主像素电极与次像素电极的电压会因为馈入效应(feed through effect)而降低。在步骤S406中在第三致能期间，致能第二扫描线，将第二级像素的主像素电极与次像素电极的充电，并开启第一级像素的第三晶体管。在步骤S408中，在第四致能期间，停止致能第二扫描线，并于第三致能期间与第四致能期间，利用第一级像素的第三晶体管的分享电容，拉低第一级像素的次像素电极的电压。藉由将第二级像素的第一晶体管与第二晶体管与第一级像素的第三晶体管共享一条扫描线，使得这一条扫描线既能给第二级像素(主像素与次像素)提高电位，还可以将第一级像素的次像素电极在第二级像素的驱动时间，利用第三晶体管的分享电容拉低第一级像素的次像素电压，来达到低色偏的目的。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
工业实用性
序列表自由内容

Claims (12)

  1. 一种液晶显示设备的像素驱动方法，所述液晶显示设备包含第一级像素、第二级像素、第一晶体管、第二晶体管、第三晶体管、第一扫描线、第二扫描线、复数条资料线、主像素电极、次像素电极与分享电容，其中所述像素驱动方法包含：
    在第一致能期间，致能所述第一扫描线，将所述第一级像素的所述主像素电极与所述次像素电极的充电；
    在第二致能期间时，停止致能所述第一扫描线，以降低所述第一级像素的所述主像素电极与所述次像素电极的电压；
    在第三致能期间，致能所述第二扫描线，并开启所述第一级像素的所述第三晶体管；以及
    在第四致能期间，停止致能所述第二扫描线，并于所述第三致能期间与所述第四致能期间，利用所述第三晶体管连接的所述分享电容，拉低所述第一级像素的所述次像素电极的电压。
  2. 根据权利要求1所述的像素驱动方法，其中在所述第三致能期间，致能所述第二扫描线以开启所述第一级像素的所述第三晶体管以及所述第二级像素的所述第一晶体管与所述第二晶体管。
  3. 根据权利要求1所述的像素驱动方法，其中所述像素驱动方法用于垂直配像型(VA)液晶显示设备，且所述第二级像素为所述第一级像素的下一级像素。
  4. 根据权利要求1所述的像素驱动方法，其中在所述第二致能期间，所述主像素电极与所述次像素电极的电压会因为馈入效应(feed through effect)而降低。
  5. 根据权利要求1所述的像素驱动方法，其中所述第二级像素的所述第一晶体管与所述第二晶体管与所述第一级像素的所述第三晶体管共享一条扫描线。
  6. 一种液晶显示设备，所述液晶显示设备包含复数个像素{P(n, m)}，n=1, 2, …, N, N+1, …, m=1, 2, …, M, M+1, …，并以阵列的形式排列，其中n, m为正整数，其中一个所述像素位于两相邻扫描线(G_N, G_N+1)与两相邻数据线(D_M, D_M+1)之间，且所述像素包含：
    第一晶体管，所述第一晶体管的闸极电性连接所述扫描线(G_N)，所述第一晶体管的漏极电性连接主像素电极；
    第二晶体管，所述第二晶体管的闸极电性连接所述扫描线(G_N)，所述第二晶体管的漏极电性连接次像素电极；以及
    第三晶体管，所述第三晶体管的闸极电性连接所述扫描线(G_N+1)，所述第三晶体管的漏极电性连接分享电容，所述第三晶体管的源极电性连接所述次像素电极；
    其中，所述第一晶体管与所述第二晶体管用于将本级的所述像素充电，所述第三晶体管利用所述分享电容用于将下一级的所述像素的所述次像素电极的电位拉低。
  7. 根据权利要求6所述的液晶显示设备，其中当所述液晶显示设备为垂直配向型液晶显示设备。
  8. 根据权利要求6所述的的液晶显示设备，其中在第一致能期间，致能所述扫描线(G_N)，将所述本级的所述像素的所述主像素电极与所述次像素电极的充电。
  9. 根据权利要求8所述的液晶显示设备，其中在第二致能期间时，停止致能所述扫描线(G_N)，所述主像素电极与所述次像素电极的电压会因为馈入效应(feed through effect)而降低。
  10. 根据权利要求9所述的液晶显示设备，其中在第三致能期间，致能所述扫描线(G_N+1)，将所述下一级的所述像素的所述主像素电极与所述次像素电极的充电，并开启所述第三晶体管。
  11. 根据权利要求10所述的液晶显示设备，其中在第四致能期间，停止致能所述扫描线(G_N+1)，并于所述第三致能期间与所述第四致能期间，利用所述第三晶体管连接的所述分享电容，拉低所述本级的所述像素的所述次像素电极的电压。
  12. 根据权利要求6所述的液晶显示设备，其中所述本级像素的所述第一晶体管与所述第二晶体管与所述下一级像素的所述第三晶体管共享一条扫描线。
PCT/CN2013/089771 2013-12-12 2013-12-18 液晶显示设备及其像素驱动方法 WO2015085608A1 (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EA201690932A EA032519B1 (ru) 2013-12-12 2013-12-18 Жидкокристаллическое дисплейное устройство и способ управления его пикселями
GB1607987.3A GB2540453B (en) 2013-12-12 2013-12-18 Liquid crystal display device and a pixel driving method thereof
KR1020167012785A KR101906924B1 (ko) 2013-12-12 2013-12-18 액정표시장치 및 이의 화소 구동방법
US14/234,393 US9224354B2 (en) 2013-12-12 2013-12-18 Liquid crystal display device and a pixel driving method thereof
JP2016535098A JP2017504822A (ja) 2013-12-12 2013-12-18 液晶表示装置及び画素駆動方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310676568.0 2013-12-12
CN201310676568.0A CN103680447B (zh) 2013-12-12 2013-12-12 液晶显示设备及其像素驱动方法

Publications (1)

Publication Number Publication Date
WO2015085608A1 true WO2015085608A1 (zh) 2015-06-18

Family

ID=50317810

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/089771 WO2015085608A1 (zh) 2013-12-12 2013-12-18 液晶显示设备及其像素驱动方法

Country Status (7)

Country Link
US (1) US9224354B2 (zh)
JP (1) JP2017504822A (zh)
KR (1) KR101906924B1 (zh)
CN (1) CN103680447B (zh)
EA (1) EA032519B1 (zh)
GB (1) GB2540453B (zh)
WO (1) WO2015085608A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103941442B (zh) * 2014-04-10 2016-07-20 深圳市华星光电技术有限公司 显示面板及其驱动方法
CN103996657B (zh) * 2014-05-13 2016-06-22 深圳市华星光电技术有限公司 一种薄膜晶体管基板及其制作方法和液晶显示器
TWI526760B (zh) * 2014-07-17 2016-03-21 友達光電股份有限公司 液晶像素電路及其驅動方法
CN104460148B (zh) * 2014-11-20 2017-09-01 深圳市华星光电技术有限公司 提升不良检出率的像素结构及检测方法
CN104375294B (zh) * 2014-11-24 2017-03-15 深圳市华星光电技术有限公司 一种显示面板的检测电路及其检测方法
CN104483792B (zh) * 2014-12-26 2017-04-12 深圳市华星光电技术有限公司 阵列基板及显示装置
CN105093743B (zh) 2015-08-07 2018-03-13 深圳市华星光电技术有限公司 一种液晶面板、tft基板及其检测方法
CN107132709A (zh) * 2017-05-05 2017-09-05 惠科股份有限公司 液晶像素电路及其驱动方法与液晶显示面板
CN107255894B (zh) * 2017-08-09 2020-05-05 深圳市华星光电技术有限公司 阵列基板及液晶显示面板
CN207352947U (zh) * 2017-10-25 2018-05-11 中华映管股份有限公司 显示面板及其像素电路
KR20200085976A (ko) * 2019-01-07 2020-07-16 삼성디스플레이 주식회사 주사 구동부
KR20210080781A (ko) * 2019-12-23 2021-07-01 엘지디스플레이 주식회사 게이트 드라이버 및 이를 포함하는 표시 장치

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1773355A (zh) * 2004-11-08 2006-05-17 夏普株式会社 液晶显示器的基板、具有该基板的液晶显示器及驱动方法
CN101236343A (zh) * 2008-03-03 2008-08-06 上海广电光电子有限公司 液晶显示装置、像素结构及其驱动方法
CN101308301A (zh) * 2007-05-17 2008-11-19 株式会社半导体能源研究所 液晶显示装置
CN101566771A (zh) * 2008-04-23 2009-10-28 三星电子株式会社 含连接至子像素电极的晶体管的显示装置
US20120033148A1 (en) * 2010-08-06 2012-02-09 Samsung Electronics Co., Ltd. Liquid crystal display
CN102591083A (zh) * 2012-03-20 2012-07-18 深圳市华星光电技术有限公司 电荷分享型像素结构
CN102866547A (zh) * 2012-07-05 2013-01-09 友达光电股份有限公司 显示面板及其驱动方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050140634A1 (en) * 2003-12-26 2005-06-30 Nec Corporation Liquid crystal display device, and method and circuit for driving liquid crystal display device
TWI364609B (en) 2007-02-16 2012-05-21 Chimei Innolux Corp Liquid crystal display panel and manufacturing method thereof
JP4989309B2 (ja) * 2007-05-18 2012-08-01 株式会社半導体エネルギー研究所 液晶表示装置
JP5366458B2 (ja) * 2007-07-11 2013-12-11 株式会社半導体エネルギー研究所 アクティブマトリクス型表示装置及びそれを用いた電子機器
KR101515081B1 (ko) * 2007-07-26 2015-05-06 삼성디스플레이 주식회사 표시장치 및 그 구동방법
KR101499843B1 (ko) * 2008-07-04 2015-03-06 삼성디스플레이 주식회사 표시장치
KR101501497B1 (ko) * 2008-09-18 2015-03-12 삼성디스플레이 주식회사 액정 표시 장치
CN101592836B (zh) * 2009-04-15 2011-03-23 深圳华映显示科技有限公司 液晶显示器及其显示方法
EP2525256A4 (en) * 2010-01-15 2013-06-26 Sharp Kk LIQUID CRYSTAL DISPLAY DEVICE
US8411003B2 (en) * 2010-02-11 2013-04-02 Au Optronics Corporation Liquid crystal display and methods of driving same
CN101866604B (zh) * 2010-03-19 2012-08-22 华映视讯（吴江）有限公司 多分区像素驱动电路及其方法
KR101738476B1 (ko) 2010-11-17 2017-05-23 삼성디스플레이 주식회사 표시 패널의 구동 방법 및 이를 수행하는 표시 장치
TWI426486B (zh) * 2010-12-16 2014-02-11 Au Optronics Corp 運用於電荷分享畫素的整合面板型閘極驅動電路
US8810491B2 (en) * 2011-10-20 2014-08-19 Au Optronics Corporation Liquid crystal display with color washout improvement and method of driving same
US9218777B2 (en) * 2013-07-19 2015-12-22 Shenzhen China Star Optoelectronics Technology Co., Ltd Array substrate and the liquid crystal panel

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1773355A (zh) * 2004-11-08 2006-05-17 夏普株式会社 液晶显示器的基板、具有该基板的液晶显示器及驱动方法
CN101308301A (zh) * 2007-05-17 2008-11-19 株式会社半导体能源研究所 液晶显示装置
CN101236343A (zh) * 2008-03-03 2008-08-06 上海广电光电子有限公司 液晶显示装置、像素结构及其驱动方法
CN101566771A (zh) * 2008-04-23 2009-10-28 三星电子株式会社 含连接至子像素电极的晶体管的显示装置
US20120033148A1 (en) * 2010-08-06 2012-02-09 Samsung Electronics Co., Ltd. Liquid crystal display
CN102591083A (zh) * 2012-03-20 2012-07-18 深圳市华星光电技术有限公司 电荷分享型像素结构
CN102866547A (zh) * 2012-07-05 2013-01-09 友达光电股份有限公司 显示面板及其驱动方法

Also Published As

Publication number Publication date
KR20160071460A (ko) 2016-06-21
US20150170595A1 (en) 2015-06-18
GB2540453B (en) 2020-12-02
US9224354B2 (en) 2015-12-29
GB201607987D0 (en) 2016-06-22
EA201690932A1 (ru) 2017-01-30
CN103680447B (zh) 2016-01-13
KR101906924B1 (ko) 2018-10-11
JP2017504822A (ja) 2017-02-09
EA032519B1 (ru) 2019-06-28
CN103680447A (zh) 2014-03-26
GB2540453A (en) 2017-01-18

Similar Documents

Publication Publication Date Title
WO2015085608A1 (zh) 液晶显示设备及其像素驱动方法
US10121431B2 (en) Shift register, gate driving circuit, display screen and method for driving the display screen
US9430975B2 (en) Array substrate and the liquid crystal panel
US10049639B2 (en) CMOS gate drive on array (GOA) circuit structure and liquid crystal display panel
US10242637B2 (en) CMOS GOA circuit
US20190004383A1 (en) Pixel array, display panel and display device
US8482687B2 (en) Liquid crystal display device
US9524665B2 (en) Display panel and gate driver
WO2016078180A1 (zh) 一种液晶显示面板及其驱动方法、液晶显示装置
US8300001B2 (en) Demultiplexer drive circuit
US9620074B2 (en) LCD panel and pixel structure thereof
US9536484B2 (en) Liquid crystal array substrate and electronic device
US10013929B2 (en) Thin film transistor array substrate and display panel
WO2021128616A1 (zh) 显示面板
WO2013086746A1 (zh) 液晶显示面板以及其制造方式
US20160246092A1 (en) Array substrate and liquid crystal display panel
WO2016045138A1 (zh) 阵列基板及液晶显示面板
JP2010244007A (ja) 液晶表示装置及びその方法
WO2015032115A1 (zh) 一种阵列基板及液晶显示面板
US20170146877A1 (en) Array Substrate And Liquid Crystal Display Panel
US20190285930A1 (en) Gate driver on array (goa) unit, goa circuit, and liquid crystal display (lcd) panel
US10606107B2 (en) Display substrate and display device
WO2015096197A1 (zh) 画素结构及液晶显示装置
US10310306B2 (en) Liquid crystal display panel and apparatus
WO2016107073A1 (zh) 阵列基板及其驱动方法、显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14234393

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13899085

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 201607987

Country of ref document: GB

Kind code of ref document: A

Free format text: PCT FILING DATE = 20131218

WWE Wipo information: entry into national phase

Ref document number: 1020167012785

Country of ref document: KR

ENP Entry into the national phase

Ref document number: 2016535098

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 201690932

Country of ref document: EA

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13899085

Country of ref document: EP

Kind code of ref document: A1