WO2015058437A1 - 电容阵列及其版图设计方法 - Google Patents

电容阵列及其版图设计方法 Download PDF

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Publication number
WO2015058437A1
WO2015058437A1 PCT/CN2013/087992 CN2013087992W WO2015058437A1 WO 2015058437 A1 WO2015058437 A1 WO 2015058437A1 CN 2013087992 W CN2013087992 W CN 2013087992W WO 2015058437 A1 WO2015058437 A1 WO 2015058437A1
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Prior art keywords
capacitor
layout
capacitor array
unit
capacitors
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PCT/CN2013/087992
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English (en)
French (fr)
Inventor
王妍
王育新
胡刚毅
李婷
刘涛
陈光炳
Original Assignee
中国电子科技集团公司第二十四研究所
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Priority to US14/396,737 priority Critical patent/US9336347B2/en
Publication of WO2015058437A1 publication Critical patent/WO2015058437A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G15/00—Structural combinations of capacitors or other devices covered by at least two different main groups of this subclass with each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/38—Multiple capacitors, i.e. structural combinations of fixed capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
    • H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/44—Sequential comparisons in series-connected stages with change in value of analogue signal
    • H03M1/442—Sequential comparisons in series-connected stages with change in value of analogue signal using switched capacitors

Definitions

  • the invention relates to a capacitor array and a layout design method thereof.
  • Pipeline analog-to-digital converters are widely used in broadband communication systems and video image processing due to their high speed, high precision, low power consumption and small chip footprint.
  • Pipeline ADC conversion circuit shown in Figure 1 it is composed of Pipeline sub-level conversion circuits 101A, 101B, ..., 101N and full parallel analog-to-digital converters (Flash) of the same N-level structure
  • the ADC) circuit 102 is constructed.
  • the analog signal VIN is sent to the first stage pipeline conversion circuit (referred to as stage 1 in FIG. 1) 101A as an input signal.
  • the first stage pipeline analog-digital conversion circuit 101A A digital code of k (1) bit and a residual analog voltage Vres1 are output.
  • the residual analog voltage Vres1 is then sent to the second stage pipeline conversion circuit 101B (denoted as stage 2 in Fig. 1) for conversion and outputs a k(2)-bit digital code and a residual analog voltage Vres2.
  • stageN the Nth stage pipeline conversion circuit 101N
  • stageN the Nth stage pipeline conversion circuit 101N
  • the circuit 102 after being processed by the full parallel analog to digital converter circuit 102, obtains a digital code of k(N+1) bits and finally outputs it to the back end circuit.
  • each of the sub-stage circuits of the pipeline sub-level conversion circuits 101A, 101B, ..., 101N which includes a sample/hold circuit (S/H) 201, a subtraction circuit (SUB) 202, and a gain amplifying circuit ( Gain) 203, a low precision analog to digital converter (Sub-ADC) 204 and a low precision digital to analog converter (Sub-DAC) 205.
  • S/H sample/hold circuit
  • S/H subtraction circuit
  • Gain gain amplifying circuit
  • Sub-ADC low precision analog to digital converter
  • Sub-DAC low precision digital to analog converter
  • the output signal of the previous sub-level conversion circuit is used as the input signal Vi of the sub-stage conversion circuit (for the first sub-stage conversion circuit 101A, the input signal Vi is the input VIN of the pipeline ADC), in the sub-stage conversion circuit
  • the sample/hold circuit 201 samples the input signal Vi
  • the low-precision analog-to-digital converter 204 performs analog-to-digital conversion on the input signal Vi
  • the converted k-bit digital code is used as the digital output code of the sub-stage conversion circuit.
  • Output to low precision digital to analog converter 205 to achieve an estimate of input signal Vi.
  • the input signal Vi and the estimated value are processed by the subtraction circuit 202, and the obtained residual voltage is amplified by the gain amplifying circuit 203 to obtain the sub-level residual output analog voltage Vres as an input signal of the latter sub-level conversion circuit.
  • the sample/hold circuit 201, the subtraction circuit 202, the gain amplifying circuit 203, and the low-precision digital-to-analog converter 205 are usually combined and implemented by a switched capacitor circuit, which is called multiplication type digital-to-analog conversion. Multiplying Digital-to-Analog Converter, MDAC).
  • FIG. 3 is a specific circuit of the MDAC.
  • MDAC is implemented by a switched capacitor circuit based on a unit capacitor array.
  • the MDAC consists of a capacitor array 301 and a residual operational amplifier (Residue).
  • Amplifier, RA The 302 and the switch are constructed, and the entire MDAC operates under the control of the sampling phase 1 and the amplification phase 2 .
  • ⁇ 1 and ⁇ 1e are sampling phase clock signals
  • ⁇ 2 is the feedback phase clock signal
  • the switch for controlling the sampling clock signal ⁇ 1e during operation is closed before the switch controlling the sampling clock signal ⁇ 1, and the high level is valid (Fig.
  • the sampling capacitor Cs1 is composed of x1 unit capacitors C.
  • the selection switch is controlled according to the output code of the comparator to connect the reference level DVR;
  • the sampling capacitor Cs2 is composed of x2 unit capacitors C.
  • the input signal Vi is connected, and the input signal Vi is sampled.
  • the AC ground is connected.
  • the feedback capacitor Cf1 is composed of x3 unit capacitors C.
  • the input signal Vi is sampled, and when the phase is amplified, the residual operational amplifier 302 is outputted to the residual analog voltage Vres; the feedback capacitor Cf2 is composed of x4 unit capacitors C, and both the sampling phase and the amplification phase are connected to the residual operational amplifier 302.
  • the difference analog voltage Vres By selecting the capacitors (Cs1, Cs2, Cf1, Cf2) of different circuit connections and the number of cell capacitors (x1, x2, x3, x4) of different capacitors, the transfer function of MDAC that meets different requirements can be realized.
  • the gain of the transmission curve of MDAC is the ratio of the sum of the capacitances Cs1, Cs2, Cf1 and the sum of the capacitances Cf1 and Cf2, ideally, (x1+x2+x3)/(x3+x4), which It is required that the size C of the cell capacitors used to form each capacitor is the same, otherwise it will cause a gain error and affect the performance of the MDAC.
  • the ratio of the DAC level to the capacitance of the transmission curve DCs1/(Cs1+Cs2+Cf1) is also related to the size C of the cell capacitor.
  • Capacitance mismatch errors are mainly divided into systematic errors and random errors. Systematic errors can be eliminated or reduced by a reasonable layout design. Capacitance mismatch system error is mainly caused by the following four factors: (1) lithography causes perimeter ratio mismatch; (2) mismatch caused by different etch rate; (3) oxide layer gradient effect; (4) parasitic capacitance Does not match.
  • the error factor (1) if the peripheral ratio of the capacitor is equal to the area ratio, the effect can be eliminated, so that the unit capacitance can be realized by parallelizing the large capacitance.
  • a dummy capacitor can be added to the periphery of the capacitor array so that the layout environment around each unit capacitor is as identical as possible.
  • the traditional layout design method usually adopts the layout layout of the unit capacitor array concentric, which reduces the influence of the oxide layer gradient on the capacitance matching accuracy. However, this design approach is only suitable for situations where there is less type of capacitance matching required.
  • the capacitance size is getting smaller and smaller, the parasitic capacitance is more and more obvious, and even larger than the unit capacitance. Therefore, the layout and layout of the capacitor array are put forward higher requirements under the advanced technology.
  • the MDAC capacitor array layout is limited by the layout area. Therefore, how to layout the capacitor array in a limited area, eliminate the capacitance mismatch error caused by parasitic capacitance, and produce a matching capacitor array is a key problem and design problem.
  • the technical problem to be solved by the present invention is to provide a layout design method for generating a matching unit capacitor array and a capacitor array under a limited layout area.
  • the invention not only eliminates the capacitance ratio mismatch error caused by the parasitic capacitance, but also makes the capacitor array match, and the operation is simple and convenient, and the realized capacitor array occupies a small chip layout area, and is particularly suitable for a high precision pipeline ADC, and can also be applied to Capacitor array matching requires high digital-to-analog converters, switched capacitor filters, etc.
  • the present invention provides a capacitor array layout method, wherein the capacitor array includes first to K-type capacitors (K is an integer greater than or equal to 1), each capacitor includes a plurality of unit capacitors, and the capacitor
  • the array layout design method includes the following steps:
  • the number of columns and the number of rows of the capacitor array are M and N, respectively, and the capacitor array includes an internal capacitor array and an external virtual capacitor array, the external virtual capacitor array being composed of a plurality of dummy capacitors and located inside
  • Mdx represents the number of columns of the external virtual capacitor array, and Mdx ⁇ 1.5
  • b determines the number of columns in the layout layout of the first to K types of capacitors in the single-sided internal capacitor array,
  • c performs the capacitance in the capacitor array Layout, wherein the sum of the number of columns of the first class to the class K capacitor is not greater than Mh, and the capacitance of each column capacitor includes at most two different circuit connection modes;
  • Capacitor array wiring making the parallel lengths of the upper and lower plates of each unit capacitor consistent
  • Parasitic extraction of the layout is performed to verify whether the layout of the capacitor array meets the matching requirements.
  • step "determining the capacitance array layout" wherein the step “b, determining the number of columns of the first type to the K-type capacitor in the layout of the single-sided internal capacitor array”: if one of the types of capacitors Unit capacitance has different circuits
  • the connection method and this type of capacitor consists of x1 unit capacitors.
  • the minimum number of columns in this layout is equal to x1/2.
  • the blank space in the unilateral internal capacitor array is filled with the dummy capacitor.
  • the present invention also provides a capacitor array comprising M columns and N rows of capacitors, the capacitor array comprising an internal capacitor array and an external virtual capacitor array, the external virtual capacitor array being composed of a plurality of dummy capacitors and located inside
  • the internal capacitor array includes two fully symmetrical single-sided internal capacitor arrays and includes first to K-type capacitors (K is an integer greater than or equal to 1), wherein each capacitor is divided into several units Capacitor composition, the upper plate connection and the lower plate connection of each unit capacitor are parallel to each other, and the lower plate connection of each unit capacitor is uniformly connected by a metal line, and the metal lines are symmetrically distributed in each unit capacitor On both sides of the lower plate, the upper plate connection of each unit capacitor is uniformly connected by the same metal wire and located at the center of the unit capacitor, and the parallel lengths of the upper and lower plates of each unit capacitor are the same;
  • the minimum number of columns of the capacitor in the layout is equal to x1/2.
  • the blank of the single-sided internal capacitor array except the first type to the K-type capacitor is a virtual capacitor.
  • the above capacitor array and layout layout method not only eliminates the capacitance mismatch error caused by the parasitic capacitance, but also makes the capacitor array match, and the operation is simple and convenient, and the implemented capacitor array occupies a small chip layout area, and is particularly suitable for a high precision pipeline ADC. It can also be applied to digital-to-analog converters, switched capacitor filters, etc., which require high capacitance array matching.
  • 1 is a circuit diagram of a conventional pipelined analog-to-digital converter.
  • FIG. 2 is a circuit diagram of each of the pipeline sub-level conversion circuits of FIG.
  • FIG. 3 is a specific circuit diagram of the unit capacitor array multiplying digital-to-analog converter (MDAC) of FIG.
  • MDAC digital-to-analog converter
  • FIG. 4 is a timing chart showing the operation of the sampling phase clock signal and the feedback phase clock signal of the unit capacitor array multiplying digital-to-analog converter of FIG.
  • Figure 5-7 shows the source of parasitic capacitance of the existing unit capacitor.
  • Figure 8 is a schematic illustration of a preferred embodiment of a capacitor array of the present invention.
  • FIG. 9 is a schematic flow chart of a preferred embodiment of a capacitor array layout design method according to the present invention.
  • Fig. 10 is a schematic view showing a method of wiring a unit capacitor.
  • Figure 11 is a schematic diagram of a capacitor array layout.
  • FIG. 12 is a schematic view showing the layout of a capacitor array of the present invention.
  • Figure 13 is a schematic diagram showing the parasitic capacitance of a unit capacitor.
  • Figure 14 is a schematic illustration of a capacitor array wiring of the present invention.
  • the present invention exemplifies the layout pattern design of the capacitor array in the pipeline ADC by taking the layout of the single-sided capacitor array as an example. After obtaining the layout of the single-sided capacitor array, the other side of the layout is completely symmetrical.
  • the capacitor array layout includes an internal capacitor array (the associated capacitor array within the identification line 61) and an external virtual capacitor array (the associated capacitor array between the identification line 61 and the identification line 62), the external virtual capacitor array Located around the internal capacitor array.
  • the internal capacitor array is a layout for several types of capacitors in the circuit, and in particular, in FIG. 3, the layout of the capacitors Cs1, Cs2, Cf1, Cf2. Since the MDAC capacitor array in Figure 3 is fully symmetrical, the internal capacitor array includes two fully symmetrical single-sided internal capacitor arrays.
  • the invention proposes a layout design method for generating a matching unit capacitor array under a limited layout area
  • 9 is a design flow chart of the present invention. Understandably, although the design flow is primarily for pipelined ADCs The capacitor array layout method in the middle, but can also be extended to digital-to-analog converters, switched capacitor filters, etc., which require high precision for capacitor array matching.
  • the design process is broken down into four main steps: Step 71 : Determine the unit capacitor wiring mode; Step 72: Determine the capacitor array layout, in particular, determine the layout of the capacitors Cs1, Cs2, Cf1, Cf2 in the pipeline ADC; 73: Capacitor array wiring; Step 74: Perform parasitic parameter extraction on the layout to verify whether the capacitor array layout design meets the matching requirements.
  • capacitors Cs1 and Cs2 mentioned in the present embodiment, Cf1 and Cf2 are only an example of a capacitor array layout in a pipelined ADC.
  • the capacitor array of other pipeline ADCs it is also possible to include only two types of capacitors (Cs1 & Cf1, Cs1&Cf2, etc.), or three types of capacitors (Cs1&Cs2&Cf1 and many more).
  • the classification of capacitors is not Cs1, Cs2, Cf1, Cf2. It is also possible that there is no even a statement of sampling capacitors and feedback capacitors.
  • the design principle of the entire capacitor layout is the same, except that the classification of the capacitors is different.
  • the classification of the capacitor it is selected according to the specific circuit. Even in other embodiments, only one type of capacitor may be included in the entire capacitor layout.
  • step 72 (determining the capacitance array layout) is further divided into four sub-steps:
  • Step 720 Determine a maximum value of the number of columns of the single-sided internal capacitor array layout Mh;
  • Step 721 Determine the minimum number of columns M1 of the capacitance Cs1 in the layout of the single-sided internal capacitor array layout
  • Step 722 Determine the number of columns M2 of the capacitors Cs2, Cf1, and Cf2 in the layout of the single-sided internal capacitor array layout. M3 and M4; Of course, if only one capacitor is included in the entire capacitor layout, this step can be omitted, that is, only Mh and M1 are determined.
  • Step 723 Layout the unit capacitors in the capacitor array.
  • Each step in the design flow is an indispensable task in generating a matching capacitor array layout. The design criteria and methods for each task are detailed below.
  • Figure 10 is step 71 The specific implementation.
  • the upper plate connection and the lower plate connection of the capacitor are parallel to the direction of the signal flow.
  • the lower plate connection of the capacitor is uniformly connected by the metal aluminum wire 1 and the metal aluminum wire 1 Symmetrically distributed on both sides of the lower plate.
  • the metal aluminum wire 1 is connected to the lower plate through the perforation 10. Need to pay attention to is two metal aluminum wire 1 Both are connected to the lower plate, or there is only one metal aluminum wire 1 connected to the lower plate is elegant, the specific method is in step 73 Explain in detail. When the external signal is not connected to the lower plate of the capacitor, no punching is required.
  • the upper plate connection of the capacitor is uniformly connected by the metal aluminum wire 2 and is located at the center of the capacitor.
  • all the capacitors in the capacitor array that is, the capacitors Cs1, Cs2, Cf1, and Cf2 are wired in the manner shown in Figure 10.
  • the unit capacitors are wired in a uniform manner, so that the surrounding environment of each unit capacitor is the same.
  • the upper and lower plates of the capacitor are parallel to the signal flow direction (ie, the upper plate of the capacitor and the lower plate).
  • the wires are parallel to each other and are fixed in the area of the unit capacitor, which not only reduces the capacitance mismatch error caused by the mismatch of the peripheral ratio mismatch and the etch rate, but also makes the entire capacitor array
  • the layout wiring is not messy, reducing the layout area and making the layout look very beautiful.
  • the lower plate of the unit capacitor is connected through two metal aluminum wires 1 Connected to the outside, it limits the number of signals that can be connected to the outside world for each column of the layout.
  • Step 72 refers to sorting and arranging the columns according to the circuit connection characteristics of the capacitors under the limited layout area.
  • capacitors There are four types of capacitors in the pipeline ADC Cs1 , Cs2, Cf1, and Cf2. The methods for determining the number of columns for each capacitor in the layout layout and the overall layout method are described below.
  • step 720 determining the maximum number Mh of the single-sided internal capacitor array layout column number.
  • Mh the maximum number Mh of the single-sided internal capacitor array layout column number.
  • the internal capacitor array is a layout for several types of capacitors in the circuit. In particular, in Figure 3, the layout of the capacitors Cs1, Cs2, Cf1, Cf2.
  • the unit capacitance size and the virtual capacitance area determine the maximum value M of the number of capacitor array columns.
  • the smaller the area of the layout the smaller the maximum number of columns M of the capacitor.
  • the larger the unit capacitor size the smaller the maximum number of columns M of the capacitor is, the higher the layout requirement for the capacitor array is.
  • the number of columns of the virtual capacitor is 1.5 columns.
  • the maximum number of Mh of the single-sided internal capacitor array layout is equal to 7.
  • the number of columns of the virtual capacitor may also be other values greater than 1.5.
  • the wiring method of the unit capacitor described in step 71 ensures the uniformity of the unit capacitor environment. At the same time, it also limits the number of signals that can be connected to the outside world for each column of the layout.
  • MDAC In the structure, the capacitor Cs1 is composed of x1 unit capacitors, and each unit capacitor controls the selection switch to be connected to the reference level VR according to the output code D of the comparator when the phase is amplified, meaning that the capacitor is formed.
  • the lower plate of the x1 unit capacitor of Cs1 is connected to different signals (that is, the unit capacitance of the capacitor Cs1 has different circuit connections), so the capacitor Cs1
  • capacitor Cf1 The number of columns M3 in the unilateral internal capacitor array layout and the number of columns in the capacitor Cf2 in the unilateral internal capacitor array layout.
  • the capacitor Cs2 consists of x2
  • the unit capacitance is composed, and the circuit connection of each unit capacitor is exactly the same when the phase is amplified. Therefore, it is possible to arrange these unit capacitors into one or more columns, even if the capacitor Cs1
  • the minimum number of columns M1 in a single-sided internal capacitor array layout is an odd multiple of 0.5
  • a portion of the unit capacitance in capacitor Cs2 can share a column with a unit capacitor in Cs1.
  • Capacitor Cf1 and The layout of Cf2 is the same as that of capacitor Cs2.
  • the capacitor array layout is not unique, but two principles must be met.
  • the number of columns in capacitor Cs2 in the layout of the single-sided internal capacitor array layout M2 Capacitance Cf1 Number of columns in the layout of the single-sided internal capacitor array M3, Capacitance Cf2 Number of columns in the layout of the single-sided internal capacitor array layout M4, and capacitor Cs1
  • the minimum number of columns in a single-sided internal capacitor array layout is M1 less than or equal to the maximum number of single-sided internal capacitor array layouts.
  • each column of capacitors can only contain up to two capacitors with different circuit connections. The circuit connection of the capacitor is explained as follows: Please refer to the capacitor arrays Cf1, Cf2 and Cs2 shown in Figure 3.
  • the upper plates of the three types of capacitors are connected to the input terminal of the residual operational amplifier 302, and the lower plate of the capacitor has different circuit connections, specifically: the lower plate of the capacitor Cf1 is sampling the phase clock signal ⁇ 1
  • the control is connected to the input signal Vi, and the lower plate is connected to the output terminal Vres of the residual operational amplifier 302 when the feedback phase clock signal ⁇ 2 is controlled; the lower plate of the capacitor Cf2 is sampling the phase clock signal.
  • ⁇ 1 and Vres are connected under the control of the feedback phase clock signal ⁇ 2; the lower plate of the capacitor Cs2 is connected to the input signal Vi when the sampling phase clock signal ⁇ 1 is controlled, and the feedback phase clock signal ⁇ 2 Control is connected to the AC ground.
  • capacitors Cf1, Cf2, and Cs2 are different.
  • capacitors Cf1, Cf2, and Cs2 can be used. Any two types of capacitors are placed in the same column, and Cf1, Cf2, and Cs2 cannot be placed in the same column at the same time.
  • the number of columns M and the number of rows of the capacitor array can be N Make a compromise. If the capacitor Cs2 has a smaller number of columns M2 in the layout of the single-sided internal capacitor array layout, and the number of cell capacitors x2 constituting such a capacitor is larger, the number of rows of the entire capacitor array is N. Will increase. Therefore, in the case where the maximum number of single-sided internal capacitor array layouts Mh is sufficient, the capacitance Cs2 can be listed in the layout of the single-sided internal capacitor array layout. Appropriately increased to reduce the height of the entire layout N .
  • step 723 will be described.
  • step 720, step 721, and step 722 Determine the number of columns in each type of capacitor in the layout of the single-sided internal capacitor array layout
  • step 72 The rest of the work on the capacitor array layout is how to layout each type of capacitor.
  • the capacitor layout is considered to facilitate external layout wiring.
  • the layout of the single-sided internal capacitor array is as shown in the figure. As shown in Figure 11, the capacitor Cs2 is placed in the center of the layout, which is the M2 column.
  • capacitor Cf1 and the capacitor Cf2 are placed on the outermost one of the single-sided internal capacitor array layout for easy output connection, and are respectively M3 column and M4.
  • Column, capacitor Cs1 is placed between Cf1, Cf2 and Cs2, which is M1 Column.
  • the virtual capacitor is filled in the blank inside the unilateral internal capacitor array. Of course, at least 1.5 turns of dummy capacitors should be placed on the periphery of the internal capacitor array (not shown in Figure 9).
  • the number of capacitors Cs1 is equal to 7 and the capacitance is Cs2.
  • the number of unit capacitors x2 is equal to 7, the number of capacitors of capacitor Cf1 is equal to 2, and the number of capacitors of capacitor Cf2 is equal to 2
  • the maximum number of layouts of the single-sided capacitor array Mh is equal to 7, and the minimum number of columns of capacitance Cs1 in the layout of the single-sided internal capacitor array M1 is equal to 3.5. Therefore, the remaining number of columns M2+M3+M4 used to connect capacitors Cs2, Cf1, and Cf2 should be less than or equal to Mh-M1, which is 3.5.
  • Capacitor Cs2 is located in the center of the single-sided internal capacitor array layout. Capacitor Cf1 and capacitor Cf2 are on the outside of the single-sided internal capacitor array layout, and capacitor Cs1 is placed on Cf1 and Cf2. In the middle of Cs2. Here 1.5 turns of dummy capacitors on the periphery of the capacitor array are not shown in the figure.
  • reference numeral 100 denotes a unit capacitance of the capacitor Cf1
  • reference numeral 200 denotes a capacitor.
  • the unit capacitance of Cf2 the reference numeral 300 represents the unit capacitance of the capacitor Cs1
  • the reference numeral 400 represents the unit capacitance of the capacitor Cs2.
  • Capacitor Cf1 is arranged in 3.5 Columns, each two unit capacitors are arranged in a column. In order to make full use of the horizontal area of the layout, and try not to increase the height N of the layout, the seven capacitors of the capacitor Cs2 are divided into two columns for layout. Due to the number of layout columns M Restricted, capacitor Cf1 and capacitor Cf2 are placed in a column, and the remaining blanks are filled with dummy capacitors. In this way, you can see that the number of layouts of the single-sided internal capacitor array is 7 and the number of rows is equal to 4, counting the periphery of the capacitor. With 1.5 laps of virtual capacitance, the number of layouts for a single-sided capacitor array is 8.5 and the number of rows is equal to 7.
  • the capacitor array routing described in step 73 can be performed.
  • Figure 13 As shown, due to step 71 The determination of the unit capacitor wiring mode makes the parasitic capacitance mismatch between the unit capacitors mainly the parasitic capacitance between the upper plate connection and the lower plate connection.
  • the upper plate is connected to the metal aluminum wire 2 Parasitic capacitance between the metal aluminum wire 1 connected to the lower plate.
  • the parasitic capacitance Cpl in Figure 11 is the parasitic capacitance added to the capacitor 91.
  • the main source is the capacitor 91 Parasitic capacitance between the upper plate connection and the lower plate connection.
  • the parasitic capacitance Cp2 is a parasitic capacitance added to another unit capacitor, and the upper plate wiring and capacitance of the unit capacitor 91 The upper plates are connected and the lower plates are connected to the right metal aluminum wire 1.
  • the parasitic capacitance is related to the wiring pitch and the parallel length L of the connection. The smaller the connection pitch, the larger the parallel length L of the connection, and the parasitic capacitance Cp It is bigger. Since the unit capacitor wiring method ensures the same pitch between the upper and lower plates, the key to ensure the parasitic capacitance Cp of each unit capacitor is the same, that is, the parallel length L of the upper and lower plates of the unit capacitor is the same.
  • FIG 14 is a schematic diagram of the capacitor array wiring corresponding to Figure 12. For convenience of explanation, combined with Figure 14 This section describes the capacitor array wiring method.
  • Capacitors Cs1, Cs2, Cf1 The upper plates are connected to the input of the operational amplifier, so the upper plates of these capacitors pass through the metal aluminum wire 2 Connected to the input of the op amp along the direction of the signal flow.
  • the lower plate connections of all unit capacitors are connected to the outside in the opposite direction of the signal flow.
  • the capacitor on the layout Cs1 Each column contains up to two different unit capacitors connected to the lower plate, so when the external signal and capacitor Cs1 When the lower plates are connected, the wiring of the lower plates is divided into two cases.
  • Capacitor Cs2 is connected in exactly the same way when the phase is amplified. It is also placed in one or more columns on the layout. In order to ensure the capacitance Cs2 The length L of the upper plate connection and the lower plate connection are both the length of two unit capacitors. Similarly, when the capacitance of this column is all Cs2 unit capacitance, as shown in Figure 14 M21 and M22 Columns, two metal aluminum wires 1 are connected to the lower plate by perforation. When a unit capacitor in capacitor Cs2 shares a column with another unit capacitor of another type, only one metal aluminum wire 1 is connected to the lower plate by punching.
  • the capacitors Cf1 and Cf2 are wired in a similar way, and the purpose is to ensure the parallel length of the upper and lower plates of the unit capacitor.
  • the capacitor Cf1 and the capacitor Cf2 share a column. Therefore, the lower plate of each capacitor is only connected to one metal aluminum wire. Connected. In the wiring of the virtual capacitor, it is necessary to connect both the upper plate and the lower plate (not shown).
  • parasitic parameter extraction step The purpose of parasitic extraction is to verify and determine the matching accuracy of the capacitor array.
  • the tool can perform layout verification and extract parasitic parameters.
  • the parasitic parameters of each unit capacitor in the capacitor array can be displayed by tools. Based on this, it can be analyzed whether the parasitic parameters of each unit capacitor and the matching accuracy of the capacitor array meet the requirements.
  • the main innovation of the above capacitor array and its layout design method is to eliminate the parasitic capacitance mismatch to produce a match.
  • Capacitor array so the present invention is fully applicable to capacitive array layout design and metal under advanced processes - Metal capacitor array layout design.

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Abstract

本发明提供了一种电容阵列版图设计方法，包括以下步骤：确定单位电容布线方式：使得单位电容的上极板连线和下极板连线相互平行；确定电容阵列布局：a、确定单边电容阵列版图的列数的最大值Mh，b、确定单边电容阵列中第一类至第K类电容在版图布局中的列数，c、对电容阵列中的电容进行布局；电容阵列布线：使得每一单位电容的上下极板连线的并行长度一致；以及对版图进行寄生参数提取，验证电容阵列版图设计是否满足匹配要求。本发明还提供了一种电容阵列。上述电容阵列及版图布局方法不仅消除了由寄生电容引起的电容比例失配误差，以使电容阵列匹配，而且操作简单方便。

Description

电容阵列及其版图设计方法
【技术领域】
本发明涉及一种电容阵列及其版图设计方法。
【背景技术】
流水线模数转换器（ADC）因拥有高速、高精度、低功耗和芯片占用面积小的优势而被广泛应用于宽带通讯***以及视频图像处理。流水线ADC转换电路如图1所示，它由 N级结构相同的流水线子级转换电路101A、101B、…、101N和全并行模数转换器（Flash ADC）电路102构成。模拟信号VIN被送到第一级流水线转换电路（图1中记为stage1）101A作为输入信号，经过第一级流水线转换电路101A的模数转换后，所述第一级流水线模数转换电路101A输出k(1)比特（bit）的数字码和残差模拟电压Vres1。所述残差模拟电压Vres1接着被送到第二级流水线转换电路101B（图1中记为stage2）进行转换并输出k(2)比特的数字码和残差模拟电压Vres2。由此流水工作，可得到各级数字输出码，其中第N级流水线转换电路101N（图1中记为stageN）输出k(N)比特的数字码和残差模拟电压VresN至全并行模数转换器电路102，经过全并行模数转换器电路102处理之后，得到k(N+1)比特的数字码并最终输出至后端电路。
图2是流水线子级转换电路101A、101B、…、101N中的每一子级电路的具体结构，它包括采样/保持电路（S/H）201、减法电路（SUB）202、增益放大电路（Gain）203、低精度模数转换器（Sub-ADC）204和低精度数模转换器（Sub-DAC）205。它的工作原理是：上一子级转换电路的输出信号作为本子级转换电路的输入信号Vi（对于第一子级转换电路101A，输入信号Vi就是流水线ADC的输入VIN），本子级转换电路中的采样/保持电路201对输入信号Vi进行采样，同时低精度模数转换器204对输入信号Vi进行模数转换，转换后得到的k比特的数字码作为本子级转换电路的数字输出码，同时输出到低精度数模转换器205以实现对输入信号Vi的估计。输入信号Vi与估计值经减法电路202处理，所得的残差电压经增益放大电路203进行放大，得到本子级残差输出模拟电压Vres，作为后一子级转换电路的输入信号。在电路实现中，通常将采样/保持电路201、减法电路202、增益放大电路203和低精度数模转换器205结合在一起，用开关电容电路来实现，这种电路被叫做乘法型数模转换器（Multiplying Digital-to-Analog Converter，MDAC）。
图3是MDAC的具体电路。为了保证更好的电容匹配度，MDAC由基于单位电容阵列的开关电容电路实现。如图3所示，MDAC由电容阵列301、残差运算放大器（Residue Amplifier，RA 302和开关构成，且整个MDAC在采样相Ф1和放大相Ф2的控制下工作。其中Ф1和Ф1e为采样相时钟信号，Ф2为反馈相时钟信号，工作时用于控制采样时钟信号Ф1e的开关先于控制采样时钟信号Ф1的开关被闭合，且高电平有效（图4为采样相时钟信号Ф1、Ф1e以及反馈相时钟信号Ф2的工作时序图）。电容阵列301中所有电容（包括采样电容Cf1、Cf2及反馈电容Cs1、Cs2）的上极板都连接残差运算放大器302的输入端，而电容的下极板根据其电路连接方式，可以分为四类。
采样电容Cs1由x1个单位电容C组成，采样相时连接输入信号Vi，对输入信号Vi进行采样，放大相时根据比较器的输出码控制选择开关是否导通以连接基准电平DVR；采样电容Cs2由x2个单位电容C组成，采样相时连接输入信号Vi，对输入信号Vi进行采样，放大相时接交流地；反馈电容Cf1由x3个单位电容C构成，采样相时连接输入信号Vi，对输入信号Vi进行采样，放大相时接到残差运算放大器302输出残差模拟电压Vres；反馈电容Cf2由x4个单位电容C构成，采样相和放大相时都连接残差运算放大器302输出残差模拟电压Vres。通过选择不同电路连接方式的电容（Cs1、Cs2、Cf1、Cf2）以及不同电容的单元电容个数（x1、x2、x3、x4），可以实现满足不同需求的MDAC的传输函数。
根据电荷守恒，可以得到在忽略残差运算放大器302的增益误差的情况下， MDAC的传输函数为： Vres=[(Cs1+Cs2+Cf1)/(Cf1+Cf2)][Vi-(DVrCs1)/(Cs1+Cs2+Cf1)]。
可以看到，MDAC的传输曲线的增益就是电容Cs1、Cs2、Cf1之和与电容Cf1、Cf2之和的比例，理想情况下，也就是（x1+x2+x3）/（x3+x4），这就要求用于构成每种电容的单元电容的大小C是相同的，否则，会引起增益误差，影响MDAC的性能。同理，传输曲线的DAC电平与电容之比DCs1/（Cs1+Cs2+Cf1）也与单元电容的大小C相关，如果这些类型的单元电容大小C不同，产生失配，那么DAC电平会出现偏差，每个电容贡献的权重不同，同样会影响MDAC的性能，严重时甚至影响ADC的功能。
电容失配误差主要分为***误差和随机误差。***误差可以通过合理的版图设计消除或减小。电容失配***误差主要由以下四个因素引起：（1）光刻引起周长比例不匹配；（2）刻蚀率不同引起的不匹配；（3）氧化层梯度效应；（4）寄生电容的不匹配。
针对误差因素（1），如果电容的周长比与面积比相等，则可以消除此影响，因此通过将单位电容并联实现大电容的方法来解决。针对误差因素（2），可以在电容阵列***加上虚拟（dummy）电容，使得每个单位电容周围的版图环境尽可能相同。针对误差因素（3），传统的版图设计方法通常采用单位电容阵列共心的版图布局，这样就减小了氧化层梯度对电容匹配精度的影响。然而，这种设计方法只适合于需要电容匹配的类型少的情况。随着需要电容匹配的类型的增加，共心版图设计变得越来越繁琐，布局布线越来越复杂，使得引线电容和外引线寄生电容增加，并且加大了寄生电容不匹配因素，同时会浪费芯片面积。
对于误差因素（4），版图上电容的上极板和下极板与邻近电容的走线之间会存在大量的寄生电容，使得单元电容的实际值CA不等于自身电容C，而是自身电容C与寄生电容Cp之和，如图5所示。图6中，当电容附近有一条金属走线时，则电容的上下极板都会与该金属连线形成寄生电容Cp。图7中，通过引线给上极板加电位时，引线和多出来的这部分下极板也形成了寄生电容Cp。MDAC电容阵列布局布线的不同，会导致每个单位电容的寄生电容Cp不同，使得实际的单位电容CA不一致，造成电容不匹配，从而引起MDAC传输曲线的增益误差和DAC误差，会严重影响MDAC的性能，从而降低整个ADC的线性度，严重时甚至影响ADC的功能。
随着MOS工艺的提高，电容尺寸越来越小，寄生电容越来越明显，甚至比单位电容还大，因此，先进工艺下对电容阵列的版图布局布线提出了更高的要求。而MDAC电容阵列布局会受到版图面积限制。因此，如何在有限面积下对电容阵列进行版图设计，消除寄生电容引起的电容失配误差，产生匹配的电容阵列，是一个关键问题和设计难题。
【发明内容】
有鉴于此，本发明所要解决的技术问题是在有限版图面积下，提供一种产生匹配单位电容阵列的版图设计方法以及一种电容阵列。本发明不仅消除了由寄生电容引起的电容比例失配误差，以使电容阵列匹配，而且操作简单方便，实现的电容阵列占用芯片版图面积小，特别适用于高精度流水线ADC，也可以推广应用到电容阵列匹配要求高的数模转换器，开关电容滤波器等。
第一方面，本发明提供了一种电容阵列版图设计方法，其中电容阵列包括第一类至第K类电容（K为大于或等于1的整数），每一电容包括若干单位电容，所述电容阵列版图设计方法包括以下步骤：
确定单位电容布线方式：使得每一单位电容的上极板连线和下极板连线相互平行，且每一单位电容的下极板连线统一由同种金属线相连，所述金属线对称分布在各单位电容的下极板的两侧，每一单位电容的上极板连线统一由同种金属线相连且位于单位电容的中心；
确定电容阵列布局：所述电容阵列的列数和行数分别为M和N，且所述电容阵列包括内部电容阵列和外部虚拟电容阵列，所述外部虚拟电容阵列由若干虚拟电容组成且位于内部电容阵列的四周，所述内部电容阵列包括两个完全对称的单边内部电容阵列，a、确定单边内部电容阵列的列数的最大值Mh，Mh=M/2-Mdx，Mh取整数，其中Mdx表示外部虚拟电容阵列的列数，且Mdx≥1.5，b、确定单边内部电容阵列中第一类至第K类电容在版图布局中的列数，c、对电容阵列中的电容进行布局，其中第一类至第K类电容的列数之和不大于Mh，且每一列电容中至多包括两种不同电路连接方式的电容；
电容阵列布线：使得每一单位电容的上下极板连线的并行长度一致；以及
对版图进行寄生参数提取，验证电容阵列版图设计是否满足匹配要求。
其中，所述步骤“确定电容阵列布局”中，其中所述步骤“b、确定单边内部电容阵列中第一类至第K类电容在版图布局中的列数”：如果其中一类电容的单位电容具有不同的电路 连接方式且该类电容由x1个单位电容组成，则该类电容在版图布局中的最小列数等于x1/2。
其中，所述步骤“确定电容阵列布局”中，确定Mh及每一类电容在版图布局中的列数之后，单边内部电容阵列中空白的地方使用虚拟电容补齐。
其中，当一列电容中有两种不同电路连接方式的电容时，分布于单位电容的下极板的两条金属线中只有一条金属线通过通孔连接到该单位电容的下级板。
其中，当一列电容中只有一种电路连接方式的电容时，分布于单位电容的下极板的两条金属线均通过通孔连接到下级板。
第二方面，本发明还提供了一种电容阵列，包括M列和N行电容，所述电容阵列包括内部电容阵列和外部虚拟电容阵列，所述外部虚拟电容阵列由若干虚拟电容组成且位于内部电容阵列的四周，所述内部电容阵列包括两个完全对称的单边内部电容阵列且包括第一类至第K类电容（K为大于或等于1的整数），其中每一电容均由若干单位电容组成，每一单位电容的上极板连线和下极板连线相互平行，且每一单位电容的下极板连线统一由金属线相连，所述金属线对称分布在各单位电容的下极板的两侧，每一单位电容的上极板连线统一由同种金属线相连且位于单位电容的中心，且所述每一单位电容的上下极板连线的并行长度一致；所述单边内部电容阵列中列数的最大值为Mh，Mh=M/2-Mdx，Mh取整数，其中Mdx表示外部虚拟电容的列数，且Mdx≥1.5；所述单边内部电容阵列中第一类至第K类电容的列数之和不大于Mh且每一列电容中至多包括两种不同电路连接方式的电容。
其中，如果其中一类电容的单位电容具有不同的电路连接方式且该类电容由x1个单位电容组成，则该类电容在版图布局中的最小列数等于x1/2。
其中，所述单边内部电容阵列中除去第一类至第K类电容之外空白的地方均为虚拟电容。
其中，当一列电容中有两种不同电路连接方式的电容时，分布于单位电容的下极板的两条金属线中只有一条金属线通过通孔连接到该单位电容的下级板。
其中，当一列电容中只有一种电路连接方式的电容时，分布于单位电容的下极板的两条金属线均通过通孔连接到下级板。
上述电容阵列及版图布局方法不仅消除了由寄生电容引起的电容比例失配误差，以使电容阵列匹配，而且操作简单方便，实现的电容阵列占用芯片版图面积小，特别适用于高精度流水线ADC，也可以推广应用到电容阵列匹配要求高的数模转换器，开关电容滤波器等。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有的流水线模数转换器的电路示意图。
图2为图1中每一流水线子级转换电路的电路示意图。
图3为图2中单位电容阵列乘法型数模转换器（MDAC）的具体电路图。
图4为图3中单位电容阵列乘法型数模转换器的采样相时钟信号以及反馈相时钟信号的工作时序图。
图5-7为现有的单位电容的寄生电容来源示意图。
图8为本发明电容阵列的较佳实施方式的示意图。
图9为本发明电容阵列版图设计方法的较佳实施方式的流程示意图。
图10为单位电容布线方法的示意图。
图11为电容阵列布局的示意图。
图12为本发明电容阵列的布局示意图。
图13为单位电容的寄生电容说明示意图。
图14为本发明电容阵列布线的示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
由于MDAC电容阵列完全对称，所以本发明以单边电容阵列的版图为例来阐述流水线ADC中的电容阵列版图设计方法。得到单边电容阵列版图后，另外一边版图完全对称即可。
假设电容阵列在版图中的列数和行数分别为M和N，如图8所示。M表示与信号流垂直的电容个数，N表示与信号流方向平行的电容个数。M及N均为0.5的整数倍。当M、N为0.5的奇数倍时，表示采用了半个虚拟电容。如图8所示，电容阵列版图包括内部电容阵列（标识线61以内的所属电容阵列）和外部虚拟电容阵列（标识线61与标识线62之间的所属电容阵列），所述外部虚拟电容阵列位于内部电容阵列的四周。所述内部电容阵列是针对电路中的若干类电容的版图，特别地，在图3中是指电容Cs1、Cs2、Cf1、Cf2的版图。由于图3中MDAC电容阵列完全对称，因此所述内部电容阵列包括两个完全对称的单边内部电容阵列。
本发明的具体实施方式不仅限于下面的描述，现结合附图加以进一步说明。
本发明提出了一种在有限版图面积下，产生匹配单位电容阵列的版图设计方法，图 9是本发明的设计流程图。可以理解的是，虽然该设计流程主要针对流水线 ADC 中的电容阵列版图设计方法，但亦可扩展到对电容阵列匹配精度要求高的数模转换器、开关电容滤波器等。设计流程主要分解为四个步骤：步骤 71 ：确定单位电容布线方式；步骤 72 ：确定电容阵列布局，特别地，在流水线 ADC 中是确定电容 Cs1 、 Cs2 、 Cf1 、 Cf2 的版图布局；步骤 73 ：电容阵列布线；步骤 74 ：对版图进行寄生参数提取，验证电容阵列版图设计是否满足匹配要求。当然，本实施方式中所提到的电容 Cs1 、 Cs2 、 Cf1 、 Cf2 仅为针对流水线 ADC 中的电容阵列版图的一示例。在其他流水线 ADC 的电容阵列中，还有可能只包含两类电容（ Cs1&Cf1 、 Cs1&Cf2 等等），或者三类电容（ Cs1&Cs2&Cf1 等等）。另外，当这种电容版图设计方法应用于电容阵列匹配要求高的数模转换器、开关电容滤波器等时，电容的分类就不是 Cs1 、 Cs2 、 Cf1 、 Cf2 了，也可能甚至没有采样电容和反馈电容的说法。但是，整个电容版图的设计原则是相同的，只不过电容的分类不一样而已。至于电容的分类则根据具体电路来选定。甚至于其他实施方式中，整个电容版图中亦可只包括一种电容。
具体的，所述步骤 72 （确定电容阵列布局）又分为四个子步骤：
步骤 720 ：确定单边内部电容阵列版图的列数的最大值 Mh ；
步骤 721 ：确定电容 Cs1 在单边内部电容阵列版图布局中的最小列数 M1 ；
步骤 722 ：确定电容 Cs2 、 Cf1 和 Cf2 在单边内部电容阵列版图布局中的列数 M2 、 M3 和 M4 ；当然，如果整个电容版图中只包括一种电容，此步即可省略，即只需确定 Mh 和 M1 即可。
步骤 723 ：对电容阵列中的单位电容进行布局。设计流程中的每个步骤都是产生匹配电容阵列版图的不可缺少的一个任务，下面将对每个任务的设计准则和方法进行详细阐述。
图 10 是步骤 71 的具体实现方式。电容的上极板连线和下极板连线都与信号流的方向平行。电容的下极板连线统一由金属铝线 1 进行连接，金属铝线 1 对称分布在下极板的两侧。当外部信号与该电容的下极板相连接时，金属铝线 1 通过打孔 10 连接到下极板。需要注意的是两条金属铝线 1 都连接到下极板，或者只有一条金属铝线 1 连接到下极板是有讲究的，具体方法在步骤 73 中进行详细阐述。当外部信号与该电容的下极板不相连接时，则不需打孔。电容的上极板连线则统一由金属铝线 2 进行连接，位于电容中心。在流水线 ADC 中，电容阵列中的所有电容，也就是电容 Cs1 、 Cs2 、 Cf1 和 Cf2 的布线方式都按照图 10 所示的布线方式进行。
单位电容布线方式统一，使得每个单位电容的周围环境都相同，同时，电容上极板连线和下极板连线都与信号流方向平行（即电容的上极板连线和下极板连线相互平行），并且都固定在单位电容面积内，不仅减小了光刻引起周长比例不匹配和刻蚀率不同引起的不匹配所带来的电容失配误差，而且使得整个电容阵列版图布线不会凌乱，减小了版图面积，也让版图看起来非常美观。
特别地，单位电容的下极板连线通过两条金属铝线 1 与外部相连，也就限制了版图上每一列电容可以与外界连接的信号个数最多只能是两个。
步骤 72 是指在有限版图面积下，根据电容的电路连接特性分类布局成列。流水线 ADC 中有四类电容 Cs1 、 Cs2 、 Cf1 和 Cf2 ，下面分别讲述每种电容在版图布局中列数确定的方法以及整体布局方法。
首先，步骤 720 ：确定单边内部电容阵列版图列数最大值 Mh 。如图 8 中所示，电容阵列版图中，为了让每个单位电容的周围环境尽量相同，需要在内部电容阵列四周布局至少 1.5 圈虚拟电容阵列，即与信号流方向垂直的外部虚拟电容的列数 Mdx≥1.5 ，与信号流方向平行的外部虚拟电容的行数 Mdy≥1.5 。所述内部电容阵列是针对电路中若干类电容的版图，特别地，在图 3 中是指电容 Cs1 、 Cs2 、 Cf1 、 Cf2 的版图。因此，在有限的版图面积下，单位电容尺寸和虚拟电容面积确定了电容阵列列数的最大值 M 。版图面积越小，那么电容最大列数 M 越小；同理，单位电容尺寸越大，在版图面积一定的情况下，电容最大列数 M 越小，对电容阵列版图布局要求就越高。单边内部电容阵列版图列数的最大值 Mh 等于电容阵列列数最大值 M 的一半减去虚拟电容的列数 Mdx ，即 Mh=M/2-Mdx ， Mh 取整数， Mdx≥1.5 。本实施例中，虚拟电容的列数取 1.5 列，此时，例如，当版图上最多能布局 17 列电容阵列时，单边内部电容阵列版图列数最大值 Mh 就等于 7 。当然，其他实施方式中，所述虚拟电容的列数也可以是大于 1.5 的其他值。
接下来将描述步骤 721 中如何确定电容 Cs1 在单边内部电容阵列版图布局中的最小列数 M1 。如前所述，步骤 71 中所述的单位电容的布线方法保证了单位电容环境的一致性。同时也限制了版图上每一列电容可以与外界连接的信号个数最多只能是两个。 MDAC 结构中，电容 Cs1 由 x1 个单位电容组成，每个单位电容在放大相时根据比较器的输出码 D 控制选择开关是否导通以连接基准电平 VR ，意味着构成电容 Cs1 的 x1 个单位电容的下极板连接着不同的信号（也就是说，电容 Cs1 的单位电容具有不同的电路连接方式），因此电容 Cs1 在单边内部电容阵列版图布局中的最小列数 M1=x1/2 。例如，假设当电容 Cs1 的个数 x1 等于 7 时，电容 Cs1 在单边内部电容阵列版图布局中的最小列数 M1 则等于 3.5 。
接下来描述步骤 722 中如何确定电容 Cs2 在单边内部电容阵列版图布局中的列数 M2 、电容 Cf1 在单边内部电容阵列版图布局中的列数 M3 以及电容 Cf2 在单边内部电容阵列版图布局中的列数 M4 。 MDAC 结构中，电容 Cs2 由 x2 个单位电容构成，每个单位电容在放大相时的电路连接方式完全一致，因此，将这些单位电容排成一列或多列都可以，甚至，如果电容 Cs1 在单边内部电容阵列版图布局中的最小列数 M1 为 0.5 的奇数倍时，电容 Cs2 中的部分单位电容可以与 Cs1 中的某个单位电容共用一列。电容 Cf1 和 Cf2 的版图布局与电容 Cs2 同理。
因此，电容阵列布局不是唯一的，但必须满足两个原则。第一，电容 Cs2 在单边内部电容阵列版图布局中的列数 M2 ，电容 Cf1 在单边内部电容阵列版图布局中的列数 M3 ，电容 Cf2 在单边内部电容阵列版图布局中的列数 M4 ，与电容 Cs1 在单边内部电容阵列版图布局中的最小列数 M1 小于或等于单边内部电容阵列版图列数的最大值 Mh ；第二，每一列电容最多只能含有两种不同电路连接方式的电容。电容的电路连接方式解释如下：请参考图 3 所示的电容阵列 Cf1 、 Cf2 和 Cs2 ，这三类电容的上极板都连接残差运算放大器 302 的输入端，而电容的下极板具有不同的电路连接方式，具体为：电容 Cf1 的下极板在采样相时钟信号 Ф1 控制时与输入信号 Vi 相连、在反馈相时钟信号 Ф2 控制时其下极板与残差运算放大器 302 的输出端 Vres 相连；电容 Cf2 的下极板在采样相时钟信号 Ф1 以及在反馈相时钟信号 Ф2 控制下都与 Vres 相连；电容 Cs2 的下极板在采样相时钟信号 Ф1 控制时与输入信号 Vi 相连、以及在反馈相时钟信号 Ф2 控制时与交流地相连。也就是说，电容 Cf1 、 Cf2 以及 Cs2 的电路连接方式均不同，此时，可以将电容 Cf1 、 Cf2 、 Cs2 中的任意两类电容放在同一列，而不能同时将 Cf1 、 Cf2 、 Cs2 放在同一列。
在单边内部电容阵列版图列数最大值 Mh 充裕的情况下，可以对电容阵列的列数 M 和行数 N 进行折衷。如果电容 Cs2 在单边内部电容阵列版图布局中列数 M2 越小，而构成这种电容的单元电容个数 x2 比较大，则整个电容阵列版图行数 N 会增加。所以，在单边内部电容阵列版图列数最大值 Mh 比较充裕的情况下，可以让电容 Cs2 在单边内部电容阵列版图布局中列数 M2 适当增加，以降低整个版图的高度 N 。同理，对于电容 Cf1 在单边内部电容阵列版图布局中的列数 M3 以及电容 Cf2 在单边内部电容阵列版图布局中的列数 M4 要求也是如此。然而，如果单边内部电容阵列版图列数最大值 Mh 非常紧张，只有增加电容阵列版图行数 N 。
接下来将描述步骤 723 。在电容阵列列数 M 受限的情况下，步骤 720 、步骤 721 及步骤 722 分别确定了每种类型电容在单边内部电容阵列版图布局中的列数，步骤 72 中电容阵列布局剩下的工作就是如何对每种类型的电容进行布局了。在这一步骤中，电容布局的考虑是要方便外部版图布线。特别地，流水线模数转换器中，为了方便外部版图布线，单边内部电容阵列布局如图 11 所示，其中电容 Cs2 放在版图中心，为 M2 列，电容 Cf1 和电容 Cf2 放在单边内部电容阵列版图最外面方便输出连线，且分别为 M3 列和 M4 列，电容 Cs1 则放在 Cf1 、 Cf2 与 Cs2 中间，为 M1 列。在单边内部电容阵列内部空白的地方则用虚拟电容补齐。当然，在内部电容阵列***还应该打上至少 1.5 圈虚拟电容（图 9 中未示）。
例如，当版图上最多能布局 17 列电容阵列，电容 Cs1 的个数 x1 等于 7 ，电容 Cs2 的单位电容个数 x2 等于 7 ，电容 Cf1 的单位电容个数 x3 等于 2 ，电容 Cf2 的单位电容个数 x4 等于 2 时，由前所述，单边电容阵列版图列数最大值 Mh 就等于 7 ，电容 Cs1 在单边内部电容阵列版图布局中的最小列数 M1 等于 3.5 ，因此，剩下的用于连接电容 Cs2 、 Cf1 和 Cf2 的列数 M2+M3+M4 应该小于或等于 Mh-M1 ，为 3.5 。该电容阵列版图布局如图 12 所示。电容 Cs2 位于单边内部电容阵列版图中心，电容 Cf1 和电容 Cf2 位于单边内部电容阵列版图外侧，电容 Cs1 放在 Cf1 、 Cf2 与 Cs2 中间。这里电容阵列***的 1.5 圈虚拟电容没有在图中展示出来。图 12 中，标号 100 表示电容 Cf1 的单位电容，标号 200 表示电容 Cf2 的单位电容，标号 300 表示电容 Cs1 的单位电容，标号 400 表示电容 Cs2 的单位电容。
电容 Cf1 排列成 3.5 列，每两个单位电容排成一列。为了充分利用版图的横向面积，而尽量不增加版图的高度 N ，将电容 Cs2 的 7 个电容分成两列进行布局。由于版图列数 M 受限，电容 Cf1 和电容 Cf2 放置成一列，其余空白的地方用虚拟电容补齐。这样，可以看到单边内部电容阵列版图列数是 7 ，行数等于 4 ，算上电容***的 1.5 圈虚拟电容，单边电容阵列版图列数是 8.5 ，行数等于 7 。
当电容布局完成后（即步骤 72 执行完成后），就可以进行步骤 73 中描述的电容阵列布线。如图 13 所示，由于步骤 71 中的单位电容布线方式的确定，使得单位电容之间寄生电容的不匹配来源主要就是上极板连线与下极板连线之间的寄生电容。在这里，也就是上极板连线金属铝线 2 和下极板连线金属铝线 1 之间的寄生电容。图 11 中的寄生电容 Cpl 是附加于电容 91 的寄生电容，主要来源是电容 91 上极板连线和下极板连线之间的寄生电容。寄生电容 Cp2 是附加在另外一个单位电容的寄生电容，所述单位电容的上极板连线与电容 91 的上极板相连，下极板与右侧金属铝线 1 相连。寄生电容与连线间距、连线并行长度 L 有关。连线间距越小，连线并行长度 L 越大，寄生电容 Cp 就越大。由于单位电容布线方式保证了上下极板连线的间距相同，因此，要使每个单位电容的寄生电容 Cp 一致，关键就是保证单位电容上下极板连线的并行长度 L 一致。
图 14 是图 12 对应的电容阵列布线示意图。为了方便说明，结合图 14 介绍电容阵列布线方法。流水线模数转换器的 MDAC 结构中，电容 Cs1 、 Cs2 、 Cf1 和 Cf2 的上极板都是连接到运算放大器的输入端，因此这些电容的上极板都通过金属铝线 2 沿着信号流方向与运算放大器的输入端连接。而所有单位电容的下极板连线都沿着信号流的反方向与外部连接。由前面可知，版图上电容 Cs1 在每一列最多包含两个不同下极板连接的单位电容，因此，当外部信号与电容 Cs1 的下极板相连接时，下极板的布线分为两种情况。当这一列电容有两个不同下极板连接的单位电容时，如图 14 中的 M12 、 M13 、 M14 列电容，只有一条金属铝线 1 通过打孔连接到下极板。当这一列电容只有一种下极板连接的电容，如图 14 中的 M11 列，则有两条金属铝线 1 通过打孔连接到下极板，这样每个单位电容的上极板连线与下极板连线并行的长度 L 都为两个单位电容的长度。
电容 Cs2 在放大相时的电路特性连接方式完全一致，在版图布局上也被放置成一列或多列。为了保证电容 Cs2 的上极板连线与下极板连线并行的长度 L 都为两个单位电容的长度，同理，当这一列电容全都是 Cs2 的单位电容时，如图 14 中的 M21 和 M22 列，两条金属铝线 1 均通过打孔连接到下极板。当电容 Cs2 中的某个单位电容与其他类型的某个单位电容共用一列时，只有一条金属铝线 1 通过打孔连接到下极板。
电容 Cf1 和 Cf2 的布线方法类似，目的都是保证单位电容上下极板连线的并行长度 L 为两个单位电容的长度。图 14 中，电容 Cf1 和电容 Cf2 共用一列，因此，每个电容的下极板都只与一条金属铝线 1 相连。在虚拟电容的布线中，需要让其上极板和下极板都连接地（图未示）。
完成步骤 72 中的电容阵列布局和步骤 73 中的电容阵列布线后，随即进行步骤 74 （即寄生参数提取步骤）。寄生参数提取的目的是验证并确定电容阵列的匹配精度。利用 ASSURA 等工具进行版图验证并提取寄生参数，电容阵列中的每个单位电容的寄生参数都可以通过工具显示出来，据此可以分析每个单元电容的寄生参数和电容阵列的匹配精度是否满足要求。
随着 MOS 工艺的进步，寄生电容的影响越来越严重，寄生电容不匹配逐渐成为电容不匹配的主要因素，上述电容阵列及其版图设计方法的主要创新点是消除了寄生电容的不匹配，以产生匹配的电容阵列，因此本发明完全适用于先进工艺下的电容阵列版图设计和金属 - 金属电容阵列版图设计。
以上所述并不用于限制本发明，显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

  1. 一种电容阵列版图设计方法，其中电容阵列包括第一类至第 K 类电容（ K 为大于或等于 1 的整数），每一电容包括若干单位电容，其特征在于：所述电容阵列版图设计方法包括以下步骤：
    确定单位电容布线方式：使得每一单位电容的上极板连线和下极板连线相互平行，且每一单位电容的下极板连线统一由同种金属线相连，所述金属线对称分布在各单位电容的下极板的两侧，每一单位电容的上极板连线统一由同种金属线相连且位于单位电容的中心；
    确定电容阵列布局：所述电容阵列的列数和行数分别为 M 和 N ，且所述电容阵列包括内部电容阵列和外部虚拟电容阵列，所述外部虚拟电容阵列由若干虚拟电容组成且位于内部电容阵列的四周，所述内部电容阵列包括两个完全对称的单边内部电容阵列， a 、确定单边内部电容阵列的列数的最大值 Mh ， Mh=M/2-Mdx ， Mh 取整数，其中 Mdx 表示外部虚拟电容阵列的列数，且 Mdx≥1.5 ， b 、确定单边内部电容阵列中第一类至第 K 类电容在版图布局中的列数， c 、对电容阵列中的电容进行布局，其中第一类至第 K 类电容的列数之和不大于 Mh ，且每一列电容中至多包括两种不同电路连接方式的电容；
    电容阵列布线：使得每一单位电容的上下极板连线的并行长度一致；以及
    对版图进行寄生参数提取，验证电容阵列版图设计是否满足匹配要求。
  2. 如权利要求1所述的电容阵列版图设计方法，其特征在于：所述步骤“确定电容阵列布局”中，其中所述步骤“b、确定单边内部电容阵列中第一类至第K类电容在版图布局中的列
    数”：如果其中一类电容的单位电容具有不同的电路连接方式且该类电容由x1个单位电容组成，则该类电容在版图布局中的最小列数等于x1/2。
  3. 如权利要求1或2所述的电容阵列版图设计方法，其特征在于：所述步骤“确定电容阵列布局”中，确定Mh及每一类电容在版图布局中的列数之后，单边内部电容阵列中空白的地
    方使用虚拟电容补齐。
  4. 如权利要求1所述的电容阵列版图设计方法，其特征在于：当一列电容中有两种不同电路连接方式的电容时，分布于单位电容的下极板的两条金属线中只有一条金属线通过通孔连
    接到该单位电容的下级板。
  5. 如权利要求1所述的电容阵列版图设计方法，其特征在于：当一列电容中只有一种电路连接方式的电容时，分布于单位电容的下极板的两条金属线均通过通孔连接到下级板。
  6. 一种电容阵列，包括M列和N行电容，其特征在于：所述电容阵列包括内部电容阵列和外部虚拟电容阵列，所述外部虚拟电容阵列由若干虚拟电容组成且位于内部电容阵列的四周
    ，所述内部电容阵列包括两个完全对称的单边内部电容阵列且包括第一类至第K类电容（K为大于或等于1的整数），其中每一电容均由若干单位电容组成，每一单位电容的上极板连线和下极板连线相互平行，且每一单位电容的下极板连线统一由金属线相连，所述金属线对称分布在各单位电容的下极板的两侧，每一单位电容的上极板连线统一由同种金属线相连且位于单位电容的中心，且所述每一单位电容的上下极板连线的并行长度一致；所述单边内部电容阵列中列数的最大值为Mh，Mh=M/2-Mdx，Mh取整数，其中Mdx表示外部虚拟电容的列数，且Mdx≥1.5；所述单边内部电容阵列中第一类至第K类电容的列数之和不大于Mh且每一列电容中至多包括两种不同电路连接方式的电容。
  7. 权利要求6所述的电容阵列，其特征在于：如果其中一类电容的单位电容具有不同的电路连接方式且该类电容由x1个单位电容组成，则该类电容在版图布局中的最小列数等于
    x1/2。
  8. 如权利要求6或7所述的电容阵列，其特征在于：所述单边内部电容阵列中除去第一类至第K类电容之外空白的地方均为虚拟电容。
  9. 权利要求6所述的电容阵列版图设计方法，其特征在于：当一列电容中有两种不同电路连接方式的电容时，分布于单位电容的下极板的两条金属线中只有一条金属线通过通孔连
    接到该单位电容的下级板。
  10. 如权利要求6所述的电容阵列版图设计方法，其特征在于：当一列电容中只有一种电路连接方式的电容时，分布于单位电容的下极板的两条金属线均通过通孔连接到下级板。
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104681412A (zh) * 2015-02-02 2015-06-03 南京宇都通讯科技有限公司 匹配电容及其制造方法
US10410398B2 (en) * 2015-02-20 2019-09-10 Qualcomm Incorporated Systems and methods for reducing memory bandwidth using low quality tiles
CN106469227A (zh) * 2015-08-14 2017-03-01 北京华大九天软件有限公司 一种自动搭建级联电路的方法
CN106571827B (zh) * 2015-10-09 2021-03-02 国民技术股份有限公司 差分sar adc和其开关电容结构、a/d转换方法、版图实现方法
US9609259B1 (en) * 2016-01-25 2017-03-28 Pixart Imaging (Penang) Sdn. Bhd. Pipelined analog-to-digital converter incorporating variable input gain and pixel read out analog front end having the same
CN106253904B (zh) * 2016-08-04 2019-11-26 成都博思微科技有限公司 一种流水线adc***中采样mom电容的版图设计方法
MX2019006368A (es) 2016-12-02 2019-08-21 Carver Scient Inc Dispositivo de memoria y dispositivo de almacenamiento de energia capacitiva.
CN107633128A (zh) * 2017-09-15 2018-01-26 北京华大九天软件有限公司 Mom电容、mom电容阵列及mom电容阵列的布局和走线方法
US20200410153A1 (en) 2019-05-30 2020-12-31 Celera, Inc. Automated circuit generation
CN110535473B (zh) * 2019-09-03 2022-04-22 中国电子科技集团公司第二十四研究所 无路径失配的无采保高速高输入带宽流水线结构adc
US11476262B2 (en) * 2020-07-28 2022-10-18 Micron Technology, Inc. Methods of forming an array of capacitors
CN113708768A (zh) * 2021-08-17 2021-11-26 联芸科技（杭州）有限公司 电容阵列、匹配方法及其逐次逼近型模数转换器
CN116094523B (zh) * 2023-03-06 2023-06-09 电子科技大学 一种适用于二进制电容式dac的紧凑型电容排布方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004207518A (ja) * 2002-12-25 2004-07-22 Nokia Corp 多層プリント回路基板、受動素子アレイ、多層プリント回路基板の製造方法および受動素子アレイの製造方法
CN101097913A (zh) * 2006-06-29 2008-01-02 联发科技股份有限公司 电容阵列、电容与电容阵列布局方法
CN103023504A (zh) * 2012-12-18 2013-04-03 中国科学院微电子研究所 一种逐次逼近型adc版图结构

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7149072B2 (en) * 2004-11-04 2006-12-12 Samsung Electro-Mechanics Co., Ltd. Multilayered chip capacitor array
US7724496B2 (en) * 2005-11-04 2010-05-25 Avx Corporation Multilayer vertically integrated array technology
CN100478966C (zh) * 2007-09-28 2009-04-15 中国电子科技集团公司第五十四研究所 对芯片中的海量模块进行阵列布局的方法
JP4548471B2 (ja) * 2007-10-18 2010-09-22 株式会社村田製作所 コンデンサアレイおよびその製造方法
JP4548492B2 (ja) * 2008-02-13 2010-09-22 Ｔｄｋ株式会社 積層コンデンサアレイ
US8537523B1 (en) * 2009-02-11 2013-09-17 Altera Corporation Method and apparatus for implementing a metal capacitor with L-shaped fingers
US8770002B2 (en) * 2009-10-28 2014-07-08 Orii & Mec Corporation Linear-spring forming apparatus
CN102339331B (zh) * 2010-07-19 2013-06-05 中国科学院微电子研究所 一种电路问题设计布图定位调整的方法
CN102332921A (zh) * 2011-07-28 2012-01-25 复旦大学 一种适用于自动增益控制环路的逐次逼近型模数转换器
CN103023503B (zh) * 2012-12-31 2016-02-10 芯锋宽泰科技（北京）有限公司 一种流水线型模数转换器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004207518A (ja) * 2002-12-25 2004-07-22 Nokia Corp 多層プリント回路基板、受動素子アレイ、多層プリント回路基板の製造方法および受動素子アレイの製造方法
CN101097913A (zh) * 2006-06-29 2008-01-02 联发科技股份有限公司 电容阵列、电容与电容阵列布局方法
CN103023504A (zh) * 2012-12-18 2013-04-03 中国科学院微电子研究所 一种逐次逼近型adc版图结构

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