WO2019242396A1 - 采用负电压和栅压自举的低电压电荷传输电路 - Google Patents
采用负电压和栅压自举的低电压电荷传输电路 Download PDFInfo
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- H—ELECTRICITY
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- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
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- the invention relates to an input signal swing-enhanced charge signal transmission circuit for a charge domain pipelined analog-to-digital converter, and belongs to the technical field of integrated circuits.
- analog-to-digital converters will be indispensable in the future digital system design Part.
- applications such as broadband communications, digital high-definition television, and radar, the system requires an analog-to-digital converter with a very high sampling rate and resolution.
- the requirements for analog-to-digital converters for portable terminal products in these applications not only require high sampling rates and high resolution, but their power consumption should also be minimized.
- an analog-to-digital converter structure capable of achieving both a high sampling rate and a high resolution is a pipelined analog-to-digital converter.
- the pipeline structure is a multi-stage conversion structure. Each stage uses an analog-to-digital converter with a low-precision basic structure. The input signal is processed step by step. Finally, the results of each stage are combined to generate a high-precision output.
- the basic idea is to evenly distribute the overall required conversion accuracy to each level, and the conversion results of each level can be combined to get the final conversion result. Because the pipelined analog-to-digital converter can achieve the best compromise in speed, power consumption, and chip area, it can still maintain higher speed and lower power consumption when achieving higher-precision analog-to-digital conversion.
- a more mature way to implement a pipelined analog-to-digital converter is a pipelined structure based on switched capacitor technology.
- the work of the sample-and-hold circuit and each sub-stage circuit in the pipeline analog-to-digital converter based on this technology must also use high-gain and wide-bandwidth operational amplifiers.
- the speed and processing accuracy of the analog-to-digital converter depends on the speed and accuracy of the negative feedback establishment of the high-gain and ultra-wide bandwidth operational amplifiers used. Therefore, the core of the design of this type of pipelined analog-to-digital converter is the design of the operational amplifier with high gain and ultra-wide bandwidth.
- the charge-domain pipelined analog-to-digital converter is an analog-to-digital converter that does not use operational amplifiers with high gain and ultra-wide bandwidth.
- the structure of the analog-to-digital converter has low power consumption characteristics while achieving high speed and high accuracy.
- the charge-domain pipelined analog-to-digital converter uses charge-domain signal processing technology.
- the signal is expressed in the form of a charge packet.
- the size of the charge packet represents the amount of signals of different sizes.
- the storage, transmission, addition / subtraction, and comparison of charge packets of different sizes between different storage nodes implement signal processing functions. By using a periodic clock to drive and control the signal processing of charge packets of different sizes between different storage nodes, the analog-to-digital conversion function can be realized.
- the charge-stage pipelined sub-level circuits at each level are controlled by the charge transfer switch at the current level, multiple charge physical storage nodes, multiple charge storage elements connected to the charge storage node, multiple comparators, A plurality of reference charge selection circuits controlled by the comparator output results are configured under the control of a control clock.
- the functions of charge transfer, addition / subtraction, and comparison and quantification are all performed around the physical storage nodes of the charge of the sub-stages.
- the ordinary CMOS process is the best process to implement these large-scale digital circuits.
- digital signal processing technology to achieve ultra-high-speed and ultra-high-precision charge-domain pipelined analog-to-digital converters, one of the core issues is the key steps of charge signal storage and transmission, comparison and quantization, and addition and subtraction operations in existing ordinary CMOS. Can be efficiently and accurately achieved under process conditions. Therefore, in order to realize high-speed and high-precision charge-domain pipelined analog-to-digital converters by means of large-scale digital signal processing technology, it is necessary to provide a high-precision charge signal transmission circuit suitable for ordinary CMOS processes.
- FIG. 1 For the realization of high-efficiency signal transmission technology, the existing technology is typically patented: US2007 / 0279507A1 enhanced signal transmission circuit, and its typical circuit structure is shown in Figure 1.
- Signal charge transfer gate V G S of the MOSFET is connected to the output terminal of the operational amplifier composed of MOS transistors M1, M2 and M3 1 is. Before output of the operational amplifier a charge transfer operation, S is in the OFF state, the charge to be transferred is stored on C 1.
- Figure 2 is a schematic diagram of the working voltage waveform of the circuit. At t0, Ck1 undergoes a negative step change and Ck1n undergoes a positive step change, which causes the Ni voltage V Ni to change to a low potential and the No voltage V No to a high potential.
- Operational amplifier 1 will respond to the change and drive the MOSFET.
- the voltage of the gate G of the tube S is high, so that S starts to conduct; due to the potential difference, the charge stored on Ni will be transferred to No in the form of electrons, causing V Ni to rise and V No to fall.
- Operational amplifier 1 will It will also respond to this change and drive the MOSFET S gate's V G voltage to gradually decrease; at time t1, when V Ni rises to the voltage V R , the V G voltage gradually decreases to the cut-off voltage V th , S turns off again, and the charge transfers The process ends, where V R is determined by the static operating point of the cascode operational amplifier.
- the signal nodes mainly related to the input signal swing of the signal transmission circuit shown in FIG. 1 are the gate, drain, source, and substrate terminals of the charge transfer tube MOSFET tube S.
- the source terminal and the drain terminal are two sub-circuits connected to each other. Therefore, the capacitance of the source terminal is 2 N times the capacitance of the drain terminal (N is the number of bits of the sub-circuit in which the source terminal is located).
- V CK1n voltage is the chip's global reference voltage, and its theoretical maximum value can be V DD , but in practice its maximum value is still Limited by the voltage at the G terminal, and the maximum value of the voltage at the G terminal can only be the power supply voltage V DD , which is obviously limited; the minimum voltage of V R is limited by the S terminal, and the minimum voltage of S is limited by the signal 'ground level' voltage . Therefore, to increase the signal swing V DD must overcome limit signal "ground level" and the voltage V R V CK1n voltage.
- the V DD limitation of the V CK1n voltage is overcome, and the gate voltage bootstrap technology is used to raise the G terminal voltage by a V DD voltage during the charge transfer.
- the upper limit of the V CK1n voltage can be increased to the V DD voltage;
- the V R voltage signal's ground level is limited.
- the negative voltage step-down method is used to reduce the minimum value of the S terminal voltage by connecting the substrate voltage of the MOSFET S to the negative voltage. This can significantly reduce the V R voltage. Lower limit, thereby increasing the signal swing of the BCT.
- the object of the present invention is to overcome the shortcomings in the prior art, and to provide a low-voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap, which is a high-precision charge transfer circuit suitable for a common CMOS process.
- the technical solution of the low voltage charge transfer circuit using the negative voltage and gate voltage bootstrap according to the present invention is characterized by including a charge transfer MOSFET tube S, a gate voltage bootstrap boost circuit, and a negative voltage transfer MOSFET tube B.
- the corresponding connection relationship of the low voltage charge transfer circuit using the negative voltage and the gate voltage bootstrap is: the gate terminal of the first NMOS tube M1 is connected to the charge to be transferred node Ni, that is, the source of the charge transfer MOSFET tube S, and is also connected to The voltage input terminal of the gate voltage bootstrap boost circuit; the source terminal of the first NMOS tube M1 and the substrate are connected to the ground level, and the drain terminal of the first NMOS tube M1 is connected to the source terminal of the second NMOS tube M2; the second The drain terminal of the NMOS tube M2 is connected to the drain terminal of the PMOS tube M3 and the gate terminal of the charge transfer MOSFET tube S. The gate terminal of the second NMOS tube M2 is connected to the first bias voltage.
- the substrate of the second NMOS tube M2 is grounded. Flat; the gate terminal of the PMOS tube M3 is connected to the second bias voltage, and the source terminal and the substrate of the PMOS tube M3 are connected to the voltage output terminal V boost of the gate voltage bootstrap boost circuit; the charge transfer target node No, that is, the charge transfer
- the drain of the MOSFET tube S is connected to the charge transfer control signal Ck1n through the second capacitor C2; the charge transfer node Ni is connected to the charge transfer control signal Ck1 through the first capacitor C1; the substrate of the charge transfer MOSFET tube S is connected to the voltage switch K At the top, the substrate of the charge transfer MOSFET S is also connected to the negative voltage transfer MOSFET
- the drain terminal of the tube B; the ground level of the lower end of the voltage switch K, which is turned on and off by the charge transfer control signal Ck1; the substrate and source of the negative voltage transfer MOSFET tube B are connected to the output terminal of the negative voltage generating circuit
- the first and second input terminals of the voltage clock generating circuit are respectively connected to the charge transfer control signal Ck1 and the charge transfer control signal Ck1n; the clock input terminal of the gate voltage bootstrap boost circuit is connected to the charge transfer control signal Ck1;
- the signal Ck1 and the charge transfer control signal Ck1n are high-level non-overlapping pulse signals, the high level is a positive voltage greater than zero potential, the ground level is zero potential, and the negative potential is less than ground potential. Negative voltage.
- the low-voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap is further characterized in that: when performing charge transfer, the gate voltage bootstrap boost circuit is in a boosted state, and the gate of the charge transfer MOSFET tube is Very high level V DD + V Ni , the charge voltage transfer MOSFET tube is in an on state; after the charge transfer is completed, the gate voltage bootstrap boost circuit is in a charging state, and the gate of the charge transfer MOSFET tube is grounded. Level, the charge transfer MOSFET is in an off state; wherein V DD is the power supply voltage and V Ni is the source voltage of the MOSFET.
- the low voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap is further characterized in that: when a charge transfer is performed, the gate of the negative voltage transfer MOSFET B is connected to a high level, and the negative voltage transfer MOSFET B is connected to a high level. In the conducting state, the substrate of the charge transfer MOSFET S is connected to a negative voltage; when the charge transfer is completed, the gate of the negative voltage transfer MOSFET B is connected to a negative voltage, and the negative voltage transfer MOSFET B is turned off. Off state, the substrate ground level of the charge transfer MOSFET S.
- the advantage of the present invention is that the low voltage charge transfer circuit using negative voltage and gate voltage bootstrap provided by the present invention is suitable for ordinary CMOS process, which overcomes the problem of limited signal swing in the existing signal transmission circuit and can be widely used. It is applied to the charge domain sub-stage pipeline circuits in the charge domain pipelined analog-to-digital converter.
- FIG. 1 is a schematic diagram of an existing signal transmission circuit
- FIG. 2 is a schematic diagram of a working voltage waveform of an existing signal transmission circuit
- FIG. 3 is a schematic structural diagram of a low voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap according to the present invention
- FIG. 4 is a schematic diagram of a working voltage waveform of a low voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap according to the present invention
- FIG. 5 is a circuit diagram of an implementation of a gate voltage bootstrap boost circuit according to the present invention.
- FIG. 6 is an implementation circuit diagram of the negative voltage generating circuit according to the present invention.
- FIG. 7 (a) is a schematic circuit diagram of an implementation circuit of the positive and negative voltage clock generating circuit according to the present invention.
- FIG. 7 (b) is a voltage waveform diagram of the positive and negative voltage clock generating circuit according to the present invention.
- FIG. 8 shows the application of a low-voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap in a charge-domain pipelined analog-to-digital converter according to the present invention.
- FIG. 3 is a schematic structural diagram of a low-voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap designed according to the present invention.
- a negative voltage is added to the substrate of the MOSFET tube S in the signal transmission circuit shown in FIG. 1.
- the generating circuit and the negative voltage transmission circuit add a gate voltage bootstrap booster circuit between the source of the MOSFET S and the power supply VDD.
- the low-voltage charge transfer circuit using a negative voltage and gate voltage bootstrap includes a charge transfer MOSFET tube S, a gate voltage bootstrap boost circuit, a negative voltage transfer MOSFET tube B, a voltage switch K, and a negative voltage generation. Circuit, a positive and negative voltage clock generating circuit, a first NMOS tube M1, a second NMOS tube M2, a PMOS tube M3, a first capacitor C1 and a second capacitor C2.
- the corresponding connection relationship of the low voltage charge transfer circuit using the negative voltage and the gate voltage bootstrap is: the gate terminal of the first NMOS tube M1 is connected to the charge to be transferred node Ni, that is, the source of the charge transfer MOSFET tube S, and is also connected to The voltage input terminal of the gate voltage bootstrap boost circuit; the source terminal of the first NMOS tube M1 and the substrate are connected to the ground level, and the drain terminal of the first NMOS tube M1 is connected to the source terminal of the second NMOS tube M2; the second The drain terminal of the NMOS tube M2 is connected to the drain terminal of the PMOS tube M3 and the gate terminal of the charge transfer MOSFET tube S. The gate terminal of the second NMOS tube M2 is connected to the first bias voltage.
- the substrate of the second NMOS tube M2 is grounded. Flat; the gate terminal of the PMOS tube M3 is connected to the second bias voltage, and the source terminal and the substrate of the PMOS tube M3 are connected to the voltage output terminal V boost of the gate voltage bootstrap boost circuit; the charge transfer target node No, that is, the charge transfer
- the drain of the MOSFET tube S is connected to the charge transfer control signal Ck1n through the second capacitor C2; the charge transfer node Ni is connected to the charge transfer control signal Ck1 through the first capacitor C1; the substrate of the charge transfer MOSFET tube S is connected to the voltage switch K At the top, the substrate of the charge transfer MOSFET S is also connected to the negative voltage transfer MOSFET
- the drain terminal of the tube B; the ground level of the lower end of the voltage switch K, which is turned on and off by the charge transfer control signal Ck1; the substrate and source of the negative voltage transfer MOSFET tube B are connected to the output terminal of the negative voltage generating circuit
- FIG. 4 is a schematic diagram of a working voltage waveform of a low-voltage charge transfer circuit using a negative voltage and a gate voltage bootstrap according to the present invention.
- the gate bootstrap boost technology By using the gate bootstrap boost technology, the voltage at the G terminal is raised by a V DD voltage during the charge transfer, so that the upper limit of the V CK1n voltage can be increased to the V DD voltage, thereby achieving the purpose of increasing the BCT signal swing.
- the voltage of V CK1n is increased to V ' CK1n .
- the theoretical upper limit can be increased to V DD . It can be seen that the signal swing V' A of the BCT circuit has increased (V ' CK1n -V CK1n ).
- V R voltage is reduced to V ' R
- the minimum value of the S terminal voltage is negative voltage. It can be seen that the signal swing V A of the BCT circuit increases the difference voltage between V R -V' R. At the same time, the negative voltage and After the gate voltage bootstrap boost technology, the signal swing of the output end of the low voltage charge transfer circuit using the negative voltage and the gate voltage bootstrap according to the present invention has been increased by (V ' CK1n -V CK1n ) + (V R -V ' R ).
- FIG. 5 shows a schematic diagram of a gate voltage bootstrap boost circuit that can be used in the present invention.
- the principle is as follows: When the clock Ck1 is at a high level, the MOS tubes Mb2 and Mb6 are turned on, the MOS tube Mb7 is turned off and Mb4 is turned on, so that the MOS tube Mb1 is also turned on; the circuit charges the capacitor Cb1 through the MOS tubes Mb1 and Mb2, so that The voltage across Cb1 is close to the power supply voltage V DD , so the capacity of V DD * Cb1 is stored on the capacitor Cb1, and the gate voltage bootstrap boost circuit is in a charging state.
- the gate voltage bootstrap booster circuit When charge transfer is performed, the gate voltage bootstrap booster circuit is in a boosted state, the gate of the charge transfer MOSFET tube is at a high level V DD + V Ni , and the charge transfer MOSFET tube S is in an on state; when the charge transfer ends Then, the gate voltage bootstrap boost circuit is in a charging state, the gate of the charge transfer MOSFET tube S is grounded, and the charge transfer MOSFET tube is in an off state.
- V DD is the power supply voltage
- V Ni is the source voltage of the charge transfer MOSFET S.
- FIG. 6 is a schematic diagram of a negative voltage generating circuit that can be used in the present invention to provide a negative bias voltage for the substrate of the charge transfer MOSFET S of FIG. 3.
- This circuit uses similar capacitor charging and discharging and MOS switch on and off characteristics to achieve negative voltage output.
- the detailed circuit working principle can refer to US patent US5831844, which will not be explained here.
- the negative voltage output by the negative voltage generating circuit in the present invention is transmitted through a negative voltage transmitting MOSFET tube B.
- the gate of the negative voltage transfer MOSFET B is connected to a high level, the negative voltage transfer MOSFET B is in an on state, and the liner of the charge transfer MOSFET S is lined up.
- the negative voltage is connected to the bottom; after the input signal swing-enhanced signal transmission circuit finishes the charge transmission, the gate of the negative voltage transmission MOSFET B is connected to a negative voltage, the negative voltage transmission MOSFET B is in an off state, and the charge transmission MOSFET tube
- the substrate of S is grounded under the control of the charge transfer control signal Ck1.
- the present invention uses a positive and negative voltage clock to control the signal transmission of the negative voltage transmission MOSFET tube B.
- the main reason is that when the source terminal and the substrate of the negative voltage transmission MOSFET tube B are both negative voltage, the negative voltage transmission MOSFET tube B is turned off. Off, the voltage difference between the gate terminal and the source terminal of the negative voltage transmission MOSFET B must be less than the threshold voltage (V thB ) that is turned on. If a common voltage clock is used to control the gate terminal of the negative voltage transmission MOSFET B, when the clock level is low, the gate and source voltages of the negative voltage transmission MOSFET B are greater than the threshold voltage (V thB ) that is turned on. As a result, the negative voltage transmitting MOSFET B cannot be turned off. Therefore, the gate control clock of the negative voltage transmitting MOSFET B must be controlled by using a positive and negative voltage clock.
- the high level is a positive voltage greater than zero potential; the ground level is zero voltage; the negative potential is a negative voltage less than the ground level; the charge transfer control signal Ck1 and the charge transfer control signal Ck1n are High-level non-overlapping pulse signals.
- FIG. 7 (a) and Fig. 7 (b) show a circuit principle and a working voltage waveform diagram of a positive-negative voltage clock generating circuit shown in Fig. 3 which can be used in the present invention.
- FIG. 7 (a) is a circuit principle of the positive and negative voltage clock generating circuit
- FIG. 7 (b) is a voltage waveform of the input charge transfer control signal Ck1n and the output signal Ck1nout obtained by simulation when the positive and negative voltage clock generating circuit operates. Illustration.
- This circuit uses similar characteristics of capacitor charging and discharging and digital flip-flop circuits to achieve positive and negative voltage clock output.
- Chinese patent ZL201010175033.1 a negative voltage effective transmission circuit suitable for standard CMOS technology. The principle is not explained here.
- FIG. 8 shows the application of the present invention in a charge domain pipeline ADC.
- the figure shows the specific implementation of the 1.5-bit / stage charge-domain sub-stage pipeline circuit in the charge-domain pipelined analog-to-digital converter and the specific connection relationship between the charge-domain sub-stage pipeline circuits in the front and back stages.
- the charge domain sub-stage pipeline circuit is composed of fully differential signal processing channels 100p and 100n.
- the charge domain sub-stage pipeline circuit includes two low-voltage charge transfer circuits (101p and 101n) using negative voltage and gate voltage bootstrap according to the present invention.
- a low-voltage charge transfer circuit (102p and 102n) using a negative voltage and a gate voltage bootstrap, two charge storage capacitors (109p and 109n) connected to a charge storage node of a next-stage sub-circuit.
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Abstract
一种采用负电压和栅压自举的低电压电荷传输电路,包括一个电荷传输MOSFET管(S)、一个栅压自举增压电路、一个负电压传输MOSFET管(B)、一个电压开关(K)、一个负电压产生电路、一个正负电压时钟产生电路、第一NMOS管(M1)、第二NMOS管(M2)、PMOS管(M3)、第一电容(C1)和第二电容(C2)。该电路克服了现有信号传输电路中信号摆幅受限的问题,可以广泛应用于各类信号处理电路中。
Description
本发明涉及一种用于电荷域流水线模数转换器的输入信号摆幅增强型电荷信号传输电路,属于集成电路技术领域。
随着数字信号处理技术的不断发展,电子***的数字化和集成化是必然趋势。然而现实中的信号大都是连续变化的模拟量,需经过模数转换变成数字信号方可输入到数字***中进行处理和控制,因而模数转换器在未来的数字***设计中是不可或缺的组成部分。在宽带通信、数字高清电视和雷达等应用领域,***要求模数转换器同时具有非常高的采样速率和分辨率。这些应用领域的便携式终端产品对于模数转换器的要求不仅要高采样速率和高分辨率,其功耗还应该最小化。
目前,能够同时实现高采样速率和高分辨率的模数转换器结构为流水线结构模数转换器。流水线结构是一种多级的转换结构,每一级使用低精度的基本结构的模数转换器,输入信号经过逐级的处理,最后由每级的结果组合生成高精度的输出。其基本思想就是把总体上要求的转换精度平均分配到每一级,每一级的转换结果合并在一起可以得到最终的转换结果。由于流水线结构模数转换器可以在速度、功耗和芯片面积上实现最好的折中,因此在实现较高精度的模数转换时仍然能保持较高的速度和较低的功耗。
现有比较成熟的实现流水线结构模数转换器的方式是基于开关电容技术的流水线结构。基于该技术的流水线模数转换器中采样保持电路和各个子级电路的工作也都必须使用高增益和宽带宽的运算放大器。模数转换器的速度和处理精度取决于所使用高增益和超宽带宽的运算放大器负反馈的建立速度和精度。因此该类流水线结构模数转换器设计的核心是所使用高增益和超宽带宽的运算放大器的设计。这些高增益和宽带宽运算放大器的使用限制了开关电容流水线模数转换器的速度和精度,成为该类模数转换器性能提高的主要限制瓶颈,并且精度不变的情况下模数转换器功耗水平随速度的提高呈直线上升趋势。要降低基于开关电容电路的流水线模数转换器的功耗水平,最直接的方法就是减少或者消去高增益和超宽带宽的运算放大器的使用。
电荷域流水线模数转换器就是一种不使用高增益和超宽带宽的运算放大器的模数转换器,该结构模数转换器具有低功耗特性同时又能实现高速度和高精度。电荷域流水线模数转换器采用电荷域信号处理技术。电路中,信号以电荷包的形式表示,电荷包的大小代表不同大小的信号量,不同大小的电荷包在不同存储节点间的存储、传输、加/减、比较等处理实现信号处理功能。通过采用 周期性的时钟来驱动控制不同大小的电荷包在不同存储节点间的信号处理便可以实现模数转换功能。
在电荷域流水线模数转换器中,各级电荷域流水线子级电路由本级电荷传输控制开关、多个电荷物理存储节点、多个连接到电荷存储节点的电荷存储元件、多个比较器、多个受比较器输出结果控制的基准电荷选择电路在控制时钟的控制下构成。各级流水线子级电路的工作过程中,电荷的传输、加/减、比较量化等功能均围绕各子级的电荷物理存储节点进行。
由于流水线模数转换器的实现包括了大量的数字电路,而普通CMOS工艺是实现这些大规模数字电路的最佳工艺。要借助数字信号处理技术来实现超高速和超高精度的电荷域流水线模数转换器,最核心的一个问题就是电荷信号的存储传输、比较量化以及加减运算等关键步骤在现有的普通CMOS工艺条件下能够高效并精确地实现。因此,为借助大规模数字信号处理技术来实现高速度和高精度电荷域流水线模数转换器,必须提供一种适用于普通CMOS工艺的高精度电荷信号传输电路。
对于高效信号传输技术的实现,现有的技术实现方式典型的有专利:US2007/0279507A1增强型信号传输电路,其典型电路结构如图1所示。电荷信号传输MOSFET管S的栅极V
G被连接到由MOS管M1、M2和M3构成的运算放大器1的输出端。运算放大器1的输出端运算电荷传输之前,S处于关断状态,待传输电荷被存储在C
1上。图2为该电路的工作电压波形示意图。t0时刻,Ck1发生负阶越变化,Ck1n发生正阶越变化,导致Ni电压V
Ni突变到一个低电位而No的电压V
No突变到一个高电位,运算放大器1将会响应该变化并驱动MOSFET管S栅极V
G电压为高电平,使得S开始导通;由于电势差的缘故,Ni上所存储电荷将会以电子形式向No转移,引起V
Ni上升而V
No下降,运算放大器1将同样会响应该变化并驱动MOSFET管S栅极V
G电压逐渐降低;t1时刻,当V
Ni上升到电压V
R时,V
G电压逐渐降低到截止电压V
th时,S重新关断,电荷传输过程结束,其中V
R由共源共栅运算放大器的静态工作点确定。
对于图1所示信号传输电路,在低电压条件下面临的一个突出问题是它们能处理的输入模拟信号摆幅受限,无法达到通用ADC对输入模拟信号差分摆幅的需求。如图2中所示,电荷传输和电压传输的一个最大区别是电荷传输结束时,MOSFET管S的源和漏两端保持了一个压差V
DS,为保证电荷传输过程的安全可靠,MOSFET管S的这个V
DS压差通常被设置在20%的VDD电源电压左右。在前期的1.8V电压条件下,M
S的V
DS压差通常被设置在0.35~0.4V,这就明显降低了电荷域ADC流水线子级电路能处理的输入模拟信号摆幅范围。
与图1所示信号传输电路的输入信号摆幅主要相关的信号节点为电荷传输管MOSFET管S的栅、漏、源和衬底四端。由于在实际电路中源端和漏端分别属于前后相连的两个子级电路,因此源端的电容是漏端电容的2
N倍(N为源端所在子级电路的位数),导致电荷传输时漏端电压下降幅度是源端的2
N倍,因此电路的有效信号摆幅主要表现为漏端电压下降幅度,即:V
A=V
CK1n-V
DS-V
R,V
CK1n 为控制信号CK1n的高电平电压。在低电压条件下,V
DS所占用的20%V
DD电压的压差没有优化空间;V
CK1n电压为芯片的全局性基准电压,其理论最大值可为V
DD,但实际中其最大值还受G端电压限制,而G端电压最大值只能为电源电压V
DD,有明显限制;V
R的最低电压受S端限制,而S的最低电压会受到信号‘地电平’电压的限制。因此,要增大信号摆幅,必须克服V
R电压的信号‘地电平’和V
CK1n电压的V
DD限制。本发明中,克服V
CK1n电压的V
DD限制,采用栅压自举技术,在电荷传输时将G端电压抬高一个V
DD电压,这样V
CK1n电压的上限可以提高到V
DD电压;为克服V
R电压的信号‘地电平’限制,采用负电压降压的方式,通过将MOSFET管S的衬底电压接负电压的方式降低S端电压的最低值,这样可以明显降低V
R电压的下限,从而增加BCT的信号摆幅。
发明内容
本发明的目的是克服现有技术中存在的不足,提供一种采用负电压和栅压自举的低电压电荷传输电路,是一种适用于普通CMOS工艺的高精度电荷传输电路。
按照本发明提供的采用负电压和栅压自举的低电压电荷传输电路技术方案,其特征是:包括一个电荷传输MOSFET管S、一个栅压自举增压电路、一个负电压传输MOSFET管B、一个电压开关K、一个负电压产生电路、一个正负电压时钟产生电路、第一NMOS管M1、第二NMOS管M2、PMOS管M3、第一电容C1和第二电容C2;
所述采用负电压和栅压自举的低电压电荷传输电路对应连接关系为:第一NMOS管M1的栅端连接到电荷待传输节点Ni,即电荷传输MOSFET管S的源极,还连接到栅压自举增压电路的电压输入端;第一NMOS管M1的源端和衬底连接到地电平,第一NMOS管M1的漏端连接到第二NMOS管M2的源端;第二NMOS管M2的漏端连接到PMOS管M3的漏端和电荷传输MOSFET管S的栅端,第二NMOS管M2的栅端连接到第一偏置电压,第二NMOS管M2的衬底接地电平;PMOS管M3的栅端连接到第二偏置电压,PMOS管M3的源端和衬底连接到栅压自举增压电路的电压输出端V
boost;电荷传输目标节点No,即电荷传输MOSFET管S的漏极,通过第二电容C2接电荷传输控制信号Ck1n;电荷待传输节点Ni通过第一电容C1接电荷传输控制信号Ck1;电荷传输MOSFET管S的衬底连接到电压开关K的上端,电荷传输MOSFET管S的衬底还连接到负电压传输MOSFET管B的漏端;电压开关K的下端接地电平,其导通和关断受电荷传输控制信号Ck1控制;负电压传输MOSFET管B的衬底和源端连接到负电压产生电路的输出端,负电压传输MOSFET管B的栅端连接到正负电压时钟产生电路的输出端;负电压产生电路的第一和第二输入端分别连接电荷传输控制信号Ck1和电荷传输控制信号Ck1n,正负电压时钟产生电路的第一和第二输入端分别连接电荷传输控制信号Ck1和电荷传输控制信号Ck1n;栅压自举增压电路的时钟输入端连接电荷传输控制信号Ck1;其中,述电荷传输 控制信号Ck1和电荷传输控制信号Ck1n为高电平不交叠脉冲信号,所述高电平为大于零电位的正电压;所述地电平为零电位;所述负电位为小于地电平的负电压。
所述采用负电压和栅压自举的低电压电荷传输电路,其特征还在于:当进行电荷传输时,所述栅压自举增压电路处于增压状态,所述电荷传输MOSFET管的栅极为高电平V
DD+V
Ni,电荷电压传输MOSFET管处于导通状态;当电荷传输结束后,所述栅压自举增压电路处于充电状态,所述电荷传输MOSFET管的栅极接地电平,所述电荷传输MOSFET管处于关断状态;其中,V
DD为电源电压,V
Ni为MOSFET管的源极电压。
所述采用负电压和栅压自举的低电压电荷传输电路,其特征还在于:当进行电荷传输时,所述负电压传输MOSFET管B的栅极接高电平,负电压传输MOSFET管B处于导通状态,所述电荷传输MOSFET管S的衬底接负电压;当电荷传输结束后,所述负电压传输MOSFET管B的栅极接负电压,所述负电压传输MOSFET管B处于关断状态,所述电荷传输MOSFET管S的衬底接地电平。
本发明的优点是:本发明所提供的适用于普通CMOS工艺的采用负电压和栅压自举的低电压电荷传输电路,克服了现有信号传输电路中信号摆幅受限的问题,可以广泛应用于电荷域流水线模数转换器中各级电荷域子级流水电路中。
图1为现有信号传输电路原理图;
图2为现有信号传输电路工作电压波形示意图;
图3为本发明采用负电压和栅压自举的低电压电荷传输电路结构原理图;
图4为本发明采用负电压和栅压自举的低电压电荷传输电路工作电压波形示意图;
图5为本发明所述栅压自举增压电路的一种实现电路图;
图6为本发明所述负电压产生电路的一种实现电路图;
图7(a)为本发明所述正负电压时钟产生电路的一种实现电路原理图;
图7(b)为本发明所述正负电压时钟产生电路工作的电压波形图;
图8为本发明采用负电压和栅压自举的低电压电荷传输电路在电荷域流水线模数转换器中的应用。
下面结合附图和实例对本发明进行进一步详细的说明。
图3所示为本发明设计的采用负电压和栅压自举的低电压电荷传输电路的结构原理图,其在图1所示信号传输电路中的MOSFET管S的衬底增加了一个负电压产生电路和负电压传输电路,在MOSFET管S的源极和电源VDD之间 增加了一个栅压自举增压电路。所述采用负电压和栅压自举的低电压电荷传输电路包括一个电荷传输MOSFET管S、一个栅压自举增压电路、一个负电压传输MOSFET管B、一个电压开关K、一个负电压产生电路、一个正负电压时钟产生电路、第一NMOS管M1、第二NMOS管M2、PMOS管M3、第一电容C1和第二电容C2。
所述采用负电压和栅压自举的低电压电荷传输电路对应连接关系为:第一NMOS管M1的栅端连接到电荷待传输节点Ni,即电荷传输MOSFET管S的源极,还连接到栅压自举增压电路的电压输入端;第一NMOS管M1的源端和衬底连接到地电平,第一NMOS管M1的漏端连接到第二NMOS管M2的源端;第二NMOS管M2的漏端连接到PMOS管M3的漏端和电荷传输MOSFET管S的栅端,第二NMOS管M2的栅端连接到第一偏置电压,第二NMOS管M2的衬底接地电平;PMOS管M3的栅端连接到第二偏置电压,PMOS管M3的源端和衬底连接到栅压自举增压电路的电压输出端V
boost;电荷传输目标节点No,即电荷传输MOSFET管S的漏极,通过第二电容C2接电荷传输控制信号Ck1n;电荷待传输节点Ni通过第一电容C1接电荷传输控制信号Ck1;电荷传输MOSFET管S的衬底连接到电压开关K的上端,电荷传输MOSFET管S的衬底还连接到负电压传输MOSFET管B的漏端;电压开关K的下端接地电平,其导通和关断受电荷传输控制信号Ck1控制;负电压传输MOSFET管B的衬底和源端连接到负电压产生电路的输出端,负电压传输MOSFET管B的栅端连接到正负电压时钟产生电路的输出端;负电压产生电路的第一和第二输入端分别连接电荷传输控制信号Ck1和电荷传输控制信号Ck1n,正负电压时钟产生电路的第一和第二输入端分别连接电荷传输控制信号Ck1和电荷传输控制信号Ck1n;栅压自举增压电路的时钟输入端连接电荷传输控制信号Ck1。
图4给出了本发明采用负电压和栅压自举的低电压电荷传输电路的工作电压波形示意图。通过采用栅自举升压技术,在电荷传输时将G端电压抬高一个V
DD电压,这样V
CK1n电压的上限可以提高到V
DD电压,从而达到增加BCT信号摆幅的目的。V
CK1n电压被提高到V’
CK1n,理论上的上限可以提高到V
DD,可以看出BCT电路的信号摆幅V’
A增加了(V’
CK1n-V
CK1n);通过采用负电压降压后,V
R电压被降低为V’
R,S端电压的最低值为负电压,可以看出BCT电路的信号摆幅V
A增加了V
R-V’
R的差值电压;同时采用负电压和栅压自举升压技术后,本发明所述采用负电压和栅压自举的低电压电荷传输电路的输出端信号摆幅共增加了(V’
CK1n-V
CK1n)+(V
R-V’
R)的摆幅。
图5所示为一种可以用于本发明的栅压自举增压电路的原理图。其原理如下:时钟Ck1为高电平时,MOS管Mb2、Mb6导通,MOS管Mb7截至,Mb4导通,使得MOS管Mb1也导通;电路通过MOS管Mb1和Mb2对电容Cb1充电,使得电容Cb1两端的电压接近电源电压V
DD,从而在电容Cb1上存储了 V
DD*Cb1的电量,栅压自举增压电路处于充电状态。当时钟Ck1从高变低时,MOS管Mb2、Mb6截止,MOS管Mb7导通,Mb4导通;电源通过MOS管Mb4、Mb7对结点V
boost的对地寄生电容充电,使得结点V
boost电压升高,MOS管Mb1截止,Mb5、Mb3导通;输入信号通过MOS管Mb3抬升电容Cb1下极板电压直到其值等于输入电压V
Ni;由于电容Cb1上存储的电荷在时钟CK变化过程中没有放电回路,存储在其上的电荷保持不变,电容Cb1上极板的电压就会同步上升,直到其值等于V
DD+V
Ni,实现了栅压自举功能,栅压自举增压电路处于增压状态。
结合图4的波形示意图可以知道。当进行电荷传输时,栅压自举增压电路处于增压状态,所述电荷传输MOSFET管的栅极为高电平V
DD+V
Ni,电荷传输MOSFET管S处于导通状态;当电荷传输结束后,栅压自举增压电路处于充电状态,所述电荷传输MOSFET管S的栅极接地电平,所述电荷传输MOSFET管处于关断状态。其中,V
DD为电源电压,V
Ni为电荷传输MOSFET管S的源极电压。
图6所示为一种可以用于本发明中为图3中电荷传输MOSFET管S衬底提供负偏置电压的一种负电压产生电路的原理图。该电路采用类似的电容充放电和MOS开关的导通和关断特性实现负电压输出,详细的电路工作原理可以参考美国专利US5831844,在此不再阐述。
本发明中负电压产生电路输出的负电压通过一个负电压传输MOSFET管B来进行传输。当所述输入信号摆幅增强型信号传输电路开始进行电荷传输时,负电压传输MOSFET管B的栅极接高电平,负电压传输MOSFET管B处于导通状态,电荷传输MOSFET管S的衬底接负电压;当所述输入信号摆幅增强型信号传输电路电荷传输结束后,负电压传输MOSFET管B的栅极接负电压,负电压传输MOSFET管B处于关断状态,电荷传输MOSFET管S的衬底在电荷传输控制信号Ck1控制下接地电平。
本发明采用正负电压时钟来控制负电压传输MOSFET管B的信号传输,主要原因是在负电压传输MOSFET管B的源端和衬底均为负电压时,要将负电压传输MOSFET管B关断,必须使负电压传输MOSFET管B的栅端和源端电压差小于其开启的阈值电压(V
thB)。若采用普通电压时钟控制负电压传输MOSFET管B的栅端,则会出现时钟低电平时,负电压传输MOSFET管B的栅端和源端电压大于其开启的阈值电压(V
thB)的状态,导致负电压传输MOSFET管B不能关断。因此,负电压传输MOSFET管B的栅端控制时钟必须采用正负电压时钟来进行控制。
本发明所述高电平为大于零电位的正电压;所述地电平为零电压;所述负电位为小于地电平的负电压;述电荷传输控制信号Ck1和电荷传输控制信号Ck1n为高电平不交叠脉冲信号。
图7(a)和图7(b)所示为一种可以用于本发明中为图3中的一种正负 电压时钟产生电路的电路原理和工作电压波形图。图7(a)为所述正负电压时钟产生电路的电路原理,图7(b)为所述正负电压时钟产生电路工作时仿真得到的输入电荷传输控制信号Ck1n和输出信号Ck1nout的电压波形图。该电路采用类似的电容充放电和数字触发器电路的特性实现正负电压时钟输出,详细的电路工作原理可以参考中国专利ZL201010175033.1(一种适用于标准CMOS工艺的负电压有效传输电路),其原理在此不再阐述。
图8为本发明在电荷域流水线ADC中的应用。图中所示为电荷域流水线模数转换器中1.5位/级电荷域子级流水线电路具体实现和前后级电荷域子级流水线电路的具体连接关系。电荷域子级流水线电路由全差分的信号处理通道100p和100n构成,电荷域子级流水线电路包括2个本发明所述的采用负电压和栅压自举的低电压电荷传输电路(101p和101n)、2个电荷存储节点(104p和104n)、2个连接到前级子级电路电荷存储节点的电荷存储电容(106p和106n)、6个连接到本级1.5位/级子级电路电荷存储节点的电荷存储电容(107p、107n、108p、108n)、2个比较器,2个受比较器输出结果控制的基准电荷选择电路,2个连接到本级电荷存储节点的下一级子级电路的本发明所述采用负电压和栅压自举的低电压电荷传输电路(102p和102n),2个连接到下一级子级电路电荷存储节点的电荷存储电容(109p和109n)。
以上所述仅为本发明的较佳实施例,并不用以限制本发明,凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (3)
- 一种采用负电压和栅压自举的低电压电荷传输电路,其特征是:包括一个电荷传输MOSFET管S、一个栅压自举增压电路、一个负电压传输MOSFET管B、一个电压开关K、一个负电压产生电路、一个正负电压时钟产生电路、第一NMOS管M1、第二NMOS管M2、PMOS管M3、第一电容C1和第二电容C2;所述采用负电压和栅压自举的低电压电荷传输电路对应连接关系为:第一NMOS管M1的栅端连接到电荷待传输节点Ni,即电荷传输MOSFET管S的源极,还连接到栅压自举增压电路的电压输入端;第一NMOS管M1的源端和衬底连接到地电平,第一NMOS管M1的漏端连接到第二NMOS管M2的源端;第二NMOS管M2的漏端连接到PMOS管M3的漏端和电荷传输MOSFET管S的栅端,第二NMOS管M2的栅端连接到第一偏置电压,第二NMOS管M2的衬底接地电平;PMOS管M3的栅端连接到第二偏置电压,PMOS管M3的源端和衬底连接到栅压自举增压电路的电压输出端V boost;电荷传输目标节点No,即电荷传输MOSFET管S的漏极,通过第二电容C2接电荷传输控制信号Ck1n;电荷待传输节点Ni通过第一电容C1接电荷传输控制信号Ck1;电荷传输MOSFET管S的衬底连接到电压开关K的上端,电荷传输MOSFET管S的衬底还连接到负电压传输MOSFET管B的漏端;电压开关K的下端接地电平,其导通和关断受电荷传输控制信号Ck1控制;负电压传输MOSFET管B的衬底和源端连接到负电压产生电路的输出端,负电压传输MOSFET管B的栅端连接到正负电压时钟产生电路的输出端;负电压产生电路的第一和第二输入端分别连接电荷传输控制信号Ck1和电荷传输控制信号Ck1n,正负电压时钟产生电路的第一和第二输入端分别连接电荷传输控制信号Ck1和电荷传输控制信号Ck1n;栅压自举增压电路的时钟输入端连接电荷传输控制信号Ck1;其中,述电荷传输控制信号Ck1和电荷传输控制信号Ck1n为高电平不交叠脉冲信号;所述高电平为大于零电位的正电压;所述地电平为零电位;所述负电位为小于地电平的负电压。
- 根据权利要求1所述采用负电压和栅压自举的低电压电荷传输电路,其特征在于:当进行电荷传输时,所述栅压自举增压电路处于增压状态,所述电荷传输MOSFET管S的栅极为高电平V DD+V Ni,电荷电压传输MOSFET管S处于导通状态;当电荷传输结束后,所述栅压自举增压电路处于充电状态,所述电荷传输MOSFET管S的栅极接地电平,所述电荷传输MOSFET管S处于关断状态;其中,V DD为电源电压,V Ni为MOSFET管的源极电压。
- 根据权利要求1所述输入信号摆幅增强型信号传输电路,其特征在于: 当进行电荷传输时,所述负电压传输MOSFET管B的栅极接高电平,负电压传输MOSFET管B处于导通状态,所述电荷传输MOSFET管S的衬底接负电压;当电荷传输结束后,所述负电压传输MOSFET管B的栅极接负电压,所述负电压传输MOSFET管B处于关断状态,所述电荷传输MOSFET管S的衬底接地电平。
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