WO2015007486A1 - Puce semi-conductrice opto-électronique - Google Patents

Puce semi-conductrice opto-électronique Download PDF

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Publication number
WO2015007486A1
WO2015007486A1 PCT/EP2014/063423 EP2014063423W WO2015007486A1 WO 2015007486 A1 WO2015007486 A1 WO 2015007486A1 EP 2014063423 W EP2014063423 W EP 2014063423W WO 2015007486 A1 WO2015007486 A1 WO 2015007486A1
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WO
WIPO (PCT)
Prior art keywords
layer
encapsulation layer
encapsulation
semiconductor chip
region
Prior art date
Application number
PCT/EP2014/063423
Other languages
German (de)
English (en)
Inventor
Karl Engl
Georg Hartung
Johann Eibl
Michael Huber
Markus Maute
Original Assignee
Osram Opto Semiconductors Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors Gmbh filed Critical Osram Opto Semiconductors Gmbh
Priority to DE112014003318.9T priority Critical patent/DE112014003318A5/de
Priority to KR1020167003831A priority patent/KR102268352B1/ko
Priority to JP2016526490A priority patent/JP6284634B2/ja
Priority to CN201480040795.7A priority patent/CN105393369B/zh
Priority to US14/905,763 priority patent/US10014444B2/en
Publication of WO2015007486A1 publication Critical patent/WO2015007486A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H01L33/505—Wavelength conversion elements characterised by the shape, e.g. plate or foil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/56—Materials, e.g. epoxy or silicone resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0025—Processes relating to coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials

Definitions

  • Optoelectronic Semiconductor Chip An optoelectronic semiconductor chip is specified.
  • the optoelectronic semiconductor chip comprises a semiconductor body.
  • the semiconductor body is
  • the semiconductor body includes an n-type region, a p-type region, and an active region therebetween for generating electromagnetic
  • the n-conducting region and the p-conducting region are produced, for example, by appropriate doping of the semiconductor material of the semiconductor body.
  • the electromagnetic radiation generated in the active region of the semiconductor body is, for example, UV radiation, infrared radiation and / or visible light.
  • the electromagnetic radiation is generated, for example, by energizing the active region.
  • electromagnetic radiation leaves the semiconductor body at least in part by an outer surface of the
  • the optoelectronic semiconductor chip comprises a first mirror layer, which is used for reflection of the
  • the first mirror layer is
  • electromagnetic radiation which is generated in the active region of the semiconductor body, partly impinges on the first mirror layer and is reflected by it in the direction of the outer surface of the semiconductor body, in particular in the direction of the second main surface, where it then partially emerges.
  • the mirror layer is formed in particular metallic.
  • the mirror layer contains or consists of one of the following metals: silver, aluminum.
  • These metals have good to very good visible light reflectivity, but may have the disadvantage of being prone to diffusion or electromigration, especially when there is an electromagnetic field as in the case of the optoelectronic semiconductor die. Furthermore, these metals can oxidize especially in a moist environment, which increasingly reduces the reflectivity and thus the efficiency of the semiconductor body with increasing operating time.
  • the optoelectronic semiconductor chip comprises at least three encapsulation layers.
  • the optoelectronic semiconductor chip may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer
  • Encapsulation layer include. The least three
  • Encapsulation layers are each formed electrically insulating and to an electrically insulating
  • the encapsulation layers may each comprise one or more layers.
  • Encapsulation layers may be formed by different processes for their production and / or different material composition and / or a different
  • the encapsulation layers are in particular provided to prevent diffusion of material from the first mirror layer into other regions of the optoelectronic semiconductor chip and / or to hinder or prevent the penetration of atmospheric gases and / or moisture to the first mirror layer and / or regions of the optoelectronic semiconductor chip of FIG electrically isolate other areas of the optoelectronic semiconductor chip.
  • the first mirror layer is at one
  • the lower side of the p-type region is, for example, the side of the n-type region facing away from the n-type region
  • the mirror layer may be in direct contact with the p-type region.
  • the active region is arranged on a side of the p-conducting region facing away from the first mirroring layer, and the n-conducting region is arranged on a side of the active region facing away from the p-conducting region. That is, the active region is arranged between the p-type region and the n-type region, wherein the first mirror layer is arranged on the underside of the p-type region facing away from the n-type region.
  • Encapsulation layer the semiconductor body at its
  • Encapsulation layers may be in direct contact with the semiconductor body.
  • the first one may be in direct contact with the semiconductor body.
  • the third encapsulation layer covers the first mirror layer at its p-conducting region
  • Encapsulation layer and the first mirror layer at least one further layer, for example a metallic layer, is arranged. However, there is at least one area in the third encapsulation layer with the first
  • the third encapsulation layer may for example be applied directly to the mirror layer.
  • Encapsulation layer covers the mirror layer gap-free on its side facing away from the p-type region, wherein the mirror layer, for example, directly adjoins the p-type region at its underside facing the p-type region and the remaining free outer surface of the first mirror layer from the third encapsulation layer
  • the second encapsulation layer and the third encapsulation layer are locally in direct contact with each other in a region laterally of the first mirror layer.
  • An area laterally of the first mirror layer is, for example, an area that is in a lateral
  • the lateral directions are those directions that are parallel to a main plane of extension of the first
  • Mirror layer run.
  • the second is located laterally of the mirror layer, in particular at a distance from the region in which the third encapsulation layer and the first mirror layer are in direct contact with one another
  • Encapsulation layer and the third encapsulation layer in direct contact with each other.
  • the third encapsulation layer and the second encapsulation layer are ALD layers. That is, at least these two encapsulation layers, optionally also other encapsulation layers, such as, for example, the First encapsulation layer are layers made by ALD (Atomic Layer Deposition) method.
  • ALD Atomic Layer Deposition
  • At least the second and the third encapsulation layers are thus produced by means of an ALD method such as, for example, the flash ALD, the photo-induced ALD or another ALD method.
  • an ALD method such as, for example, the flash ALD, the photo-induced ALD or another ALD method.
  • High-temperature ALD methods are used where the encapsulation layer is deposited at temperatures of 100 ° C or higher.
  • a manufactured by an ALD process is used where the encapsulation layer is deposited at temperatures of 100 ° C or higher.
  • Encapsulation layer is via electro-microscopic
  • an encapsulation layer is an ALD layer, It is therefore an objective feature that can be detected on the finished optoelectronic semiconductor chip.
  • the encapsulation layer which is an ALD layer, is formed with an electrically insulating material and has for example a thickness between 0.05 nm and at most 500 nm, in particular between at least 30 nm and at most 50 nm, for example a thickness of 40 nm ,
  • the encapsulation layer is formed with an electrically insulating material and has for example a thickness between 0.05 nm and at most 500 nm, in particular between at least 30 nm and at most 50 nm, for example a thickness of 40 nm .
  • Encapsulation layer may comprise a plurality of sub-layers, which are arranged on top of each other.
  • Encapsulation layer contains or consists for example of one of the following materials: Ta2Ü5, Al2O3, A1N, SiO2 It is also possible, in particular, for the encapsulation layer, which is an ALD layer, to contain a combination of these materials.
  • the ALD layers are preferably free of silicon dioxide and / or silicon nitride.
  • the optoelectronic semiconductor chip comprises a semiconductor body which has an n-type region, an active region provided for generating electromagnetic radiation and a p-type region.
  • the optoelectronic semiconductor chip comprises a first mirror layer, which is used for reflection of the
  • Optoelectronic semiconductor chip also comprises a first, a second and a third encapsulation layer, wherein the encapsulation layers each with an electrically
  • the first mirror layer is disposed on a lower surface of the p-type region
  • the active region is disposed on a side of the p-type region facing away from the first mirror layer
  • the n-type region is on a p-type region arranged away from the active area.
  • the first, second and third encapsulation layers cover the semiconductor body on its outer surface and the third encapsulation layer completely covers the first mirror layer on its side facing away from the p-conducting region, wherein it is locally in direct contact with the first mirror layer .
  • the encapsulation layer and the third encapsulation layer are locally in direct contact with each other in at least one region laterally of the first mirror layer, and the second and third encapsulation layers are ALD layers.
  • An optoelectronic semiconductor chip described here is based inter alia on the following considerations: An optoelectronic semiconductor chip, in particular a
  • LED chip must be reliably protected against exposure to moisture from the environment to ensure its durability.
  • mirror layers in the optoelectronic semiconductor chip which with a for
  • Migration in the electric field and oxidation-prone material such as silver are formed, for example, by metallic encapsulation before the penetration of
  • the first mirror layer is completely covered, in particular, by the third encapsulation layer, which is an ALD layer. This provides a particularly effective protection of the first mirror layer from the penetration of Moisture and atmospheric gases.
  • the mirror layer can be guided particularly close to an outer side surface of the semiconductor body without damaging the first mirror layer during the production of the optoelectronic layer
  • Encapsulation layers which are ALD layers, are particularly thin and made of a radiation-transmissive material
  • the semiconductor chip comprises a second
  • the second mirror layer may be formed with the same material as the first mirror layer.
  • Mirror layer serves, otherwise light-absorbing
  • the second mirror layer may be formed electrically conductive.
  • the second mirror layer for example, with the n-type region of the semiconductor body electrically conductive be connected and serves in addition to their optical properties for current injection into the n-type region of the semiconductor body.
  • At least some of the encapsulation layers may be located at least indirectly between the first mirror layer and the second mirror layer. In this way, for example, the third and optionally further encapsulation layers may or may not provide electrical insulation between the first mirror layer and the second
  • the second mirror layer projects beyond the second mirror layer
  • At least some of the encapsulation layers may extend on the side of the second mirror layer facing the semiconductor body.
  • the second mirror layer is provided for reflecting electromagnetic radiation generated in the semiconductor body during operation.
  • the second mirror layer projects beyond the semiconductor body in a lateral direction parallel to the semiconductor body
  • Main extension plane of the semiconductor body runs.
  • the second mirror layer is thus laterally over the
  • Mirror layer also electromagnetic radiation that emerges from the side surfaces of the semiconductor body and then extends in the direction of the second mirror layer
  • the first encapsulation layer extends on the outer surface of the semiconductor body from the active region along the p-type region to a side surface of the first mirror layer.
  • the first encapsulation layer extends on the outer surface of the semiconductor body from the active region along the p-type region to a side surface of the first mirror layer.
  • Encapsulation layer in places in direct contact with the first mirror layer.
  • the first mirror layer is Encapsulation layer in places in direct contact with the first mirror layer.
  • the first encapsulation layer is not an ALD layer.
  • the first encapsulation layer can be produced, for example, by means of a CVD method and comprise, for example, sublayers which have SiC> 2 and / or
  • the SiN sublayers are preferably thinner than the SiC> 2 sublayers.
  • the sublayers may be stacked in a vertical direction parallel to the growth direction of the layer.
  • the first encapsulation layer can be, for example, a first SiC> 2 formed
  • Lower layer having a thickness between 130 nm and 170 nm, in particular of 150 nm.
  • Underlayer which is formed with SiN and has a thickness between 10 nm and 14 nm, in particular of 12 nm.
  • the first encapsulation layer may comprise one or more of these sequences of sub-layers formed with SiC> 2 and SiN.
  • regions covered by the first encapsulation layer can be protected from materials such as those used in the formation of ALD layers, for example in the formation of the second encapsulation layer
  • Encapsulation layer are used.
  • the covered by the first encapsulation layer Semiconductor bodies are protected by the first encapsulation layer from a precursor such as oxygen or ozone, which is used in the production of subsequent encapsulation layers, which are ALD layers.
  • the optoelectronic semiconductor chip comprises a fourth encapsulation layer, which is the third
  • Encapsulation layer is located. At the fourth
  • the encapsulation layer may also be a layer that is not an ALD layer.
  • the fourth encapsulation layer is then deposited not with an ALD method but, for example, with a CVD method.
  • the fourth encapsulation layer may, for example, be formed identically to the first encapsulation layer and also has a protective function of the covered regions in the case of
  • Forming materials used in ALD layers are Forming materials used in ALD layers.
  • the optoelectronic semiconductor chip comprises a fifth encapsulation layer which is an ALD layer, wherein the fifth encapsulation layer covers the outer surface of the semiconductor body at least at the n-conducting region
  • Encapsulation layer is located.
  • the semiconductor body may be exposed to areas without the fifth
  • Encapsulation layer would be uncovered by the fifth
  • Encapsulation be covered and there in direct contact with the fifth encapsulation layer are located.
  • the fifth encapsulation layer may, for example, be constructed identically to the second encapsulation layer. So it can be the same thickness and the same
  • the fifth encapsulation layer is located laterally from the semiconductor body, that is, for example, in a lateral direction to the semiconductor body, in direct contact with the second encapsulation layer.
  • the fifth encapsulation layer and the second encapsulation layer thus have at least one common contact point (hereinafter also:
  • the second encapsulation layer has traces of an etching process in the region of the contact with the fifth encapsulation layer. Especially the fifth
  • Encapsulation layer may be in direct contact, has traces of an etching process.
  • the second encapsulation layer is during the production of the optoelectronic
  • Etching process produces characteristic traces on the second encapsulation layer which is an ALD layer common investigation methods of semiconductor electronics are detectable. These tracks may be
  • the fifth encapsulation layer adheres particularly well to the second encapsulation layer in the regions in which the second encapsulation layer has the traces of the etching process.
  • the second encapsulation layer is in
  • Encapsulation layer consists. The thickness of the second
  • Encapsulation layer for example, by a
  • the second one is
  • Encapsulation layer in the region of contact with the fifth encapsulation layer by between 4 nm and 8 nm, in particular by between 5 nm and 7 nm thinner than in a region in which there is no contact between the second encapsulation layer and the fifth encapsulation layer.
  • the encapsulation layer has no breakdown, but its thickness is only reduced in the region of contact with the fifth encapsulation layer.
  • Encapsulation layer is for example in a
  • Encapsulation layer which is in direct contact with the second encapsulation layer before the etching step, is to be removed.
  • the first encapsulation layer is, for example, a layer containing silicon dioxide.
  • the selectivity in etching between silicon dioxide and the second encapsulant layer, which is an ALD layer, is in the range of 1:80. In this way, the risk that the second encapsulation layer is etched through, is not given.
  • the etching takes place, for example, dry chemical. Due to the fact that in the etching process this does not end, as is often customary, on a metallic layer which may be formed, for example, with platinum, no metals are deposited on the semiconductor body and in particular none by redeposition
  • the optoelectronic semiconductor chip is characterized by a simplified production and improved efficiency. It has been found that the small current behavior of the optoelectronic
  • Encapsulation layer is greatly improved, so that even at very low currents of 1 ⁇ electromagnetic
  • the optoelectronic semiconductor chip comprises a via which extends through the p-conducting semiconductor chip
  • Area of the semiconductor body extends. Apart from the at least one via, the semiconductor body is completely enclosed by the third encapsulation layer and the fifth encapsulation layer. That is, the semiconductor body is down to the area of Through-hole completely enclosed by layers that are ALD layers.
  • the at least one via can comprise at least some of the encapsulation layers, the first mirror layer, the p-type region of the semiconductor body and the active
  • the optoelectronic semiconductor chip Penetrate the area.
  • the optoelectronic semiconductor chip it is possible in particular for the optoelectronic semiconductor chip to comprise a multiplicity of identical plated-through holes.
  • the plated-through hole comprises, for example, a recess in the semiconductor body, which is filled with the n-contact material.
  • the n-contact material is, for example, a metal.
  • the n-contact material is in direct contact with the n-type region and provides an electrically conductive connection, for example, to one
  • connection point of the optoelectronic semiconductor chip which is contacted from outside the semiconductor chip.
  • the first, second, third, and fourth encapsulant layers may directly adjoin the n-type contact material.
  • at least some of the encapsulant layers cover the semiconductor body within the via and thus serve to electrically isolate the n-type contact material from the first mirror layer, the p-type region of the semiconductor body, and the active region.
  • the semiconductor chip comprises a second
  • the second mirror layer can be the same
  • Material may be formed as the first mirror layer.
  • the second mirror layer serves, otherwise
  • the second mirror layer is for example
  • n-contact material arranged below the n-contact material and is in the lateral direction via the via.
  • the second mirror layer may be electrically conductive to the n-contact material
  • Semiconductor body electrically conductively connected and used in addition to their optical properties for current injection into the n-type region of the semiconductor body.
  • At least some of the encapsulation layers may be located at least indirectly between the first mirror layer and the second mirror layer. In this way, for example, the third and fourth encapsulation layers can provide electrical insulation between the first and second encapsulant layers
  • the first mirror layer can then be electrically connected to the p-type region of the semiconductor body.
  • the first mirror layer next to Their optical properties also for electrical connection of the p-type region of the semiconductor body.
  • the second mirror layer projects beyond the second mirror layer
  • At least some of the encapsulation layers may extend on the side of the second mirror layer facing the semiconductor body.
  • the second mirror layer is provided for reflecting electromagnetic radiation generated in the semiconductor body during operation.
  • the second mirror layer projects beyond the semiconductor body in a lateral direction parallel to the semiconductor body
  • Main extension plane of the semiconductor body runs.
  • the second mirror layer is thus laterally over the
  • Mirror layer also electromagnetic radiation that emerges from the side surfaces of the semiconductor body and then extends in the direction of the second mirror layer
  • the region of the second mirror layer which projects beyond the outer surface of the semiconductor body in a lateral direction, does not have to coincide with the region of the second
  • Manufacturing step for example, using a mask technique, are applied.
  • Side surfaces each extend transversely or perpendicular to the lateral directions and represent outer surfaces of the first mirror layer or of the n-conductive region.
  • the third encapsulation layer which is an ALD layer.
  • the further encapsulation layers such as the second encapsulation layer
  • the p-conductive region and the first mirror layer are locally covered by a metallic encapsulation layer at their side surfaces, wherein the at least some of the encapsulation layers at least
  • the region of the semiconductor body protrudes in places into the metallic encapsulation layer which, for example, leads to a carrier of the semiconductor body facing away from the semiconductor body
  • Planarization layer acts.
  • Encapsulation layer can thus, for example, a
  • the metallic encapsulation layer is
  • an encapsulation layer for example, an encapsulation layer
  • the metallic encapsulation layer may be formed of or with metals such as platinum, gold, tungsten and titanium. That is, the metallic encapsulation layer then comprises at least one of these metals or is characterized by a
  • Figures 1A to IQ show process steps for a
  • the figure IQ shows a schematic sectional view of an optoelectronic described here
  • FIG. 1A shows how, first of all, a growth substrate 1, for example of sapphire, is provided, onto which the semiconductor body 10 is epitaxially deposited in particular.
  • the semiconductor body 10 includes the n-type region 2, the p-type region 3, and the active one therebetween
  • the growth substrate 1 is provided for example as a wafer, wherein the dashed lines A, A ', the chip pattern of the manufactured optoelectronic
  • the dashed lines C, C represent the position of a contact region, in which, for example, a bonding pad for contacting the optoelectronic semiconductor chip is formed during the manufacturing process.
  • the semiconductor body 10 is based for example on a nitride compound semiconductor material.
  • Area 4 and the n-type region 2 for example, by etching the epitaxially deposited layers of the semiconductor body 10 to form an outer surface of the
  • step IC a full-area coating of the growth substrate 1 takes place
  • first encapsulation layer 11 which is an electrically insulating layer, for example, a layer which is produced by means of a CVD method.
  • the first encapsulation layer 11 may be referred to as
  • Encapsulation layer sequence may be formed and includes, for example, sub-layers, which are formed with SiC> 2 and SiN.
  • the sublayers are stacked in a vertical direction perpendicular to the lateral direction.
  • the lateral direction is parallel to the plane of the
  • the sublayers formed with SiC> 2 have a thickness between 130 nm and 170 nm, in particular of
  • the sublayers formed with SiN may have a thickness between 10 nm and 14 nm, in particular 12 nm. In particular, this way
  • Encapsulation layers are formed, which are also particularly impermeable to materials used in the production of ALD layers used.
  • the first encapsulation layer 11 completely covers the exposed side surfaces of the p-type region 3 and of the active region 4, so that in particular the p / n junction of the semiconductor body and thus the active region 4 are protected by the first encapsulation layer 11.
  • the upper side of the first side facing away from the growth substrate 1 is used Encapsulation layer 11, a second encapsulation layer 12 applied.
  • the second encapsulation layer 12 is an ALD layer.
  • the second encapsulation layer 12, which is an ALD layer is produced by means of an ALD method, wherein the second encapsulation layer 12 can be deposited at least in places, for example with the use of ozone as a precursor. In this case, it is possible that the entire second encapsulation layer 12 under the
  • the second encapsulation layer 12 has at least two sub-layers, which are arranged stacked, for example, wherein at least one of the sub-layers is produced by means of an ALD method in which ozone is used as precursor.
  • an ALD layer which uses ozone as a precursor has a particularly high
  • the layer or underlayer which is precipitated with ozone as a precursor is, for example, an Al 2 O 3 layer or an SiO 2 layer or a Ta 2 O 5 layer.
  • the second encapsulation layer 12 it is possible for the second encapsulation layer 12 to comprise a lower layer or to consist of a lower layer which is deposited using a precursor that is free of ozone.
  • a precursor that is free of ozone For example, in this case, water or oxygen can be used as a precursor material.
  • the second encapsulation layer 12 also has a further sublayer, which may be formed, for example, using a Precursors is deposited, which comprises ozone, wherein the second sub-layer is deposited directly on the lower layer.
  • the first sub-layer may, for example, have a thickness between 5 and 10 nm.
  • the second sub-layer may then, for example, have a thickness between 25 and 45 nm
  • the second encapsulation layer 12 also covers, at least indirectly, the outer surfaces of the p-type region 3 and of the active region 4 of the semiconductor body.
  • the encapsulation layer and the second encapsulation layer together form an encapsulation layer sequence, which forms on the outer surface of the semiconductor body 10 from the active
  • Area 4 along the p-type region 3 extends.
  • Mirror layer 21 which is formed, for example, with silver, is deposited.
  • a p-terminal layer 31 is applied to the first mirror layer 21 using a further phototechnical technique
  • Optoelectronic semiconductor chip extends, in which later a contact portion 43 for contacting the p-type
  • the p-type terminal layer 31 covers the first one
  • the p-terminal layer 31 may
  • Encapsulation layer 13 is applied to the exposed outer surface of the second encapsulation layer 12, the first mirror layer 21 and the p-type terminal layer 31. In regions, the second encapsulation layer 12 and the third encapsulation layer 13 are locally in direct contact with each other in a region laterally of the first mirror layer 21. In this case is also the third
  • Encapsulation layer 13 an ALD layer, which may be constructed, for example, identical to the second encapsulation layer 12.
  • the third encapsulation layer 13 extends over the entire upper side of the semiconductor body 10 facing away from the growth substrate 1.
  • Encapsulation layer 14 takes place. The fourth
  • encapsulation layer 14 is not an ALD layer and may be formed identically to first encapsulation layer 11.
  • the fourth encapsulation layer 14 completely covers the upper side of the third encapsulation layer 13 facing away from the growth substrate 1 and, for example, conforms it in a conforming manner.
  • Figure II is a
  • Encapsulation layers 11, 12, 13, 14 produced.
  • Through-hole 40 is the n-type region 2 free.
  • Photographic technology use which in the following also when inserting the n-contact material 41 in the
  • the etching process which is necessary for the removal of the encapsulation layers, would be significantly more expensive. That is, by the fact that the two ALD layers, the second encapsulation layer 12 and the third encapsulation layer 13, directly adjoin one another, the via 40 can be particularly
  • n-contact material 41 is introduced in the region B in the through-contacting 40.
  • the n-type contact material 41 is formed by a metal, for example, and may include materials such as titanium and / or gold.
  • the second mirror layer 22 becomes on the underside of the n-contact material 41 facing away from the n-conductive region 2 arranged, with some encapsulation layers
  • Mirror layer 22 are arranged.
  • Encapsulation layer 14 immediately between the first
  • the second mirror layer 22 may locally directly adjoin the fourth encapsulation layer 14.
  • Lateral areas of the second encapsulation layer 22 project beyond the via 40 and the outer surface of the semiconductor body 10, in particular of the p-type region 3, in lateral directions.
  • the metallic encapsulation layer 42 is applied, which overmoulds the topography facing away from the growth substrate 1 and acts as a planarization layer.
  • Encapsulation layer 42 includes, for example, a Pt / Au / Ti layer sequence and serves as a diffusion barrier for material from the second mirror layer 22. Die Metallische
  • Encapsulation layer 42 can be used as a seed layer for a
  • the carrier 50 may in this case
  • the carrier 50 may be formed, for example, of copper. Furthermore, it is possible for the carrier 50 to be formed from silicon or germanium or another semiconductor material. On the side facing away from the growth substrate 1 side of the carrier 50, the back side metallization 51 may be arranged, the one
  • Growth substrate 1 detached and the growth substrate originally facing top of the n-type region 2 is roughened.
  • the detachment of the growth substrate 1 can be effected, for example, by means of a laser lift-off method; the roughening takes place, for example, by means of lithographic etching with KOH.
  • a mesa etching takes place. This etching stops on the first encapsulation layer 11. Subsequently, a hardmask 60, for example, is made
  • Silicon dioxide applied to the n-type region 2.
  • FIG. 10 shows that the hard mask 60 has been removed by dry-chemical etching of the mask layer 60 and the first encapsulation layer 11. The thickness of the
  • Mask layer 60 is the thickness of the first
  • Encapsulation layer 11 is coupled, such that an etch stop on the second encapsulation layer 12 takes place.
  • the etch stop may be accomplished by endpoint detection on, for example, the Al 2 O 3 layer or the Ta 2 O 5 layer of the second encapsulant layer 12.
  • the first encapsulation layer 11 is removed during the etching process. It is important that the etching does not stop on the p-terminal layer 31, that is, for example, not on a platinum layer, but on the second
  • Encapsulation layer 12 with an electric
  • the second encapsulation layer 2 Due to the dry etching step used, the second encapsulation layer 2, due to its lower selectivity compared to
  • Etching on silica hardly attacked and reduced in thickness, for example by between 5 nm and 7 nm.
  • the fact that no metals are attacked during the etching, eliminates a redeposition of detached metals, for example, on the semiconductor body in the region of the active region 4.
  • the small-current behavior is improved and potential aging problems are reduced in terms of small-current behavior.
  • contact points TP form between the second and fifth encapsulation layers, in which these two encapsulation layers are in direct contact with one another.
  • the second encapsulation layer 12 has in the region of the direct contact to the fifth
  • Encapsulation layer 15 has an etched surface and is reduced in thickness there. Subsequently, a sixth encapsulation layer 16, which is formed for example with silicon dioxide or consists of silicon dioxide, as the final passivation of
  • the p-type terminal layer 31 is exposed and a contact region 43 is deposited on the p-type terminal layer 31, which
  • it can be wire-contactable.
  • Optoelectronic semiconductor chip described with the semiconductor body 10 comprising the n-type region 2, the active region 4 provided for generating electromagnetic radiation and the p-type region 3,
  • the first encapsulation layer 11 which with a
  • the first mirror layer 21 is arranged on an underside of the p-type region 3,
  • the active region 4 is arranged on a side of the p-conducting region 3 facing away from the first mirror layer 21,
  • the n-type region 2 is arranged on a side of the active region 4 facing away from the p-type region 3,
  • the second encapsulation layer 12 and the third encapsulation layer 13 are in direct contact locally in a region laterally of the first mirror layer 21
  • Encapsulation layer 13 are ALD layers. The invention is not limited by the description based on the embodiments of these. Rather, the invention encompasses every new feature as well as every combination of features, which in particular includes any combination of features in the patent claims, even if this feature or combination itself is not explicitly described in the claims

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

L'invention concerne une puce semi-conductrice opto-électronique dans laquelle une couche d'encapsulation (13), qui est une couche ALD, recouvre complètement une première couche de réflexion (21), sur son côté opposé à une zone (3) conductrice de type p et se trouve, par endroits, en contact direct avec la première couche de réflexion (21).
PCT/EP2014/063423 2013-07-16 2014-06-25 Puce semi-conductrice opto-électronique WO2015007486A1 (fr)

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DE112014003318.9T DE112014003318A5 (de) 2013-07-16 2014-06-25 Optoelektronischer Halbleiterchip
KR1020167003831A KR102268352B1 (ko) 2013-07-16 2014-06-25 광전 반도체 칩
JP2016526490A JP6284634B2 (ja) 2013-07-16 2014-06-25 オプトエレクトロニクス半導体チップ
CN201480040795.7A CN105393369B (zh) 2013-07-16 2014-06-25 光电子半导体芯片
US14/905,763 US10014444B2 (en) 2013-07-16 2014-06-25 Optoelectronic semiconductor chip

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DE102013107531.2A DE102013107531A1 (de) 2013-07-16 2013-07-16 Optoelektronischer Halbleiterchip

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CN105393369A (zh) 2016-03-09
US10014444B2 (en) 2018-07-03
DE112014003318A5 (de) 2016-05-04
KR20160031011A (ko) 2016-03-21
DE102013107531A1 (de) 2015-01-22
TW201511336A (zh) 2015-03-16
CN105393369B (zh) 2018-01-12
CN107946428B (zh) 2020-10-23
CN107946428A (zh) 2018-04-20
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