WO2015000248A1 - Structure et procédé de collage de puce sur verre - Google Patents

Structure et procédé de collage de puce sur verre Download PDF

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Publication number
WO2015000248A1
WO2015000248A1 PCT/CN2013/087438 CN2013087438W WO2015000248A1 WO 2015000248 A1 WO2015000248 A1 WO 2015000248A1 CN 2013087438 W CN2013087438 W CN 2013087438W WO 2015000248 A1 WO2015000248 A1 WO 2015000248A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
chip
reserved area
absorbing structure
energy
Prior art date
Application number
PCT/CN2013/087438
Other languages
English (en)
Chinese (zh)
Inventor
权宁万
姜太声
李�瑞
Original Assignee
北京京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 北京京东方光电科技有限公司 filed Critical 北京京东方光电科技有限公司
Publication of WO2015000248A1 publication Critical patent/WO2015000248A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Definitions

  • Embodiments of the present invention relate to a bonding method of a chip and a chip bonding structure. Background technique
  • the current small-size liquid crystal display product basically uses a chip bonding process for fixing a chip (Chip On Glass, COG) on a substrate to drive the liquid crystal display panel, for example, forming a bump on the chip. After that, it is directly connected to the lead of the liquid crystal display on the substrate.
  • a chip bonding process for fixing a chip (Chip On Glass, COG) on a substrate to drive the liquid crystal display panel, for example, forming a bump on the chip. After that, it is directly connected to the lead of the liquid crystal display on the substrate.
  • COG Chip On Glass
  • the high temperature indenter first contacts the chip, and the heat is conducted to the anisotropic conductive paste and the substrate through the chip. At this time, the temperature difference between the chip and the substrate is large, causing a difference in the expansion size between the two.
  • the anisotropic conductive paste is cured, the relative position between the chip and the substrate is fixed.
  • the chip and the substrate are cooled down, and the chip shrinks to a larger size than the substrate, so that the opposite ends of the chip generate a larger pair of substrates.
  • the stress causes the chip and substrate to warp.
  • the warpage of the chip and the substrate may cause chip peeling, chip breakage, and display effects such as uneven brightness.
  • Embodiments of the present invention provide a chip bonding method and a chip bonding structure capable of preventing warpage of a chip and a substrate.
  • An aspect of the invention provides a bonding method for a chip, comprising: providing an energy absorbing structure on a substrate, the energy absorbing structure being located beside a reserved area of the substrate, wherein the reserved area is for placing a chip; The chip is bonded within the reserved area on the substrate.
  • the energy absorbing structure may be symmetrically located on both sides of the reserved area.
  • the energy absorbing structure may include a groove or a through hole.
  • the providing an energy absorbing structure on the substrate may include: The substrate is etched, and an energy absorbing structure is disposed on the substrate.
  • the method before the chip is bonded in the reserved area on the substrate, the method further includes: coating an anisotropic conductive paste on the reserved area.
  • a chip bonding structure comprising: a substrate and a chip disposed on the substrate, the two sides of the substrate are provided with an energy absorbing structure, the energy absorbing structure is located outside the reserved area of the substrate, The chip is disposed on the reserved area.
  • the energy absorbing structure may be symmetrically located on both sides of the reserved area.
  • the energy absorbing structure may be a groove or a through hole provided on the substrate.
  • an anisotropic conductive paste is coated on the reserved area, and the chip is disposed on the anisotropic conductive paste, and the chip and the reserved area are set by the anisotropic conductive adhesive.
  • the metal wire is turned on.
  • FIG. 1 is a schematic flow chart of a bonding method of a chip according to an embodiment of the present invention
  • FIG. 2 is a schematic structural view of a substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural view of a substrate in an embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a substrate in an embodiment of the present invention.
  • FIG. 5 is a schematic structural view of a substrate according to an embodiment of the present invention.
  • One embodiment of the present invention provides a bonding method for a chip. As shown in FIG. 1, the bonding method for a chip can be performed as follows.
  • Step S101 An energy absorbing structure is disposed on the substrate, the energy absorbing structure is located beside a reserved area of the substrate, and the reserved area is used for placing a chip.
  • an energy absorbing structure 2 is disposed on the substrate 1.
  • the energy absorbing structure 2 can be placed next to the reserved area 3 reserved for the placement of the chip by the substrate 1, with a predetermined distance d therebetween.
  • the predetermined distance d can be determined as needed.
  • the size of the energy absorbing structure 2 can be determined according to the bonding temperature, the thickness of the substrate 1, and the combined IC size to obtain a better effect.
  • Step S102 Bond the chip in the reserved area on the substrate.
  • the reserved area of the substrate 1 is located on two adjacent edge sides of the substrate 1, and the width of the coated anisotropic conductive paste 5 and the edges of the anisotropic conductive paste 5 and the substrate 1 are different according to the model of the different substrate 1. The distance between them is different. For example, for a rectangular substrate 1 of about 64 inches, the width of the anisotropic conductive paste 5 is 1.0 mm, which is 0.5 mm from the edge of the substrate 1; the thickness of the coated anisotropic conductive paste 5 may be about 0.3 mm to 0.5. Mm.
  • the anisotropic conductive paste 5 mainly comprises two parts of a resin adhesive and conductive particles.
  • the resin adhesive is mainly used to bond the chip 4 on the substrate 1, fix the relative position of the electrode between the chip 4 and the substrate 1, and provide a pressing force to maintain the electrode.
  • Contact area with conductive particles may be metal particles or resin particles whose surface is coated with, for example, carbon.
  • the high temperature indenter 6 first contacts the chip 4, and the heat is transmitted to the anisotropic conductive paste 5 and the substrate through the chip 4. 1.
  • the ductility of the substrate 1 is not as good as that of the chip 4, resulting in a difference in the expansion size between the substrate 1 and the chip 4.
  • the anisotropic conductive paste 5 is cured, the relative position between the chip 4 and the substrate 1 is fixed.
  • the chip 4 and the substrate 1 are cooled down, and the chip 4 is shrunk to a larger size than the substrate 1, so that the chip 4 is Both ends generate a large stress on the substrate 1.
  • the energy absorbing structure 2 on the substrate 1 can absorb the stress generated by the chip 4 on the substrate 1 to prevent the chip 4 and the substrate 1 from warping, thereby preventing the chip 4 from being peeled off, the chip 4 being broken, and the display effect being uneven. The occurrence of adverse consequences.
  • a bonding method of a chip is provided.
  • the energy absorbing structure can absorb the chip on the substrate during the cooling process by providing an energy absorbing structure on the substrate beside the reserved area where the chip is placed.
  • the generated stress causes the chip and the substrate to be flat after the cooling is completed, thereby preventing warpage of the chip and the substrate, thereby preventing the occurrence of adverse effects such as chip peeling, chip breakage, and display unevenness.
  • the stress of the chip 4 on the substrate 1 is located at opposite ends of the chip 4, in order to enable the energy absorbing structure 2 to better absorb the stress of the chip 4 on the substrate 1, preferably, as shown in FIG. 1 or 2.
  • the energy absorbing structure 2 is symmetrically located on both sides of the reserved area 3.
  • the energy absorbing structure 2 can be disposed as a groove in the surface of the substrate 1 on which the chip is disposed, for example, a groove having a trapezoidal cross section, and the cross section of the groove can also be set as a rectangle, a semicircle, or the like.
  • the size, shape, and the like of the groove can be set according to actual conditions.
  • the planar pattern of the energy absorbing structure 2, which is set as a groove for example, may be rectangular or other shapes such as a triangle, an ellipse, a wave, an irregular figure or the like.
  • the energy absorbing structure 2 may also be a through hole or other structure, such as a circular or rectangular through hole, which is not limited in the embodiment of the present invention.
  • the energy absorbing structure 2 is a groove or a through hole
  • a suitable energy absorbing structure 2 can be disposed on the substrate 1 by etching the substrate 1.
  • the energy absorbing structure 2 is a groove formed on the same side of the substrate 1 as the chip 4, or may be formed on the opposite side of the substrate 1 from the chip 4.
  • the substrate 1 may be a glass substrate, a quartz substrate or the like.
  • the embodiment of the present invention further provides a chip bonding structure, comprising a substrate 1 and a chip 4 disposed on the substrate 1.
  • the substrate 1 is provided with an energy absorbing structure 2 on both sides thereof, and the energy absorbing structure 2 is located on the substrate.
  • the chip 4 is disposed on the outside of the reserved area 3.
  • the energy absorbing structure 2 is symmetrically located on both sides of the reserved area 3, for example.
  • the energy absorbing structure 2 is, for example, a groove or a through hole provided on the substrate 1.
  • the anisotropic conductive paste 5 is coated on the reserved area 3, and the chip 4 is disposed on the anisotropic conductive paste 5, and the metal disposed on the chip 4 and the reserved area 3 is passed through the anisotropic conductive adhesive 5. The line is turned on.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

L'invention concerne une structure et un procédé de collage de puce sur verre, le procédé de collage comprenant les étapes suivantes : disposition d'une structure à absorption d'énergie (2) sur un substrat (1), la structure à absorption d'énergie (2) étant placée à proximité d'une zone de réserve (3) du substrat (1), la zone de réserve (3) servant à recevoir une puce sur verre (4) ; et collage de la puce sur verre (4) sur la zone de réserve (3) du substrat (1). Le substrat (1) et la puce sur verre (4) sont disposés sur la structure de collage. La structure à absorption d'énergie (2) est disposée sur deux côtés du substrat (1), et est placée à l'extérieur de la zone de réserve (3) du substrat (1). La zone de réserve (3) est pourvue de la puce sur verre (4).
PCT/CN2013/087438 2013-07-04 2013-11-19 Structure et procédé de collage de puce sur verre WO2015000248A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310279262.1 2013-07-04
CN2013102792621A CN103325702A (zh) 2013-07-04 2013-07-04 芯片的绑定方法及芯片绑定结构

Publications (1)

Publication Number Publication Date
WO2015000248A1 true WO2015000248A1 (fr) 2015-01-08

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WO (1) WO2015000248A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103325702A (zh) * 2013-07-04 2013-09-25 北京京东方光电科技有限公司 芯片的绑定方法及芯片绑定结构
CN105829996B (zh) * 2016-03-23 2019-10-01 深圳信炜科技有限公司 电子设备
CN107369761B (zh) * 2017-08-10 2020-04-14 武汉华星光电技术有限公司 一种柔性显示面板及其基板pi层结构、制备方法
CN110265373B (zh) * 2019-04-29 2021-01-29 京东方科技集团股份有限公司 显示装置及驱动芯片的绑定方法
CN110544655B (zh) * 2019-09-03 2021-09-14 云谷（固安）科技有限公司 绑定装置及绑定方法

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JP2000082868A (ja) * 1998-09-07 2000-03-21 Sony Corp フレキシブルプリント配線板およびフレキシブルプリント回路板とその製造方法
JP2004266016A (ja) * 2003-02-28 2004-09-24 Seiko Epson Corp 半導体装置、半導体装置の製造方法、及び半導体基板
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