WO2014192437A1 - Dispositif à semi-conducteur en carbure de silicium - Google Patents

Dispositif à semi-conducteur en carbure de silicium Download PDF

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WO2014192437A1
WO2014192437A1 PCT/JP2014/060379 JP2014060379W WO2014192437A1 WO 2014192437 A1 WO2014192437 A1 WO 2014192437A1 JP 2014060379 W JP2014060379 W JP 2014060379W WO 2014192437 A1 WO2014192437 A1 WO 2014192437A1
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silicon carbide
guard ring
main surface
semiconductor device
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Japanese (ja)
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増田　健良
和田　圭司
透 日吉
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住友電気工業株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/0485—Ohmic electrodes
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts

Definitions

  • the present invention relates to a silicon carbide semiconductor device, and more particularly to a silicon carbide semiconductor device having a termination region.
  • silicon carbide has been increasingly adopted as a material for semiconductor devices in order to enable the use of high-voltage, low-loss and high-temperature environments in semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). It is being Silicon carbide is a wide band gap semiconductor having a larger band gap than silicon that has been widely used as a material for forming semiconductor devices. Therefore, by adopting silicon carbide as a material constituting the semiconductor device, it is possible to achieve a high breakdown voltage and a low on-resistance of the semiconductor device. In addition, a semiconductor device that employs silicon carbide as a material has an advantage that a decrease in characteristics when used in a high temperature environment is small as compared with a semiconductor device that employs silicon as a material.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2003-101039
  • a guard ring layer having a high concentration of impurities is formed inside the RESURF layer, and a guard ring layer having an impurity concentration similar to that of the RESURF layer is formed outside the RESURF layer.
  • a formed high voltage silicon carbide semiconductor device is described. Accordingly, it is said that the breakdown voltage can be prevented from deteriorating even if there is a variation in impurity concentration or a variation in dimensions due to mask displacement.
  • the present invention has been made in view of the above problems, and an object thereof is to provide a silicon carbide semiconductor device capable of reducing variations in breakdown voltage.
  • the silicon carbide semiconductor device includes a silicon carbide layer and an insulating layer.
  • the silicon carbide layer has a first main surface and a second main surface opposite to the first main surface, and surrounds the element region in plan view and an element region provided with a semiconductor element portion And a termination region.
  • the insulating layer is in contact with the first main surface of the silicon carbide layer.
  • the termination region includes a guard ring region having a first conductivity type, and a second conductivity type region located between the first main surface and the guard ring region and having a conductivity type different from the guard ring region. .
  • 1 is a schematic cross-sectional view schematically showing a structure of a silicon carbide semiconductor device according to one embodiment of the present invention.
  • 1 is a schematic plan view schematically showing structures of a guard ring region and a JTE (Junction Termination Extension) region of a silicon carbide semiconductor device according to a first embodiment of the present invention. It is a figure which shows the relationship between the impurity region in a guard ring region, and the position of a Y direction. It is a figure for demonstrating the position of the Y direction in FIG. It is a cross-sectional schematic diagram which shows schematically the 1st process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention.
  • the guard ring region is formed by introducing an acceptor impurity such as aluminum into the main surface of the silicon carbide layer by ion implantation. It is formed.
  • ion implantation is usually performed by multistage implantation in which the ion implantation depth is changed.
  • the dose amount of the guard ring region varies due to, for example, variations in ion implantation depth.
  • the main surface of the silicon carbide layer is thermally oxidized, the position of the interface between the thermal oxide film (insulating layer) and the silicon carbide layer along the direction perpendicular to the main surface varies due to variations in the amount of thermal oxidation, for example. Therefore, the dose amount in the guard ring region fluctuated, and the breakdown voltage of the silicon carbide semiconductor device varied.
  • the inventors have provided a guard ring region separated from the main surface of the silicon carbide layer, and provided a region of a conductivity type different from the guard ring region between the guard ring region and the silicon carbide layer.
  • the variation in the dose amount of the guard ring region can be reduced.
  • the guard ring region away from the main surface of the silicon carbide layer, even when the ion implantation depth varies somewhat, it is possible to suppress variation in the total dose of the guard ring region.
  • the main surface of the silicon carbide layer is thermally oxidized to form a thermal oxide film, a part of the main surface is oxidized to become a thermal oxide film made of silicon dioxide.
  • the guard ring region When the guard ring region is provided apart from the main surface, it can be suppressed that a part of the guard ring region is oxidized to become a thermal oxide film made of silicon dioxide. Therefore, fluctuations in the total dose amount in the guard ring region can be suppressed. As a result, for example, even when the position of the interface between the thermal oxide film (insulating layer) and the silicon carbide layer along the direction perpendicular to the main surface varies due to the difference in thermal oxidation amount, the dose amount of the guard ring region is reduced. Fluctuation can be suppressed. In other words, by increasing the robustness of the breakdown voltage against the fluctuation of the interface position, it is possible to reduce the variation in breakdown voltage of the silicon carbide semiconductor device.
  • the p-type silicon carbide thermal oxide film tends to be thinner than the adjacent n-type silicon carbide thermal oxide film. Therefore, thermal oxidation is more effective when p-type silicon carbide is formed inside and only n-type silicon carbide is exposed on the main surface than when p-type and n-type silicon carbide are exposed on the main surface. The difference in film thickness is reduced. Thereby, the electric field distribution on the main surface is made uniform, so that the effect of suppressing breakdown due to electric field concentration is great when a high voltage of 600 V or higher (more preferably 1200 V or higher) is applied. This is the same when the p-type and the n-type are inverted.
  • the silicon carbide semiconductor device includes a silicon carbide layer 10 and an insulating layer 15.
  • Silicon carbide layer 10 has a first main surface 10a, a second main surface 10b opposite to first main surface 10a, and an element region IR provided with semiconductor element portion 7 and a plane.
  • the terminal region OR that surrounds the element region in view.
  • Insulating layer 15 is in contact with first main surface 10a of silicon carbide layer 10.
  • Termination region OR is guard ring region 3 having the first conductivity type, and second conductivity having a conductivity type that is located between first main surface 10a and guard ring region 3 and that is different from guard ring region 3. And a mold region 12c.
  • termination region OR is positioned between guard ring region 3 having the first conductivity type, first main surface 10a and guard ring region 3, and guard region OR.
  • Ring region 3 includes a second conductivity type region 12c having a different conductivity type.
  • the dose amount of second conductivity type region 12 c is smaller than the dose amount of guard ring region 3.
  • the dose amount of the second conductivity type region 12c is a donor dose amount
  • the dose amount of the guard ring region 3 is an acceptor dose amount.
  • the second conductivity type region 12c has a p-type conductivity type
  • the dose amount of the second conductivity type region 12c is the dose amount of the acceptor
  • the dose amount of the guard ring region 3 is the dose amount of the donor.
  • the second conductivity type region 12c can be sufficiently depleted. Therefore, it is possible to prevent the high electric field from being concentrated on the semiconductor element portion and the semiconductor element portion from being destroyed.
  • the distance from the peak position of the impurity concentration of guard ring region 3 along the normal direction of first main surface 10a to first main surface 10a. Is 0.1 ⁇ m or more and 1.0 ⁇ m or less. If the distance is 0.1 ⁇ m or more, since the distance is larger than the thickness of the insulating layer 15, a part of the guard ring region 3 is oxidized and becomes the insulating layer 15 due to variations in the thickness of the insulating layer 15. Can be suppressed. Therefore, fluctuations in the dose amount of the guard ring region 3 can be suppressed. If the distance is 1.0 ⁇ m or less, the guard ring region 3 can be efficiently formed by ion implantation.
  • the dose amount of guard ring region 3 is preferably 1 ⁇ 10 13 cm ⁇ 2 or more. Thereby, the breakdown voltage of the silicon carbide semiconductor device can be improved.
  • the dose amount of guard ring region 3 is larger than the fixed charge density at the interface between silicon carbide layer 10 and insulating layer 15. Thereby, the dispersion
  • the first conductivity type is a p-type and the second conductivity type region is an n-type region.
  • MOSFET 1 as a silicon carbide semiconductor device according to an embodiment of the present invention.
  • MOSFET 1 includes a silicon carbide layer 10, an insulating layer 15, a gate electrode 27, a source electrode 16, a drain electrode 20, an interlayer insulating film 71, and a pad electrode. 65 and the back surface protective electrode 50 are mainly included.
  • silicon carbide layer 10 of MOSFET 1 includes an element region IR (active region) and a termination region OR (invalid region) provided outside element region IR.
  • Termination region OR includes a guard ring region 3 and a JTE region 2 as electric field relaxation regions.
  • a MOSFET part as the semiconductor element part 7 is provided in the element region IR.
  • the semiconductor element portion 7 includes a drift region 12a having an n type (second conductivity type).
  • Silicon carbide layer 10 is made of, for example, polytype 4H hexagonal silicon carbide, and has a first main surface 10a and a second main surface 10b opposite to first main surface 10a.
  • the termination region OR surrounds the element region IR in a plan view (a visual field viewed from the normal direction of the first main surface 10a).
  • the JTE region 2 is disposed so as to surround the element region IR in plan view.
  • the guard ring region 3 is disposed outside the JTE region 2 in plan view and is disposed so as to surround the JTE region 2.
  • the guard ring region 3 is provided apart from the JTE region 2.
  • the guard ring region 3 may have a plurality of guard ring portions 3a to 3i. Each of the plurality of guard ring portions 3a to 3i has an annular shape and is disposed with a gap therebetween.
  • the width W1 of the JTE region 2 is, for example, 15 ⁇ m, and the widths W2 to W10 of the nine guard ring portions 3a to 3i are, for example, 5 ⁇ m.
  • An interval d1 between the JTE region 2 and the guard ring region 3 is, for example, about 3 ⁇ m to about 5 ⁇ m, and an interval d2 between the adjacent guard ring portions 3a to 3i is, for example, about 3 ⁇ m to about 5 ⁇ m.
  • Termination region OR may have an n-type field stop region (not shown) on the outer peripheral side of guard ring region 3.
  • Each of JTE region 2 and guard ring region 3 has a p-type (first conductivity type).
  • the impurity concentration contained in each of JTE region 2 and guard ring region 3 is lower than the impurity concentration of body region 13.
  • Each dose amount of JTE region 2 and guard ring region 3 is, for example, 1 ⁇ 10 13 cm ⁇ 2 or more.
  • the width W1 of the JTE region 2 is, for example, about 15 ⁇ m to 55 ⁇ m, and the dimension of the JTE region 2 along the normal direction of the first main surface 10a is, for example, about 0.5 ⁇ m to 0.8 ⁇ m.
  • the guard ring region 3 may be grounded.
  • guard ring region 3 is provided apart from first main surface 10 a of silicon carbide layer 10.
  • An n-type region 12c having an n-type is arranged between first main surface 10a and guard ring region 3.
  • An n-type region 12c is arranged on the first main surface 10a side of the guard ring region 3, and an n-type region 12a is arranged on the second main surface 10b side.
  • the guard ring region 3 is provided between the n-type region 12c and the n-type region 12a along the normal direction of the first main surface 10a, and in a direction parallel to the first main surface 10a.
  • the impurity concentration of each of n-type region 12c and n-type region 12a is, for example, about 7.5 ⁇ 10 15 cm ⁇ 3 .
  • each of the plurality of guard ring portions 3a to 3i is provided apart from the first main surface 10a, and between the first main surface 10a and each of the guard ring portions 3a to 3i.
  • N-type region 12c is arranged.
  • the dose amount of the n-type region 12c is smaller than the dose amount of the guard ring region 3.
  • the guard ring region 3 has a plurality of guard ring portions 3a to 3i, the dose amount of the n-type region 12c facing each of the guard ring portions 3a to 3i of the guard ring region 3 is equal to that of the guard ring portions 3a to 3i. Less than each dose.
  • the dose amount of guard ring region 3 is determined so that n type region 12c sandwiched between guard ring region 3 and first main surface 10a can be depleted.
  • the dose amount of the guard ring region 3 is, for example, about 1 ⁇ 10 13 cm ⁇ 2 .
  • the dose amount of n-type region 12c is, for example, about 1 ⁇ 10 11 cm ⁇ 2 or more and 1 ⁇ 10 12 cm ⁇ 2 or less.
  • the Y direction is a normal direction of first main surface 10 a of silicon carbide layer 10.
  • the first main surface 10a is defined as position 0, and the direction from the first main surface 10a to the second main surface 10b is positive.
  • the impurity concentration in FIG. 3 indicates an acceptor concentration when the guard ring region 3 has a p-type, and indicates a donor concentration when the guard ring region 3 has an n-type.
  • the dose amount corresponds to the amount obtained by integrating the impurity concentration at the position in the Y direction (that is, the area of the region indicated by the oblique lines in FIG. 3).
  • the dose amount of the guard ring region 3 is 1 ⁇ 10 13 cm ⁇ 2 or more.
  • the dose amount of each of the plurality of guard ring portions 3a to 3i is 1 ⁇ 10 13 cm ⁇ 2 or more.
  • the dose amount of guard ring region 3 is larger than the fixed charge density at the interface between silicon carbide layer 10 and insulating layer 15.
  • the fixed charges at the interface include ions that are present from the beginning and those in which holes or electrons are trapped at the interface state.
  • the fixed charge is generated by, for example, nitrogen or hydrogen introduced into the insulating layer 15.
  • the interface state density is, for example, about 1 ⁇ 10 11 cm ⁇ 2 .
  • the implantation dose amount in the guard ring region 3 is 100 times or more the interface state density.
  • the fixed charge density is, for example, about 1 ⁇ 10 12 cm ⁇ 2 .
  • the fixed charge density can be measured by, for example, a high-frequency CV (Capacitance-Voltage) method.
  • the concentration of impurities contained in the guard ring region increases as the distance from the first main surface 10a increases, and the impurity concentration peaks between position P1 and position P2.
  • the impurity concentration decreases.
  • the distance from the first main surface 10a to the position P1 where the impurity concentration becomes the first peak is, for example, 0.1 ⁇ m
  • the distance from the first main surface 10a to the position P2 where the impurity concentration becomes the last peak is, for example, 1.0 ⁇ m.
  • the distance from the position in the Y direction showing the peak of the impurity concentration to the first main surface 10a is preferably about 0.1 ⁇ m or more and 1.0 ⁇ m or less.
  • semiconductor element portion 7 in element region IR of silicon carbide layer 10 mainly includes n + substrate 11, drift region 12 a, body region 13, source region 14, and p + region 18. Have.
  • N + substrate 11 is made of, for example, polytype 4H hexagonal silicon carbide and has a conductivity type of n type.
  • N + substrate 11 contains an impurity (donor) such as N (nitrogen) at a high concentration.
  • the concentration of impurities such as nitrogen contained in the n + substrate 11 is, for example, about 1.0 ⁇ 10 18 cm ⁇ 3 .
  • Drift region 12a is an epitaxial layer made of, for example, polytype 4H hexagonal silicon carbide and having n-type.
  • the impurity contained in drift region 12a is, for example, nitrogen.
  • the impurity concentration in drift region 12 a is lower than the impurity concentration in n + substrate 11.
  • the concentration of impurities such as nitrogen contained in drift region 12a is, for example, about 7.5 ⁇ 10 15 cm ⁇ 3 .
  • the thickness T of the drift region 12a is not less than about 10 ⁇ m and not more than about 35 ⁇ m.
  • the body region 13 is a region having a p-type different from the n-type.
  • Impurities (acceptors) contained in body region 13 are, for example, Al (aluminum), B (boron), and the like.
  • the concentration of impurities such as aluminum contained in the surface of body region 13 is about 1 ⁇ 10 16 cm ⁇ 3 or more and about 5 ⁇ 10 17 cm ⁇ 3 or less.
  • the impurity concentration in the deep part of the body region 13 is about 1 ⁇ 10 18 cm ⁇ 3 .
  • the thickness of body region 13 is not less than about 0.5 ⁇ m and not more than about 1.0 ⁇ m, for example.
  • the body region 13 and the JTE region 2 are in contact with each other at the boundary line 2a between the element region IR and the termination region OR.
  • the source region 14 is an n-type region. Source region 14 is separated by body region 13 and from drift region 12a.
  • the source region 14 includes the first main surface 10 a and is formed inside the body region 13 so as to be surrounded by the body region 13.
  • Source region 14 contains, for example, an impurity such as P (phosphorus) at a concentration of about 1 ⁇ 10 20 cm ⁇ 3 .
  • the concentration of the impurity contained in the source region 14 is higher than the concentration of the impurity contained in the drift region 12a.
  • the p + region 18 is a region having a p-type. P + region 18 is formed in contact with body region 13 and source region 14.
  • the p + region 18 contains impurities such as aluminum and boron at a concentration of about 1 ⁇ 10 20 cm ⁇ 3 , for example.
  • the concentration of impurities contained in p + region 18 is higher than the concentration of impurities contained in body region 13.
  • insulating layer 15 is exposed at gate insulating film portion 15 a provided at a position facing channel region CH formed in body region 13, end portion 10 c of silicon carbide layer 10, and JTE And an insulating film portion 15b in contact with the region 2.
  • Gate insulating film portion 15 a is formed in contact with body region 13, source region 14, and drift region 12 a so as to extend from the upper surface of one source region 14 to the upper surface of the other source region 14. .
  • Insulating layer 15 is made of, for example, silicon dioxide.
  • the thickness of the insulating layer 15 (the dimension of the insulating layer 15 along the normal direction of the first main surface 10a) is, for example, about 50 nm.
  • Gate electrode 27 faces drift region 12a, source region, and body region 13 so as to extend from one source region 14 to the other source region 14, and is in contact with gate insulating film portion 15a. Has been placed.
  • the gate electrode 27 is made of a conductor such as polysilicon doped with impurities, aluminum, or the like.
  • Source electrode 16 is in contact with gate insulating film portion 15 a, source region 14, and p + region 18.
  • the source electrode 16 is preferably made of a material having nickel and silicon.
  • the source electrode 16 may be made of a material having titanium, aluminum, and silicon.
  • source electrode 16 is in ohmic contact with source region 14 and p + region 18.
  • Drain electrode 20 is formed in contact with second main surface 10b of silicon carbide layer 10.
  • the drain electrode 20 may have a configuration similar to that of the source electrode 16, for example, or may be made of another material capable of ohmic contact with the n + substrate 11 such as nickel. Thereby, the drain electrode 20 is electrically connected to the n + substrate 11.
  • the pad electrode 65 is formed so as to be in contact with the source electrode 16 and cover the interlayer insulating film 71.
  • the pad electrode 65 is made of aluminum, for example.
  • protective film 70 is formed in contact with pad electrode 65 and insulating film portion 15b.
  • drain electrode 20 is arranged in contact with second main surface 10b of silicon carbide layer 10.
  • a back surface protective electrode 50 made of, for example, titanium, nickel, silver or an alloy thereof is disposed in contact with the drain electrode 20.
  • MOSFET 1 In a state where a voltage equal to or lower than the threshold value is applied to the gate electrode 27, that is, in an off state, the body region 13 located immediately below the gate insulating film portion 15a and the drift region 12a are reverse-biased and become non-conductive.
  • a positive voltage is applied to the gate electrode 27, an inversion layer is formed in the channel region CH in the vicinity of the body region 13 in contact with the gate insulating film portion 15a.
  • the source region 14 and the drift region 12 a are electrically connected, and a current flows between the source electrode 16 and the drain electrode 20.
  • silicon carbide layer 10 is prepared by a substrate preparation process. Specifically, n-type region 12 is formed by epitaxial growth on one main surface of n + substrate 11 made of hexagonal silicon carbide having polytype 4H. Epitaxial growth can be carried out, for example, using a mixed gas of SiH 4 (silane) and C 3 H 8 (propane) as a raw material gas. At this time, for example, N (nitrogen) is introduced as an impurity. As a result, an n-type region 12 containing impurities having a lower concentration than the impurities contained in the n + substrate 11 is formed. Thus, silicon carbide layer 10 including n + substrate 11 and n-type region 12 and having first main surface 10a and second main surface 10b is formed.
  • an oxide film made of silicon dioxide is formed on first main surface 10a of silicon carbide layer 10 by, for example, CVD. Then, after a resist is applied on the oxide film, exposure and development are performed, and a resist film having an opening in a region corresponding to the shape of the desired body region 13 is formed. Then, using the resist film as a mask, the oxide film is partially removed by, for example, RIE (Reactive Ion Etching) to form an oxide film having an opening pattern on the n-type region 12. A mask layer is formed.
  • RIE reactive Ion Etching
  • an ion implantation process is performed.
  • ions are implanted into first main surface 10 a of silicon carbide layer 10, so that body region 13, source region 14, and element region IR are formed in silicon carbide layer 10.
  • P + region 18 is formed, and JTE region 2 and guard ring region 3 as an electric field relaxation region are formed in termination region OR of silicon carbide layer 10.
  • the guard ring region 3 has a plurality of guard ring portions 3a to 3i, and each of the plurality of guard ring portions 3a to 3i is formed so as to be separated from the first main surface 10a.
  • the body region 13 is formed by removing the resist film and ion-implanting impurities such as Al into the n-type region 12 using the mask layer as a mask. Further, an n-type impurity such as P (phosphorus) is introduced into the n-type region 12 by ion implantation, whereby the source region 14 is formed. Next, impurities such as Al and B are introduced into the n-type region 12 by ion implantation, whereby the p + region 18 is formed. Ion implantation may be performed by heating silicon carbide layer 10 to 300 ° C. to 500 ° C.
  • the JTE region 2 and the guard ring region 3 are formed.
  • the guard ring region 3 may be formed deeper than the JTE region 2.
  • JTE region 2 is formed in contact with body region 13.
  • the implantation dose amount of the guard ring region 3 is 1 ⁇ 10 13 cm ⁇ 2 or more.
  • the guard ring region 3 has a distance from the peak position of the impurity concentration of the guard ring region 3 along the normal direction of the first main surface 10a to the first main surface 10a of 0.1 ⁇ m or more. It is formed to be 0 ⁇ m or less.
  • an activation annealing step is performed.
  • a heat treatment for activating the impurities introduced by the ion implantation is performed. Specifically, silicon carbide layer 10 subjected to ion implantation is heated to, for example, about 1700 ° C. in an Ar (argon) atmosphere and held for about 30 minutes.
  • Ar argon
  • first main surface 10a of silicon carbide layer 10 in which the ion implantation region is formed is thermally oxidized.
  • Thermal oxidation can be carried out, for example, by heating to about 1300 ° C. in an oxygen atmosphere and holding for about 40 minutes.
  • insulating layer 15 made of silicon dioxide is formed in contact with first main surface 10a of silicon carbide layer 10.
  • Silicon carbide layer 10 on which insulating layer 15 is formed may be heated from 1100 ° C. to 1300 ° C. in an atmosphere containing nitrogen, NO, or N 2 O.
  • gate electrode 27 made of, for example, polysilicon or aluminum as a conductor extends from one source region 14 to the other source region 14 and is insulated. It is formed in contact with the layer 15.
  • the polysilicon may contain phosphorus at a high concentration exceeding 1 ⁇ 10 20 cm ⁇ 3 .
  • an interlayer insulating film 71 made of, for example, silicon dioxide is formed so as to cover gate electrode 27.
  • source electrode 16 made of a material containing, for example, nickel and silicon is formed in contact with source region 14 and p + region 18.
  • the source electrode 16 may be a material containing titanium, aluminum, and silicon.
  • silicon carbide layer 10 on which source electrode 16 is formed is heated to about 1000 ° C., source electrode 16 is silicided, and source electrode 16 in ohmic contact with source region 14 and p + region 18 of silicon carbide layer 10 is formed. It is formed.
  • drain electrode 20 is formed in ohmic contact with second main surface 10b of silicon carbide layer 10.
  • the material forming the drain electrode 20 may be a material containing nickel and silicon, or may be a material containing titanium, aluminum and silicon.
  • a pad electrode 65 made of, for example, aluminum is formed in contact with the source electrode 16.
  • the back surface protective electrode 50 containing, for example, titanium, nickel, and silver is formed. As described above, MOSFET 1 shown in FIGS. 1 and 8 is completed.
  • the MOSFET is described as an example of the silicon carbide semiconductor device.
  • the silicon carbide semiconductor device may be a diode such as a Schottky barrier diode, or an IGBT (Insulated Gate Bipolar). (Transistor) or the like.
  • the MOSFET may be a planar type MOSFET or a trench type MOSFET.
  • the silicon carbide semiconductor device may be a vertical semiconductor device.
  • the first conductivity type is p-type and the second conductivity type is n-type.
  • the first conductivity type is n-type and the second conductivity type is p-type. It may be a mold.
  • termination region OR is located between guard ring region 3 having the first conductivity type, first main surface 10a and guard ring region 3, and guard ring region. 3 includes an n-type region 12c having a different conductivity type. Thereby, the dispersion
  • the dose amount of n-type region 12 c is smaller than the dose amount of guard ring region 3.
  • the second conductivity type region 12c can be sufficiently depleted. Therefore, it is possible to suppress the high electric field from being concentrated on the semiconductor element portion and the semiconductor element portion from being destroyed.
  • the distance from the peak position of the impurity concentration of guard ring region 3 along the normal direction of first main surface 10a to first main surface 10a is 0.1 ⁇ m. It is 1.0 ⁇ m or less. If the distance is 0.1 ⁇ m or more, since the distance is larger than the thickness of the insulating layer 15, a part of the guard ring region 3 is oxidized and becomes the insulating layer 15 due to variations in the thickness of the insulating layer 15. Can be suppressed. Therefore, fluctuations in the dose amount of the guard ring region 3 can be suppressed. If the distance is 1.0 ⁇ m or less, the guard ring region 3 can be efficiently formed by ion implantation.
  • the dose amount of guard ring region 3 is 1 ⁇ 10 13 cm ⁇ 2 or more. Therefore, the breakdown voltage of MOSFET 1 can be improved.
  • the dose amount of guard ring region 3 is larger than the fixed charge density at the interface between silicon carbide layer 10 and insulating layer 15. Thereby, the dispersion
  • the first conductivity type is p-type
  • the second conductivity type region is an n-type region.
  • SYMBOLS 1 MOSFET silicon carbide semiconductor device

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Abstract

L'invention concerne un dispositif à semi-conducteur en carbure de silicium (1) pourvu d'une couche de carbure de silicium (10) et d'une couche isolante (15). La couche de carbure de silicium (10) présente une première surface principale (10a) et une seconde surface principale (10b) sur le côté opposé de la première surface principale (10a), et est composée d'une zone d'élément (IR) pourvue d'une section d'élément à semi-conducteur (7), et d'une zone de terminaison (OR) entourant la zone d'élément (IR) dans une vue en plan. La couche isolante (15) est en contact avec la première surface principale (10a) de la couche de carbure de silicium (10). La zone de terminaison (OR) comprend une zone de grille de protection (3) présentant un premier type de conductivité, et une zone présentant un second type de conductivité (12c) positionnée entre la première surface principale (10a) et la zone de grille de protection (3), et présentant un type de conductivité différent de celui de la zone de grille de protection (3). Ainsi, un dispositif à semi-conducteur en carbure de silicium (1) permet de réduire les variations d'une tension de claquage.
PCT/JP2014/060379 2013-05-30 2014-04-10 Dispositif à semi-conducteur en carbure de silicium WO2014192437A1 (fr)

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CN109417088A (zh) * 2016-07-05 2019-03-01 株式会社电装 碳化硅半导体装置及其制造方法

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JP2022168904A (ja) 2021-04-27 2022-11-09 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
JP2024060452A (ja) * 2022-10-19 2024-05-02 株式会社デンソー 半導体装置とその製造方法

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JP2008010506A (ja) * 2006-06-27 2008-01-17 Matsushita Electric Ind Co Ltd 半導体装置
JP4189415B2 (ja) * 2006-06-30 2008-12-03 株式会社東芝 半導体装置
EP2244297B1 (fr) * 2008-02-12 2015-07-01 Mitsubishi Electric Corporation Dispositif à semi-conducteur de carbure de silicium
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JP2011181805A (ja) * 2010-03-03 2011-09-15 Toshiba Corp 半導体装置

Cited By (4)

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Publication number Priority date Publication date Assignee Title
CN109417088A (zh) * 2016-07-05 2019-03-01 株式会社电装 碳化硅半导体装置及其制造方法
CN109417088B (zh) * 2016-07-05 2021-09-14 株式会社电装 碳化硅半导体装置及其制造方法
WO2018016165A1 (fr) * 2016-07-20 2018-01-25 三菱電機株式会社 Dispositif à semi-conducteur à base de carbure de silicium et procédé permettant de fabriquer ce dernier
JPWO2018016165A1 (ja) * 2016-07-20 2018-11-22 三菱電機株式会社 炭化珪素半導体装置およびその製造方法

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