WO2014153870A1 - 阵列基板、显示装置及制作方法 - Google Patents
阵列基板、显示装置及制作方法 Download PDFInfo
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- WO2014153870A1 WO2014153870A1 PCT/CN2013/077591 CN2013077591W WO2014153870A1 WO 2014153870 A1 WO2014153870 A1 WO 2014153870A1 CN 2013077591 W CN2013077591 W CN 2013077591W WO 2014153870 A1 WO2014153870 A1 WO 2014153870A1
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 5
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- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims description 4
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- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910001257 Nb alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
- H01L21/441—Deposition of conductive or insulating materials for electrodes
- H01L21/443—Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/4763—Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
- H01L21/47635—After-treatment of these layers
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
Definitions
- Embodiments of the present invention relate to an array substrate, a display device, and a method of fabricating the same. Background technique
- OLED Organic Light-Emitting Diode
- the storage capacitor in the OLED driving circuit in the prior art is formed by an opaque metal electrode and a pixel electrode. Therefore, the opaque metal electrode directly affects the aperture ratio. Moreover, the current intensity required for the display device to emit light is increased, and the service life of the display device is shortened. Summary of the invention
- Embodiments of the present invention provide an array substrate, a display device, and a manufacturing method thereof, wherein a first electrode plate of a storage capacitor is formed by a second region of a transparent oxide active layer to increase an aperture ratio of the array substrate.
- An embodiment of the present invention provides an array substrate, including: a thin film transistor and a pixel electrode, wherein an active layer of the thin film transistor is formed by a first region of an oxide semiconductor layer, and the oxide semiconductor layer further includes a second region, the pixel electrode overlaps with a second region of the oxide semiconductor layer to form a storage capacitor, and a second region of the oxide semiconductor layer constitutes a first electrode plate of the storage capacitor, the oxide and the oxide a pixel electrode corresponding to the second region of the semiconductor layer constitutes a second electrode plate of the storage capacitor, and
- a dielectric layer is disposed between the first electrode plate and the second electrode plate.
- the first electrode plate is formed by performing a hydrogen plasma process on a second region of the oxide semiconductor.
- the first electrode plate has a resistivity of less than 5 ⁇ 1 ( ⁇ 3 ⁇ ⁇ cm. In one example, the resistivity of the second region of the oxide semiconductor layer is less than the resistivity of the first region of the oxide semiconductor layer.
- the first region of the oxide semiconductor layer and the second region of the oxide semiconductor layer are isolated from each other.
- the dielectric layer between the first electrode plate and the second electrode plate includes a passivation layer and/or an etch stop layer.
- the material of the oxide semiconductor layer is indium gallium oxide, indium oxide, indium tin oxide or indium gallium tin oxide.
- the etch stop layer and the passivation layer are each one of an oxide of silicon, a nitride of silicon, an oxide of cerium, an oxynitride of silicon, or an oxide of aluminum, or A variety of transparent single or composite layer structures are formed.
- the dielectric layer between the first electrode plate and the second electrode plate includes an etch stop layer and a gate insulating layer.
- Another embodiment of the present invention provides a display device comprising an array substrate according to any of the embodiments of the present invention.
- Still another embodiment of the present invention provides a method of fabricating an array substrate, comprising: forming an oxide semiconductor layer, forming a pixel electrode pattern, and forming a dielectric layer between the oxide semiconductor layer and the pixel electrode pattern, wherein formation
- the oxide semiconductor layer includes:
- the second region of the oxide semiconductor layer constitutes a first electrode plate of the storage capacitor
- the pixel electrode corresponding to the second region of the oxide active layer constitutes a second electrode plate of the storage capacitor, the first electrode plate and
- the dielectric layer between the second electrode plates constitutes a dielectric for the storage capacitor.
- the second region of the oxide semiconductor layer is subjected to a hydrogen plasma process to form a pattern including the first electrode plate, the first electrode plate having a resistivity of less than 5> ⁇ 10" 3 ⁇ ⁇ cm .
- the hydrogen plasma treatment process has a processing time of 150 s, a processing power of 800 to 2000 W, and a hydrogen plasma flow rate of 80 SCCM.
- the dielectric layer includes an etch stop layer and/or a passivation layer.
- the array substrate, the display device and the manufacturing method of the present invention provide a first electrode plate of a storage capacitor by using a transparent oxide material, so that the formed storage capacitor structure has light transmissivity, thereby increasing the aperture ratio of the array substrate and reducing the display device.
- the current intensity required for illumination extends the life of the display device.
- 1 is a driving circuit diagram of an AMOLED array substrate
- FIG. 2 is a schematic view showing the layout of an array substrate according to an embodiment of the present invention.
- FIG. 3 is a schematic cross-sectional view of the interlayer of the array substrate A-A of FIG. 2;
- FIG. 4 is a second schematic cross-sectional view of an embodiment of the present invention.
- FIG. 5 is a schematic view showing a second region of a photoresist-treated oxide active layer coated with a photoresist according to an embodiment of the present invention. detailed description
- Embodiments of the present invention provide an array substrate, a display device, and a manufacturing method thereof, wherein a first electrode plate of a storage capacitor is formed through a second region of a transparent oxide active layer to increase an aperture ratio of the array substrate.
- FIG. 1 is a driving circuit diagram of a pixel structure of an AMOLED, the pixel unit circuit structure including two thin film transistors and a capacitor.
- the gate line is electrically connected to the gate electrode of the first thin film transistor
- the data line is electrically connected to the drain electrode of the first thin film transistor.
- the electrical signal provided by the gate line causes the first thin film transistor to be in an on/off state; when the first thin film transistor is turned on, the electrical signal provided by the data line causes the second thin film transistor to be in an on/off state; when the second thin film When the transistor is turned on, the signal input from the power line drives the AMOLED to emit light through the second thin film transistor.
- FIG. 2 is a schematic plan view of a pixel unit of an array substrate according to an embodiment of the present invention
- FIG. 3 is a cross-sectional view taken along line A-A of FIG. Figure 3 is a cross-sectional view showing a thin film transistor of the present invention, reflecting the structure of a thin film transistor.
- the main structure of the thin film transistor of the present embodiment includes a gate electrode 2 formed on the substrate 1, a gate insulating layer 3, an oxide active layer, an etch barrier layer 5, a source electrode 6, a drain electrode 7, a passivation layer 8, and a pixel.
- the thin film transistor includes, in particular, an oxide active layer first region 401 and an oxide active layer second region 402.
- the oxide active layer first region 401 and the oxide active layer second region 402 are formed in the same patterning process.
- the above pattern may not be formed in the same patterning process as needed.
- a portion of the pixel electrode 9 corresponding to the oxide active layer second region 402 forms a storage capacitor, and the oxide active layer second region 402 constitutes a first electrode plate of a storage capacitor, the oxide and the oxide
- the pixel electrode 9 corresponding to the second region 402 of the active layer constitutes a second electrode plate of the storage capacitor, and the film layer between the first electrode plate and the second electrode plate constitutes a dielectric material of the storage capacitor.
- the main structure of the AMOLED array substrate of the present embodiment includes a gate line 11, a data line 12, and a power line 13, the data line 12 and the power line 13 are perpendicular to the gate line 11, and are adjacent to two
- the gate lines 11 together define a pixel area.
- a first thin film transistor also referred to as a switching thin film transistor
- a second thin film transistor also referred to as a driving thin film transistor
- a pixel electrode 9 are formed in the pixel region, respectively.
- the first thin film transistor is located at a intersection of the gate line 11 and the data line 12, and the second thin film transistor is located at a position where the gate line 11 and the power line 13 intersect, wherein the first drain 701 of the first thin film transistor passes through the first via 111 is connected to the second gate 202 of the second thin film transistor, or the first drain 701 of the first thin film transistor is disposed at the position of the gate of the second thin film transistor, directly serving as the second gate 202.
- the first gate 201, the second gate 202, and the gate line 11 are disposed on the substrate 1 and formed in the same patterning process, wherein the first gate 201 is connected to the gate line 11.
- the second gate 202 is not connected to the gate line 11 while the first gate 201 and the second gate 202 are not connected.
- the gate insulating layer 3 is formed on the first gate 201, the second gate 202, and the gate line 11 and covers the entire substrate 1.
- the oxide active layer first region 401 forms a first thin film transistor semiconductor channel and a second thin film transistor semiconductor channel, the first thin film transistor semiconductor trench
- the track is disposed above the first gate 201
- the second thin film transistor semiconductor channel is disposed above the second gate 202, and the first thin film transistor semiconductor channel and the second thin film transistor semiconductor channel are not connected to each other.
- the etch barrier layer 5 is formed on the oxide active layer first region 401 and the oxide active layer second region 402 and covers the entire substrate 1.
- the data line 12, the first source 601, the first drain 701, and the power line 13, the second source 602, and the second drain 702 are formed in the same patterning process, wherein one end of the first source 601 Connected to the data line 12, the first source 601 and the first drain 701 are connected by a first thin film semiconductor channel region; one end of the second source 602 is connected to the power line 13, the second source 602 and the second The drains 702 are connected by a second thin film semiconductor channel region.
- the passivation layer 8 is formed on the data line 12, the first source 601, the first drain 701 and the power line 13, the second source 602, and the second drain 702 and covers the entire substrate 1.
- the pattern of the pixel electrode 9 is then formed by the fourth patterning process.
- the names of the source and drain of the array substrate vary depending on the flow direction of the current.
- the connection to the pixel electrode is referred to as a drain.
- the first via hole 111 and the second via hole 112 are formed thereon, wherein the first via hole 111 is opened above the second gate electrode 202, and penetrates The etch barrier layer 5 and the gate insulating layer 3 reach the second gate 202.
- the first drain 701 is connected to the second gate 202 through the first via 111.
- the second via 112 is opened in the second region of the oxide active layer.
- the etch barrier layer 5 is passed through to the oxide active layer second region 402, and the first drain 701 is connected to the oxide active layer second region 402 through the second via 112.
- a third via 113 is formed thereon, wherein the third via 113 is formed above the second drain 702, penetrates the passivation layer 8 to reach the second drain 702, and the pixel electrode 9 passes through The third via 113 is connected to the second drain 702.
- a portion of the array substrate in which the oxide active layer second region 402 corresponds to the pixel electrode 9 in the above-described step is referred to as an overlap region 10.
- the overlap area 10 is the area where the storage capacitor is located.
- the oxide active layer second region 402 constitutes a first electrode plate of the storage capacitor
- the pixel electrode 9 corresponding to the oxide active layer second region 402 constitutes a second electrode plate of the storage capacitor, the first electrode plate and the second electrode plate
- the film layer between the electrode plates constitutes the dielectric of the storage capacitor. Since the storage capacitors are made of a transparent material, the storage capacitors are translucent.
- the gate, the gate line, the source, the drain, and the data line may be made of molybdenum (Mo), a phase milling alloy.
- Mo molybdenum
- Single or multi-layer composite stack formed of any one or more of (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), chromium (Cr), copper (Cu), and the like Layer structure.
- the above material includes a metal material that is opaque, and thus the gate, gate line, source, drain, and data line structures are formed to be opaque.
- the gate, the gate line, the source, the drain and the data line are a single layer or a multilayer composite film structure composed of MoAl or an alloy containing MoAl, and the film layer is formed to have a thickness of 100 nm to 3000 nm.
- the gate insulating layer may be any one of silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx), silicon oxynitride (SiON), aluminum oxide (AlOx), or the like.
- SiOx silicon oxide
- SiNx silicon nitride
- HfOx germanium oxide
- SiON silicon oxynitride
- AlOx aluminum oxide
- a multilayer composite film structure formed of one or any two materials.
- the oxide active layer is formed of a thin film containing an element of In (indium), Ga (gallium), Zn (express), 0 (oxygen), Sn (tin), etc., wherein the film must contain oxygen and the other two or Two or more elements, for example, an oxide active layer may be made of IGZO (Indium Oxide), IZO (Indium Oxide), InSnO (Indium Tin Oxide), InGaSnO (InGaAs) or the like.
- the etching stopper layer and the passivation layer may be any one or any two of an oxide of silicon (SiOx), a nitride of silicon (SiNx), an oxide of HfOx, and an oxide of aluminum (AlOx).
- the etch stop layer and the passivation layer are characterized by a layer having a low low hydrogen content and having excellent surface characteristics.
- the pixel electrode can be made of indium tin oxide ( ⁇ ) or indium oxide (izo) or other transparent oxide.
- ITO material as an example, an amorphous ITO is usually prepared by a sputtering film formation method, and then crystallized by an annealing process.
- the thickness of the pixel electrode is 20 ⁇ 150
- the storage capacitor of the array substrate in the embodiment of the invention is a parallel plate capacitor structure.
- ⁇ is the dielectric constant
- S is the corresponding area of the two plates of the storage capacitor
- d is the distance between the two plates of the storage capacitor
- k is the electrostatic force constant.
- the corresponding area of the two plates of the storage capacitor depends on the corresponding region of the second region of the oxide active layer and the pixel electrode, and the distance between the plates depends on the film sandwiched between the second region of the oxide active layer and the pixel electrode. Layer thickness. Therefore, the required storage capacitance can be generated by adjusting the corresponding area and the thickness of the sandwiched film.
- the corresponding region of the second region of the oxide active layer and the pixel electrode is determined by the second region of the oxide active layer and the pixel electrode, so that the shape of the corresponding region formed may have Multiple possibilities, for example: corresponding areas formed
- the domain can be a common shape such as a rectangle, a square, a triangle, or an irregular shape.
- the corresponding regions formed may also be formed by a plurality of regions, and are not limited to being formed by one region.
- the array substrate of the present invention only cites a bottom gate structure, and the technical solution mentioned in the present invention is also applicable to a top gate structure, including a source and a drain formed on a substrate, and sequentially formed thereon.
- the structure of the passivation layer, the gate insulating layer, and the gate are sequentially formed thereon.
- the common point is the function of the oxide active layer and the arrangement of the second region of the oxide active layer. Therefore, the array substrate of the top gate structure is also suitable for the technical solution.
- the top gate structure of the above two structures and the manufacturing method thereof are not described herein again.
- the present invention only exemplifies the array substrate of the 2T1C type pixel structure, that is, the pixel driving circuit in the array substrate includes two thin film transistors and one capacitor.
- the oxide active layer includes a first region of the oxide active layer and a second region of the oxide active layer, the first region of the oxide active layer is used to form a semiconductor channel region of the thin film transistor, and the oxide active layer is second The area is used to form the first electrode plate of the storage capacitor, so that the formed storage capacitor has opacity, which ultimately increases the aperture ratio of the array substrate.
- the array substrate formed by the technical solution mentioned in the present invention may have other variations, for example: the pixel driving circuit of the array substrate is composed of three thin film transistors or four thin film transistors, compared with the array substrate of the above embodiment.
- the common point is the function of the oxide active layer and the arrangement of the second region of the oxide active layer, which will not be described herein.
- the first electrode plate of the storage capacitor is formed by using the second region of the transparent oxide active layer, and the second electrode plate of the storage capacitor is formed by the pixel electrode corresponding to the second region of the transparent oxide active layer.
- the formed storage capacitor structure is made translucent, thereby increasing the aperture ratio of the array substrate, reducing the current intensity required for the display device to emit light, and prolonging the service life of the display device.
- the substrate for performing the above process is subjected to hydrogen plasma treatment, and the first electrode plate is formed by performing a hydrogen plasma process on the second region of the oxide active layer, so that the resistance of the first electrode plate The rate is less than 5 ⁇ 10_ 3 ⁇ ⁇ cm, and its conductivity is closer to that of the metal electrode plate.
- the second region of the oxide active layer is subjected to hydrogen plasma treatment, and the process is passed through a reactive ion etching device.
- the processing time is 150S
- the processing power is 800 ⁇ 2000W
- the hydrogen flow rate used for processing is 80SCCM (English: standard-state cubic Centimeter per minute, Chinese: standard cc per minute).
- the resistivity of the second region of the oxide active layer becomes l xl (T 3 Q .
- the resistivity of a region is greater than 10 6 ⁇ cm, which constitutes the semiconductor channel region of the thin film transistor and exhibits semiconductor characteristics.
- a gate electrode 2 and a gate line, a gate insulating layer 3, and an oxide active layer are formed on the substrate 1, and the oxide active layer first region 401 is formed by one patterning process. And a pattern of the oxide active layer second region 402. Then, a photoresist is coated on the substrate, a photoresist is removed from the second region 402 of the oxide active layer by a patterning process, and a substrate subjected to the above process is subjected to a hydrogen plasma process to make a process after the process
- the oxide active layer second region 402 behaves as a conductor characteristic.
- the resistivity of the oxide active layer second region 402 becomes 1 ⁇ 10 ⁇ 3 ⁇ cm. It should be noted that, due to the protection of the photoresist, the first region of the oxide active layer is not affected by the hydrogen plasma process, and therefore, the photoresist in the first region of the oxide active layer is removed. The rate is still greater than 10 6 Q ⁇ cm, which constitutes the semiconductor channel region of the thin film transistor and exhibits semiconductor characteristics.
- the array substrate further includes an etch barrier layer and/or a passivation layer
- the film layer between the first electrode plate and the second electrode plate includes a passivation layer and/or an etch barrier layer.
- the passivation layer and/or the etch barrier layer are both transparent insulating film layers and thus can be used to form a dielectric structure of the storage capacitor.
- the material of the oxide active layer is indium gallium oxide, indium oxide, indium tin oxide or indium gallium tin oxide.
- the etch stop layer and the passivation layer are respectively one or more of silicon oxide, silicon nitride, germanium oxide, silicon oxynitride or aluminum oxide.
- a transparent single layer or composite layer structure is formed.
- the first electrode plate of the storage capacitor is formed by the second region 402 of the transparent oxide active layer, and the pixel electrode 9 corresponding to the second region 402 of the transparent oxide active layer is formed to form a second storage capacitor.
- the electrode plate makes the formed storage capacitor structure transparent, thereby increasing the aperture ratio of the array substrate, reducing the current intensity required for the display device to emit light, and prolonging the service life of the display device.
- a display device comprising the array substrate described above.
- the structure and working principle of the array substrate are the same as those in the foregoing embodiment, and details are not described herein again.
- the structure of other parts of the display device can refer to the prior art, which will not be described in detail herein.
- the first region of the above oxide active layer actually constitutes the active layer of the thin film transistor, and the second region of the oxide active layer constitutes an electrode plate of the storage capacitor. Since the oxide active layer is formed of an oxide semiconductor layer, the first region of the above oxide active layer may be referred to as a first region of the oxide semiconductor, and the second region of the above oxide active layer may be referred to as A second region of the oxide semiconductor layer. As described above, the second region of the oxide semiconductor layer may be subjected to hydrogen plasma treatment so that its resistivity is close to that of the metal electrode.
- the array substrate forms a first electrode plate of the storage capacitor by using a transparent oxide material, so that the formed storage capacitor structure has light transmissivity, thereby increasing the aperture ratio of the array substrate and reducing the illumination of the display device.
- the required current intensity extends the life of the display unit.
- a method for fabricating an array substrate includes the following steps: Step S1, depositing a gate metal film on a substrate, and forming a pattern including a gate and a gate line by a patterning process;
- Step S2 forming a gate insulating layer on the substrate on which the foregoing steps are completed;
- Step S3 depositing an oxide active layer film on the substrate on which the foregoing steps are completed, and forming a pattern including a first region of the oxide active layer and a second region of the oxide active layer by a patterning process;
- Step S4 forming an etch barrier film on the substrate on which the foregoing steps are completed, and forming a first via hole including an etch barrier layer, an etch barrier layer, and a second via hole of the etch barrier layer by a patterning process, the etch barrier
- the first via of the layer is located at the gate, penetrates the etch barrier layer and the gate insulating layer reaches the gate, and the gate exposes the gate
- the second via of the etch barrier is located at the oxide active layer Positioning the two regions, penetrating the etch barrier layer to reach the second region of the oxide active layer, and exposing the second region of the oxide active layer in the via hole;
- Step S5 depositing a source/drain metal film on the substrate on which the foregoing steps are completed, and forming a pattern including a source, a drain, a data line, and a power line through a patterning process;
- Step S6 depositing a passivation layer film on the substrate on which the foregoing steps are completed, and forming a pattern including a passivation layer and a passivation layer via hole by a patterning process, wherein the passivation layer via hole is located at the drain and penetrates bluntly The layer reaches the drain and the drain is exposed in the via.
- Step S7 depositing a transparent conductive film on the substrate on which the foregoing steps are completed, and forming a pattern including a pixel electrode through a patterning process, wherein the pixel electrode is connected to the drain through the via hole.
- the method for fabricating an array substrate according to an embodiment of the present invention utilizes a second region of a transparent oxide active layer a first electrode plate that is a storage capacitor, and a pixel electrode corresponding to the second region of the transparent oxide active layer form a second electrode plate of the storage capacitor, and a film layer between the first electrode plate and the second electrode plate constitutes a storage capacitor
- the dielectric material makes the formed storage capacitor structure light transmissive, thereby increasing the aperture ratio of the array substrate, reducing the current intensity required for the display device to emit light, and prolonging the service life of the display device.
- the pattern including the first electrode plate is formed by subjecting the second region of the oxide active layer to a hydrogen plasma process, and the first electrode plate has a resistivity of less than 5 ⁇ 10 ⁇ 3 ⁇ cm.
- Step S101 using a method of magnetron sputtering or thermal evaporation, depositing a gate metal film on the substrate, forming a pattern including the first gate, the second gate, and the gate line by a patterning process by using a common mask;
- Step S102 adopting a method of spin coating coating a gate insulating layer;
- Step S103 depositing an oxide active layer film by a plasma enhanced chemical vapor deposition method, and forming a pattern including a first region of the oxide active layer and a second region of the oxide active layer by a patterning process;
- Step S104 coating a photoresist on the oxide active layer film, forming a photoresist pattern exposing the first region of the active layer of the oxide by a patterning process; and performing the substrate for completing the above steps under hydrogen conditions Hydrogen plasma treatment, the specific processing time is 150S, the processing power is 800 ⁇ 2000W, and the flow rate of hydrogen used for processing is 80SCCM. After the treatment is completed, the photoresist on the substrate is stripped;
- Step S105 using a plasma enhanced chemical vapor deposition method, depositing an etch barrier film, and forming a pattern including a first via and a second via by a patterning process using a common mask, the first via being located in the second a position of the gate penetrates the etch barrier layer and the gate insulating layer reaches the second gate; the second via is located at the second region of the oxide active layer, penetrates the etch barrier to reach the oxide active Second area of the layer;
- Step S106 depositing a source/drain metal film by magnetron sputtering or thermal evaporation, and forming a pattern including first and second source drains, data lines, and power lines by a patterning process; Connecting the second gate and the second region of the oxide active layer through the first via hole and the second via hole respectively;
- Step S107 depositing a passivation layer film by using a plasma enhanced chemical vapor deposition method, and adopting a common mask Forming a pattern including a third via hole by a patterning process, the third via hole being located at a position of the second drain, penetrating the passivation layer to reach the second drain;
- Step S108 depositing a transparent conductive film, forming a pattern of the pixel electrode by a patterning process, The pixel electrode is connected to the second drain through the third via.
- This embodiment is a technical solution for performing hydrogen plasma treatment on the second region of the oxide active layer after the step of completing the oxide active layer.
- the preparation process has been described in detail in the foregoing technical solutions, and is not described herein.
- the processing time of the hydrogen plasma treatment process is 150S, and the processing power is
- hydrogen plasma flow rate is 80SCCM.
- the array substrate further includes an etch barrier layer and/or a passivation layer, and the film layer between the first electrode plate and the second electrode plate includes a passivation layer and/or an etch barrier layer.
- the method for fabricating an array substrate according to the embodiment of the present invention the first electrode plate constituting the storage capacitor by the second region of the transparent oxide active layer, and the second electrode of the storage capacitor formed by the pixel electrode corresponding to the second region of the transparent oxide active layer
- the plate makes the formed storage capacitor structure translucent, thereby increasing the aperture ratio of the array substrate, reducing the current intensity required for the display device to emit light, and prolonging the service life of the display device.
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Abstract
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