WO2014153870A1 - 阵列基板、显示装置及制作方法 - Google Patents

阵列基板、显示装置及制作方法 Download PDF

Info

Publication number
WO2014153870A1
WO2014153870A1 PCT/CN2013/077591 CN2013077591W WO2014153870A1 WO 2014153870 A1 WO2014153870 A1 WO 2014153870A1 CN 2013077591 W CN2013077591 W CN 2013077591W WO 2014153870 A1 WO2014153870 A1 WO 2014153870A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
layer
array substrate
oxide semiconductor
electrode plate
Prior art date
Application number
PCT/CN2013/077591
Other languages
English (en)
French (fr)
Inventor
成军
陈江博
孔祥永
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/353,580 priority Critical patent/US20150214249A1/en
Publication of WO2014153870A1 publication Critical patent/WO2014153870A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H01L21/441—Deposition of conductive or insulating materials for electrodes
    • H01L21/443—Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/4763—Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
    • H01L21/47635—After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

Definitions

  • Embodiments of the present invention relate to an array substrate, a display device, and a method of fabricating the same. Background technique
  • OLED Organic Light-Emitting Diode
  • the storage capacitor in the OLED driving circuit in the prior art is formed by an opaque metal electrode and a pixel electrode. Therefore, the opaque metal electrode directly affects the aperture ratio. Moreover, the current intensity required for the display device to emit light is increased, and the service life of the display device is shortened. Summary of the invention
  • Embodiments of the present invention provide an array substrate, a display device, and a manufacturing method thereof, wherein a first electrode plate of a storage capacitor is formed by a second region of a transparent oxide active layer to increase an aperture ratio of the array substrate.
  • An embodiment of the present invention provides an array substrate, including: a thin film transistor and a pixel electrode, wherein an active layer of the thin film transistor is formed by a first region of an oxide semiconductor layer, and the oxide semiconductor layer further includes a second region, the pixel electrode overlaps with a second region of the oxide semiconductor layer to form a storage capacitor, and a second region of the oxide semiconductor layer constitutes a first electrode plate of the storage capacitor, the oxide and the oxide a pixel electrode corresponding to the second region of the semiconductor layer constitutes a second electrode plate of the storage capacitor, and
  • a dielectric layer is disposed between the first electrode plate and the second electrode plate.
  • the first electrode plate is formed by performing a hydrogen plasma process on a second region of the oxide semiconductor.
  • the first electrode plate has a resistivity of less than 5 ⁇ 1 ( ⁇ 3 ⁇ ⁇ cm. In one example, the resistivity of the second region of the oxide semiconductor layer is less than the resistivity of the first region of the oxide semiconductor layer.
  • the first region of the oxide semiconductor layer and the second region of the oxide semiconductor layer are isolated from each other.
  • the dielectric layer between the first electrode plate and the second electrode plate includes a passivation layer and/or an etch stop layer.
  • the material of the oxide semiconductor layer is indium gallium oxide, indium oxide, indium tin oxide or indium gallium tin oxide.
  • the etch stop layer and the passivation layer are each one of an oxide of silicon, a nitride of silicon, an oxide of cerium, an oxynitride of silicon, or an oxide of aluminum, or A variety of transparent single or composite layer structures are formed.
  • the dielectric layer between the first electrode plate and the second electrode plate includes an etch stop layer and a gate insulating layer.
  • Another embodiment of the present invention provides a display device comprising an array substrate according to any of the embodiments of the present invention.
  • Still another embodiment of the present invention provides a method of fabricating an array substrate, comprising: forming an oxide semiconductor layer, forming a pixel electrode pattern, and forming a dielectric layer between the oxide semiconductor layer and the pixel electrode pattern, wherein formation
  • the oxide semiconductor layer includes:
  • the second region of the oxide semiconductor layer constitutes a first electrode plate of the storage capacitor
  • the pixel electrode corresponding to the second region of the oxide active layer constitutes a second electrode plate of the storage capacitor, the first electrode plate and
  • the dielectric layer between the second electrode plates constitutes a dielectric for the storage capacitor.
  • the second region of the oxide semiconductor layer is subjected to a hydrogen plasma process to form a pattern including the first electrode plate, the first electrode plate having a resistivity of less than 5> ⁇ 10" 3 ⁇ ⁇ cm .
  • the hydrogen plasma treatment process has a processing time of 150 s, a processing power of 800 to 2000 W, and a hydrogen plasma flow rate of 80 SCCM.
  • the dielectric layer includes an etch stop layer and/or a passivation layer.
  • the array substrate, the display device and the manufacturing method of the present invention provide a first electrode plate of a storage capacitor by using a transparent oxide material, so that the formed storage capacitor structure has light transmissivity, thereby increasing the aperture ratio of the array substrate and reducing the display device.
  • the current intensity required for illumination extends the life of the display device.
  • 1 is a driving circuit diagram of an AMOLED array substrate
  • FIG. 2 is a schematic view showing the layout of an array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional view of the interlayer of the array substrate A-A of FIG. 2;
  • FIG. 4 is a second schematic cross-sectional view of an embodiment of the present invention.
  • FIG. 5 is a schematic view showing a second region of a photoresist-treated oxide active layer coated with a photoresist according to an embodiment of the present invention. detailed description
  • Embodiments of the present invention provide an array substrate, a display device, and a manufacturing method thereof, wherein a first electrode plate of a storage capacitor is formed through a second region of a transparent oxide active layer to increase an aperture ratio of the array substrate.
  • FIG. 1 is a driving circuit diagram of a pixel structure of an AMOLED, the pixel unit circuit structure including two thin film transistors and a capacitor.
  • the gate line is electrically connected to the gate electrode of the first thin film transistor
  • the data line is electrically connected to the drain electrode of the first thin film transistor.
  • the electrical signal provided by the gate line causes the first thin film transistor to be in an on/off state; when the first thin film transistor is turned on, the electrical signal provided by the data line causes the second thin film transistor to be in an on/off state; when the second thin film When the transistor is turned on, the signal input from the power line drives the AMOLED to emit light through the second thin film transistor.
  • FIG. 2 is a schematic plan view of a pixel unit of an array substrate according to an embodiment of the present invention
  • FIG. 3 is a cross-sectional view taken along line A-A of FIG. Figure 3 is a cross-sectional view showing a thin film transistor of the present invention, reflecting the structure of a thin film transistor.
  • the main structure of the thin film transistor of the present embodiment includes a gate electrode 2 formed on the substrate 1, a gate insulating layer 3, an oxide active layer, an etch barrier layer 5, a source electrode 6, a drain electrode 7, a passivation layer 8, and a pixel.
  • the thin film transistor includes, in particular, an oxide active layer first region 401 and an oxide active layer second region 402.
  • the oxide active layer first region 401 and the oxide active layer second region 402 are formed in the same patterning process.
  • the above pattern may not be formed in the same patterning process as needed.
  • a portion of the pixel electrode 9 corresponding to the oxide active layer second region 402 forms a storage capacitor, and the oxide active layer second region 402 constitutes a first electrode plate of a storage capacitor, the oxide and the oxide
  • the pixel electrode 9 corresponding to the second region 402 of the active layer constitutes a second electrode plate of the storage capacitor, and the film layer between the first electrode plate and the second electrode plate constitutes a dielectric material of the storage capacitor.
  • the main structure of the AMOLED array substrate of the present embodiment includes a gate line 11, a data line 12, and a power line 13, the data line 12 and the power line 13 are perpendicular to the gate line 11, and are adjacent to two
  • the gate lines 11 together define a pixel area.
  • a first thin film transistor also referred to as a switching thin film transistor
  • a second thin film transistor also referred to as a driving thin film transistor
  • a pixel electrode 9 are formed in the pixel region, respectively.
  • the first thin film transistor is located at a intersection of the gate line 11 and the data line 12, and the second thin film transistor is located at a position where the gate line 11 and the power line 13 intersect, wherein the first drain 701 of the first thin film transistor passes through the first via 111 is connected to the second gate 202 of the second thin film transistor, or the first drain 701 of the first thin film transistor is disposed at the position of the gate of the second thin film transistor, directly serving as the second gate 202.
  • the first gate 201, the second gate 202, and the gate line 11 are disposed on the substrate 1 and formed in the same patterning process, wherein the first gate 201 is connected to the gate line 11.
  • the second gate 202 is not connected to the gate line 11 while the first gate 201 and the second gate 202 are not connected.
  • the gate insulating layer 3 is formed on the first gate 201, the second gate 202, and the gate line 11 and covers the entire substrate 1.
  • the oxide active layer first region 401 forms a first thin film transistor semiconductor channel and a second thin film transistor semiconductor channel, the first thin film transistor semiconductor trench
  • the track is disposed above the first gate 201
  • the second thin film transistor semiconductor channel is disposed above the second gate 202, and the first thin film transistor semiconductor channel and the second thin film transistor semiconductor channel are not connected to each other.
  • the etch barrier layer 5 is formed on the oxide active layer first region 401 and the oxide active layer second region 402 and covers the entire substrate 1.
  • the data line 12, the first source 601, the first drain 701, and the power line 13, the second source 602, and the second drain 702 are formed in the same patterning process, wherein one end of the first source 601 Connected to the data line 12, the first source 601 and the first drain 701 are connected by a first thin film semiconductor channel region; one end of the second source 602 is connected to the power line 13, the second source 602 and the second The drains 702 are connected by a second thin film semiconductor channel region.
  • the passivation layer 8 is formed on the data line 12, the first source 601, the first drain 701 and the power line 13, the second source 602, and the second drain 702 and covers the entire substrate 1.
  • the pattern of the pixel electrode 9 is then formed by the fourth patterning process.
  • the names of the source and drain of the array substrate vary depending on the flow direction of the current.
  • the connection to the pixel electrode is referred to as a drain.
  • the first via hole 111 and the second via hole 112 are formed thereon, wherein the first via hole 111 is opened above the second gate electrode 202, and penetrates The etch barrier layer 5 and the gate insulating layer 3 reach the second gate 202.
  • the first drain 701 is connected to the second gate 202 through the first via 111.
  • the second via 112 is opened in the second region of the oxide active layer.
  • the etch barrier layer 5 is passed through to the oxide active layer second region 402, and the first drain 701 is connected to the oxide active layer second region 402 through the second via 112.
  • a third via 113 is formed thereon, wherein the third via 113 is formed above the second drain 702, penetrates the passivation layer 8 to reach the second drain 702, and the pixel electrode 9 passes through The third via 113 is connected to the second drain 702.
  • a portion of the array substrate in which the oxide active layer second region 402 corresponds to the pixel electrode 9 in the above-described step is referred to as an overlap region 10.
  • the overlap area 10 is the area where the storage capacitor is located.
  • the oxide active layer second region 402 constitutes a first electrode plate of the storage capacitor
  • the pixel electrode 9 corresponding to the oxide active layer second region 402 constitutes a second electrode plate of the storage capacitor, the first electrode plate and the second electrode plate
  • the film layer between the electrode plates constitutes the dielectric of the storage capacitor. Since the storage capacitors are made of a transparent material, the storage capacitors are translucent.
  • the gate, the gate line, the source, the drain, and the data line may be made of molybdenum (Mo), a phase milling alloy.
  • Mo molybdenum
  • Single or multi-layer composite stack formed of any one or more of (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), chromium (Cr), copper (Cu), and the like Layer structure.
  • the above material includes a metal material that is opaque, and thus the gate, gate line, source, drain, and data line structures are formed to be opaque.
  • the gate, the gate line, the source, the drain and the data line are a single layer or a multilayer composite film structure composed of MoAl or an alloy containing MoAl, and the film layer is formed to have a thickness of 100 nm to 3000 nm.
  • the gate insulating layer may be any one of silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx), silicon oxynitride (SiON), aluminum oxide (AlOx), or the like.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • HfOx germanium oxide
  • SiON silicon oxynitride
  • AlOx aluminum oxide
  • a multilayer composite film structure formed of one or any two materials.
  • the oxide active layer is formed of a thin film containing an element of In (indium), Ga (gallium), Zn (express), 0 (oxygen), Sn (tin), etc., wherein the film must contain oxygen and the other two or Two or more elements, for example, an oxide active layer may be made of IGZO (Indium Oxide), IZO (Indium Oxide), InSnO (Indium Tin Oxide), InGaSnO (InGaAs) or the like.
  • the etching stopper layer and the passivation layer may be any one or any two of an oxide of silicon (SiOx), a nitride of silicon (SiNx), an oxide of HfOx, and an oxide of aluminum (AlOx).
  • the etch stop layer and the passivation layer are characterized by a layer having a low low hydrogen content and having excellent surface characteristics.
  • the pixel electrode can be made of indium tin oxide ( ⁇ ) or indium oxide (izo) or other transparent oxide.
  • ITO material as an example, an amorphous ITO is usually prepared by a sputtering film formation method, and then crystallized by an annealing process.
  • the thickness of the pixel electrode is 20 ⁇ 150
  • the storage capacitor of the array substrate in the embodiment of the invention is a parallel plate capacitor structure.
  • ⁇ is the dielectric constant
  • S is the corresponding area of the two plates of the storage capacitor
  • d is the distance between the two plates of the storage capacitor
  • k is the electrostatic force constant.
  • the corresponding area of the two plates of the storage capacitor depends on the corresponding region of the second region of the oxide active layer and the pixel electrode, and the distance between the plates depends on the film sandwiched between the second region of the oxide active layer and the pixel electrode. Layer thickness. Therefore, the required storage capacitance can be generated by adjusting the corresponding area and the thickness of the sandwiched film.
  • the corresponding region of the second region of the oxide active layer and the pixel electrode is determined by the second region of the oxide active layer and the pixel electrode, so that the shape of the corresponding region formed may have Multiple possibilities, for example: corresponding areas formed
  • the domain can be a common shape such as a rectangle, a square, a triangle, or an irregular shape.
  • the corresponding regions formed may also be formed by a plurality of regions, and are not limited to being formed by one region.
  • the array substrate of the present invention only cites a bottom gate structure, and the technical solution mentioned in the present invention is also applicable to a top gate structure, including a source and a drain formed on a substrate, and sequentially formed thereon.
  • the structure of the passivation layer, the gate insulating layer, and the gate are sequentially formed thereon.
  • the common point is the function of the oxide active layer and the arrangement of the second region of the oxide active layer. Therefore, the array substrate of the top gate structure is also suitable for the technical solution.
  • the top gate structure of the above two structures and the manufacturing method thereof are not described herein again.
  • the present invention only exemplifies the array substrate of the 2T1C type pixel structure, that is, the pixel driving circuit in the array substrate includes two thin film transistors and one capacitor.
  • the oxide active layer includes a first region of the oxide active layer and a second region of the oxide active layer, the first region of the oxide active layer is used to form a semiconductor channel region of the thin film transistor, and the oxide active layer is second The area is used to form the first electrode plate of the storage capacitor, so that the formed storage capacitor has opacity, which ultimately increases the aperture ratio of the array substrate.
  • the array substrate formed by the technical solution mentioned in the present invention may have other variations, for example: the pixel driving circuit of the array substrate is composed of three thin film transistors or four thin film transistors, compared with the array substrate of the above embodiment.
  • the common point is the function of the oxide active layer and the arrangement of the second region of the oxide active layer, which will not be described herein.
  • the first electrode plate of the storage capacitor is formed by using the second region of the transparent oxide active layer, and the second electrode plate of the storage capacitor is formed by the pixel electrode corresponding to the second region of the transparent oxide active layer.
  • the formed storage capacitor structure is made translucent, thereby increasing the aperture ratio of the array substrate, reducing the current intensity required for the display device to emit light, and prolonging the service life of the display device.
  • the substrate for performing the above process is subjected to hydrogen plasma treatment, and the first electrode plate is formed by performing a hydrogen plasma process on the second region of the oxide active layer, so that the resistance of the first electrode plate The rate is less than 5 ⁇ 10_ 3 ⁇ ⁇ cm, and its conductivity is closer to that of the metal electrode plate.
  • the second region of the oxide active layer is subjected to hydrogen plasma treatment, and the process is passed through a reactive ion etching device.
  • the processing time is 150S
  • the processing power is 800 ⁇ 2000W
  • the hydrogen flow rate used for processing is 80SCCM (English: standard-state cubic Centimeter per minute, Chinese: standard cc per minute).
  • the resistivity of the second region of the oxide active layer becomes l xl (T 3 Q .
  • the resistivity of a region is greater than 10 6 ⁇ cm, which constitutes the semiconductor channel region of the thin film transistor and exhibits semiconductor characteristics.
  • a gate electrode 2 and a gate line, a gate insulating layer 3, and an oxide active layer are formed on the substrate 1, and the oxide active layer first region 401 is formed by one patterning process. And a pattern of the oxide active layer second region 402. Then, a photoresist is coated on the substrate, a photoresist is removed from the second region 402 of the oxide active layer by a patterning process, and a substrate subjected to the above process is subjected to a hydrogen plasma process to make a process after the process
  • the oxide active layer second region 402 behaves as a conductor characteristic.
  • the resistivity of the oxide active layer second region 402 becomes 1 ⁇ 10 ⁇ 3 ⁇ cm. It should be noted that, due to the protection of the photoresist, the first region of the oxide active layer is not affected by the hydrogen plasma process, and therefore, the photoresist in the first region of the oxide active layer is removed. The rate is still greater than 10 6 Q ⁇ cm, which constitutes the semiconductor channel region of the thin film transistor and exhibits semiconductor characteristics.
  • the array substrate further includes an etch barrier layer and/or a passivation layer
  • the film layer between the first electrode plate and the second electrode plate includes a passivation layer and/or an etch barrier layer.
  • the passivation layer and/or the etch barrier layer are both transparent insulating film layers and thus can be used to form a dielectric structure of the storage capacitor.
  • the material of the oxide active layer is indium gallium oxide, indium oxide, indium tin oxide or indium gallium tin oxide.
  • the etch stop layer and the passivation layer are respectively one or more of silicon oxide, silicon nitride, germanium oxide, silicon oxynitride or aluminum oxide.
  • a transparent single layer or composite layer structure is formed.
  • the first electrode plate of the storage capacitor is formed by the second region 402 of the transparent oxide active layer, and the pixel electrode 9 corresponding to the second region 402 of the transparent oxide active layer is formed to form a second storage capacitor.
  • the electrode plate makes the formed storage capacitor structure transparent, thereby increasing the aperture ratio of the array substrate, reducing the current intensity required for the display device to emit light, and prolonging the service life of the display device.
  • a display device comprising the array substrate described above.
  • the structure and working principle of the array substrate are the same as those in the foregoing embodiment, and details are not described herein again.
  • the structure of other parts of the display device can refer to the prior art, which will not be described in detail herein.
  • the first region of the above oxide active layer actually constitutes the active layer of the thin film transistor, and the second region of the oxide active layer constitutes an electrode plate of the storage capacitor. Since the oxide active layer is formed of an oxide semiconductor layer, the first region of the above oxide active layer may be referred to as a first region of the oxide semiconductor, and the second region of the above oxide active layer may be referred to as A second region of the oxide semiconductor layer. As described above, the second region of the oxide semiconductor layer may be subjected to hydrogen plasma treatment so that its resistivity is close to that of the metal electrode.
  • the array substrate forms a first electrode plate of the storage capacitor by using a transparent oxide material, so that the formed storage capacitor structure has light transmissivity, thereby increasing the aperture ratio of the array substrate and reducing the illumination of the display device.
  • the required current intensity extends the life of the display unit.
  • a method for fabricating an array substrate includes the following steps: Step S1, depositing a gate metal film on a substrate, and forming a pattern including a gate and a gate line by a patterning process;
  • Step S2 forming a gate insulating layer on the substrate on which the foregoing steps are completed;
  • Step S3 depositing an oxide active layer film on the substrate on which the foregoing steps are completed, and forming a pattern including a first region of the oxide active layer and a second region of the oxide active layer by a patterning process;
  • Step S4 forming an etch barrier film on the substrate on which the foregoing steps are completed, and forming a first via hole including an etch barrier layer, an etch barrier layer, and a second via hole of the etch barrier layer by a patterning process, the etch barrier
  • the first via of the layer is located at the gate, penetrates the etch barrier layer and the gate insulating layer reaches the gate, and the gate exposes the gate
  • the second via of the etch barrier is located at the oxide active layer Positioning the two regions, penetrating the etch barrier layer to reach the second region of the oxide active layer, and exposing the second region of the oxide active layer in the via hole;
  • Step S5 depositing a source/drain metal film on the substrate on which the foregoing steps are completed, and forming a pattern including a source, a drain, a data line, and a power line through a patterning process;
  • Step S6 depositing a passivation layer film on the substrate on which the foregoing steps are completed, and forming a pattern including a passivation layer and a passivation layer via hole by a patterning process, wherein the passivation layer via hole is located at the drain and penetrates bluntly The layer reaches the drain and the drain is exposed in the via.
  • Step S7 depositing a transparent conductive film on the substrate on which the foregoing steps are completed, and forming a pattern including a pixel electrode through a patterning process, wherein the pixel electrode is connected to the drain through the via hole.
  • the method for fabricating an array substrate according to an embodiment of the present invention utilizes a second region of a transparent oxide active layer a first electrode plate that is a storage capacitor, and a pixel electrode corresponding to the second region of the transparent oxide active layer form a second electrode plate of the storage capacitor, and a film layer between the first electrode plate and the second electrode plate constitutes a storage capacitor
  • the dielectric material makes the formed storage capacitor structure light transmissive, thereby increasing the aperture ratio of the array substrate, reducing the current intensity required for the display device to emit light, and prolonging the service life of the display device.
  • the pattern including the first electrode plate is formed by subjecting the second region of the oxide active layer to a hydrogen plasma process, and the first electrode plate has a resistivity of less than 5 ⁇ 10 ⁇ 3 ⁇ cm.
  • Step S101 using a method of magnetron sputtering or thermal evaporation, depositing a gate metal film on the substrate, forming a pattern including the first gate, the second gate, and the gate line by a patterning process by using a common mask;
  • Step S102 adopting a method of spin coating coating a gate insulating layer;
  • Step S103 depositing an oxide active layer film by a plasma enhanced chemical vapor deposition method, and forming a pattern including a first region of the oxide active layer and a second region of the oxide active layer by a patterning process;
  • Step S104 coating a photoresist on the oxide active layer film, forming a photoresist pattern exposing the first region of the active layer of the oxide by a patterning process; and performing the substrate for completing the above steps under hydrogen conditions Hydrogen plasma treatment, the specific processing time is 150S, the processing power is 800 ⁇ 2000W, and the flow rate of hydrogen used for processing is 80SCCM. After the treatment is completed, the photoresist on the substrate is stripped;
  • Step S105 using a plasma enhanced chemical vapor deposition method, depositing an etch barrier film, and forming a pattern including a first via and a second via by a patterning process using a common mask, the first via being located in the second a position of the gate penetrates the etch barrier layer and the gate insulating layer reaches the second gate; the second via is located at the second region of the oxide active layer, penetrates the etch barrier to reach the oxide active Second area of the layer;
  • Step S106 depositing a source/drain metal film by magnetron sputtering or thermal evaporation, and forming a pattern including first and second source drains, data lines, and power lines by a patterning process; Connecting the second gate and the second region of the oxide active layer through the first via hole and the second via hole respectively;
  • Step S107 depositing a passivation layer film by using a plasma enhanced chemical vapor deposition method, and adopting a common mask Forming a pattern including a third via hole by a patterning process, the third via hole being located at a position of the second drain, penetrating the passivation layer to reach the second drain;
  • Step S108 depositing a transparent conductive film, forming a pattern of the pixel electrode by a patterning process, The pixel electrode is connected to the second drain through the third via.
  • This embodiment is a technical solution for performing hydrogen plasma treatment on the second region of the oxide active layer after the step of completing the oxide active layer.
  • the preparation process has been described in detail in the foregoing technical solutions, and is not described herein.
  • the processing time of the hydrogen plasma treatment process is 150S, and the processing power is
  • hydrogen plasma flow rate is 80SCCM.
  • the array substrate further includes an etch barrier layer and/or a passivation layer, and the film layer between the first electrode plate and the second electrode plate includes a passivation layer and/or an etch barrier layer.
  • the method for fabricating an array substrate according to the embodiment of the present invention the first electrode plate constituting the storage capacitor by the second region of the transparent oxide active layer, and the second electrode of the storage capacitor formed by the pixel electrode corresponding to the second region of the transparent oxide active layer
  • the plate makes the formed storage capacitor structure translucent, thereby increasing the aperture ratio of the array substrate, reducing the current intensity required for the display device to emit light, and prolonging the service life of the display device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种阵列基板、显示装置及制作方法。阵列基板包括薄膜晶体管和像素电极（9）。薄膜晶体管的有源层（4）由氧化物半导体层（4）的第一区域（401）形成，氧化物半导体层还包括第二区域（402），像素电极（9）与氧化物半导体层（4）的第二区域（402）重叠以形成储存电容，氧化物半导体层（4）的第二区域（402）构成储存电容的第一电极板（402），与氧化物半导体层（4）的第二区域（402）相对应的像素电极（9）构成储存电容的第二电极板（9），并且第一电极板（402）与第二电极板（9）之间设置有介电层（7、8）。

Description

阵列基板、 显示装置及制作方法 技术领域
本发明的实施例涉及一种阵列基板、 显示装置及制作方法。 背景技术
近年来，随着科技水平的不断进步和提高，显示技术得到了快速的发展。 基于其高品质的图像显示、 自发光、 响应速度快、 宽视角等优势特点， OLED(Organic Light-Emitting Diode,有机发光二极管显示器)在显示领域中占 据了广阔的市场。越来越多的 OLED显示装置为人们所熟知并在日常生活领 域中得到了广泛的应用。
然而发明人发现现有技术阵列基板至少存在如下问题： 现有技术中 OLED驱动电路中的储存电容是由不透明的金属电极与像素电极形成的， 因 此， 不透明的金属电极直接影响了开口率的大小， 进而增加了显示装置发光 所需要的电流强度， 缩短了显示装置的使用寿命。 发明内容
本发明的实施例提供一种阵列基板、 显示装置及制作方法， 通过透明氧 化物有源层第二区域形成储存电容的第一电极板， 增加阵列基板的开口率。
本发明的一个实施例提供一种阵列基板， 包括： 薄膜晶体管和像素电极， 其中， 所述薄膜晶体管的有源层由氧化物半导体层的第一区域形成， 所述氧化物半导体层还包括第二区域， 所述像素电极与所述氧化物半导 体层的第二区域重叠以形成储存电容， 所述氧化物半导体层的第二区域构成 所述储存电容的第一电极板， 所述与氧化物半导体层的第二区域相对应的像 素电极构成所述储存电容的第二电极板， 并且
所述第一电极板与第二电极板之间设置有介电层。
在一个示例中， 所述第一电极板是由对氧化物半导体的第二区域进行氢 等离子体工艺处理形成的。
在一个示例中， 所述第一电极板的电阻率小于 5χ1(Τ3Ω · cm。 在一个示例中， 所述氧化物半导体层的第二区域的电阻率小于所述氧化 物半导体层的第一区域的电阻率。
在一个示例中， 所述氧化物半导体层的第一区域与所述氧化物半导体层 的第二区域相互隔离。
在一个示例中， 所述第一电极板与第二电极板之间的介电层包括钝化层 和 /或刻蚀阻挡层。
在一个示例中， 氧化物半导体层的材质为氧化铟镓辞、 氧化铟辞、 氧化 铟锡或者氧化铟镓锡。
在一个示例中， 所述刻蚀阻挡层以及所述钝化层分别为硅的氧化物、 硅 的氮化物、 铪的氧化物、 硅的氮氧化物或者铝的氧化物中的任意一种或多种 形成的透明单层或复合层结构。
在一个示例中， 所述第一电极板与第二电极板之间的介电层包括刻蚀阻 挡层和栅极绝缘层。
本发明的另一个实施例提供一种显示装置， 包括根据本发明任一实施例 的阵列基板。
本发明的再一个实施例提供一种阵列基板制造方法， 包括： 形成氧化物 半导体层， 形成像素电极图案以及在所述氧化物半导体层和所述像素电极图 案之间形成介电层， 其中形成所述氧化物半导体层包括：
沉积氧化物薄膜， 通过构图工艺形成包括氧化物半导体层的第一区域以 及氧化物半导体层的第二区域， 所述像素电极与所述氧化物半导体层的第二 区域重叠以形成储存电容， 所述氧化物半导体层的第二区域构成储存电容的 第一电极板， 所述与氧化物有源层第二区域相对应的像素电极构成储存电容 的第二电极板， 所述第一电极板与第二电极板之间的所述介电层构成储存电 容的介电质。
在一个示例中， 通过对氧化物半导体层的第二区域进行氢等离子体工艺 处理以形成包括第一电极板的图案， 所述第一电极板的电阻率小于 5>< 10"3Ω · cm。
在一个示例中， 所述氢等离子体处理工艺的处理时间为 150S, 处理功率 为 800 ~ 2000W, 氢等离子流量为 80SCCM。
在一个示例中， 所述介电层包括刻蚀阻挡层和 /或钝化层。 本发明申请提供的阵列基板、 显示装置及制作方法， 利用透明氧化物材 料形成储存电容的第一电极板， 使得形成的储存电容结构具有透光性， 从而 增加阵列基板的开口率， 降低显示装置发光所需的电流强度， 延长了显示装 置的使用寿命。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为 AMOLED阵列基板的驱动电路图；
图 2为本发明实施例阵列基板的布局示意图；
图 3为图 2所述阵列基板 A-A向的层间剖面示意图；
图 4为本发明实施例层间剖面示意图之二；
图 5为本发明实施例涂覆光刻胶处理氧化物有源层第二区域的示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例提供了一种阵列基板、 显示装置及制作方法， 通过透明氧 化物有源层的第二区域形成储存电容的第一电极板 ,增加阵列基板的开口率。
附图中各层薄膜厚度和区域大小形状不反映 AMOLED(Active Matrix OLED, 主动式矩阵有机发光二极管）阵列基板的真实比例， 目的只是示意说 明本发明内容。
下面结合下述附图对本发明实施例做详细描述。
本实施例提供一种 AMOLED的阵列基板， 所述阵列基板的驱动电路示 意图可参考图 1所示的电路图。 如图 1所示， 图 1为一种 AMOLED的像素 结构的驱动电路图，该像素单元电路结构包括两个薄膜晶体管以及一个电容。 栅线电连接于第一薄膜晶体管的栅电极， 数据线电连接于第一薄膜晶体管的 漏电极。栅线提供的电信号使第一薄膜晶体管处于导通 /关断状态； 当第一薄 膜晶体管打开时， 数据线提供的电信号使第二薄膜晶体管处于导通 /关断状 态； 当第二薄膜晶体管打开时， 电源线输入的信号通过第二薄膜晶体管驱动 AMOLED发光。
如图 2和图 3所示， 图 2为本发明实施例阵列基板像素单元的布局示意 图， 图 3为图 2中 A-A向的剖面图。 图 3为本发明薄膜晶体管的剖面图， 所 反映的是一个薄膜晶体管的结构。 本实施例薄膜晶体管的主体结构包括形成 在基板 1上的栅极 2、 栅绝缘层 3、 氧化物有源层、 刻蚀阻挡层 5、 源极 6、 漏极 7、 钝化层 8、 像素电极 9。 所述薄膜晶体管尤其包括氧化物有源层第一 区域 401以及氧化物有源层第二区域 402。例如，氧化物有源层第一区域 401 以及氧化物有源层第二区域 402在同一次构图工艺中形成， 当然， 也可以根 据需要使上述图案不在同一次构图工艺中形成。 所述像素电极 9与所述氧化 物有源层第二区域 402相对应的部分形成储存电容， 所述氧化物有源层第二 区域 402构成储存电容的第一电极板， 所述与氧化物有源层第二区域 402相 对应的像素电极 9构成储存电容的第二电极板， 所述第一电极板与第二电极 板之间的膜层构成储存电容的介电质。
例如， 如图 2所示， 本实施例 AMOLED阵列基板的主体结构包括栅线 11、 数据线 12、 电源线 13 , 数据线 12和电源线 13与栅线 11垂直， 并与两 个相邻的栅线 11一起限定了像素区域。像素区域内分别形成有作为寻址元件 的第一薄膜晶体管 （也称开关薄膜晶体管） 、 用于控制有机发光二极管的第 二薄膜晶体管 （也称驱动薄膜晶体管） 以及像素电极 9。 第一薄膜晶体管位 于栅线 11与数据线 12交叉点的位置，第二薄膜晶体管位于栅线 11与电源线 13交叉点的位置，其中第一薄膜晶体管的第一漏极 701通过第一过孔 111与 第二薄膜晶体管的第二栅极 202相连接， 亦或者将第一薄膜晶体管的第一漏 极 701设置在第二薄膜晶体管栅极所在位置， 直接作为第二栅极 202。
如图 2所示， 本实施例中第一栅极 201、 第二栅极 202、 栅线 11设置在 基板 1上并在同一次构图工艺中形成，其中第一栅极 201与栅线 11连接，第 二栅极 202不与栅线 11相连， 同时第一栅极 201与第二栅极 202不相连。栅 绝缘层 3形成在第一栅极 201、 第二栅极 202、 栅线 11上并覆盖整个基板 1。 通过第二次构图工艺形成包括氧化物有源层的图案， 其中， 氧化物有源层第 一区域 401 形成第一薄膜晶体管半导体沟道以及第二薄膜晶体管半导体沟 道， 第一薄膜晶体管半导体沟道设置在第一栅极 201上方， 第二薄膜晶体管 半导体沟道设置在第二栅极 202上方， 第一薄膜晶体管半导体沟道与第二薄 膜晶体管半导体沟道互不相连。 刻蚀阻挡层 5形成在氧化物有源层第一区域 401以及氧化物有源层第二区域 402上并覆盖整个基板 1。 然后， 数据线 12、 第一源极 601、 第一漏极 701及电源线 13、 第二源极 602、 第二漏极 702在 同一次构图工艺中形成， 其中， 第一源极 601的一端与数据线 12连接， 第一 源极 601和第一漏极 701之间通过第一薄膜半导体沟道区域相连； 第二源极 602的一端与电源线 13连接，第二源极 602和第二漏极 702之间通过第二薄 膜半导体沟道区域相连。 钝化层 8形成在数据线 12、 第一源极 601、 第一漏 极 701及电源线 13、 第二源极 602、 第二漏极 702上并覆盖整个基板 1。 然 后通过第四次构图工艺形成像素电极 9的图案。
需要说明的是， 阵列基板源极和漏极的名称， 因电流的流动方向不同而 异， 在本发明中为了方便描述， 将与像素电极相连接的称为漏极。
需要补充说明的是， 在形成刻蚀阻挡层 5后， 其上开设有第一过孔 111、 第二过孔 112, 其中第一过孔 111开设在第二栅极 202的上方， 穿透刻蚀阻 挡层 5、栅绝缘层 3到达第二栅极 202,第一漏极 701通过第一过孔 111与第 二栅极 202相连； 第二过孔 112开设在氧化物有源层第二区域 402的上方， 穿透刻蚀阻挡层 5到达氧化物有源层第二区域 402, 第一漏极 701通过第二 过孔 112与氧化物有源层第二区域 402相连。 在形成钝化层 8后， 其上开设 有第三过孔 113 ,其中第三过孔 113开设在第二漏极 702上方，穿透钝化层 8 到达第二漏极 702, 像素电极 9通过第三过孔 113与第二漏极 702相连。
将完成上述步骤的阵列基板中氧化物有源层第二区域 402与像素电极 9 相对应的部分称为重叠区域 10。 如图 2所示， 重叠区域 10即为储存电容所 在区域。 氧化物有源层第二区域 402构成储存电容的第一电极板， 与氧化物 有源层第二区域 402相对应的像素电极 9构成储存电容的第二电极板， 第一 电极板与第二电极板之间的膜层构成储存电容的介电质。 由于储存电容均由 透明材料构成， 因此储存电容呈现透光性。
另夕卜， 栅极、 栅线、 源极、 漏极以及数据线可为由钼（Mo )、 相铣合金 ( MoNb ) 、 铝 ( Al ) 、 铝钕合金 ( AlNd ) 、 钛 ( Ti ) 、 铬 ( Cr ) 、 铜 ( Cu ) 等中的任意一种或多种材料形成的单层或多层的复合叠层结构。 上述材质中 包含不透光的金属材料， 因此形成的栅极、 栅线、 源极、 漏极以及数据线结 构为不透光结构。 优选的， 栅极、 栅线、 源极、 漏极以及数据线为 Mo Al 或含 Mo Al 的合金组成的单层或多层复合膜结构， 其形成的膜层厚度为 100nm ~ 3000nm。
栅绝缘层可为由硅的氧化物（SiOx ) 、 硅的氮化物（SiNx ) 、 铪的氧化 物 （HfOx ) 、 硅的氮氧化物 （SiON ) 、 铝的氧化物 （AlOx )等中的任意一 种或任意两种材料形成的多层复合膜结构。 氧化物有源层由包含 In (铟） 、 Ga (镓） 、 Zn (辞） 、 0 (氧） 、 Sn (锡）等元素的薄膜形成， 其中该薄膜 中必须包含氧元素和其他两种或两种以上的元素， 例如氧化物有源层的材质 可为 IGZO (氧化铟镓辞）、 IZO (氧化铟辞 )、 InSnO (氧化铟锡 )、 InGaSnO (氧化铟镓锡）等。
刻蚀阻挡层、 钝化层可为由硅的氧化物（SiOx )、 硅的氮化物（SiNx ) 铪的氧化物 （HfOx ) 、 铝的氧化物 （AlOx ) 中的任意一种或任意两种材料 形成的多层复合透明膜层结构。 刻蚀阻挡层以及钝化层其特点 层中含有 较低的低氢含量， 并且具有很好的表面特性。
像素电极可为氧化铟锡（ιτο )或者氧化铟辞（izo )或者其它透明氧化 物制作而成。 以 ITO材质为例， 通常使用溅射成膜的方法制备形成非晶态的 ITO, 再通过退火工艺使之晶体化。 优选的， 像素电极的膜层厚度为 20 ~ 150
本发明实施例所述的阵列基板储存电容为平行板电容结构。 根据平行板 电容结构的计算公式， 所述储存电容满足 C=sS/½kd。 其中， ε为介电常数， S为储存电容的两极板的对应面积， d为储存电容的两极板间的距离， k是静 电力常量。 储存电容的两极板对应面积取决于氧化物有源层第二区域与像素 电极的相对应的区域， 极板间的距离取决于氧化物有源层第二区域与像素电 极之间夹置的膜层厚度。 因此， 通过调整对应的区域以及夹置的膜层厚度可 生成所需的储存电容。 另外， 本领域技术人员可以明白， 氧化物有源层第二 区域与像素电极的相对应的区域由氧化物有源层第二区域与像素电极共同决 定， 因此形成的相对应区域的形状可有多种可能， 例如： 形成的相对应的区 域可为长方形、 正方形、 三角形等常见形状或者不规则的形状。 另外， 形成 的相对应的区域还可由多块区域共同形成， 而不仅限于由一块区域形成。
需要说明的是， 本发明所述的阵列基板仅列举了底栅型结构， 本发明所 提及的技术方案也同样适用于顶栅型结构， 包括源漏极形成在基板上， 其上 依次形成钝化层、 氧化物有源层、 栅绝缘层以及栅极的结构； 也或者如图 4 所示， 包括氧化物有源层形成在基板上， 其上依次形成钝化层、 源漏极、 钝 化层、 栅绝缘层以及栅极的结构。 与底栅型结构的阵列基板相比， 共同点在 于氧化物有源层所起的作用以及氧化物有源层第二区域的设置， 因此， 顶栅 型结构的阵列基板同样适用于本技术方案， 以上所述两种结构的顶栅型结构 及其制造方法在此不再赘述。
另外， 需要说明的是， 本发明仅列举了 2T1C型像素结构的阵列基板， 即阵列基板中像素驱动电路中包括 2个薄膜晶体管以及一个电容。 氧化物有 源层包括氧化物有源层第一区域以及氧化物有源层第二区域， 氧化物有源层 第一区域用于构成薄膜晶体管的半导体沟道区域， 氧化物有源层第二区域用 于构成储存电容的第一电极板， 使得形成的储存电容具有可透光性， 最终增 加了阵列基板的开口率。 显然， 本发明所提及的技术方案形成的阵列基板也 可具有其它变化， 例如： 阵列基板的像素驱动电路由三个薄膜晶体管构成或 由四个薄膜晶体管构成， 与上述实施例阵列基板相比， 共同点在于氧化物有 源层所起的作用以及氧化物有源层第二区域的设置， 在此不作赘述。
本发明实施例的阵列基板， 利用透明氧化物有源层第二区域形成储存电 容的第一电极板、 与透明氧化物有源层第二区域对应的像素电极形成储存电 容的第二电极板， 使得形成的储存电容结构具有透光性， 从而增加阵列基板 的开口率， 降低显示装置发光所需的电流强度，延长了显示装置的使用寿命。
优选的， 此后， 对完成上述工艺的基板进行氢等离子体处理， 第一电极 板是由对氧化物有源层第二区域进行氢等离子体工艺处理形成的， 使得所述 第一电极板的电阻率小于 5χ10_3Ω · cm, 其导电性能更接近于金属电极板。
以用 IGZO ( In-Ga-Zn-Ox, 铟镓辞氧化物）作为氧化物有源层为例， 对 氧化物有源层第二区域进行氢等离子体处理， 处理过程通过反应离子刻蚀装 置或者等离子体增强型化学气相沉积装置来完成， 处理时间为 150S, 处理功 率为 800 ~ 2000W,处理使用的氢气流量为 80SCCM(英文： standard-state cubic centimeter per minute, 中文： 标况毫升每分）。 处理完成后， 氧化物有源层第 二区域的电阻率变为 l xl(T3Q . cm, 构成储存电容的第一电极板， 体现导体 特性； 而未经处理的氧化物有源层第一区域的电阻率大于 106Ω . cm, 构成 薄膜晶体管的半导体沟道区域， 体现半导体特性。
具体的， 如图 5所示， 本实施例中在基板上 1形成栅极 2以及栅线、 栅 绝缘层 3、氧化物有源层，通过一次构图工艺形成氧化物有源层第一区域 401 以及氧化物有源层第二区域 402的图案。 然后， 在上述基板上涂覆光刻胶， 经构图工艺除去氧化物有源层第二区域 402上方的光刻胶， 对完成上述工艺 的基板进行氢等离子体工艺处理， 以使经处理过程后的氧化物有源层第二区 域 402表现为导体特性。 具体的， 处理完成后， 氧化物有源层第二区域 402 的电阻率变为 1χ 10·3Ω . cm。 需要说明的是， 由于光刻胶的保护， 氧化物有 源层第一区域并不受氢等离子体工艺处理的影响， 因此， 在除去光刻^ ^， 氧化物有源层第一区域的电阻率仍大于 106Q . cm, 构成薄膜晶体管的半导 体沟道区域， 体现半导体特性。
进一步的， 所述阵列基板还包括刻蚀阻挡层和 /或钝化层， 所述第一电极 板与第二电极板之间的膜层包括钝化层和 /或刻蚀阻挡层。 钝化层和 /或刻蚀 阻挡层均为透明的绝缘膜层， 因此可用于构成储存电容的介电质结构。
进一步的， 氧化物有源层的材质为氧化铟镓辞、 氧化铟辞、 氧化铟锡或 者氧化铟镓锡。
进一步的， 所述刻蚀阻挡层以及所述钝化层分别为硅的氧化物、 硅的氮 化物、 铪的氧化物、 硅的氮氧化物或者铝的氧化物中的任意一种或多种形成 的透明单层或复合层结构。
本发明实施例的阵列基板， 利用透明氧化物有源层第二区域 402形成储 存电容的第一电极板、 与透明氧化物有源层第二区域 402对应的像素电极 9 形成储存电容的第二电极板， 使得形成的储存电容结构具有透光性， 从而增 加阵列基板的开口率， 降低显示装置发光所需的电流强度， 延长了显示装置 的使用寿命。
本发明的另一方面， 提供一种显示装置， 包括上述的阵列基板。 其中， 所述阵列基板的结构以及工作原理同上述实施例， 在此不再赘述。 另外， 显 示装置的其他部分的结构可以参考现有技术， 对此本文不再详细描述。 以上氧化物有源层的第一区域实际上构成了薄膜晶体管的有源层， 而氧 化物有源层的第二区域则构成了储存电容的一个电极板。 由于氧化物有源层 是由氧化物半导体层形成， 因此， 以上氧化物有源层的第一区域可以称为氧 化物半导体的第一区域， 以上氧化物有源层的第二区域可以称为氧化物半导 体层的第二区域。 如上所述， 可以对氧化物半导体层的第二区域进行氢等离 子体处理， 以使得其电阻率接近于金属电极的电阻率。
本发明实施例的显示装置， 其中的阵列基板利用透明氧化物材料形成储 存电容的第一电极板， 使得形成的储存电容结构具有透光性， 从而增加阵列 基板的开口率， 降低显示装置发光所需的电流强度， 延长了显示装置的使用 寿命。
本发明的再一方面， 提供一种阵列基板的制作方法， 包括以下步骤： 步骤 Sl、 在基板上沉积栅金属薄膜， 通过构图工艺形成包括栅极、 栅线 的图形；
步骤 S2、 在完成前述步骤的基板上形成栅绝缘层；
步骤 S3、在完成前述步骤的基板上沉积氧化物有源层薄膜， 通过构图工 艺形成包括氧化物有源层第一区域以及氧化物有源层第二区域的图形；
步骤 S4、在完成前述步骤的基板上形成刻蚀阻挡层薄膜， 通过构图工艺 形成包括刻蚀阻挡层、 刻蚀阻挡层第一过孔以及刻蚀阻挡层第二过孔， 所述 刻蚀阻挡层第一过孔位于栅极的所在位置， 穿透刻蚀阻挡层以及栅绝缘层到 达栅极， 过孔内露出栅极； 所述刻蚀阻挡层第二过孔位于氧化物有源层第二 区域的所在位置， 穿透刻蚀阻挡层到达氧化物有源层第二区域， 过孔内露出 氧化物有源层第二区域；
步骤 S5、在完成前述步骤的基板上沉积源漏金属薄膜， 通过构图工艺形 成包括源极、 漏极、 数据线及电源线的图形；
步骤 S6、在完成前述步骤的基板上沉积钝化层薄膜， 通过构图工艺形成 包括钝化层及钝化层过孔的图形， 所述钝化层过孔位于漏极的所在位置， 穿 透钝化层到达漏极， 过孔内露出漏极。
步骤 S7、在完成前述步骤的基板上沉积透明导电薄膜， 通过构图工艺形 成包括像素电极的图形， 所述像素电极通过过孔与漏极连接。
本发明实施例的阵列基板制造方法， 利用透明氧化物有源层第二区域构 成储存电容的第一电极板、 与透明氧化物有源层第二区域对应的像素电极形 成储存电容的第二电极板， 第一电极板与第二电极板之间的膜层构成储存电 容的介电质， 使得形成的储存电容结构具有透光性， 从而增加阵列基板的开 口率， 降低显示装置发光所需的电流强度， 延长了显示装置的使用寿命。
优选的， 通过对氧化物有源层第二区域进行氢等离子体工艺处理形成包 括第一电极板的图案， 所述第一电极板的电阻率小于 5χ10·3Ω · cm。
本发明优选实施例阵列基板制造方法包括：
步骤 S101、 采用磁控溅射或热蒸发的方法， 在基板上沉积栅金属薄膜， 采用普通掩模板通过构图工艺形成包括第一栅极、 第二栅极及栅线的图形； 步骤 S102、 采用旋转涂覆的方法涂覆一层栅绝缘层；
步骤 S103、采用等离子体增强化学气相沉积方法， 沉积氧化物有源层薄 膜， 通过构图工艺形成包括氧化物有源层第一区域以及氧化物有源层第二区 域的图形；
步骤 S104、在氧化物有源层薄膜上涂覆一层光刻胶， 通过构图工艺形成 暴露氧化物有源层第一区域的光刻胶图形； 在氢气条件下， 对完成以上步骤 的基板进行氢等离子体处理， 具体的处理时间为 150S , 处理功率为 800 ~ 2000W, 处理使用的氢气流量为 80SCCM处理完成后， 剥除上述基板上的光 刻胶；
步骤 S105、采用等离子体增强化学气相沉积方法，沉积刻蚀阻挡层薄膜， 并采用普通掩模板通过构图工艺形成包括第一过孔以及第二过孔的图形， 所 述第一过孔位于第二栅极的所在位置， 穿透刻蚀阻挡层、 栅绝缘层到达第二 栅极； 第二过孔位于氧化物有源层第二区域的所在位置， 穿透刻蚀阻挡层到 达氧化物有源层第二区域；
步骤 S106、 采用磁控溅射或热蒸镀的方法， 沉积源漏金属薄膜， 通过构 图工艺形成包括第一、 第二源极漏极、 数据线、 电源线的图形； 所述第一漏 极通过第一过孔、 第二过孔分别与第二栅极、 氧化物有源层第二区域连接； 步骤 S107、 采用等离子体增强化学气相沉积方法， 沉积钝化层薄膜， 并 采用普通掩模板通过构图工艺形成包括第三过孔的图形， 所述第三过孔位于 第二漏极的所在位置， 穿透钝化层到达第二漏极；
步骤 S108、 沉积透明导电薄膜， 通过构图工艺形成像素电极的图形， 所 述像素电极通过第三过孔与第二漏极连接。
本实施例是一种在完成氧化物有源层步骤后对氧化物有源层第二区域进 行氢等离子体处理的技术方案， 其制备过程已在前述技术方案中详细介绍， 这里不在赘述。
进一步的， 所述氢等离子体处理工艺的处理时间为 150S , 处理功率为
800 ~ 2000W, 氢等离子流量为 80SCCM。
进一步的， 所述阵列基板还包括刻蚀阻挡层和 /或钝化层， 所述第一电极 板与第二电极板之间的膜层包括钝化层和 /或刻蚀阻挡层。
本发明实施例的阵列基板制造方法， 利用透明氧化物有源层第二区域构 成储存电容的第一电极板、 与透明氧化物有源层第二区域对应的像素电极形 成储存电容的第二电极板， 使得形成的储存电容结构具有透光性， 从而增加 阵列基板的开口率， 降低显示装置发光所需的电流强度， 延长了显示装置的 使用寿命。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
I、 一种阵列基板， 包括： 薄膜晶体管和像素电极，
其中， 所述薄膜晶体管的有源层由氧化物半导体层的第一区域形成， 所述氧化物半导体层还包括第二区域， 所述像素电极与所述氧化物半导 体层的第二区域重叠以形成储存电容， 所述氧化物半导体层的第二区域构成 所述储存电容的第一电极板， 所述与氧化物半导体层的第二区域相对应的像 素电极构成所述储存电容的第二电极板， 并且
所述第一电极板与第二电极板之间设置有介电层。
2、根据权利要求 1所述的阵列基板， 其中， 所述第一电极板是由对氧化 物半导体的第二区域进行氢等离子体工艺处理形成的。
3、根据权利要求 1或 2所述的阵列基板， 其中， 所述第一电极板的电阻 率小于 5χ1(Τ3Ω · cm。
4、 根据权利要求 1-3中任一项所述的阵列基板， 其中， 所述氧化物半导 体层的第二区域的电阻率小于所述氧化物半导体层的第一区域的电阻率。
5、 根据权利要求 1-4中任一项所述的阵列基板， 其中， 所述氧化物半导 体层的第一区域与所述氧化物半导体层的第二区域相互隔离。
6、 根据权利要求 1-5中任一项所述的阵列基板， 其中， 所述第一电极板 与第二电极板之间的介电层包括钝化层和 /或刻蚀阻挡层。
7、 根据权利要求 1-6中任一项所述的阵列基板， 其中， 氧化物半导体层 的材质为氧化铟镓辞、 氧化铟辞、 氧化铟锡或者氧化铟镓锡。
8、根据权利要求 6所述的阵列基板， 其中， 所述刻蚀阻挡层以及所述钝 化层分别为硅的氧化物、 硅的氮化物、 铪的氧化物、 硅的氮氧化物或者铝的 氧化物中的任意一种或多种形成的透明单层或复合层结构。
9、根据权利要求 1-5中任一项所述的阵列基板， 所述第一电极板与第二 电极板之间的介电层包括刻蚀阻挡层和栅极绝缘层。
10、 一种显示装置， 包括权利要求 1-9中任一项所述阵列基板。
I I、 一种阵列基板制造方法， 包括： 形成氧化物半导体层， 形成像素电 极图案以及在所述氧化物半导体层和所述像素电极图案之间形成介电层， 其 中形成所述氧化物半导体层包括： 沉积氧化物薄膜， 通过构图工艺形成包括氧化物半导体层的第一区域以 及氧化物半导体层的第二区域， 所述像素电极与所述氧化物半导体层的第二 区域重叠以形成储存电容， 所述氧化物半导体层的第二区域构成储存电容的 第一电极板， 所述与氧化物有源层第二区域相对应的像素电极构成储存电容 的第二电极板， 所述第一电极板与第二电极板之间的所述介电层构成储存电 容的介电质。
12、根据权利要求 11所述的阵列基板的制作方法， 其中， 通过对氧化物 半导体层的第二区域进行氢等离子体工艺处理以形成包括第一电极板的图 案， 所述第一电极板的电阻率小于 5χ1(Τ3Ω · cm。
13、根据权利要求 12所述的阵列基板的制作方法， 其中， 所述氢等离子 体处理工艺的处理时间为 150S, 处理功率为 800 ~ 2000W, 氢等离子流量为 80SCCM。
14、 根据权利要求 11-13中任一项所述的阵列基板的制作方法， 其中， 所述介电层包括刻蚀阻挡层和 /或钝化层。
PCT/CN2013/077591 2013-03-28 2013-06-20 阵列基板、显示装置及制作方法 WO2014153870A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/353,580 US20150214249A1 (en) 2013-03-28 2013-06-20 Array Substrate, Display Device and Manufacturing Method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310104658.2 2013-03-28
CN2013101046582A CN103208506A (zh) 2013-03-28 2013-03-28 阵列基板、显示装置及制作方法

Publications (1)

Publication Number Publication Date
WO2014153870A1 true WO2014153870A1 (zh) 2014-10-02

Family

ID=48755676

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/077591 WO2014153870A1 (zh) 2013-03-28 2013-06-20 阵列基板、显示装置及制作方法

Country Status (3)

Country Link
US (1) US20150214249A1 (zh)
CN (1) CN103208506A (zh)
WO (1) WO2014153870A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107492555A (zh) * 2016-06-13 2017-12-19 三星显示有限公司 晶体管阵列面板

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI611566B (zh) * 2013-02-25 2018-01-11 半導體能源研究所股份有限公司 顯示裝置和電子裝置
JP2016001712A (ja) * 2013-11-29 2016-01-07 株式会社半導体エネルギー研究所 半導体装置の作製方法
CN104752345B (zh) * 2015-04-27 2018-01-30 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及其制作方法
CN104965336A (zh) * 2015-07-30 2015-10-07 深圳市华星光电技术有限公司 Coa阵列基板及液晶面板
KR102438782B1 (ko) * 2015-11-26 2022-09-01 엘지디스플레이 주식회사 표시장치와 이의 제조방법
US10790318B2 (en) 2016-11-22 2020-09-29 Semiconductor Energy Laboratory Co., Ltd. Display device, method for manufacturing the same, and electronic device
KR102568285B1 (ko) * 2017-12-28 2023-08-17 엘지디스플레이 주식회사 유기발광표시패널 및 이를 이용한 유기발광표시장치
KR102615707B1 (ko) * 2017-12-29 2023-12-18 엘지디스플레이 주식회사 유기발광표시패널 및 이를 이용한 유기발광표시장치
CN207909879U (zh) 2018-03-28 2018-09-25 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置
CN108428730B (zh) * 2018-05-16 2021-01-26 京东方科技集团股份有限公司 Oled显示基板及其制作方法、显示装置
US10861929B2 (en) * 2018-06-27 2020-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Electronic device including a capacitor
CN109244107B (zh) * 2018-07-20 2021-01-01 Tcl华星光电技术有限公司 Oled背板及其制作方法
CN109119440B (zh) * 2018-07-20 2020-12-25 Tcl华星光电技术有限公司 Oled背板及其制作方法
CN109256396A (zh) * 2018-09-04 2019-01-22 京东方科技集团股份有限公司 一种透明显示基板及透明显示面板
CN110047892A (zh) * 2019-04-22 2019-07-23 深圳市华星光电半导体显示技术有限公司 白光有机发光二极管显示器
CN110265406A (zh) * 2019-06-06 2019-09-20 深圳市华星光电技术有限公司 阵列基板及制作方法
CN110783490A (zh) * 2019-11-13 2020-02-11 合肥京东方卓印科技有限公司 显示面板及其制备方法
CN111384070B (zh) * 2020-03-25 2023-05-19 京东方科技集团股份有限公司 一种像素结构、阵列基板、显示装置和制作方法
CN111584577A (zh) 2020-05-14 2020-08-25 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法
EP4364540A1 (en) * 2021-06-28 2024-05-08 Emagin Corporation Monolithically integrated top-gate thin-film transistor and light-emitting diode and method of making
CN114089570B (zh) * 2021-11-22 2023-11-10 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板及显示装置
CN115312546A (zh) * 2022-10-10 2022-11-08 广州华星光电半导体显示技术有限公司 阵列基板及其制备方法、显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102208406A (zh) * 2010-03-30 2011-10-05 元太科技工业股份有限公司 一种像素的结构及其制程方法
CN102314031A (zh) * 2010-07-01 2012-01-11 群康科技(深圳)有限公司 液晶显示器用的薄膜晶体管阵列板
CN102543863A (zh) * 2012-02-06 2012-07-04 深圳市华星光电技术有限公司 一种薄膜晶体管阵列基板及其制作方法
CN102790012A (zh) * 2012-07-20 2012-11-21 京东方科技集团股份有限公司 阵列基板的制造方法及阵列基板、显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6677613B1 (en) * 1999-03-03 2004-01-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
TWI429327B (zh) * 2005-06-30 2014-03-01 Semiconductor Energy Lab 半導體裝置、顯示裝置、及電子設備
EP1793366A3 (en) * 2005-12-02 2009-11-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display device, and electronic device
US9069219B2 (en) * 2010-08-07 2015-06-30 Sharp Kabushiki Kaisha Thin film transistor substrate and liquid crystal display device provided with same
CN102361033B (zh) * 2011-10-13 2013-09-11 福州华映视讯有限公司 显示面板的画素结构及其制作方法
CN102789099A (zh) * 2012-07-16 2012-11-21 北京京东方光电科技有限公司 一种液晶显示器像素结构、阵列基板以及液晶显示器
US9514673B2 (en) * 2012-11-22 2016-12-06 Lg Display Co., Ltd. Organic light emitting display device
CN203118952U (zh) * 2013-03-28 2013-08-07 京东方科技集团股份有限公司 阵列基板、显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102208406A (zh) * 2010-03-30 2011-10-05 元太科技工业股份有限公司 一种像素的结构及其制程方法
CN102314031A (zh) * 2010-07-01 2012-01-11 群康科技(深圳)有限公司 液晶显示器用的薄膜晶体管阵列板
CN102543863A (zh) * 2012-02-06 2012-07-04 深圳市华星光电技术有限公司 一种薄膜晶体管阵列基板及其制作方法
CN102790012A (zh) * 2012-07-20 2012-11-21 京东方科技集团股份有限公司 阵列基板的制造方法及阵列基板、显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107492555A (zh) * 2016-06-13 2017-12-19 三星显示有限公司 晶体管阵列面板
CN107492555B (zh) * 2016-06-13 2023-06-23 三星显示有限公司 晶体管阵列面板

Also Published As

Publication number Publication date
US20150214249A1 (en) 2015-07-30
CN103208506A (zh) 2013-07-17

Similar Documents

Publication Publication Date Title
WO2014153870A1 (zh) 阵列基板、显示装置及制作方法
EP2800140B1 (en) Thin film transistor, array substrate and manufacturing method thereof, and display device
US9548321B2 (en) Method of manufacturing thin film transistor (TFT) array substrate
TWI570493B (zh) 顯示裝置和製造其之方法
TWI556450B (zh) 薄膜電晶體陣列基板及其製造方法
KR101991338B1 (ko) 박막트랜지스터 어레이 기판 및 그 제조방법
US8445301B2 (en) Thin-film transistor substrate, method of manufacturing the same, and display device including the same
US9202896B2 (en) TFT, method of manufacturing the TFT, and method of manufacturing organic light emitting display device including the TFT
WO2016041304A1 (zh) 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置
WO2013137045A1 (ja) 半導体装置およびその製造方法
JP2008311616A (ja) 薄膜トランジスタ表示板及びその製造方法
CN103208525B (zh) 一种薄膜晶体管及其制造方法、阵列基板和显示器件
WO2021036840A1 (zh) 显示基板及其制造方法、显示装置
US20160343739A1 (en) Thin film transistor, method of manufacturing thin film transistor, array substrate and display device
WO2013150981A1 (ja) 半導体装置およびその製造方法
JP2014225627A (ja) 酸化物薄膜トランジスタ及びその製造方法
JP2007212699A (ja) 反射型ｔｆｔ基板及び反射型ｔｆｔ基板の製造方法
KR20110083307A (ko) 박막 트랜지스터 기판 및 그 제조 방법
KR20150061302A (ko) 표시 기판, 표시 기판의 제조 방법 및 표시 기판을 포함하는 표시 장치
TWI557894B (zh) 有機發光顯示裝置及其製造方法
KR102471021B1 (ko) 박막 트랜지스터 표시판 및 이의 제조 방법
WO2015000247A1 (zh) 阵列基板、阵列基板的制备方法以及显示装置
KR102080484B1 (ko) 액정표시장치용 어레이기판 및 그의 제조방법
KR20140031671A (ko) 박막 트랜지스터 및 그 제조 방법
KR20150042989A (ko) 유기 발광 다이오드 디스플레이 장치 및 이의 제조 방법

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14353580

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13880564

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205 DATED 21-01-2016)

122 Ep: pct application non-entry in european phase

Ref document number: 13880564

Country of ref document: EP

Kind code of ref document: A1