WO2014139851A1 - Élément support comportant un substrat à semi-conducteurs pour composants électroniques et procédé de fabrication - Google Patents

Élément support comportant un substrat à semi-conducteurs pour composants électroniques et procédé de fabrication Download PDF

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Publication number
WO2014139851A1
WO2014139851A1 PCT/EP2014/054303 EP2014054303W WO2014139851A1 WO 2014139851 A1 WO2014139851 A1 WO 2014139851A1 EP 2014054303 W EP2014054303 W EP 2014054303W WO 2014139851 A1 WO2014139851 A1 WO 2014139851A1
Authority
WO
WIPO (PCT)
Prior art keywords
carrier component
semiconductor substrate
cores
layer
compensation
Prior art date
Application number
PCT/EP2014/054303
Other languages
German (de)
English (en)
Inventor
Harry Hedler
Markus Schieber
Jörg ZAPF
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO2014139851A1 publication Critical patent/WO2014139851A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a support member with a semiconducting ⁇ ter-substrate having a first side and a second side for SMD mounting.
  • ⁇ is an assembly of so-called SMD components (ie
  • the carrier component is provided with vias, each consisting of a via hole connecting the first side to the second side and an electrically conductive via core in the via hole. Vias serve to contact devices and terminals, each located on different sides of the substrate.
  • the electrically conductive via core is provided.
  • the carrier component generally has a lower coefficient of thermal expansion SU than the via cores with v i a . This is related to the fact that the via cores are usually metallic, while the carrier component consists of a semiconductor.
  • Carrier components for SMD mounting are known per se.
  • such a carrier component is described in US 2002/0088116 A1, which is used as an intermediate component between a printed circuit board and chip components.
  • a plurality of vias is provided, each having metallic cores Via aufwei- sen.
  • the material of the intermediate component is chosen such that it is adapted to that of the assembled chips with regard to its thermal expansion behavior, so that the voltages occurring between the intermediate component and the chip components can be limited.
  • stresses occur even within this intermediate component, which comes as a carrier component for use, in which the electric charge Ver ⁇ bond.
  • the object of the invention is to provide a carrier component for the SMD assembly, which is equipped with vias and which has a high reliability even under thermal stress.
  • the compensation layer causes a complete adaptation of the Ausdeh ⁇ voltage behavior of the coated semiconductor substrate to the thermal expansion behavior of the Via cores. Since the thermal expansion coefficients of the materials used are substantially linear, such expansion compensation can take place independently of a certain temperature. With the adaptation of the cherriesausdehnungsverhal ⁇ least an axial compensation for the thermal expansion is thus created so that there is no axial tension to the components involved. More particularly, the via core can not stress-related detached from the contact pads however, which are brought to the first side and the second side of the semi ⁇ conductor substrate for the purpose of making contact with the SMD-mounting on ⁇ and the via holes on the both sides abde ⁇ ck.
  • the second measure, Via cores in the via holes with ei ⁇ ner loose fit, has the advantage that the Via cores also can expand radially when heated within the via holes and in this case neither a strain takes place with the semiconductor substrate, nor an axial movement of the via core is hindered due to its thermal expansion. As a result, it is advantageously possible to create a largely stress-relieved bond for a specific temperature range.
  • the clearance is present at room temperature, since the carrier component is heated during operation and the dimensional tolerances of the clearance in the sequence for expansion are available.
  • no interference fit should be produced in operation ⁇ temperature due to increased thermal expansion of the viaducts core, ie that the via core has so greatly expanded that because of the popu ⁇ marginalized installation space in the via hole already a strain of the via core takes place with the carrier component.
  • a clearance is to be understood as a fit in which, for the internal dimension, only positive deviations from the nominal dimension and from the external dimension are permitted only negative deviations from the nominal dimension. This ensures that account the fact also taking into that set ferti ⁇ supply caused in the manufacture of the inner dimension (via hole) and the outer dimension (Via core) tolerances always a clearance between the via hole and the Via core is present.
  • both an axial compensation and a radial compensation are provided for the via connections, which reduces or even precludes the occurrence of stresses during the heating of the carrier component.
  • the carrier component preferably serves as an intermediate component, on the first side of which semiconductor components, such as, for example, are provided.
  • B. chip components can be mounted (SMD assembly).
  • the support member itself can be mounted on a circuit board by means of SMD mounting.
  • the semiconductor substrate is preferably made of silicon, the vias also being referred to as TSV (Through Silicon Via). Within the via holes can be a
  • Layer can be applied, which is located between the via cores and the walls of the via holes. This can take on different functions. The adhesion and friction of the via core in the via hole can be reduced by means of the layer, whereby a sliding of the via core in the via hole is still limited possible when the clearance changes due to the thermal expansion of the via core in a transitional fit.
  • the layer may provide the function of electrical isolation between the via core and the surrounding semiconductor substrate.
  • treadmill is intended that for the thickness d of the compensating layer coa t ⁇ ratio in comparison to the thickness of the semiconductor substrate SU d b where:
  • the compensating layer of a photoresist such as. B. SU-8, or consists of a silicone.
  • a photoresist such as. B. SU-8
  • silicone a material which have a comparatively large coefficient of thermal expansion, so that even at relatively low layer thicknesses an expansion compensation for the semiconductor substrate, which consists in particular of silicon, can be created.
  • SU-8 is a product of the company
  • Microchem - this is a trade name.
  • the tolerances t of the clearance fit are so small that the via cores are held in the via holes at room temperature. This means that the via core is not so loose at room temperature due to the tolerances that its own weight is sufficient for it to slip out of the via hole. It should be noted that even with the provision of a clearance due to tolerances due to a contact of the via core with the walls of the via hole, which may also be caused by the fact that the via core is slightly tilted in the via hole. By blocking the via core in the via hole, the handling of the carrier component prior to the production of the via contacts is advantageously considerably simplified. In order to obtain suitable tolerances t for such a design, tolerances according to DIN 7157 may preferably be provided which cause a sliding fit or a tight running fit.
  • a contact ⁇ layer of an electrically conductive material is applied to the compensating layer, which is in contact with the via cores in the region of the vias.
  • This contact layer can be Prozes ⁇ Siert in a suitable manner, so that contact pads and circuit traces on the compensation layer formed.
  • a contact layer can also be applied directly to the semiconductor substrate on the side on which no compensation layer is present on the semiconductor substrate. If the semiconductor substrate may be provided on both the first and on the second side with a balancing layer, it may also particularly advantageous both from ⁇ same layers a contact layer may be provided.
  • the invention relates to a method for producing a carrier component from a semiconductor substrate having a first side and a second side for SMD mounting.
  • the semiconductor substrate is provided with via holes, which respectively connect the first side to the second side.
  • electrically conductive via cores are produced.
  • the semiconductor substrate has a lower thermal expansion coefficient than the via cores ( SUb ⁇ o v ⁇ a ).
  • Ben is known for the production of the aforementioned carrier component.
  • the production of via cores in via holes can be carried out, for example, according to DE 10 2009 043 414 A1.
  • a further object of the invention is thus to improve the method given ⁇ in that can be generated with this insensitive to thermal stress structure of the support member. This object is achieved with the said method erfindungsge ⁇ Gurss in that a compensation layer is formed on the semiconductor substrate at ⁇ least on one of said sides prepared, the thermal expansion coefficients a
  • the composite of semiconductor substrate and compensation substrate is heated before the via cores are produced.
  • heating in the sense of the invention is meant that the composite of semiconductor substrate and leveling layer should have a temperature which is higher than the room temperature.
  • the composite of the semiconductor substrate and balancing layer to be so brought ⁇ even to a temperature which is equal to or higher than the intended operating temperature of the carrier component.
  • the via core can completely fill the via hole during production without the clearance required by the invention having to be produced directly. If the composite of the carrier component and the via core is subsequently cooled, the via core shrinks more strongly in the radial direction than the via hole Cooling to room temperature creates a gap between the walls of the via hole and the via core. This automatically creates a clearance fit, wherein the operation of the carrier component after SMD assembly and reaching the operating temperature of this game is used up because of the stronger radial expansion of the via core.
  • the shrinkage due to cooling similar or (ie, the semiconductor substrate including the compensation layer), as this according to the invention reached with a "Stretch ⁇ balancing" via the equalizing layer is equal to that of the surrounding support member.
  • the Via cores may galvanically ⁇ to.
  • the metal is then deposited on the walls of the via holes.
  • This is also referred to as galvanic filling, which can be current-bound or de-energized.
  • galvanic filling which can be current-bound or de-energized.
  • a deposition at temperatures of 80 ° C to 150 ° C is possible. Although these electrolyte temperatures do not completely prevent lateral stress at higher operating temperatures, they still reduce it sufficiently.
  • the adhesion of the electrically su ⁇ different via core on the wall must be low.
  • a starting layer for electroplating can be used, which can simultaneously fulfill the tasks of electrical insulation and a reduction in adhesion (for example a plastic layer with embedded metal particles for initiating the electrochemical deposition).
  • the via cores are produced by filling the via holes with liquefied, metallic material.
  • This method is described in the above-ge ⁇ called DE 10 2009 043 414 AI and can therefore be described as the art belong.
  • a molten conductive flues ⁇ stechnik is filled in the vias at high temperature, which has this non-wetting walls. So there is no adhesion after the solidification and cooling of the via cores, so that they are different from solve the walls of the via holes. Since the metal of the vias becomes molten is introduced into the via holes, via ⁇ this high temperatures of 500 to 800 ° C for example in copper or aluminum alloys are possible.
  • the walls of the via holes may, for example, of silicon oxide, silicon nitride, of polymers, or ceramics prepared ⁇ the.
  • the metal alloys from which the via cores are to be made are, in comparison, difficult to wetting. Further details of the invention are described below with reference to the drawing. Identical or corresponding drawing elements are each provided with the same stressesszei ⁇ chen and are only explained several times as far as differences arise between the individual figures. Show it:
  • FIG. 1 to 3 selected stages of an embodiment of the inventive beam assembly ⁇ , partly in the application of an embodiment of the method according to the invention respectively in section
  • Figure 5 shows the side view of a support member mounted on a substrate and two
  • a semiconductor substrate 11 is coated with a compensation layer 13 to form a first side 12.
  • the layer material may be, for example, a
  • a via hole 15 (and further not shown) is introduced into the carrier component 14 formed from the semiconductor substrate 11 and the equalization ⁇ layer 13, which connects the first side 12 of the support member with the second side 16.
  • the via hole 15 may be in the semiconductor substrate
  • Herge ⁇ represents, for example by means of etching in a conventional manner.
  • a masking of the sides lying in the etching treatment above is made te 16 of the semiconductor substrate 11, wherein the etching treatment ⁇ is passed through suitable mask openings. This process itself is well known.
  • FIG. 2 shows how the via hole is produced at a production temperature T P greater than the operating temperature of the mounted carrier component T w .
  • T P the already mentioned method of filling the via holes 15 (see Figure 1) with a liquid metal is used.
  • a via core 17 made of copper or aluminum forms, which conforms to walls 18 of the via holes 15.
  • the via core 17 is slide in the via hole 15.
  • the end faces 20 of the via cores 17 are connected on the first side 12 and on the second side 16 with electrically conductive contact layers from which unspecified dargestell ⁇ te contact pads or printed conductors can be produced in the further course of manufacture. These then enable the intended SMD assembly. Consequently For example, an electric current can be conducted from one contact layer 21 via the via core 17 into the other contact layer 21.
  • the finished support member 14 is to erken ⁇ NEN. This is shown in various states, namely at room temperature T R and at operating temperature T w . The two states are ge ⁇ separated via a breaking line 22 each other, thus one and the same via is shown in different states.
  • the wall is formed on both sides of the book line by a layer 23. This layer initially produces an electrical insulation to the silicon material of the semiconductor substrate 11. In addition, this layer facilitates the sliding of the via core 17 in the via hole 15.
  • the carrier component 14 room tempera ⁇ ture T R. It can be seen that the via core 17 is spaced from the wall 18 of the via hole to form a gap 19. Via the core further comprises a Lekssaus ⁇ strain, which corresponds exactly to the thickness of the support member fourteenth In this case, the thickness d of the carrier component corresponds to the thickness d SUb of the semiconductor substrate 11 plus the thickness of the two compensation layers d coa t according to FIG. 4. In contrast to FIG. 3, according to FIG. 4, the compensation layer is subdivided into two partial compensation layers 13a, 13b. wherein each of the first side 12 and the second side 16 is such a partial compensation layer. Right the fault line the carrier component is shown at Radiotem ⁇ temperature T w.
  • the Trä ⁇ gerbauteil has extended so that it now has a larger thickness d.
  • the length of the via core has spread by the same Be ⁇ support as the support member (see FIG. 4: by the amount of each ⁇ 1), so that the connection between the via-core 17 and the contact layer 21 is present largely verspan ⁇ voltage overhead ,
  • the via core 17 has also extended in the lateral direction, with the gap t returning. has formed.
  • the via core now lies on the layer 19. Via Looking at the core 17 at its edges k, which limit the lateral surface, one can clearly see Ver ⁇ shift ⁇ 1 by comparing the right and left part of the figure here.
  • FIG. 5 shows a mounting example for the carrier component 14.
  • the semiconductor substrate 11 and the compensation ⁇ layer 13 can be seen in the side view.
  • the contact pads 24 are shown, which consists of the jeweili ⁇ gen contact layers 21 (see FIG. 3) are processed. These contact pads form with the corresponding
  • the support member 14 is mounted on a substrate 28 ( beispielswei ⁇ se a circuit board). Also, on the

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

La présente invention concerne un élément support (14) composé d'un substrat à semi-conducteurs (11) et présentant des vias (17) pour l'interconnexion. L'invention concerne également un procédé de fabrication d'un tel élément support. Selon l'invention, les vias sont insérés dans l'ouverture pour via avec un jeu (t) à température ambiante (TR). Ce jeu sert à la dilatation du noyau du via dans le via (17) de telle manière que le via puisse glisser dans le trou pour via de l'ordre de la valeur (Δl) dès que l'élément support (14) se dilate en raison de la chaleur. La dilatation de l'élément support (14) est réglée au moyen de chariots de compensation (13a, 3b), par exemple en silicone, de telle manière que celle-ci corresponde exactement à la dilatation axiale du noyau de via. Le jeu (t) et la compensation de dilatation permettent de garantir que la liaison composée du via (17) et de plots de contact (21) en métal est libre de déformations, même à température ambiante (TR). Ceci augmente avantageusement la fiabilité des composants.
PCT/EP2014/054303 2013-03-13 2014-03-06 Élément support comportant un substrat à semi-conducteurs pour composants électroniques et procédé de fabrication WO2014139851A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102013204337.6 2013-03-13
DE201310204337 DE102013204337A1 (de) 2013-03-13 2013-03-13 Trägerbauteil mit einem Halbleiter-Substrat für elektronische Bauelemente und Verfahren zu dessen Herstellung

Publications (1)

Publication Number Publication Date
WO2014139851A1 true WO2014139851A1 (fr) 2014-09-18

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DE (1) DE102013204337A1 (fr)
WO (1) WO2014139851A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109389903A (zh) * 2017-08-04 2019-02-26 京东方科技集团股份有限公司 柔性基板及其加工方法、加工***

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US6010769A (en) * 1995-11-17 2000-01-04 Kabushiki Kaisha Toshiba Multilayer wiring board and method for forming the same
US20020088116A1 (en) 2000-09-19 2002-07-11 International Business Machines Corporation Method of making a CTE compensated chip interposer
US20100289155A1 (en) * 2009-05-15 2010-11-18 Shinko Electric Industries Co., Ltd. Semiconductor package
DE102009043414A1 (de) 2009-09-29 2011-06-09 Siemens Aktiengesellschaft Dreidimensionale Mikro-Struktur, Anordnung mit mindestens zwei dreidimensionalen Mikro-Strukturen, Verfahren zum Herstellen der Mikro-Struktur und Verwendung der Mikro-Struktur

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US5454928A (en) * 1994-01-14 1995-10-03 Watkins Johnson Company Process for forming solid conductive vias in substrates
JP3967239B2 (ja) * 2001-09-20 2007-08-29 株式会社フジクラ 充填金属部付き部材の製造方法及び充填金属部付き部材
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KR20110050957A (ko) * 2009-11-09 2011-05-17 삼성전자주식회사 반도체 소자의 관통 비아 콘택 및 그 형성 방법
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US8816505B2 (en) * 2011-07-29 2014-08-26 Tessera, Inc. Low stress vias

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Publication number Priority date Publication date Assignee Title
US6010769A (en) * 1995-11-17 2000-01-04 Kabushiki Kaisha Toshiba Multilayer wiring board and method for forming the same
US20020088116A1 (en) 2000-09-19 2002-07-11 International Business Machines Corporation Method of making a CTE compensated chip interposer
US20100289155A1 (en) * 2009-05-15 2010-11-18 Shinko Electric Industries Co., Ltd. Semiconductor package
DE102009043414A1 (de) 2009-09-29 2011-06-09 Siemens Aktiengesellschaft Dreidimensionale Mikro-Struktur, Anordnung mit mindestens zwei dreidimensionalen Mikro-Strukturen, Verfahren zum Herstellen der Mikro-Struktur und Verwendung der Mikro-Struktur

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109389903A (zh) * 2017-08-04 2019-02-26 京东方科技集团股份有限公司 柔性基板及其加工方法、加工***
US11430351B2 (en) 2017-08-04 2022-08-30 Boe Technology Group Co., Ltd. Processing method and processing system of a flexible substrate

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