WO2014134862A1 - 移位寄存器、栅极驱动电路、阵列基板以及显示装置 - Google Patents

移位寄存器、栅极驱动电路、阵列基板以及显示装置 Download PDF

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Publication number
WO2014134862A1
WO2014134862A1 PCT/CN2013/075072 CN2013075072W WO2014134862A1 WO 2014134862 A1 WO2014134862 A1 WO 2014134862A1 CN 2013075072 W CN2013075072 W CN 2013075072W WO 2014134862 A1 WO2014134862 A1 WO 2014134862A1
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Prior art keywords
level
thin film
shift register
film transistor
node
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PCT/CN2013/075072
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English (en)
French (fr)
Inventor
马占洁
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2015560520A priority Critical patent/JP6077681B2/ja
Priority to EP13861499.5A priority patent/EP2966649B1/en
Priority to US14/366,650 priority patent/US9472303B2/en
Priority to KR1020147017868A priority patent/KR101639496B1/ko
Publication of WO2014134862A1 publication Critical patent/WO2014134862A1/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present invention relates to the field of display devices, and in particular, to a shift register, a gate drive circuit, an array substrate, and a display device. Background technique
  • the gate driver unit is usually integrated on the array substrate to form a GOA unit by using an array driver (LED: Gate) technology.
  • the gate drive technology mainly uses a shift register to achieve the purpose of scan driving.
  • the inventors have found that at least the following problems exist in the prior art: taking the shift register structure as shown in FIG. 1 as an example, including the first to sixth thin film transistors M1' to M6' and a first capacitor C1', wherein the thin film transistors are all P-type thin film transistors, and an enable level of the thin film transistor is a low level (the enable level of the thin film transistor refers to a corresponding electric power when the thin film transistor is turned on)
  • the enable level of the thin film transistor refers to a corresponding electric power when the thin film transistor is turned on
  • the low-level control P-type thin film transistor is turned on, so the enable level of the P-type thin film transistor is low level
  • the high-level control P-type thin film transistor is turned off, so the P-type The non-enable level of the thin film transistor is high level).
  • the first node A' is input with a low level, the third node C is input with a high level; in the second phase T2, the first node A' is input with a high level, The third node C is input with a high level; in the third phase T3, the first node A' is input to a low level, and the third node C is floated and maintained at a high level; in the fourth stage T4, the first node A' Floating and keeping low, while the fifth thin film transistor M5' is turned on, so the residual level of the third node C interferes with the first node A', affecting the on state of the sixth thin film transistor M6',
  • the above shift register generates a drift phenomenon when the voltage is pulled high, resulting in instability of the output signal, which affects the operational reliability of the shift register. Summary of the invention Embodiments of the present invention provide a shift register, a gate driving circuit, an array substrate, and a display device, which can effectively improve the drift phenomenon of
  • the embodiment of the present invention adopts the following technical solutions:
  • a shift register comprising:
  • a shift register input terminal comprising a start signal input end, a first clock signal input end and a second clock signal input end;
  • a precharge circuit in response to the start signal and the first clock signal, outputting a first turn-on level and a second turn-on level
  • a first pull-up circuit that outputs a high level in response to an enable level of the start signal and an enable level of the first clock signal under control of the first turn-on level
  • a pull-down circuit responsive to a non-enable level of the start signal, a non-enable level of the first clock signal, and a second clock signal under control of the second turn-on level Energy level, output ⁇ level;
  • a second pull-up circuit when the second turn-on level is a non-enable level, output a high level; a shift register output end connected to the output end of the first pull-up circuit, the pull-down The output of the circuit and the output of the second pull-up circuit output a level signal.
  • the second pull-up circuit includes: a reverse circuit and a pull-up sub-circuit, wherein the reverse circuit outputs a high level when the second turn-on level is an enable level, and When the second conduction level is a non-enabling level, the output is low;
  • the pull-up sub-circuit outputs a high level in response to a low level of the output of the reverse circuit.
  • the pre-charging circuit includes: a first thin film transistor, a second thin film transistor, a first node, a second node, and a first capacitor, wherein
  • a first thin film transistor having a gate connected to the first clock signal input terminal, a source connected to the start signal input end, and a drain connected to the second node;
  • a second thin film transistor having a gate connected to the second node, a source connected to the start signal input end, and a drain connected to the first node;
  • a first node configured to output a first turn-on level of the pre-charge circuit
  • the first capacitor has one end connected to the second node and the other end connected to the shift register output.
  • the first pull-up circuit includes: a third thin film transistor having a gate connected to the first node, a source connected to a high level, and a drain connected to the shift register output end.
  • the pull-down circuit includes: a fourth thin film transistor having a gate connected to the second node, a source connected to the second clock signal input terminal, and a drain connected to the shift register output end.
  • the reverse circuit includes: a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, and a third node, wherein
  • a fifth thin film transistor having a gate connected to the second node, a source connected to the high level, and a drain connected to the third node;
  • a sixth thin film transistor having a gate connected to a source of the seventh thin film transistor, a source connected to a low level, and a drain connected to the third node;
  • a seventh thin film transistor having a gate connected to a low level, a source connected to a gate of the sixth thin film transistor, and a drain connected to a low level;
  • the third node is the output of the reverse circuit.
  • the pull-up sub-circuit includes: an eighth thin film transistor having a gate connected to the third node, a source connected to the high voltage, and a drain connected to the output of the shift register.
  • a gate drive circuit comprising a shift register as described above.
  • An array substrate comprising a gate drive circuit as described above.
  • a display device comprising the array substrate as described above.
  • Embodiments of the present invention provide a shift register, a gate driving circuit, an array substrate, and a display device, which eliminates the situation that multiple floating nodes interfere with each other to affect the characteristics of the output end, and can effectively improve the drift phenomenon of the output signal and improve the shift.
  • the bit register works stably.
  • 1 is a circuit diagram of a prior art shift register
  • FIG. 3 is a structural block diagram of a shift register according to an embodiment of the present invention.
  • FIG. 4 is a schematic circuit diagram of a shift register according to an embodiment of the present invention.
  • FIG. 5 is a timing waveform diagram of a shift register according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention.
  • FIG. 4 is a timing waveform diagram of a gate driving circuit according to an embodiment of the present invention. detailed description
  • an embodiment of the present invention provides a shift register, including: a shift register input terminal, a precharge circuit 1, a first pull-up circuit 2, a pull-down circuit 3, a second pull-up circuit 4, and Shift register output 6, wherein
  • the shift register input terminal includes a start signal input terminal 51, a first clock signal input terminal 52, and a second clock signal input terminal 53.
  • the pre-charging circuit 1 outputs a first on-level VI and a second on-level V2 in response to the start signal STV and the first clock signal CLK; it should be noted that the first on-level VI and the second The turn-on level V2 is both responsive to the start signal STV and the first clock signal CLK, but the first turn-on level VI is different from the second turn-on level V2: the first turn-on level VI is used to control the first The pull-up circuit 2 and the second turn-on level V2 are used to control the pull-down circuit 3 and the second pull-up circuit 4.
  • the first pull-up circuit 2 outputs a high level in response to the enable level of the start signal STV and the enable level of the first clock signal CLK under the control of the first turn-on level VI.
  • Pulling down circuit 3 in response to the start signal STV, under the control of the second conduction level V2
  • the second pull-up circuit 4 outputs a high level when the second turn-on level V2 is a non-energized level.
  • the shift register output terminal 6 is connected to the output terminal of the first pull-up circuit 2, the output terminal of the pull-down circuit 3, and the output terminal of the second pull-up circuit 4, and outputs a VOUTUT level signal.
  • the second pull-up circuit 4 includes: a reverse circuit 401 and a pull-up sub-circuit 402, wherein
  • the reverse circuit 401 outputs a high level when the second turn-on level V2 is an enable level, and outputs a low level when the second turn-on level V2 is a disable level;
  • the pull-up sub-circuit 402 outputs a high level in response to a low level of the output of the reverse circuit.
  • the shift register of the present invention will be further described below in conjunction with specific embodiments.
  • the thin film transistor in the following embodiment takes a P-type thin film transistor as an example, the enable level is a low level, and the non-enable level is a high level. It should be noted that the enable level of the thin film transistor refers to a level corresponding to when the thin film transistor is turned on.
  • a low-level control P-type thin film transistor is turned on, so that an enable level of a P-type thin film transistor is a low level; a high-level control P-type thin film transistor is turned off, so a P-type thin film transistor is turned off.
  • the non-enable level is high. Therefore, the first conduction level is an enable level corresponding to a case where the thin film transistor controlled by the first conduction level VI is turned on, and the first conduction level is a non-enable level corresponding to the first guide. The case where the level VI controlled thin film transistor is turned off.
  • the second conduction level is an enable level corresponding to a case where the thin film transistor controlled by the second conduction level V2 is turned on, and the second conduction level is a non-enable level corresponding to the second. The case where the thin film transistor controlled by the level V2 is turned off.
  • FIG. 4 is a specific embodiment of a shift register according to the present invention.
  • each of the switch tubes M1 to M8 is a TFT (English: Thin F i lm Trans is tor , Chinese: thin film transistor ).
  • the pre-charging circuit 1 includes: a first thin film transistor M1, a second thin film transistor M2, a first node, a second node B, and a first capacitor C1, wherein the first thin film transistor M1 has The gate is connected to the first clock signal input terminal 52 for accessing the first clock signal CLK, the source is connected to the start signal input terminal 51, and the drain is connected to the second node B.
  • the source of the first thin film transistor M1 is connected to the start signal input terminal 51 for access. Start signal STV.
  • the source of the first thin film transistor M1 can also be connected to the output of the corresponding upper stage shift register, and the level signal outputted by the shift register of the previous stage is used as the start signal.
  • the second thin film transistor M2 has a gate connected to the second node B, a source connected to the start signal input terminal 51, and a drain connected to the first node A.
  • the first node A is configured to output a first turn-on level VI of the pre-charge circuit.
  • the second node B is configured to output a second conduction level V2 of the precharge circuit.
  • the first capacitor C1 has one end connected to the second node B and the other end connected to the shift register output terminal 6.
  • the first pull-up circuit 2 includes: a third thin film transistor M3 having a gate connected to the first node A, a source connected to a high level VGH, and a drain connected to the shift register output 6.
  • the pull-down circuit 3 includes: a fourth thin film transistor M4 having a gate connected to the second node
  • the source is connected to the second clock signal input terminal 53 for accessing the second clock signal CLKB, and the drain is connected to the shift register output terminal 6.
  • the reverse circuit 401 includes: a fifth thin film transistor M5, a sixth thin film transistor M6, a seventh thin film transistor M7, and a third node C, wherein the fifth thin film transistor M5 has a gate connected to the second node B, the source The pole is connected to the high level VGH, the drain is connected to the third node C; the sixth thin film transistor M6 has a gate connected to the source of the seventh thin film transistor M7, and the source is connected to the low level VGL, The drain is connected to the third node C; the seventh thin film transistor M7 has a gate connected to the low level VGL, a source connected to the gate of the sixth thin film transistor M6, and a drain connected to the low level VGL The third node C is the output of the reverse circuit 401.
  • the pull-up sub-circuit 402 includes: an eighth thin film transistor M8 having a gate connected to the third node
  • the source is connected to the high voltage VGH, and the drain is connected to the shift register output 6.
  • FIG. 5 is a timing chart of the operation of the shift register of the embodiment.
  • the shift register operates under the first clock signal CLK and the second clock signal CLKB of the differential input, that is, the first clock signal CLK and the second clock signal CLKB are differentially input. Therefore, the second clock signal CLKB is at a low level when the first clock signal CLK is at a high level, and at a high level when the first clock signal CLK is at a low level.
  • the start signal STV outputs a low level
  • the first clock signal CLK outputs a low level
  • the second clock signal CLKB outputs a high level.
  • the first thin film transistor M1 is turned on
  • the second conduction level V2 outputted by the second node B is at a low level, and simultaneously starts charging the first capacitor C1
  • the second thin film transistor M2 is turned on
  • the first conduction level VI of the first node A is output. Is low.
  • the third thin film transistor M3 is turned on, so that the high level VGH pulls the output of the third thin film transistor M3 to output a high level.
  • the VOUT output from the output of the shift register 6 is at a high level.
  • the fourth thin film transistor M4 is turned on, and the second clock signal CLKB is also outputted to a high level, so the VOUT outputted by the shift register output terminal 6 is still High level.
  • the fifth thin film transistor M5 is turned on, the sixth thin film transistor M6 is turned off, the seventh thin film transistor M7 is turned off, the third node C outputs a high level, and the eighth thin film transistor M8 is turned off.
  • the start signal STV outputs a high level
  • the first clock signal CLK outputs a high level
  • the second clock signal CLKB outputs a low level.
  • the first thin film transistor M1 is turned off, at the same time, the first capacitor C1 starts to discharge, and the second turn-on level V2 outputted by the second node B is kept low until the discharge process of the first capacitor C1 ends. In fact, the discharge process of the first capacitor C1 continues until the next start of the charging process. Therefore, for the second conduction level V2 outputted by the second node B, the output is kept low in the second phase T2. level.
  • the second conduction level V2 outputted by the second node B When the second conduction level V2 outputted by the second node B is low, the second thin film transistor M2 is turned on, and the first conduction level VI outputted by the first node A is high. When the first turn-on level VI of the first node A is at a high level, the third thin film transistor M3 is turned off. When the second conduction level V2 outputted by the second node B is low level, the fifth thin film transistor M5 is turned on, the sixth thin film transistor M6 is turned off, the seventh thin film transistor M7 is turned off, and the third node C outputs high power. Flat, the eighth thin film transistor M8 is turned off.
  • the fourth thin film transistor M4 is turned on, so that the second clock signal CLKB pulls the output of the fourth thin film transistor M4 to output a low level. Therefore, the VOUT output from the output of the shift register 6 is low.
  • the start signal STV outputs a high level
  • the first clock signal CLK outputs a low level
  • the second clock signal CLKB outputs a high level.
  • the first thin film transistor M1 is turned on
  • the second turn-on level V2 outputted by the second node B is at a high level
  • charging of the first capacitor C1 is started
  • the second thin film transistor M2 is turned off.
  • the first node A becomes a floating node
  • the floating node means that the state of the node is not controlled by the input voltage of the current time but by the previous moment. Control the residual voltage at the point.
  • the first node A is a floating node, and the first conduction level VI of the residual output is still at a high level.
  • the third thin film transistor M3 is turned off.
  • the fourth thin film transistor M4 is turned off, the fifth thin film transistor M5 is turned off, the sixth thin film transistor M6 is turned on, and the seventh thin film transistor M7 is turned on.
  • the third node C outputs a low level, and the eighth thin film transistor M8 is turned on, so that the high level VGH pulls the output of the eighth thin film transistor M8 to output a high level, and the VOUT of the shift register output terminal 6 is outputted at this time. Is high.
  • the start signal STV outputs a high level
  • the first clock signal CLK outputs a high level
  • the second clock signal CLKB outputs a low level.
  • the first thin film transistor M1 is turned off, and at the same time, the first capacitor C1 starts to discharge, and the second turn-on level V2 outputted by the second node B is kept high until the discharge of the first capacitor C1 ends. In fact, the discharge process of the first capacitor C1 continues until the next start of the charging process. Therefore, for the second conduction level V2 outputted by the second node B, the output high power is maintained in the fourth phase T2. level.
  • the second conduction level V2 outputted by the second node B is high, the second thin film transistor M2 is turned off, and the first node A is still a floating node. Therefore, the first node A is a floating node, and the first conduction level VI of the residual output is still at a high level.
  • the third thin film transistor M3 is turned off.
  • the fourth thin film transistor M4 is turned off, the fifth thin film transistor M5 is turned off, the sixth thin film transistor M6 is turned on, and the seventh thin film transistor M7 is turned on.
  • the third node C outputs a low level, and the eighth thin film transistor M8 is turned on, so that the high level VGH pulls the output of the eighth thin film transistor M8 to output a high level, and the VOUT of the output of the shift register output 6 is High level.
  • the second node B of the shift register always outputs the second level V2 of the high level from the time of the fourth stage T4, so that the fifth thin film transistor M5 is turned off.
  • the sixth thin film transistor M6 is turned on, the seventh thin film transistor M7 is turned on, the eighth thin film transistor M8 is turned on to perform the pull-up, and the shift register output terminal 6 outputs the high-level VOUT. Therefore, the occurrence of interference between multiple floating nodes affecting the output signal is eliminated, thereby improving the stability of the shift register operation.
  • the second conduction level V2 outputted by the second node B is always at a high level (including the first a charging process of the second node B by the capacitor C1 and a discharging process), so that the fifth thin film transistor M5 is turned off, the sixth thin film transistor M6 is turned on, the seventh thin film transistor M7 is turned on, and the eighth thin film transistor M8 is turned on to pull
  • the output level of the high shift register output 6 is such that it outputs a high level of VOUT, thus ensuring the stability of the shift register output 6 outputting a high level of VOUT.
  • T1 ⁇ T4 is a complete signal change period. After ⁇ 4, no matter how the first clock signal CLK and the second clock signal CLKB change, as long as the start signal STV does not input a low level, the VOUT output of the shift register output terminal 6 remains high. When the start signal STV is input to the low level again, the shift register of the embodiment of the present invention repeatedly starts the operation timing change period of the first stage T1 to the fourth stage ⁇ 4.
  • Embodiments of the present invention provide a shift register that eliminates the occurrence of mutual interference of a plurality of floating nodes affecting the characteristics of the output terminal, can effectively improve the drift phenomenon of the output signal, and improve the output stability of the shift register.
  • an embodiment of the present invention further provides a gate driving circuit including the shift register described in the above embodiment.
  • the gate driving circuit includes a multi-stage shift register: a first shift register, a second shift register, a third shift register, a fourth shift register, an n-th shift register, and each Stage shift register cascade connection, output V0UT1, V0UT2, V0UT3,
  • V0UT4 VOUTn is used to generate the scan signal.
  • Each stage shift register is connected to the first clock signal CLK, the second clock signal CLKB, the start signal, and outputs a scan signal.
  • the first shift register is connected to the start signal STV, and the remaining shift registers access the scan signal outputted by the corresponding upper shift register as a start signal.
  • the shift register unit circuits of each stage adopt the shift register of the above circuit structure.
  • the source of the first thin film transistor M1 and the second thin film crystal of the precharge circuit in any one of the shift registers The source of the body tube M2 is no longer connected to the start signal STV but to the VOUT waveform outputted to the output of the shift register of the previous stage of any of the shift registers, and the other portions are unchanged. Therefore, the working principle and the circuit structure are the same as those of the above-described embodiment, and are not described herein.
  • the first scan signal VOUT1 is input as a start signal, the first clock signal CLK and the second clock signal CLKB, and the second scan signal VOUT2 is output;
  • the gate driving circuit operates under the control of the first clock signal CLK and the second clock signal CLKB, and outputs the first scan signal VOUT1 and the second scan signal V0UT2 from the top to the bottom. Scan signal VOUTN.
  • Embodiments of the present invention provide a gate driving circuit, which eliminates the situation that a plurality of floating nodes of a shift register included in the shift register affect the characteristics of the output terminal, can effectively improve the drift phenomenon of the output signal, and improve the gate driving circuit.
  • the stability of the work is a part of the work.
  • an embodiment of the present invention also provides an array substrate including the gate driving circuit in the above embodiment.
  • the portion of the gate driving circuit is the same as the above embodiment, and details are not described herein again.
  • the structure of other parts of the array substrate can refer to the prior art, which will not be described in detail herein.
  • Embodiments of the present invention provide an array substrate, which eliminates the situation that multiple floating nodes of the shift register included in the shift register affect the characteristics of the output end, can effectively improve the drift phenomenon of the output signal, and improve the operational stability of the array substrate. .
  • an embodiment of the present invention provides a display device including the array substrate in the above embodiment.
  • the array substrate portion is the same as the above embodiment, and details are not described herein again.
  • the structure of other parts of the display device can be referred to the prior art, and will not be described in detail herein.
  • Embodiments of the present invention provide a display device, which eliminates the situation that a plurality of floating nodes of a shift register included in the shift register affect the characteristics of the output terminal, can effectively improve the drift phenomenon of the output signal, and improve the operational stability of the display device. .

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Abstract

本发明实施例公开了一种移位寄存器、栅极驱动电路、阵列基板以及显示装置，能够有效改善输出信号的漂移现象，提高移位寄存器的输出稳定性。本发明实施例的移位寄存器，包括：包含有起始信号输入端、第一时钟信号输入端以及第二时钟信号输入端的移位寄存器输入端；响应于起始信号以及第一时钟信号的预充电电路；响应于所述起始信号的致能电平以及所述第一时钟信号的致能电平的第一拉高电路；响应于所述第一时钟信号的非致能电平以及第二时钟信号的致能电平的拉低电路；第二拉高电路；移位寄存器输出端。

Description

移位寄存器、 栅极驱动电路、 阵列基板以及显示装置 技术领域
本发明涉及显示装置领域， 尤其涉及一种移位寄存器、 栅极驱动电路、 阵列基板以及显示装置。 背景技术
目前， 显示装置正在朝着轻薄化、 高解析化、 窄边框化和节能化方向发 展， 因此需要在有限的空间内整合更多开关器件以及更小的像素以满足显示 装置的要求。 为了达到不增加工艺步骤以及制造成本的目的， 通常采用阵列 基板行驱动 （英文： Gate Driver on Array, 缩写： GOA )技术， 将栅极驱动 单元集成于阵列基板上形成 GOA单元。 其中， 栅极驱动技术主要以移位寄 存器来实现扫描驱动的目的。
在实现上述扫描驱动的过程中，发明人发现现有技术中至少存在如下问 题： 以如图 1所示的移位寄存器结构为例， 包括第一薄膜晶体管 Ml' 至第 六薄膜晶体管 M6' 以及第一电容 C1' ，其中上述薄膜晶体管均为 P型薄膜 晶体管， 该薄膜晶体管的致能电平为低电平（薄膜晶体管的致能电平指的是 所述薄膜晶体管导通时对应的电平。 以 P型薄膜晶体管为例， 低电平控制 P 型薄膜晶体管导通， 因此 P型薄膜晶体管的致能电平为低电平； 高电平控制 P型薄膜晶体管关断， 因此 P型薄膜晶体管的非致能电平为高电平）。 如图 2 所示， 在第一阶段 T1 , 第一节点 A' 被输入低电平， 第三节点 C 被输入高 电平； 在第二阶段 T2, 第一节点 A' 被输入高电平， 第三节点 C 被输入高 电平； 在第三阶段 T3 , 第一节点 A' 被输入低电平， 第三节点 C 浮空并保 持高电平； 在第四阶段 T4, 第一节点 A' 浮空并保持低电平， 同时第五薄 膜晶体管 M5' 导通， 因此第三节点 C 残留的电平对第一节点 A' 产生了 干扰， 影响了第六薄膜晶体管 M6' 的开启状态， 使得上述移位寄存器在拉 高电压时产生了漂移现象， 导致输出信号的不稳定， 影响了移位寄存器的工 作可靠性。 发明内容 本发明的实施例提供一种移位寄存器、 栅极驱动电路、 阵列基板以及显 示装置，能够有效改善输出信号的漂移现象，提高移位寄存器的工作稳定性。
为解决上述技术问题， 本发明的实施例采用如下技术方案：
一种移位寄存器， 包括：
移位寄存器输入端， 包括起始信号输入端、 第一时钟信号输入端以及第 二时钟信号输入端；
预充电电路， 响应于起始信号以及第一时钟信号， 输出第一导通电平以 及第二导通电平；
第一拉高电路， 在所述第一导通电平的控制下， 响应于所述起始信号的 致能电平以及所述第一时钟信号的致能电平， 输出高电平；
拉低电路， 在所述第二导通电平的控制下， 响应于所述起始信号的非致 能电平、 所述第一时钟信号的非致能电平以及第二时钟信号的致能电平， 输 出氐电平；
第二拉高电路， 当所述第二导通电平为非致能电平时， 输出高电平； 移位寄存器输出端， 连接于所述第一拉高电路的输出端、 所述拉低电路 的输出端以及所述第二拉高电路的输出端， 输出电平信号。
进一步的， 所述第二拉高电路包括： 反向电路以及拉高子电路， 其中， 反向电路， 当所述第二导通电平为致能电平时， 输出高电平， 并且当所 述第二导通电平为非致能电平时， 输出低电平；
拉高子电路， 响应于所述反向电路输出的低电平， 输出高电平。
进一步的， 所述预充电电路包括： 第一薄膜晶体管、 第二薄膜晶体管、 第一节点、 第二节点以及第一电容， 其中，
第一薄膜晶体管， 其栅极连接于第一时钟信号输入端， 源极连接于起始 信号输入端， 漏极连接于所述第二节点；
第二薄膜晶体管， 其栅极连接于所述第二节点， 源极连接于起始信号输 入端， 漏极连接于所述第一节点；
第一节点， 用于输出所述预充电电路的第一导通电平；
第二节点， 用于输出所述预充电电路的第二导通电平； 第一电容， 其一端连接于所述第二节点， 另一端连接于所述移位寄存器 输出端。
进一步的， 所述第一拉高电路包括： 第三薄膜晶体管， 其栅极连接于所 述第一节点， 源极连接于高电平， 漏极连接于所述移位寄存器输出端。
进一步的， 所述拉低电路包括： 第四薄膜晶体管， 其栅极连接于所述第 二节点， 源极连接于第二时钟信号输入端， 漏极连接于所述移位寄存器输出 端。
进一步的， 所述反向电路包括： 第五薄膜晶体管、 第六薄膜晶体管、 第 七薄膜晶体管以及第三节点， 其中，
第五薄膜晶体管， 其栅极连接于第二节点， 源极连接于高电平， 漏极连 接于所述第三节点；
第六薄膜晶体管， 其栅极连接于所述第七薄膜晶体管的源极， 源极连接 于低电平， 漏极连接于所述第三节点；
第七薄膜晶体管， 其栅极连接于低电平， 源极连接于所述第六薄膜晶体 管的栅极， 漏极连接于低电平；
第三节点， 为所述反向电路的输出端。
进一步的， 所述拉高子电路包括： 第八薄膜晶体管， 其栅极连接于第三 节点， 源极连接于高电压， 漏极连接于所述移位寄存器输出端。
一种栅极驱动电路， 包括如上所述的移位寄存器。
一种阵列基板， 包括如上所述的栅极驱动电路。
一种显示装置， 包括如上所述的阵列基板。
本发明的实施例提供一种移位寄存器、 栅极驱动电路、 阵列基板以及显 示装置， 杜绝了多个浮空节点相互干扰影响输出端特性的情况， 能够有效改 善输出信号的漂移现象， 提高移位寄存器的工作稳定。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实 施例或现有技术描述中所需要使用的附图作筒单地介绍， 显而易见地， 下面 描述中的附图仅仅是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动的前提下， 还可以根据这些附图获得其他的附图。
图 1为现有技术移位寄存器的电路示意图；
图 2为现有技术移位寄存器的时序波形图；
图 3为本发明实施例移位寄存器的结构框图；
图 4为本发明实施例移位寄存器的电路示意图；
图 5为本发明实施例移位寄存器的时序波形图；
图 6为本发明实施例栅极驱动电路的结构示意图；
图 Ί为本发明实施例栅极驱动电路的时序波形图。 具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而 不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有做 出创造性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。
如图 3所示， 本发明实施例提供了一种移位寄存器， 包括： 移位寄存器 输入端、 预充电电路 1、 第一拉高电路 2、 拉低电路 3、 第二拉高电路 4以及 移位寄存器输出端 6 , 其中，
移位寄存器输入端， 包括起始信号输入端 51、 第一时钟信号输入端 52 以及第二时钟信号输入端 53。
预充电电路 1 , 响应于起始信号 STV以及第一时钟信号 CLK, 输出第一 导通电平 VI以及第二导通电平 V2; 需要说明的是，第一导通电平 VI与第二 导通电平 V2均响应于起始信号 STV以及第一时钟信号 CLK ,但是第一导通电 平 VI与第二导通电平 V2存在不同： 第一导通电平 VI用于控制第一拉高电 路 2 , 第二导通电平 V2用于控制拉低电路 3以及第二拉高电路 4。
第一拉高电路 2 , 在第一导通电平 VI 的控制下， 响应于起始信号 STV 的致能电平以及第一时钟信号 CLK的致能电平， 输出高电平。
拉低电路 3 ,在第二导通电平 V2的控制下，响应于起始信号 STV的非致 能电平、 第一时钟信号 CLK的非致能电平以及第二时钟信号 CLKB的致能电 平， 输出低电平。
第二拉高电路 4 , 在第二导通电平 V2为非致能电平时， 输出高电平。 移位寄存器输出端 6 , 连接于所述第一拉高电路 2的输出端、 所述拉低 电路 3的输出端以及所述第二拉高电路 4的输出端， 输出 V0UT电平信号。
作为本发明的进一步的实施例，所述第二拉高电路 4包括：反向电路 401 以及拉高子电路 402 , 其中，
反向电路 401 , 当所述第二导通电平 V2为致能电平时， 输出高电平， 当 所述第二导通电平 V2为非致能电平时， 输出低电平；
拉高子电路 402 , 响应于所述反向电路输出的低电平， 输出高电平。 下面结合具体实施例对本发明所述移位寄存器作进一步地描述说明。 下 列实施例中的薄膜晶体管以 P型薄膜晶体管为例， 所述致能电平为低电平， 非致能电平为高电平。 需要说明的是， 薄膜晶体管的致能电平指的是所述薄 膜晶体管导通时对应的电平。 以 P型薄膜晶体管为例， 低电平控制 P型薄膜 晶体管导通， 因此 P型薄膜晶体管的致能电平为低电平； 高电平控制 P型薄 膜晶体管关断， 因此 P型薄膜晶体管的非致能电平为高电平。 因此， 第一导 通电平为致能电平对应的是第一导通电平 VI控制的薄膜晶体管导通的情况， 第一导通电平为非致能电平对应的是第一导通电平 VI控制的薄膜晶体管关 断的情况。 同样的， 第二导通电平为致能电平对应的是第二导通电平 V2控 制的薄膜晶体管导通的情况， 第二导通电平为非致能电平对应的是第二导通 电平 V2控制的薄膜晶体管关断的情况。
如图 4所示， 图 4为本发明所述移位寄存器的一具体实施例， 本实施例 中各开关管 Ml ~ M8均为 TFT (英文： Thin F i lm Trans i s tor , 中文： 薄膜晶 体管）。 从图中可以看出， 所述预充电电路 1包括： 第一薄膜晶体管 Ml、 第 二薄膜晶体管 M2、 第一节点 、 第二节点 B以及第一电容 C1 , 其中， 第一薄 膜晶体管 Ml , 其栅极连接于第一时钟信号输入端 52 , 用于接入第一时钟信 号 CLK, 源极连接于起始信号输入端 51 , 漏极连接于所述第二节点 B。 需要 说明的是， 第一薄膜晶体管 Ml的源极连接于起始信号输入端 51 , 用于接入 起始信号 STV。事实上， 第一薄膜晶体管 Ml的源极也可连接于对应的上一级 移位寄存器的输出端， 将上一级移位寄存器输出的电平信号用作为起始信 号。 第二薄膜晶体管 M2 , 其栅极连接于所述第二节点 B, 源极连接于起始信 号输入端 51 , 漏极连接于所述第一节点 A。 第一节点 A, 用于输出所述预充 电电路的第一导通电平 VI。 第二节点 B, 用于输出所述预充电电路的第二导 通电平 V2。 第一电容 C1 , 其一端连接于所述第二节点 B, 另一端连接于所述 移位寄存器输出端 6。
所述第一拉高电路 2包括： 第三薄膜晶体管 M3 ,其栅极连接于所述第一 节点 A, 源极连接于高电平 VGH, 漏极连接于所述移位寄存器输出端 6。
所述拉低电路 3包括： 第四薄膜晶体管 M4 ,其栅极连接于所述第二节点
B, 源极连接于第二时钟信号输入端 53 , 用于接入第二时钟信号 CLKB, 漏极 连接于所述移位寄存器输出端 6。
所述反向电路 401 包括： 第五薄膜晶体管 M5、 第六薄膜晶体管 M6、 第 七薄膜晶体管 M7以及第三节点 C, 其中， 第五薄膜晶体管 M5 , 其栅极连接 于第二节点 B, 源极连接于高电平 VGH, 漏极连接于所述第三节点 C; 第六薄 膜晶体管 M6 , 其栅极连接于所述第七薄膜晶体管 M7的源极， 源极连接于低 电平 VGL , 漏极连接于所述第三节点 C; 第七薄膜晶体管 M7 , 其栅极连接于 低电平 VGL, 源极连接于所述第六薄膜晶体管 M6的栅极， 漏极连接于低电平 VGL; 第三节点 C, 为所述反向电路 401的输出端。
所述拉高子电路 402包括： 第八薄膜晶体管 M8 ,其栅极连接于第三节点
C, 源极连接于高电压 VGH, 漏极连接于所述移位寄存器输出端 6。
如图 5所示， 图 5为本实施例移位寄存器的工作时序图。 上述移位寄存 器工作于差分输入的第一时钟信号 CLK以及第二时钟信号 CLKB下， 即第一 时钟信号 CLK以及第二时钟信号 CLKB是差分输入的。 因此， 当第一时钟信 号 CLK处于高电平时第二时钟信号 CLKB则处于低电平，当第一时钟信号 CLK 处于低电平时第二时钟信号 CLKB则处于高电平。
在第一阶段 T1时， 起始信号 STV输出低电平， 第一时钟信号 CLK输出 低电平， 第二时钟信号 CLKB输出高电平。 此时， 第一薄膜晶体管 Ml导通， 第二节点 B输出的第二导通电平 V2为低电平， 并且同时开始对第一电容 C1 进行充电， 第二薄膜晶体管 M2导通， 第一节点 A输出的第一导通电平 VI为 低电平。 当第一节点 A输出的第一导通电平 VI为低电平时， 第三薄膜晶体 管 M3导通，从而高电平 VGH拉高该第三薄膜晶体管 M3的输出以输出高电平， 此时移位寄存器输出端 6输出的 V0UT为高电平。 当第二节点 B输出的第二 导通电平 V2为低电平时， 第四薄膜晶体管 M4导通， 而第二时钟信号 CLKB 也输出高电平， 因此移位寄存器输出端 6输出的 V0UT还是高电平。 并且， 第五薄膜晶体管 M5导通， 第六薄膜晶体管 M6关断， 第七薄膜晶体管 M7关 断， 第三节点 C输出高电平， 第八薄膜晶体管 M8关断。
在第二阶段 T2时， 起始信号 STV输出高电平， 第一时钟信号 CLK输出 高电平， 第二时钟信号 CLKB输出低电平。 此时， 第一薄膜晶体管 Ml关断， 与此同时， 第一电容 C1开始放电， 保持第二节点 B输出的第二导通电平 V2 为低电平直至第一电容 C1放电过程结束。 事实上， 第一电容 C1的放电过程 会持续到下次开始充电过程前， 因此， 对于第二节点 B输出的第二导通电平 V2来说， 在第二阶段 T2中会保持输出低电平。 当第二节点 B输出的第二导 通电平 V2为低电平时， 第二薄膜晶体管 M2导通， 第一节点 A输出的第一导 通电平 VI为高电平。 当第一节点 A输出的第一导通电平 VI为高电平时， 第 三薄膜晶体管 M3关断。 当第二节点 B输出的第二导通电平 V2为低电平时， 第五薄膜晶体管 M5导通， 第六薄膜晶体管 M6关断， 第七薄膜晶体管 M7关 断， 第三节点 C输出高电平， 第八薄膜晶体管 M8 关断。 并且当第二节点 B 输出的第二导通电平 V2为低电平时， 第四薄膜晶体管 M4导通， 从而第二时 钟信号 CLKB拉低该第四薄膜晶体管 M4的输出以输出低电平， 因此移位寄存 器输出端 6输出的 V0UT为低电平。
在第三阶段 T3时， 起始信号 STV输出高电平， 第一时钟信号 CLK输出 低电平， 第二时钟信号 CLKB输出高电平。 此时， 第一薄膜晶体管 Ml导通， 第二节点 B输出的第二导通电平 V2为高电平， 并且同时开始对第一电容 C1 进行充电， 第二薄膜晶体管 M2关断， 此时第一节点 A变为浮空节点， 浮空 节点指得是该节点状态不受当前时刻的输入电压控制而是由前一时刻该节 点上残留的电压来控制。 因此， 第一节点 A为浮空节点， 残留输出的第一导 通电平 VI依然为高电平。当第一节点 A输出的第一导通电平 VI为高电平时， 第三薄膜晶体管 M3关断。当第二节点 B输出的第二导通电平 V2为高电平时， 第四薄膜晶体管 M4关断， 第五薄膜晶体管 M5关断， 第六薄膜晶体管 M6导 通， 第七薄膜晶体管 M7导通， 第三节点 C输出低电平， 第八薄膜晶体管 M8 导通， 从而高电平 VGH拉高该第八薄膜晶体管 M8的输出以输出高电平， 此 时移位寄存器输出端 6输出的 V0UT为高电平。
在第四阶段 T4时， 起始信号 STV输出高电平， 第一时钟信号 CLK输出 高电平， 第二时钟信号 CLKB输出低电平。 此时， 第一薄膜晶体管 Ml关断， 与此同时， 第一电容 C1开始放电， 保持第二节点 B输出的第二导通电平 V2 为高电平直至第一电容 C1放电过程结束。 事实上， 第一电容 C1的放电过程 会持续到下次开始充电过程前， 因此， 对于第二节点 B输出的第二导通电平 V2来说， 在第四阶段 T2中会保持输出高电平。 当第二节点 B输出的第二导 通电平 V2为高电平时， 第二薄膜晶体管 M2关断， 此时第一节点 A依然为浮 空节点。 因此， 第一节点 A为浮空节点， 残留输出的第一导通电平 VI依然 为高电平。 当第一节点 A输出的第一导通电平 VI为高电平时， 第三薄膜晶 体管 M3关断。 当第二节点 B输出的第二导通电平 V2为高电平时， 第四薄膜 晶体管 M4关断， 第五薄膜晶体管 M5关断， 第六薄膜晶体管 M6导通， 第七 薄膜晶体管 M7导通， 第三节点 C输出低电平， 第八薄膜晶体管 M8导通， 从 而高电平 VGH拉高第八薄膜晶体管 M8的输出以输出高电平， 此时移位寄存 器输出端 6输出的 V0UT为高电平。
至此， 在本发明的具体实施例中， 所述移位寄存器的第二节点 B在第四 阶段 T4时刻起始终输出高电平的第二导通电平 V2 ,使得第五薄膜晶体管 M5 关断， 第六薄膜晶体管 M6导通， 第七薄膜晶体管 M7导通， 第八薄膜晶体管 M8导通以执行拉高， 移位寄存器输出端 6输出高电平的 V0UT。 所以， 杜绝 了多个浮空节点相互干扰影响输出信号的情况出现，从而提高了移位寄存器 工作的稳定性。
另外， 如图 5所示， 通过上述分析过程可以得到， 在第一阶段 T1〜第四 阶段 T4中第一节点 Α输出的第一导通电平 VI与第二节点 B输出的第二导通 电平 V2的电平变化情况。
另外， 需要说明的是， 在后续时间周期中， 即在第四阶段 T4 时刻之后 的时间段内， 由于第二节点 B输出的第二导通电平 V2始终为高电平 （其中 包括有第一电容 C1对第二节点 B的充电过程以及放电过程），使得第五薄膜 晶体管 M5关断， 第六薄膜晶体管 M6导通， 第七薄膜晶体管 M7导通， 第八 薄膜晶体管 M8导通以拉高移位寄存器输出端 6的输出电平， 使其输出高电 平的 V0UT, 因此保证了移位寄存器输出端 6输出高电平的 V0UT的稳定性。
因此，通过分析上述信号变化过程可以发现， T1 ~ T4时刻为一个完整的 信号变化周期。 而在 Τ4时刻之后， 无论第一时钟信号 CLK以及第二时钟信 号 CLKB是如何变化的， 只要起始信号 STV不输入低电平， 移位寄存器输出 端 6输出的 V0UT 就保持为高电平。 而当起始信号 STV再次输入低电平时， 本发明实施例所述移位寄存器又重复开始上述第一阶段 T1〜第四阶段 Τ4的 工作时序变化周期。
本发明的实施例提供一种移位寄存器，杜绝了多个浮空节点相互干扰影 响输出端特性的情况出现， 能够有效改善输出信号的漂移现象， 提高移位寄 存器的输出稳定性。
另外， 本发明实施例还提供了一种栅极驱动电路， 包括上述实施例所述 的移位寄存器。 如图 6所示， 所述栅极驱动电路， 包括多级移位寄存器： 第 一移位寄存器、 第二移位寄存器、 第三移位寄存器、 第四移位寄存器 第 η移位寄存器，各级移位寄存器级联连接，分别输出 V0UT1、 V0UT2、 V0UT3、
V0UT4 VOUTn用于产生扫描信号。 每一级移位寄存器均接入第一时钟 信号 CLK、 第二时钟信号 CLKB、 起始信号， 并输出扫描信号。 其中， 第一移 位寄存器接入起始信号 STV, 其余移位寄存器将对应的上一级移位寄存器输 出的扫描信号作为起始信号进行接入。各级移位寄存器单元电路均采用上述 电路结构的移位寄存器。
需要说明的是， 对于除第一移位寄存器之外的任一移位寄存器而言， 该 任一移位寄存器中预充电电路的第一薄膜晶体管 Ml 的源极以及第二薄膜晶 体管 M2的源极不再接入起始信号 STV而是接入该任一移位寄存器的上一级 移位寄存器的输出端输出的 V0UT波形， 其它部分结构不变。 因此工作原理 以及电路结构与上述实施例的移位寄存器相同， 在此不做赘述。
该栅极驱动电路的工作过程可描述如下：
处于第一级的第一移位寄存器， 接入起始信号 STV、 第一时钟信号 CLK 以及第二时钟信号 CLKB, 输出第一扫描信号 V0UT1 ;
处于第二级的第二移位寄存器,接入第一扫描信号 V0UT1作为起始信号、 第一时钟信号 CLK以及第二时钟信号 CLKB, 输出第二扫描信号 V0UT2 ;
依次类推，直至处于第 n级的第 n移位寄存器，输出第 n扫描信号 V0UTn。 如图 Ί所示， 所述栅极驱动电路在第一时钟信号 CLK以及第二时钟信号 CLKB的控制下工作， 自上而下的逐行输出第一扫描信号 V0UT1、 第二扫描信 号 V0UT2 第 n扫描信号 V0UTn。
本发明的实施例提供一种栅极驱动电路，杜绝了其包括的移位寄存器多 个浮空节点相互干扰影响输出端特性的情况出现， 能够有效改善输出信号的 漂移现象， 提高栅极驱动电路的工作稳定性。
另外， 本发明的实施例还提供了一种阵列基板， 包括上述实施例中的栅 极驱动电路。 其中，栅极驱动电路部分同上述实施例， 在此不再赘述。 另夕卜， 阵列基板其他部分的结构可以参考现有技术， 对此本文不再详细描述。
本发明的实施例提供一种阵列基板，杜绝了其包括的移位寄存器多个浮 空节点相互干扰影响输出端特性的情况出现， 能够有效改善输出信号的漂移 现象， 提高阵列基板的工作稳定性。
另外， 本发明的实施例还提供了一种显示装置， 包括上述实施例中的阵 列基板。 其中， 阵列基板部分同上述实施例， 在此不再赘述。 另外， 显示装 置其他部分的结构可以参考现有技术， 对此本文不再详细描述。
本发明的实施例提供一种显示装置，杜绝了其包括的移位寄存器多个浮 空节点相互干扰影响输出端特性的情况出现， 能够有效改善输出信号的漂移 现象， 提高显示装置的工作稳定性。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护 范围应以所述权利要求的保护范围为准。

Claims

权利要求
1、 一种移位寄存器， 包括：
移位寄存器输入端， 包括起始信号输入端、 第一时钟信号输入端以及第 二时钟信号输入端；
预充电电路， 响应于起始信号以及第一时钟信号， 输出第一导通电平以 及第二导通电平；
第一拉高电路， 在所述第一导通电平的控制下， 响应于所述起始信号的 致能电平以及所述第一时钟信号的致能电平， 输出高电平；
拉低电路， 在所述第二导通电平的控制下， 响应于所述起始信号的非致 能电平、 所述第一时钟信号的非致能电平以及第二时钟信号的致能电平， 输 出氐电平；
第二拉高电路， 在所述第二导通电平为非致能电平时， 输出高电平； 移位寄存器输出端， 分别连接于所述第一拉高电路的输出端、 所述拉低 电路的输出端以及所述第二拉高电路的输出端， 输出电平信号。
2、 根据权利要求 1 所述的移位寄存器， 所述第二拉高电路包括： 反向 电路以及拉高子电路， 其中，
反向电路， 当所述第二导通电平为致能电平时， 输出高电平， 且当所述 第二导通电平为非致能电平时， 输出低电平；
拉高子电路， 响应于所述反向电路输出的低电平， 输出高电平。
3、 根据权利要求 1 所述的移位寄存器， 其特征在于， 所述预充电电路 包括： 第一薄膜晶体管、 第二薄膜晶体管、 第一节点、 第二节点以及第一电 容， 其中，
第一薄膜晶体管， 其栅极连接于第一时钟信号输入端， 源极连接于起始 信号输入端， 漏极连接于所述第二节点；
第二薄膜晶体管， 其栅极连接于所述第二节点， 源极连接于起始信号输 入端， 漏极连接于所述第一节点；
第一节点， 用于输出所述预充电电路的第一导通电平；
第二节点， 用于输出所述预充电电路的第二导通电平； 第一电容， 其一端连接于所述第二节点， 另一端连接于所述移位寄存器 输出端。
4、 根据权利要求 1所述的移位寄存器， 其中， 所述第一拉高电路包括： 第三薄膜晶体管， 其栅极连接于所述第一节点， 源极连接于高电平， 漏极连 接于所述移位寄存器输出端。
5、 根据权利要求 1 所述的移位寄存器， 其中， 所述拉低电路包括： 第 四薄膜晶体管， 其栅极连接于所述第二节点， 源极连接于第二时钟信号输入 端， 漏极连接于所述移位寄存器输出端。
6、 根据权利要求 2所述的移位寄存器， 其中， 所述反向电路包括： 第 五薄膜晶体管、 第六薄膜晶体管、 第七薄膜晶体管以及第三节点， 其中， 第五薄膜晶体管， 其栅极连接于第二节点， 源极连接于高电平， 漏极连 接于所述第三节点；
第六薄膜晶体管， 其栅极连接于所述第七薄膜晶体管的源极， 源极连接 于低电平， 漏极连接于所述第三节点；
第七薄膜晶体管， 其栅极连接于低电平， 源极连接于所述第六薄膜晶体 管的栅极， 漏极连接于低电平；
第三节点， 为所述反向电路的输出端。
7、 根据权利要求 6所述的移位寄存器， 其中， 所述拉高子电路包括： 第八薄膜晶体管， 其栅极连接于第三节点， 源极连接于高电压， 漏极连接于 所述移位寄存器输出端。
8、 一种栅极驱动电路， 包括如权利要求 1至 7中任意一项所述的移位 寄存器。
9、 一种阵列基板， 包括如权利要求 8所述的栅极驱动电路。
1 0、 一种显示装置， 包括如权利要求 9所述的阵列基板。
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KR101639496B1 (ko) 2016-07-13
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US20150302933A1 (en) 2015-10-22
CN103198866B (zh) 2015-08-05
JP6077681B2 (ja) 2017-02-08
KR20140119690A (ko) 2014-10-10
CN103198866A (zh) 2013-07-10
EP2966649A1 (en) 2016-01-13
US9472303B2 (en) 2016-10-18
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