WO2014134862A1 - 移位寄存器、栅极驱动电路、阵列基板以及显示装置 - Google Patents
移位寄存器、栅极驱动电路、阵列基板以及显示装置 Download PDFInfo
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- WO2014134862A1 WO2014134862A1 PCT/CN2013/075072 CN2013075072W WO2014134862A1 WO 2014134862 A1 WO2014134862 A1 WO 2014134862A1 CN 2013075072 W CN2013075072 W CN 2013075072W WO 2014134862 A1 WO2014134862 A1 WO 2014134862A1
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- thin film
- shift register
- film transistor
- node
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- 239000000758 substrate Substances 0.000 title claims abstract description 17
- 239000010409 thin film Substances 0.000 claims description 120
- 239000003990 capacitor Substances 0.000 claims description 16
- 230000000977 initiatory effect Effects 0.000 abstract 3
- 238000000034 method Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
- G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
- G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G3/2096—Details of the interface to the display terminal specific for a flat panel
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/06—Modifications for ensuring a fully conducting state
- H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
- G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/04—Maintaining the quality of display appearance
- G09G2320/043—Preventing or counteracting the effects of ageing
- G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
Definitions
- the present invention relates to the field of display devices, and in particular, to a shift register, a gate drive circuit, an array substrate, and a display device. Background technique
- the gate driver unit is usually integrated on the array substrate to form a GOA unit by using an array driver (LED: Gate) technology.
- the gate drive technology mainly uses a shift register to achieve the purpose of scan driving.
- the inventors have found that at least the following problems exist in the prior art: taking the shift register structure as shown in FIG. 1 as an example, including the first to sixth thin film transistors M1' to M6' and a first capacitor C1', wherein the thin film transistors are all P-type thin film transistors, and an enable level of the thin film transistor is a low level (the enable level of the thin film transistor refers to a corresponding electric power when the thin film transistor is turned on)
- the enable level of the thin film transistor refers to a corresponding electric power when the thin film transistor is turned on
- the low-level control P-type thin film transistor is turned on, so the enable level of the P-type thin film transistor is low level
- the high-level control P-type thin film transistor is turned off, so the P-type The non-enable level of the thin film transistor is high level).
- the first node A' is input with a low level, the third node C is input with a high level; in the second phase T2, the first node A' is input with a high level, The third node C is input with a high level; in the third phase T3, the first node A' is input to a low level, and the third node C is floated and maintained at a high level; in the fourth stage T4, the first node A' Floating and keeping low, while the fifth thin film transistor M5' is turned on, so the residual level of the third node C interferes with the first node A', affecting the on state of the sixth thin film transistor M6',
- the above shift register generates a drift phenomenon when the voltage is pulled high, resulting in instability of the output signal, which affects the operational reliability of the shift register. Summary of the invention Embodiments of the present invention provide a shift register, a gate driving circuit, an array substrate, and a display device, which can effectively improve the drift phenomenon of
- the embodiment of the present invention adopts the following technical solutions:
- a shift register comprising:
- a shift register input terminal comprising a start signal input end, a first clock signal input end and a second clock signal input end;
- a precharge circuit in response to the start signal and the first clock signal, outputting a first turn-on level and a second turn-on level
- a first pull-up circuit that outputs a high level in response to an enable level of the start signal and an enable level of the first clock signal under control of the first turn-on level
- a pull-down circuit responsive to a non-enable level of the start signal, a non-enable level of the first clock signal, and a second clock signal under control of the second turn-on level Energy level, output ⁇ level;
- a second pull-up circuit when the second turn-on level is a non-enable level, output a high level; a shift register output end connected to the output end of the first pull-up circuit, the pull-down The output of the circuit and the output of the second pull-up circuit output a level signal.
- the second pull-up circuit includes: a reverse circuit and a pull-up sub-circuit, wherein the reverse circuit outputs a high level when the second turn-on level is an enable level, and When the second conduction level is a non-enabling level, the output is low;
- the pull-up sub-circuit outputs a high level in response to a low level of the output of the reverse circuit.
- the pre-charging circuit includes: a first thin film transistor, a second thin film transistor, a first node, a second node, and a first capacitor, wherein
- a first thin film transistor having a gate connected to the first clock signal input terminal, a source connected to the start signal input end, and a drain connected to the second node;
- a second thin film transistor having a gate connected to the second node, a source connected to the start signal input end, and a drain connected to the first node;
- a first node configured to output a first turn-on level of the pre-charge circuit
- the first capacitor has one end connected to the second node and the other end connected to the shift register output.
- the first pull-up circuit includes: a third thin film transistor having a gate connected to the first node, a source connected to a high level, and a drain connected to the shift register output end.
- the pull-down circuit includes: a fourth thin film transistor having a gate connected to the second node, a source connected to the second clock signal input terminal, and a drain connected to the shift register output end.
- the reverse circuit includes: a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, and a third node, wherein
- a fifth thin film transistor having a gate connected to the second node, a source connected to the high level, and a drain connected to the third node;
- a sixth thin film transistor having a gate connected to a source of the seventh thin film transistor, a source connected to a low level, and a drain connected to the third node;
- a seventh thin film transistor having a gate connected to a low level, a source connected to a gate of the sixth thin film transistor, and a drain connected to a low level;
- the third node is the output of the reverse circuit.
- the pull-up sub-circuit includes: an eighth thin film transistor having a gate connected to the third node, a source connected to the high voltage, and a drain connected to the output of the shift register.
- a gate drive circuit comprising a shift register as described above.
- An array substrate comprising a gate drive circuit as described above.
- a display device comprising the array substrate as described above.
- Embodiments of the present invention provide a shift register, a gate driving circuit, an array substrate, and a display device, which eliminates the situation that multiple floating nodes interfere with each other to affect the characteristics of the output end, and can effectively improve the drift phenomenon of the output signal and improve the shift.
- the bit register works stably.
- 1 is a circuit diagram of a prior art shift register
- FIG. 3 is a structural block diagram of a shift register according to an embodiment of the present invention.
- FIG. 4 is a schematic circuit diagram of a shift register according to an embodiment of the present invention.
- FIG. 5 is a timing waveform diagram of a shift register according to an embodiment of the present invention.
- FIG. 6 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention.
- FIG. 4 is a timing waveform diagram of a gate driving circuit according to an embodiment of the present invention. detailed description
- an embodiment of the present invention provides a shift register, including: a shift register input terminal, a precharge circuit 1, a first pull-up circuit 2, a pull-down circuit 3, a second pull-up circuit 4, and Shift register output 6, wherein
- the shift register input terminal includes a start signal input terminal 51, a first clock signal input terminal 52, and a second clock signal input terminal 53.
- the pre-charging circuit 1 outputs a first on-level VI and a second on-level V2 in response to the start signal STV and the first clock signal CLK; it should be noted that the first on-level VI and the second The turn-on level V2 is both responsive to the start signal STV and the first clock signal CLK, but the first turn-on level VI is different from the second turn-on level V2: the first turn-on level VI is used to control the first The pull-up circuit 2 and the second turn-on level V2 are used to control the pull-down circuit 3 and the second pull-up circuit 4.
- the first pull-up circuit 2 outputs a high level in response to the enable level of the start signal STV and the enable level of the first clock signal CLK under the control of the first turn-on level VI.
- Pulling down circuit 3 in response to the start signal STV, under the control of the second conduction level V2
- the second pull-up circuit 4 outputs a high level when the second turn-on level V2 is a non-energized level.
- the shift register output terminal 6 is connected to the output terminal of the first pull-up circuit 2, the output terminal of the pull-down circuit 3, and the output terminal of the second pull-up circuit 4, and outputs a VOUTUT level signal.
- the second pull-up circuit 4 includes: a reverse circuit 401 and a pull-up sub-circuit 402, wherein
- the reverse circuit 401 outputs a high level when the second turn-on level V2 is an enable level, and outputs a low level when the second turn-on level V2 is a disable level;
- the pull-up sub-circuit 402 outputs a high level in response to a low level of the output of the reverse circuit.
- the shift register of the present invention will be further described below in conjunction with specific embodiments.
- the thin film transistor in the following embodiment takes a P-type thin film transistor as an example, the enable level is a low level, and the non-enable level is a high level. It should be noted that the enable level of the thin film transistor refers to a level corresponding to when the thin film transistor is turned on.
- a low-level control P-type thin film transistor is turned on, so that an enable level of a P-type thin film transistor is a low level; a high-level control P-type thin film transistor is turned off, so a P-type thin film transistor is turned off.
- the non-enable level is high. Therefore, the first conduction level is an enable level corresponding to a case where the thin film transistor controlled by the first conduction level VI is turned on, and the first conduction level is a non-enable level corresponding to the first guide. The case where the level VI controlled thin film transistor is turned off.
- the second conduction level is an enable level corresponding to a case where the thin film transistor controlled by the second conduction level V2 is turned on, and the second conduction level is a non-enable level corresponding to the second. The case where the thin film transistor controlled by the level V2 is turned off.
- FIG. 4 is a specific embodiment of a shift register according to the present invention.
- each of the switch tubes M1 to M8 is a TFT (English: Thin F i lm Trans is tor , Chinese: thin film transistor ).
- the pre-charging circuit 1 includes: a first thin film transistor M1, a second thin film transistor M2, a first node, a second node B, and a first capacitor C1, wherein the first thin film transistor M1 has The gate is connected to the first clock signal input terminal 52 for accessing the first clock signal CLK, the source is connected to the start signal input terminal 51, and the drain is connected to the second node B.
- the source of the first thin film transistor M1 is connected to the start signal input terminal 51 for access. Start signal STV.
- the source of the first thin film transistor M1 can also be connected to the output of the corresponding upper stage shift register, and the level signal outputted by the shift register of the previous stage is used as the start signal.
- the second thin film transistor M2 has a gate connected to the second node B, a source connected to the start signal input terminal 51, and a drain connected to the first node A.
- the first node A is configured to output a first turn-on level VI of the pre-charge circuit.
- the second node B is configured to output a second conduction level V2 of the precharge circuit.
- the first capacitor C1 has one end connected to the second node B and the other end connected to the shift register output terminal 6.
- the first pull-up circuit 2 includes: a third thin film transistor M3 having a gate connected to the first node A, a source connected to a high level VGH, and a drain connected to the shift register output 6.
- the pull-down circuit 3 includes: a fourth thin film transistor M4 having a gate connected to the second node
- the source is connected to the second clock signal input terminal 53 for accessing the second clock signal CLKB, and the drain is connected to the shift register output terminal 6.
- the reverse circuit 401 includes: a fifth thin film transistor M5, a sixth thin film transistor M6, a seventh thin film transistor M7, and a third node C, wherein the fifth thin film transistor M5 has a gate connected to the second node B, the source The pole is connected to the high level VGH, the drain is connected to the third node C; the sixth thin film transistor M6 has a gate connected to the source of the seventh thin film transistor M7, and the source is connected to the low level VGL, The drain is connected to the third node C; the seventh thin film transistor M7 has a gate connected to the low level VGL, a source connected to the gate of the sixth thin film transistor M6, and a drain connected to the low level VGL The third node C is the output of the reverse circuit 401.
- the pull-up sub-circuit 402 includes: an eighth thin film transistor M8 having a gate connected to the third node
- the source is connected to the high voltage VGH, and the drain is connected to the shift register output 6.
- FIG. 5 is a timing chart of the operation of the shift register of the embodiment.
- the shift register operates under the first clock signal CLK and the second clock signal CLKB of the differential input, that is, the first clock signal CLK and the second clock signal CLKB are differentially input. Therefore, the second clock signal CLKB is at a low level when the first clock signal CLK is at a high level, and at a high level when the first clock signal CLK is at a low level.
- the start signal STV outputs a low level
- the first clock signal CLK outputs a low level
- the second clock signal CLKB outputs a high level.
- the first thin film transistor M1 is turned on
- the second conduction level V2 outputted by the second node B is at a low level, and simultaneously starts charging the first capacitor C1
- the second thin film transistor M2 is turned on
- the first conduction level VI of the first node A is output. Is low.
- the third thin film transistor M3 is turned on, so that the high level VGH pulls the output of the third thin film transistor M3 to output a high level.
- the VOUT output from the output of the shift register 6 is at a high level.
- the fourth thin film transistor M4 is turned on, and the second clock signal CLKB is also outputted to a high level, so the VOUT outputted by the shift register output terminal 6 is still High level.
- the fifth thin film transistor M5 is turned on, the sixth thin film transistor M6 is turned off, the seventh thin film transistor M7 is turned off, the third node C outputs a high level, and the eighth thin film transistor M8 is turned off.
- the start signal STV outputs a high level
- the first clock signal CLK outputs a high level
- the second clock signal CLKB outputs a low level.
- the first thin film transistor M1 is turned off, at the same time, the first capacitor C1 starts to discharge, and the second turn-on level V2 outputted by the second node B is kept low until the discharge process of the first capacitor C1 ends. In fact, the discharge process of the first capacitor C1 continues until the next start of the charging process. Therefore, for the second conduction level V2 outputted by the second node B, the output is kept low in the second phase T2. level.
- the second conduction level V2 outputted by the second node B When the second conduction level V2 outputted by the second node B is low, the second thin film transistor M2 is turned on, and the first conduction level VI outputted by the first node A is high. When the first turn-on level VI of the first node A is at a high level, the third thin film transistor M3 is turned off. When the second conduction level V2 outputted by the second node B is low level, the fifth thin film transistor M5 is turned on, the sixth thin film transistor M6 is turned off, the seventh thin film transistor M7 is turned off, and the third node C outputs high power. Flat, the eighth thin film transistor M8 is turned off.
- the fourth thin film transistor M4 is turned on, so that the second clock signal CLKB pulls the output of the fourth thin film transistor M4 to output a low level. Therefore, the VOUT output from the output of the shift register 6 is low.
- the start signal STV outputs a high level
- the first clock signal CLK outputs a low level
- the second clock signal CLKB outputs a high level.
- the first thin film transistor M1 is turned on
- the second turn-on level V2 outputted by the second node B is at a high level
- charging of the first capacitor C1 is started
- the second thin film transistor M2 is turned off.
- the first node A becomes a floating node
- the floating node means that the state of the node is not controlled by the input voltage of the current time but by the previous moment. Control the residual voltage at the point.
- the first node A is a floating node, and the first conduction level VI of the residual output is still at a high level.
- the third thin film transistor M3 is turned off.
- the fourth thin film transistor M4 is turned off, the fifth thin film transistor M5 is turned off, the sixth thin film transistor M6 is turned on, and the seventh thin film transistor M7 is turned on.
- the third node C outputs a low level, and the eighth thin film transistor M8 is turned on, so that the high level VGH pulls the output of the eighth thin film transistor M8 to output a high level, and the VOUT of the shift register output terminal 6 is outputted at this time. Is high.
- the start signal STV outputs a high level
- the first clock signal CLK outputs a high level
- the second clock signal CLKB outputs a low level.
- the first thin film transistor M1 is turned off, and at the same time, the first capacitor C1 starts to discharge, and the second turn-on level V2 outputted by the second node B is kept high until the discharge of the first capacitor C1 ends. In fact, the discharge process of the first capacitor C1 continues until the next start of the charging process. Therefore, for the second conduction level V2 outputted by the second node B, the output high power is maintained in the fourth phase T2. level.
- the second conduction level V2 outputted by the second node B is high, the second thin film transistor M2 is turned off, and the first node A is still a floating node. Therefore, the first node A is a floating node, and the first conduction level VI of the residual output is still at a high level.
- the third thin film transistor M3 is turned off.
- the fourth thin film transistor M4 is turned off, the fifth thin film transistor M5 is turned off, the sixth thin film transistor M6 is turned on, and the seventh thin film transistor M7 is turned on.
- the third node C outputs a low level, and the eighth thin film transistor M8 is turned on, so that the high level VGH pulls the output of the eighth thin film transistor M8 to output a high level, and the VOUT of the output of the shift register output 6 is High level.
- the second node B of the shift register always outputs the second level V2 of the high level from the time of the fourth stage T4, so that the fifth thin film transistor M5 is turned off.
- the sixth thin film transistor M6 is turned on, the seventh thin film transistor M7 is turned on, the eighth thin film transistor M8 is turned on to perform the pull-up, and the shift register output terminal 6 outputs the high-level VOUT. Therefore, the occurrence of interference between multiple floating nodes affecting the output signal is eliminated, thereby improving the stability of the shift register operation.
- the second conduction level V2 outputted by the second node B is always at a high level (including the first a charging process of the second node B by the capacitor C1 and a discharging process), so that the fifth thin film transistor M5 is turned off, the sixth thin film transistor M6 is turned on, the seventh thin film transistor M7 is turned on, and the eighth thin film transistor M8 is turned on to pull
- the output level of the high shift register output 6 is such that it outputs a high level of VOUT, thus ensuring the stability of the shift register output 6 outputting a high level of VOUT.
- T1 ⁇ T4 is a complete signal change period. After ⁇ 4, no matter how the first clock signal CLK and the second clock signal CLKB change, as long as the start signal STV does not input a low level, the VOUT output of the shift register output terminal 6 remains high. When the start signal STV is input to the low level again, the shift register of the embodiment of the present invention repeatedly starts the operation timing change period of the first stage T1 to the fourth stage ⁇ 4.
- Embodiments of the present invention provide a shift register that eliminates the occurrence of mutual interference of a plurality of floating nodes affecting the characteristics of the output terminal, can effectively improve the drift phenomenon of the output signal, and improve the output stability of the shift register.
- an embodiment of the present invention further provides a gate driving circuit including the shift register described in the above embodiment.
- the gate driving circuit includes a multi-stage shift register: a first shift register, a second shift register, a third shift register, a fourth shift register, an n-th shift register, and each Stage shift register cascade connection, output V0UT1, V0UT2, V0UT3,
- V0UT4 VOUTn is used to generate the scan signal.
- Each stage shift register is connected to the first clock signal CLK, the second clock signal CLKB, the start signal, and outputs a scan signal.
- the first shift register is connected to the start signal STV, and the remaining shift registers access the scan signal outputted by the corresponding upper shift register as a start signal.
- the shift register unit circuits of each stage adopt the shift register of the above circuit structure.
- the source of the first thin film transistor M1 and the second thin film crystal of the precharge circuit in any one of the shift registers The source of the body tube M2 is no longer connected to the start signal STV but to the VOUT waveform outputted to the output of the shift register of the previous stage of any of the shift registers, and the other portions are unchanged. Therefore, the working principle and the circuit structure are the same as those of the above-described embodiment, and are not described herein.
- the first scan signal VOUT1 is input as a start signal, the first clock signal CLK and the second clock signal CLKB, and the second scan signal VOUT2 is output;
- the gate driving circuit operates under the control of the first clock signal CLK and the second clock signal CLKB, and outputs the first scan signal VOUT1 and the second scan signal V0UT2 from the top to the bottom. Scan signal VOUTN.
- Embodiments of the present invention provide a gate driving circuit, which eliminates the situation that a plurality of floating nodes of a shift register included in the shift register affect the characteristics of the output terminal, can effectively improve the drift phenomenon of the output signal, and improve the gate driving circuit.
- the stability of the work is a part of the work.
- an embodiment of the present invention also provides an array substrate including the gate driving circuit in the above embodiment.
- the portion of the gate driving circuit is the same as the above embodiment, and details are not described herein again.
- the structure of other parts of the array substrate can refer to the prior art, which will not be described in detail herein.
- Embodiments of the present invention provide an array substrate, which eliminates the situation that multiple floating nodes of the shift register included in the shift register affect the characteristics of the output end, can effectively improve the drift phenomenon of the output signal, and improve the operational stability of the array substrate. .
- an embodiment of the present invention provides a display device including the array substrate in the above embodiment.
- the array substrate portion is the same as the above embodiment, and details are not described herein again.
- the structure of other parts of the display device can be referred to the prior art, and will not be described in detail herein.
- Embodiments of the present invention provide a display device, which eliminates the situation that a plurality of floating nodes of a shift register included in the shift register affect the characteristics of the output terminal, can effectively improve the drift phenomenon of the output signal, and improve the operational stability of the display device. .
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Liquid Crystal Display Device Control (AREA)
- Shift Register Type Memory (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
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JP2015560520A JP6077681B2 (ja) | 2013-03-06 | 2013-05-02 | シフトレジスタ、ゲート駆動回路、アレイ基板及び表示装置 |
EP13861499.5A EP2966649B1 (en) | 2013-03-06 | 2013-05-02 | Shift register, gate electrode driver circuit, array substrate, and display device |
US14/366,650 US9472303B2 (en) | 2013-03-06 | 2013-05-02 | Shift register, gate driving circuit, array substrate and display device for eliminating the drifting phenomenon of output signal |
KR1020147017868A KR101639496B1 (ko) | 2013-03-06 | 2013-05-02 | 시프트 레지스터, 게이트 구동 회로, 어레이 기판, 및 디스플레이 디바이스 |
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CN201310071435.0A CN103198866B (zh) | 2013-03-06 | 2013-03-06 | 移位寄存器、栅极驱动电路、阵列基板以及显示装置 |
CN201310071435.0 | 2013-03-06 |
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US (1) | US9472303B2 (zh) |
EP (1) | EP2966649B1 (zh) |
JP (1) | JP6077681B2 (zh) |
KR (1) | KR101639496B1 (zh) |
CN (1) | CN103198866B (zh) |
WO (1) | WO2014134862A1 (zh) |
Cited By (1)
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EP3217383A4 (en) * | 2014-11-06 | 2018-07-18 | Boe Technology Group Co. Ltd. | Array substrate gate drive unit, method and circuit and display device |
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CN104485065B (zh) * | 2014-12-30 | 2017-02-22 | 上海天马有机发光显示技术有限公司 | 移位寄存器、驱动方法、栅极驱动电路 |
US10019923B2 (en) * | 2015-02-03 | 2018-07-10 | Boe Technology Group Co., Ltd. | Shift register and driving method thereof, gate driving circuit, display apparatus |
CN104835442B (zh) * | 2015-05-28 | 2017-09-26 | 京东方科技集团股份有限公司 | 移位寄存器及其驱动方法、栅极驱动电路和显示装置 |
CN105185411B (zh) * | 2015-06-30 | 2019-03-26 | 上海天马有机发光显示技术有限公司 | 一种移位寄存器及其驱动方法 |
CN105096812B (zh) * | 2015-09-24 | 2017-10-27 | 京东方科技集团股份有限公司 | 预充电电路、扫描驱动电路、阵列基板和显示装置 |
US10777116B1 (en) * | 2015-09-25 | 2020-09-15 | Apple Inc. | Electronic display emission scanning |
KR101882435B1 (ko) | 2016-10-05 | 2018-08-24 | 실리콘 디스플레이 (주) | 시프트 레지스터 |
CN106448540B (zh) * | 2016-11-18 | 2020-11-17 | 上海天马有机发光显示技术有限公司 | 显示面板、移位寄存器电路以及驱动方法 |
CN108111161A (zh) * | 2017-12-29 | 2018-06-01 | 中航(重庆)微电子有限公司 | 一种准静态动态移位寄存器及红外焦平面阵列读出电路 |
CN108806597B (zh) | 2018-08-30 | 2020-08-18 | 合肥京东方卓印科技有限公司 | 移位寄存器单元、栅极驱动电路、显示装置及驱动方法 |
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- 2013-05-02 JP JP2015560520A patent/JP6077681B2/ja active Active
- 2013-05-02 WO PCT/CN2013/075072 patent/WO2014134862A1/zh active Application Filing
- 2013-05-02 KR KR1020147017868A patent/KR101639496B1/ko active IP Right Grant
- 2013-05-02 US US14/366,650 patent/US9472303B2/en active Active
- 2013-05-02 EP EP13861499.5A patent/EP2966649B1/en active Active
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US10262572B2 (en) | 2014-11-06 | 2019-04-16 | Boe Technology Group Co., Ltd. | Gate-on-array driving unit, gate-on-array driving method, gate-on-array driving circuit, and display device |
Also Published As
Publication number | Publication date |
---|---|
EP2966649B1 (en) | 2024-01-03 |
KR101639496B1 (ko) | 2016-07-13 |
EP2966649A4 (en) | 2016-10-12 |
US20150302933A1 (en) | 2015-10-22 |
CN103198866B (zh) | 2015-08-05 |
JP6077681B2 (ja) | 2017-02-08 |
KR20140119690A (ko) | 2014-10-10 |
CN103198866A (zh) | 2013-07-10 |
EP2966649A1 (en) | 2016-01-13 |
US9472303B2 (en) | 2016-10-18 |
JP2016517606A (ja) | 2016-06-16 |
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