WO2014097454A1 - 半導体装置 - Google Patents
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- WO2014097454A1 WO2014097454A1 PCT/JP2012/083100 JP2012083100W WO2014097454A1 WO 2014097454 A1 WO2014097454 A1 WO 2014097454A1 JP 2012083100 W JP2012083100 W JP 2012083100W WO 2014097454 A1 WO2014097454 A1 WO 2014097454A1
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Definitions
- the technology described in this specification relates to a semiconductor device.
- Japanese Patent Publication No. 2012-43890 discloses a semiconductor device in which an IGBT region and a diode region are formed on the same semiconductor substrate.
- a surface electrode is provided on the front surface of the semiconductor substrate, and a back electrode is provided on the back surface of the semiconductor substrate.
- the IGBT region includes a first conductivity type collector layer in contact with the back electrode, a second conductivity type IGBT drift layer provided on the surface side of the semiconductor substrate with respect to the collector layer, and an IGBT drift layer.
- a first conductivity type body layer that is provided on the surface side of the semiconductor substrate and is in contact with the surface electrode, and a trench that extends from the surface of the semiconductor substrate to the IGBT drift layer.
- a gate electrode insulated from the surface electrode, and a second conductivity type emitter layer that is partially provided between the body layer and the surface electrode and is in contact with the insulating film of the gate electrode and the surface electrode .
- the diode region is provided with a high second conductivity type cathode layer in contact with the back electrode, and a second conductivity type diode having an impurity concentration lower than that of the cathode layer.
- the drift layer is provided on the surface side of the semiconductor substrate with respect to the diode drift layer.
- the first conductivity type anode layer is in contact with the surface electrode, and the trench extends from the surface of the semiconductor substrate to the diode drift layer.
- a first conductivity type that is disposed between the trench electrode insulated from the semiconductor substrate by the insulating film and between the anode layer and the surface electrode, and is in contact with the surface electrode and has a higher impurity concentration than the anode layer;
- the anode contact layer is provided.
- the diode region is partitioned into unit diode regions by a gate electrode or a trench electrode.
- the anode contact layer is widely formed in the diode region, the amount of holes injected from the anode contact layer to the diode drift layer increases during diode operation, and switching loss increases. For this reason, in order to improve the switching loss during the diode operation, it is preferable to reduce the proportion of the anode contact layer in the diode region. However, if the anode contact layer is simply reduced, forward voltage fluctuations due to gate interference increase during diode operation.
- This specification discloses a semiconductor device in which an IGBT region and a diode region are formed on the same semiconductor substrate.
- a surface electrode is provided on the front surface of the semiconductor substrate, and a back electrode is provided on the back surface of the semiconductor substrate.
- the IGBT region includes a first conductivity type collector layer in contact with the back electrode, a second conductivity type IGBT drift layer provided on the surface side of the semiconductor substrate with respect to the collector layer, and an IGBT drift layer.
- a first conductivity type body layer that is provided on the surface side of the semiconductor substrate and is in contact with the surface electrode, and a trench that extends from the surface of the semiconductor substrate to the IGBT drift layer.
- a gate electrode insulated from the surface electrode, and a second conductivity type emitter layer that is partially provided between the body layer and the surface electrode and is in contact with the insulating film of the gate electrode and the surface electrode .
- the diode region is provided with a high second conductivity type cathode layer in contact with the back electrode, and a second conductivity type diode having an impurity concentration lower than that of the cathode layer.
- the drift layer is provided on the surface side of the semiconductor substrate with respect to the diode drift layer.
- the first conductivity type anode layer is in contact with the surface electrode, and the trench extends from the surface of the semiconductor substrate to the diode drift layer.
- An anode contact layer of one conductivity type is provided.
- the diode region is partitioned into unit diode regions by a gate electrode or a trench electrode. In the unit diode region adjacent to the IGBT region, when the surface of the semiconductor substrate is viewed in plan, the anode layer and the anode contact layer are mixedly arranged, and at least at the place facing the emitter layer with the gate electrode interposed therebetween, An anode contact layer is disposed.
- the anode contact layer is not formed entirely but partially formed in the unit diode region adjacent to the IGBT region. With this configuration, the amount of holes injected from the anode contact layer into the diode drift layer during diode operation is reduced. The reverse recovery characteristic of the diode region can be improved and the switching loss can be reduced.
- the influence of gate interference during diode operation can be suppressed. That is, even when a gate voltage is applied to the gate electrode in the IGBT region and a channel connecting the emitter layer and the IGBT drift layer is formed in the vicinity of the gate electrode during diode operation, a unit adjacent to the IGBT region is formed. In the diode region, since the anode contact layer is formed at a position facing the emitter layer with the gate electrode interposed therebetween, it is possible to suppress the reduction of holes due to the formation of the channel. Thereby, fluctuations in the forward voltage due to gate interference during diode operation can be suppressed.
- FIG. 1 is a plan view of a semiconductor device according to Example 1.
- FIG. FIG. 2 is a sectional view taken along line II-II in FIG.
- FIG. 3 is a sectional view taken along line III-III in FIG. 1. It is a top view of the semiconductor device which concerns on a modification. It is a top view of the semiconductor device which concerns on a modification. It is a top view of the semiconductor device which concerns on a modification. It is a top view of the semiconductor device which concerns on a modification.
- anode contact layers and anode layers are alternately arranged in the unit diode region adjacent to the IGBT region in the direction in which the gate electrode extends when the surface of the semiconductor substrate is viewed in plan view. Can be configured.
- the anode contact layer is left in a portion facing the emitter layer with the gate electrode interposed therebetween, and the proportion of the anode contact layer in the unit diode region is reduced. Can be made.
- the semiconductor device disclosed in this specification includes an anode contact layer in the vicinity of a gate electrode in a unit diode region adjacent to the IGBT region in a direction orthogonal to the direction in which the gate electrode extends when the surface of the semiconductor substrate is viewed in plan view.
- the anode layer is arranged in the center of the unit diode region.
- the anode contact layer is left in a portion facing the emitter layer with the gate electrode interposed therebetween, and the proportion of the anode contact layer in the unit diode region is reduced. Can be made.
- the semiconductor device 2 shown in FIG. 1 to FIG. 3 is an RC-IGBT in which an IGBT and a diode are formed on the same semiconductor substrate 4.
- the semiconductor device 2 has a plurality of IGBT regions and a plurality of diode regions alternately arranged, and has a plurality of boundaries between the IGBT regions and the diode regions.
- 1 to 3 illustrate one of the boundaries between the plurality of IGBT regions and the diode region, and each of the plurality of boundaries of the semiconductor device 2 has the same configuration as in FIGS. ing.
- the semiconductor device 2 includes a semiconductor substrate 4, a dummy gate 8, an insulating gate 10 and a surface insulating film 12 formed on the surface side of the semiconductor substrate 4, a surface electrode 6 in contact with the surface of the semiconductor substrate 4, and the semiconductor substrate 4 And a back electrode 14 in contact with the back surface.
- the dummy gate 8 and the insulated gate 10 are formed on the semiconductor substrate 4 at a substantially constant interval.
- the semiconductor substrate 4 includes a diode region 16 and an IGBT region 18.
- the diode region 16 is made of an anode contact layer 20 made of a p-type semiconductor having a high impurity concentration, an anode layer 22 made of a p-type semiconductor, and an n-type semiconductor having a low impurity concentration.
- a drift layer 24, a buffer layer 26 made of an n-type semiconductor, and a cathode layer 28 made of an n-type semiconductor having a high impurity concentration are formed.
- the anode contact layer 20 and the anode layer 22 are exposed on the surface of the semiconductor substrate 4 and are in contact with the surface electrode 6.
- the anode contact layer 20 is partially formed on the surface layer portion of the anode layer 22.
- the drift layer 24 is formed on the back surface of the anode layer 22.
- the buffer layer 26 is formed on the back surface of the drift layer 24.
- the cathode layer 28 is formed on the back surface of the buffer layer 26. The cathode layer 28 is exposed on the back surface of the semiconductor substrate 4 and is in contact with the back electrode 14.
- the IGBT region 18 includes a body contact layer 30 made of a p-type semiconductor having a high impurity concentration, an emitter layer 32 made of an n-type semiconductor having a high impurity concentration, a body layer 34 made of a p-type semiconductor, and an n having a low impurity concentration.
- a drift layer 24 made of a p-type semiconductor, a buffer layer 26 made of an n-type semiconductor, and a collector layer 36 made of a p-type semiconductor having a high impurity concentration are formed.
- the body contact layer 30, the emitter layer 32, and the body layer 34 are exposed on the surface of the semiconductor substrate 4 and are in contact with the surface electrode 6.
- the body contact layer 30 and the emitter layer 32 are partially formed on the surface layer portion of the body layer 34.
- the drift layer 24 is formed on the back surface of the body layer 34.
- the buffer layer 26 is formed on the back surface of the drift layer 24.
- the collector layer 36 is formed on the back surface of the buffer layer 26. The collector layer 36 is exposed on the back surface of the semiconductor substrate 4 and is in contact with the back electrode 14.
- the drift layer 24 (also referred to as a diode drift layer) in the diode region 16 and the drift layer 24 (also referred to as an IGBT drift layer) in the IGBT region 18 are formed as a common layer.
- the buffer layer 26 in the diode region 16 and the buffer layer 26 in the IGBT region 18 are formed as a common layer.
- the anode layer 22 in the diode region 16 and the body layer 34 in the IGBT region 18 are formed as a common layer. In other words, the anode layer 22 in the diode region 16 and the body layer 34 in the IGBT region 18 have a common depth and impurity concentration from the surface of the semiconductor substrate 4.
- the dummy gate 8 penetrates the anode layer 22 from the surface side of the semiconductor substrate 4 and reaches the inside of the drift layer 24 in the diode region 16.
- the dummy gate 8 includes a dummy gate insulating film 40 formed inside a trench 38 formed on the surface side of the semiconductor substrate 4, and a dummy gate electrode covered with the dummy gate insulating film 40 and filled in the trench 38. 42.
- the dummy gate electrode 42 is in contact with the surface electrode 6 and is electrically connected to the surface electrode 6.
- the insulated gate 10 penetrates the body layer 34 from the surface side of the semiconductor substrate 4 and reaches the inside of the drift layer 24 in the IGBT region 18.
- the insulated gate 10 includes a gate insulating film 46 formed on the inner wall of the trench 44 formed on the surface side of the semiconductor substrate 4 and a gate electrode 48 covered with the gate insulating film 46 and filled in the trench 44. I have.
- the gate electrode 48 is isolated from the surface electrode 6 by the surface insulating film 12.
- the gate electrode 48 is electrically connected to a gate electrode terminal (not shown).
- the diode region 16 is composed of a plurality of unit diode regions partitioned by the trench 38 of the dummy gate 8 or the trench 44 of the insulated gate 10.
- the IGBT region 18 is composed of a plurality of unit IGBT regions partitioned by the trench 44 of the insulated gate 10.
- a unit diode region adjacent to the IGBT region 18 is referred to as a unit diode region 16a
- a unit IGBT region adjacent to the unit diode region 16a is referred to as a unit IGBT region 18a.
- the emitter layer 32 is between two insulated gates 10 arranged side by side in a direction (Y direction in the figure) in which the insulated gate 10 extends from one insulated gate 10 to the other insulated gate 10. It arrange
- the body layer 34 is partitioned into a rectangular range by the insulated gate 10 and the emitter layer 32, and the body contact layer 30 is disposed near the center of the partitioned body layer 34. Has been.
- the anode contact layer 20 is disposed only in a region close to the insulated gate 10 or the dummy gate 8.
- the anode contact layer 20 is disposed only on the extension line in the direction in which the emitter layer 32 extends in the IGBT region 18. That is, in the unit diode region 16a adjacent to the IGBT region 18, the anode contact layer 20 is disposed at a position facing the emitter layer 32 of the unit IGBT region 18a adjacent to the unit diode region 16a with the insulating gate 10 interposed therebetween. Yes.
- the anode contact layer 20 and the anode layer 22 are alternately arranged in the vicinity of the insulating gate 10 in the direction in which the insulating gate 10 extends (Y direction in the figure).
- the anode contact layer 20 is disposed in the vicinity of the insulating gate 10 in the unit diode region 16a adjacent to the unit IGBT region 18a in the direction orthogonal to the direction in which the insulating gate 10 extends (X direction in the figure).
- the anode layer 22 is disposed at the center of the unit diode region 16a.
- the impurity concentration of the anode layer 22 at a location facing the emitter layer 32 with the insulating gate 10 interposed therebetween is higher.
- the impurity concentration of the anode layer 22 in the unit diode region 16a adjacent to the unit IGBT region 18a is a maximum value at a location facing the emitter layer 32 with the insulated gate 10 interposed therebetween.
- the anode contact layer 20 is formed in a unit diode region 16a adjacent to the unit IGBT region 18a at a location facing the emitter layer 32 with the insulating gate 10 interposed therebetween.
- the influence of gate interference during diode operation can be suppressed. That is, even when a gate voltage is applied to the gate electrode 48 of the unit IGBT region 18a and a channel connecting the emitter layer 32 and the drift layer 24 is formed in the vicinity of the insulated gate 10 during diode operation, Since the anode contact layer 20 is formed at a position facing the emitter layer 32 across the insulated gate 10 in the diode region 16a, the reduction of holes due to the formation of the channel can be suppressed. Thereby, fluctuations in the forward voltage due to gate interference during diode operation can be suppressed.
- the anode contact layer 20 is not formed entirely but partially formed in the unit diode region 16a adjacent to the unit IGBT region 18a. With this configuration, the amount of holes injected from the anode contact layer 20 into the drift layer 24 during diode operation is reduced. The reverse recovery characteristic of the diode region 16 can be improved and the switching loss can be reduced.
- the arrangement of the anode contact layer 20 in the diode region 16 is not limited to that in the above embodiment.
- the anode contact layer 20 has a direction (X direction in the figure) orthogonal to the direction (Y direction in the figure) in which the insulated gate 10 or the dummy gate 8 extends. It may be arranged to extend.
- the anode contact layer 20 is disposed only on the extension line in the direction in which the emitter layer 32 extends in the IGBT region 18.
- the anode contact layer 20 and the anode layer 22 are alternately arranged in the direction in which the insulated gate 10 extends (Y direction in the drawing). .
- the anode contact layer 20 may be formed in a ladder shape having a partial opening.
- the anode contact layer 20 and the anode layer are formed in the center of the unit diode region 16a with respect to the direction in which the insulated gate 10 extends (Y direction in the figure). 22 are alternately arranged.
- the anode contact layer is located in the vicinity of the insulating gate 10 in the direction orthogonal to the direction in which the insulating gate 10 extends (X direction in the figure). 20 is disposed, and the anode layer 22 is disposed in the center of the unit diode region 16a.
- the arrangement of the emitter layer 32 in the IGBT region 18 is not limited to that in the above embodiment.
- the emitter layers 32 may be arranged in a lattice pattern as in the semiconductor device 54 of the modification shown in FIG.
- the emitter layer 32 may be arranged in a ladder shape having a partial opening.
- the anode contact layer 20 in the diode region 16 is disposed at a location facing the emitter layer 32 with the insulated gate 10 interposed therebetween.
- the anode contact layer 20 in the diode region 16 extends parallel to the direction (Y direction) in which the insulated gate 10 or the dummy gate 8 extends at a location close to the insulated gate 10 or the dummy gate 8. Is arranged.
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Abstract
Description
ダイオード領域16におけるアノードコンタクト層20の配置は、上記の実施例のものに限られるものではない。例えば、図4に示す変形例の半導体装置50のように、アノードコンタクト層20は、絶縁ゲート10またはダミーゲート8が伸びる方向(図のY方向)に対して直交する方向(図のX方向)に伸びるように配置されていてもよい。図4に示す変形例では、アノードコンタクト層20は、IGBT領域18においてエミッタ層32が伸びる方向の延長線上にのみ配置されている。図4に示す変形例では、単位IGBT領域18aに隣接する単位ダイオード領域16aにおいて、絶縁ゲート10が伸びる方向(図のY方向)に関して、アノードコンタクト層20とアノード層22が交互に配置されている。
Claims (3)
- IGBT領域とダイオード領域が同一半導体基板に形成されている半導体装置であって、
半導体基板の表面には表面電極が設けられており、半導体基板の裏面には裏面電極が設けられており、
IGBT領域は、
裏面電極に接している第1導電型のコレクタ層と、
コレクタ層に対して半導体基板の表面側に設けられた、第2導電型のIGBTドリフト層と、
IGBTドリフト層に対して半導体基板の表面側に設けられており、表面電極に接している第1導電型のボディ層と、
半導体基板の表面からIGBTドリフト層まで達するトレンチの内部に配置されており、絶縁膜によって半導体基板と表面電極から絶縁されたゲート電極と、
ボディ層と表面電極の間に部分的に設けられており、ゲート電極の絶縁膜と表面電極に接している第2導電型のエミッタ層を備えており、
ダイオード領域は、
裏面電極に接している高い第2導電型のカソード層と、
カソード層に対して半導体基板の表面側に設けられており、不純物濃度がカソード層よりも低い第2導電型のダイオードドリフト層と、
ダイオードドリフト層に対して半導体基板の表面側に設けられており、表面電極に接している第1導電型のアノード層と、
半導体基板の表面からダイオードドリフト層まで達するトレンチの内部に配置されており、絶縁膜によって半導体基板から絶縁されたトレンチ電極と、
アノード層と表面電極の間に部分的に設けられており、表面電極に接している、不純物濃度がアノード層よりも高い第1導電型のアノードコンタクト層を備えており、
ダイオード領域は、ゲート電極またはトレンチ電極によって、単位ダイオード領域に区画されており、
IGBT領域と隣接する単位ダイオード領域において、半導体基板の表面を平面視したときに、アノード層とアノードコンタクト層が混在して配置されており、少なくともゲート電極を挟んでエミッタ層と対向する箇所に、アノードコンタクト層が配置されている、半導体装置。 - IGBT領域と隣接する単位ダイオード領域において、半導体基板の表面を平面視したときに、ゲート電極が伸びる方向に関して、アノードコンタクト層とアノード層が交互に配置されている、請求項1の半導体装置。
- IGBT領域と隣接する単位ダイオード領域において、半導体基板の表面を平面視したときに、ゲート電極が伸びる方向に直交する方向に関して、ゲート電極の近傍にアノードコンタクト層が配置されており、単位ダイオード領域の中央にアノード層が配置されている、請求項1または2の半導体装置。
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US14/443,199 US10074719B2 (en) | 2012-12-20 | 2012-12-20 | Semiconductor device in which an insulated-gate bipolar transistor ( IGBT) region and a diode region are formed on one semiconductor substrate |
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Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015177058A (ja) * | 2014-03-14 | 2015-10-05 | 株式会社東芝 | 半導体装置 |
WO2016009714A1 (ja) * | 2014-07-14 | 2016-01-21 | トヨタ自動車株式会社 | 半導体装置 |
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JP2018182216A (ja) * | 2017-04-20 | 2018-11-15 | トヨタ自動車株式会社 | 半導体装置 |
US10763252B2 (en) | 2017-03-15 | 2020-09-01 | Fuji Electric Co., Ltd. | Semiconductor device |
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Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6537711B2 (ja) * | 2016-04-25 | 2019-07-03 | 三菱電機株式会社 | 半導体装置 |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007221012A (ja) * | 2006-02-20 | 2007-08-30 | Fuji Electric Device Technology Co Ltd | Mos型半導体装置とその製造方法 |
JP2010171385A (ja) * | 2008-12-24 | 2010-08-05 | Denso Corp | 半導体装置 |
JP2012043890A (ja) * | 2010-08-17 | 2012-03-01 | Denso Corp | 半導体装置 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008066694A (ja) * | 2006-03-16 | 2008-03-21 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
EP2003694B1 (en) * | 2007-06-14 | 2011-11-23 | Denso Corporation | Semiconductor device |
JP4952638B2 (ja) | 2008-04-07 | 2012-06-13 | トヨタ自動車株式会社 | 半導体素子と半導体装置とその駆動方法 |
JP5672766B2 (ja) | 2010-05-17 | 2015-02-18 | 株式会社デンソー | 半導体装置 |
DE102011079747A1 (de) * | 2010-07-27 | 2012-02-02 | Denso Corporation | Halbleitervorrichtung mit Schaltelement und Freilaufdiode, sowie Steuerverfahren hierfür |
US8716746B2 (en) | 2010-08-17 | 2014-05-06 | Denso Corporation | Semiconductor device |
JP2012064849A (ja) | 2010-09-17 | 2012-03-29 | Toshiba Corp | 半導体装置 |
MX2014002269A (es) | 2011-08-30 | 2014-04-25 | Toyota Motor Co Ltd | Dispositivo de semiconductor. |
-
2012
- 2012-12-20 DE DE112012007249.9T patent/DE112012007249B4/de active Active
- 2012-12-20 WO PCT/JP2012/083100 patent/WO2014097454A1/ja active Application Filing
- 2012-12-20 JP JP2014552840A patent/JP5924420B2/ja active Active
- 2012-12-20 US US14/443,199 patent/US10074719B2/en not_active Expired - Fee Related
- 2012-12-20 CN CN201280077788.5A patent/CN104871312B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007221012A (ja) * | 2006-02-20 | 2007-08-30 | Fuji Electric Device Technology Co Ltd | Mos型半導体装置とその製造方法 |
JP2010171385A (ja) * | 2008-12-24 | 2010-08-05 | Denso Corp | 半導体装置 |
JP2012043890A (ja) * | 2010-08-17 | 2012-03-01 | Denso Corp | 半導体装置 |
Cited By (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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EP3171410A4 (en) * | 2014-07-14 | 2017-07-26 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
WO2016009714A1 (ja) * | 2014-07-14 | 2016-01-21 | トヨタ自動車株式会社 | 半導体装置 |
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US9793266B2 (en) | 2014-07-14 | 2017-10-17 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
JP2016039215A (ja) * | 2014-08-06 | 2016-03-22 | トヨタ自動車株式会社 | 半導体装置及び半導体装置の製造方法 |
US9966372B2 (en) | 2014-08-06 | 2018-05-08 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device and method of manufacturing semiconductor device having parallel contact holes between adjacent trenches |
WO2016021299A1 (ja) * | 2014-08-06 | 2016-02-11 | トヨタ自動車株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2018113470A (ja) * | 2014-11-17 | 2018-07-19 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
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US11908954B2 (en) | 2020-03-26 | 2024-02-20 | Mitsubishi Electric Corporation | Semiconductor device with insulated gate bipolar transistor region and diode region provided on semiconductor substrate and adjacent to each other |
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US10074719B2 (en) | 2018-09-11 |
US20150295042A1 (en) | 2015-10-15 |
DE112012007249B4 (de) | 2021-02-04 |
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