WO2014027570A1 - 信号生成装置 - Google Patents
信号生成装置 Download PDFInfo
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- WO2014027570A1 WO2014027570A1 PCT/JP2013/070737 JP2013070737W WO2014027570A1 WO 2014027570 A1 WO2014027570 A1 WO 2014027570A1 JP 2013070737 W JP2013070737 W JP 2013070737W WO 2014027570 A1 WO2014027570 A1 WO 2014027570A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
- H04L7/0025—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of clock signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0223—Computation saving measures; Accelerating measures
- H03H17/0227—Measures concerning the coefficients
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0283—Filters characterised by the filter structure
- H03H17/0286—Combinations of filter structures
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0294—Variable filters; Programmable filters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
- H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/08—Speed or phase control by synchronisation signals the synchronisation signals recurring cyclically
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0219—Compensation of undesirable effects, e.g. quantisation noise, overflow
- H03H2017/0222—Phase error
Definitions
- the present invention relates to a signal generation apparatus that performs interpolation of digital signals.
- Non-Patent Document 1 discloses a technique for generating a signal having a desired phase using a digital filter and a filter coefficient corresponding to each phase interval to be adjusted, and interpolating the digital signal.
- Patent Document 1 a technique related to a variable digital filter that can change the frequency characteristics without disturbing the characteristics of the digital filter is disclosed. Coefficients that can interpolate different phases by changing the multiplier of the multiplier are stored in the memory address, coefficient data that complements the phase closest to the desired phase value is read, and the multiplier multiplier is changed to obtain a true value By obtaining an interpolation value close to 0, the memory capacity is reduced while allowing fine adjustment of the frequency characteristics without disturbing the filter characteristics.
- the present invention has been made in view of the above, and an object of the present invention is to obtain a signal generator capable of generating an interpolation signal without increasing the memory capacity when an interpolation value close to a true value is obtained.
- the present invention interpolates an input signal and outputs a first interpolation signal, and interpolates the first interpolation signal to obtain a phase.
- a second digital filter that corrects an error and outputs a second interpolation signal;
- a phase calculation unit that calculates a phase of the digital signal that changes at a time step updated in units of output sampling periods of the two digital filters;
- the first phase signal which is an address indicating the filter coefficient used for the interpolation of the first digital filter, and the filter coefficient used for the interpolation of the second digital filter are indicated.
- Phase accuracy conversion means for calculating a second phase signal for calculating an address to be calculated, and a frame for the address indicated by the first phase signal.
- a first memory for storing a filter coefficient, and a first coefficient for reading out a filter coefficient from the first memory based on the first phase signal and switching a filter coefficient of a multiplier included in the first digital filter
- a phase error calculating means for calculating a phase error signal which is an address indicating a filter coefficient used for interpolation of the second digital filter based on the second phase signal;
- a second memory for storing the filter coefficient at the indicated address; a second coefficient reading means for reading the filter coefficient from the second memory based on the phase error signal; and the second coefficient reading means in the second coefficient reading means.
- the gain normalization of the filter coefficients is performed, and the second digit is obtained.
- Rufiruta characterized in that it comprises a gain normalization means for switching the filter coefficient of the multiplier provided in the.
- the signal generation device has an effect that an interpolation signal can be generated without increasing the memory capacity when an interpolation value close to a true value is obtained.
- FIG. 1 is a diagram illustrating a configuration example of a signal generation device.
- FIG. 2 is a diagram illustrating a configuration example of the phase calculation unit 3.
- FIG. 3 is a diagram illustrating a specific example of the calculation method of equations (3) to (5) in the phase accuracy conversion unit 4.
- FIG. 4 is a diagram showing an internal configuration of the memory 5.
- FIG. 5 is a diagram illustrating a shift register included in the phase error calculation unit 7.
- FIG. 6 is a diagram showing an internal configuration of the memory 8.
- FIG. 1 is a diagram illustrating a configuration example of a signal generation device according to the present embodiment.
- the signal generation device includes a digital filter unit 1, a digital filter unit 2, a phase calculation unit 3, a phase accuracy conversion unit 4, a memory 5, a coefficient reading unit 6, a phase error calculation unit 7, a memory 8, A coefficient reading unit 9 and a gain normalization unit 10.
- the digital filter unit 1 is a first digital filter, and performs a product-sum operation on the input signal and the filter coefficient stored in the memory 5 to generate an interpolation signal D (m).
- the digital filter unit 1 includes delay units 11, 12 and 13, multipliers 14, 15 and 16, and adders 17 and 18. Since the configuration of the digital filter unit 1 is a commonly used configuration, a detailed description thereof is omitted.
- the digital filter unit 2 is a second digital filter, and performs a product-sum operation on the output of the digital filter unit 1 (interpolation signal D (m)) and the filter coefficient stored in the memory 8 to obtain an interpolation signal D ′ (m ) Is generated.
- the digital filter unit 2 includes delay devices 21, 22, 23, multipliers 24, 25, 26, and adders 27, 28.
- the configuration of the digital filter unit 2 is a commonly used configuration, and thus detailed description thereof is omitted.
- the phase calculation unit 3 calculates the phase ( ⁇ (m)) of the digital signal used in the own device based on the given set value and the phase resolution of the own device.
- the phase accuracy conversion unit 4 is a phase signal (A (m)) that is an address for selecting a filter coefficient to be used in the digital filter unit 1 based on the phase of the digital signal calculated by the phase calculation unit 3, and the digital filter unit 2 calculates a phase signal (B (m)) for calculating a phase error signal which is an address for selecting a filter coefficient to be used.
- the memory 5 is a first memory (storage means) for storing filter coefficients used in the digital filter unit 1.
- the coefficient reading unit 6 is a first coefficient reading unit that reads the filter coefficient from the memory 5 and switches the filter coefficient used in the digital filter unit 1.
- the phase error calculation unit 7 uses the past value of the phase signal (B (m)) from the phase accuracy conversion unit 4 and the number of oversampling, and is a phase that is an address for selecting a filter coefficient used in the digital filter unit 2. Error signals (B ′ (m ⁇ 1), B ′ (m ⁇ 2), B ′ (m ⁇ 3)) are calculated.
- the memory 8 is a second memory (storage means) for storing filter coefficients used in the digital filter unit 2.
- the coefficient reading unit 9 is a second coefficient reading unit that reads the filter coefficient from the memory 8 and outputs the filter coefficient to the gain normalization unit 10.
- the gain normalization unit 10 normalizes the filter coefficient and switches the filter coefficient used in the digital filter unit 2.
- phase calculation unit 3 First, the operation of the phase calculation unit 3 will be described. First, a value R obtained by the following equation (1) is given as a set value to the phase calculation unit 3.
- M represents the phase resolution of the signal generation device, and is an integer value of 0 or more. If the right side is not divisible, the first decimal place is rounded off to obtain an integer value. A method for setting the phase resolution M will be described later.
- the phase calculation unit 3 cumulatively adds the set value R in units of output sampling frequency as shown in the following equation (2), and calculates it as the phase of the digital signal.
- the phase of the digital signal that is the cumulative addition result is ⁇ (m)
- m is a time step that is updated in units of output sampling periods
- mod is a remainder calculation.
- the phase calculation unit 3 outputs the calculated phase ⁇ (m) of the digital signal to the phase accuracy conversion unit 4.
- the phase calculation unit 3 generates a clock having an input sampling frequency by generating a pulse at a timing when the phase ⁇ (m) of the digital signal returns to 0 after exceeding the phase resolution M.
- the generated clock is used as the input sampling clock for the input timing of the input signal of the digital filter unit 1.
- FIG. 2 is a diagram illustrating a configuration example of the phase calculation unit 3.
- the phase calculation unit 3 includes a cumulative adder 31.
- the set value R is a value calculated by the above equation (1).
- the output sampling clock is a clock having an output sampling period.
- the phase ⁇ (m) of the digital signal is a value calculated by the above equation (2), and indicates the phase of the digital signal for each output sampling period.
- the cumulative adder 31 receives the phase ⁇ (m) of the output digital signal as feedback and uses it when calculating the phase of the next digital signal.
- the phase calculation unit 3 can calculate the phase ⁇ (m) of the digital signal by using the cumulative adder 31 shown in FIG. 2 to cumulatively add the set value R in units of output sampling clocks. Further, as described above, an input sampling clock is generated and output.
- the phase accuracy conversion unit 4 is a first phase signal for reading out the filter coefficient used in the digital filter unit 1 based on the phase ⁇ (m) of the digital signal input from the phase calculation unit 3.
- a phase signal A (m) and a phase signal B (m) that is a second phase signal for calculating a phase error signal that is an address for selecting a filter coefficient used in the digital filter unit 2 are respectively It calculates according to Formula (3) and Formula (4).
- the phase accuracy conversion unit 4 outputs the phase signal A (m) to the coefficient reading unit 6 and outputs the phase signal B (m) to the phase error calculation unit 7.
- the above P and Q are integer values of 0 or more that satisfy the following formula (5), P is the phase resolution in the digital filter unit 2, and Q is the phase resolution in the digital filter unit 1. Therefore, the phase resolution M of the signal generation device can be obtained from the product of the phase resolution P of the digital filter unit 2 and the phase resolution Q of the digital filter unit 1.
- FIG. 3 is a diagram showing a specific example of the calculation method of the equations (3) to (5) in the phase accuracy conversion unit 4.
- the range ⁇ (m) of the digital signal is determined by the phase resolution M as represented by the equation (2).
- M 4096 (12 bits)
- the phase ⁇ (m) of the digital signal is expressed by 12 bits.
- the phase signal A (m) is a value calculated by the equation (3).
- P 16
- the phase signal A (m) is the upper 8 bits ((11, m) of the phase ⁇ (m) of the digital signal. ) To (4, m)).
- (x, y) in FIG. 3 indicates a bit number
- y indicates a time step number updated in units of output sampling periods.
- phase signal B (m) is obtained by taking the lower 4 bits ((3, m) to (0, m)) of the phase ⁇ (m) of the digital signal. be able to.
- the phase accuracy conversion unit 4 outputs the phase signal A (m) to the coefficient reading unit 6 and outputs the phase signal B (m) to the phase error calculation unit 7.
- the memory 5 stores a total of Q sets of filter coefficients in the order of 0 / Q, 1 / Q, 2 / Q,..., (Q ⁇ 1) / Q at a phase interval of 1 / Q of the period of the input sampling frequency.
- One set of filter coefficients is composed of filter coefficients corresponding to the number of multipliers included in the digital filter unit 1, and filter coefficients corresponding to each multiplier are determined.
- FIG. 4 is a diagram showing an internal configuration of the memory 5.
- the i-th filter coefficient is a filter coefficient for i / Q phase, and is composed of w (i, 0) to w (i, L ⁇ 1).
- w (i, 0) corresponds to the multiplier 14
- w (i, 1) corresponds to the multiplier 15
- w (i, 2) corresponds to the multiplier 16.
- the phase information A (m) instructed from the coefficient reading unit 6 has a value from 0 to Q-1.
- the coefficient reading unit 6 reads out the filter coefficient from the memory 5 according to the phase signal A (m) using the phase signal A (m) output from the phase accuracy conversion unit 4 as a read address, and outputs the filter coefficient to the digital filter unit 1.
- the filter coefficients used in the multipliers 14, 15, and 16 are switched.
- the digital filter unit 1 performs a product-sum operation on the input signal and the filter coefficient output from the coefficient reading unit 6, and generates and outputs an interpolation signal D (m) from the input signal.
- FIG. 5 is a diagram illustrating a shift register included in the phase error calculation unit 7.
- the phase error calculation unit 7 receives the phase signal B (m) from the phase accuracy conversion unit 4 and outputs the phase signal B (m ⁇ 1) to B (m ⁇ K) up to K steps before the sampling period of the output signal. ) Are stored in the shift register.
- K is the same value as the number of multipliers provided in the digital filter unit 2 for the convolution operation.
- the phase error calculation unit 7 converts these stored phase signals from the phase error signal B ′ (m ⁇ 1) to B ′ (m ⁇ K) by the following equation (6).
- N is the number of oversamples calculated from (output sampling frequency) / (input sampling frequency). The oversampling number always takes a constant value when the output sampling frequency and the input sampling frequency are fixed.
- the phase error calculation unit 7 outputs a phase error signal corresponding to the number of delay time steps of the output data from the digital filter unit 1 stored in the shift register of the digital filter unit 2.
- the digital filter unit 2 shown in FIG. 1 internally outputs the output data D (m ⁇ 1), D (m ⁇ 2), D (m ⁇ 3) from the digital filter unit 1. Therefore, B ′ (m ⁇ 1), B ′ (m ⁇ 2), and B ′ (m ⁇ 3) are output.
- the memory 8 has N / (P ⁇ N) phase intervals of the period of the input sampling frequency, and 0 / (P ⁇ N), N / (P ⁇ N), 2N / (P ⁇ N),.
- a total of P sets of filter coefficients are stored in the order of (N ⁇ N) / (P ⁇ N).
- One set of filter coefficients is composed of filter coefficients corresponding to the number of multipliers included in the digital filter unit 2, and the filter coefficients corresponding to each multiplier are determined.
- FIG. 6 is a diagram showing an internal configuration of the memory 8.
- the i-th filter coefficient is a filter coefficient for (i ⁇ N) / (P ⁇ N) phase, and is composed of u (i, 0) to u (i, K ⁇ 1).
- the correspondence between the filter coefficient and the multiplier is that u (i, 0) corresponds to the multiplier 24, u (i, 1) corresponds to the multiplier 25, and u (i, 2) corresponds to the multiplier 26.
- u (B ′ (m ⁇ 1), 0) of the B ′ (m ⁇ 1) th filter coefficient indicated by the phase error information B ′ (m ⁇ 1) to B ′ (m ⁇ 3) The u ′ (B ′ (m ⁇ 2), 1) of the B ′ (m ⁇ 2) th filter coefficient and u (B ′ (m ⁇ 3), 2) of the B ′ (m ⁇ 3) th filter coefficient are the filters.
- the coefficient is read by the coefficient reading unit 9 as a coefficient.
- the memory 8 receives a plurality of pieces of phase error information. For each of the phase error information, one multiplier is used depending on the value of the phase error information and the number of delay steps of the phase error information. One filter coefficient u (x, y) corresponding to is read out.
- the coefficient reading unit 9 uses the phase signals B ′ (m ⁇ 1) to B ′ (m ⁇ K) output from the phase accuracy conversion unit 4 as read addresses, and uses the phase signals B ′ (m ⁇ 1) to B ′ ( m ⁇ 3), the filter coefficients are read out from the memory 8, and the filter coefficients u (B ′ (m ⁇ 1), 0) to u (B ′ (m ⁇ 3), 2) (in FIG. 1, T (m ⁇ 1) to T (m-3)) are taken out.
- the total sum u (i, 0) + u (i, 1) + u (i, 2) Z of the filter coefficients is designed to be constant. .
- Z is an arbitrary real number fixed value.
- the total sum u (B ′ (m ⁇ 1), 0) + u (B ′ (m ⁇ 2), 1) of the extracted filter coefficients. + U (B ′ (m ⁇ 3), 2) is not constant and varies depending on the combination of B ′ (m ⁇ 1) to B ′ (m ⁇ 3).
- the gain normalization unit 10 obtains a normalization factor using the following equations (7) to (9), and normalizes the filter coefficient extracted thereby, thereby obtaining a filter gain B ′ (m ⁇ 1 ) To B ′ (m ⁇ 3) regardless of the combination.
- w0 u (B ′ (m ⁇ 1), 0) ⁇ Z / (u (B ′ (m ⁇ 1), 0) + u (B ′ (m ⁇ 2), 1) + u (B ′ (m ⁇ 3) ), 2)) ...
- w1 u (B ′ (m ⁇ 2), 1) ⁇ Z / (u (B ′ (m ⁇ 1), 0) + u (B ′ (m ⁇ 2), 1) + u (B ′ (m ⁇ 3) ), 2)) ...
- the gain normalization unit 10 uses the filter coefficients (T (m ⁇ 1), T (m ⁇ 2), T (m ⁇ 3)) output from the coefficient reading unit 9 as normalized filter coefficients w0, w1.
- W2 in FIG. 1, T ′ (m ⁇ 1), T ′ (m ⁇ 2), T ′ (m ⁇ 3)) are converted and output to the digital filter unit 2, and multipliers 24, 25, 26 Switch the filter coefficient used in.
- the digital filter unit 2 performs a product-sum operation with the filter coefficient output from the gain normalization unit 10 using the interpolation signal D (m) output from the digital filter unit 1 as an input signal, and performs an interpolation signal D (m ) Is corrected, and an interpolation signal D ′ (m) is generated and output.
- signals multiplied by the multipliers 24, 25, and 26 are interpolation signals D (m ⁇ 1), D (m ⁇ 2), and D (m ⁇ 3), respectively.
- the phase error included in the interpolation signal that is the output of the digital filter unit 1 is different for each output sampling timing in the digital filter unit 2 connected to the subsequent stage.
- the phase error is corrected by setting the filter coefficient in the multiplier according to the phase error.
- the signal generation apparatus according to the present invention is useful for digital signal communication, and is particularly suitable for interpolating signals.
- phase error calculation section 1, 2, digital filter section, 3 phase calculation section, 4 phase accuracy conversion section, 5, 8 memory, 6, 9 coefficient readout section, 7 phase error calculation section, 10 gain normalization section, 11, 12, 13, 21, 22, 23 delay device, 14, 15, 16, 24, 25, 26 multiplier, 17, 18, 27, 28 adder, 31 cumulative adder.
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Abstract
Description
図1は、本実施の形態の信号生成装置の構成例を示す図である。信号生成装置は、ディジタルフィルタ部1と、ディジタルフィルタ部2と、位相算出部3と、位相精度変換部4と、メモリ5と、係数読出し部6と、位相誤差算出部7と、メモリ8と、係数読出し部9と、利得正規化部10と、を備える。
B(m)=Φ(m)modQ …(4)
w1=u(B´(m-2),1)×Z/(u(B´(m-1),0)+u(B´(m-2),1)+u(B´(m-3),2)) …(8)
w2=u(B´(m-3),2)×Z/(u(B´(m-1),0)+u(B´(m-2),1)+u(B´(m-3),2)) …(9)
Claims (5)
- 入力信号を補間して第1の補間信号を出力する第1のディジタルフィルタと、
前記第1の補間信号を補間して位相誤差を補正し、第2の補間信号を出力する第2のディジタルフィルタと、
2つのディジタルフィルタの出力サンプリング周期単位に更新される時間ステップで変化するディジタル信号の位相を算出する位相算出手段と、
前記ディジタル信号の位相に基づいて、前記第1のディジタルフィルタの補間に使用するフィルタ係数を指示するアドレスである第1の位相信号、および前記第2のディジタルフィルタの補間に使用するフィルタ係数を指示するアドレスを算出するための第2の位相信号を算出する位相精度変換手段と、
前記第1の位相信号で示されるアドレスにフィルタ係数を記憶する第1のメモリと、
前記第1の位相信号に基づいて前記第1のメモリからフィルタ係数を読み出し、前記第1のディジタルフィルタが備える乗算器のフィルタ係数を切り替える第1の係数読出し手段と、
前記第2の位相信号に基づいて、前記第2のディジタルフィルタの補間に使用するフィルタ係数を指示するアドレスである位相誤差信号を算出する位相誤差算出手段と、
前記位相誤差信号で示されるアドレスにフィルタ係数を記憶する第2のメモリと、
前記位相誤差信号に基づいて前記第2のメモリからフィルタ係数を読み出す第2の係数読出し手段と、
前記第2の係数読出し手段において前記第2のメモリから読み出されたフィルタ係数の総和を一定とするためにフィルタ係数の利得正規化を行い、前記第2のディジタルフィルタが備える乗算器のフィルタ係数を切り替える利得正規化手段と、
を備えることを特徴とする信号生成装置。 - 自装置の位相分解能が前記第1のディジタルフィルタの位相分解能および前記第2のディジタルフィルタの位相分解能の積として表される場合に、
前記位相精度変換手段は、前記ディジタル信号の位相を示すビットのうち、前記第1のディジタルフィルタの位相分解能を表すビット数分の上位ビットを前記第1の位相信号とし、残りの下位ビットを前記第2の位相信号とする、
ことを特徴とする請求項1に記載の信号生成装置。 - 前記第2のディジタルフィルタが備える乗算器がK個の場合に、
前記位相誤差算出手段は、
出力サンプリング周期単位でKステップ前までの前記第2の位相信号を保存可能なレジスタ、を備え、
前記レジスタに保存した1ステップ前からKステップ前の前記第2の位相信号とオーバーサンプリング数とに基づいて、1ステップ前からKステップ前に対応する前記第2のディジタルフィルタの補間に用いるフィルタ係数を指示する複数のアドレスである位相誤差信号を算出する、
ことを特徴とする請求項1または2に記載の信号生成装置。 - 前記第2の係数読出し手段は、1ステップ前からKステップ前の位相誤差信号に基づいて、1ステップ前からKステップ前に前記第1のディジタルフィルタから出力された信号に対して、前記第2のディジタルフィルタの乗算器において乗算するためのフィルタ係数を前記第2のメモリから読み出す、
ことを特徴とする請求項3に記載の信号生成装置。 - 前記第2の係数読出し手段は、前記位相誤差信号の位相誤差値と当該位相誤差値が何ステップ前の前記第2の位相信号から算出されたかを示す情報とに基づいて、一意に前記第2のメモリからフィルタ係数を読み出す、
ことを特徴とする請求項3に記載の信号生成装置。
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US9306728B2 (en) | 2016-04-05 |
EP2884660B1 (en) | 2020-07-22 |
JP5931204B2 (ja) | 2016-06-08 |
US20150188692A1 (en) | 2015-07-02 |
JPWO2014027570A1 (ja) | 2016-07-25 |
EP2884660A4 (en) | 2016-04-13 |
EP2884660A1 (en) | 2015-06-17 |
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