WO2013181908A1 - 阵列基板及其制作方法和显示装置 - Google Patents

阵列基板及其制作方法和显示装置 Download PDF

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Publication number
WO2013181908A1
WO2013181908A1 PCT/CN2012/086218 CN2012086218W WO2013181908A1 WO 2013181908 A1 WO2013181908 A1 WO 2013181908A1 CN 2012086218 W CN2012086218 W CN 2012086218W WO 2013181908 A1 WO2013181908 A1 WO 2013181908A1
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WIPO (PCT)
Prior art keywords
layer
conductive layer
slit
electrode
gate
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PCT/CN2012/086218
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English (en)
French (fr)
Inventor
徐超
张春芳
魏燕
金熙哲
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/126,905 priority Critical patent/US9281325B2/en
Publication of WO2013181908A1 publication Critical patent/WO2013181908A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • ADvanced Super Dimension Switch ADS for short
  • AD-ADS ADS for short
  • wide viewing angle technology has been applied to more and more products, and its excellent display characteristics have been It is highly respected by more and more users, and the market is very competitive.
  • the ADS technology forms a multi-dimensional electric field by the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer, so that all the aligned liquid crystal molecules are directly between the slit electrodes in the liquid crystal cell and above the electrode.
  • the rotation can be generated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field conversion technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, no squeeze water wave (ush Mura), etc. advantage.
  • FIG. 1 is a schematic structural view of an array substrate of an existing ADS product.
  • the patterning process requires six patterning processes, namely: Gate composition, active composition, S/D composition, IstlTO composition (formation of plate electrodes), PVX composition And 2nd ITO patterning (forming slit electrodes), the patterning process is complicated, and the manufacturing cost is high. Summary of the invention
  • the embodiment of the invention provides an array substrate, a manufacturing method thereof and a display device.
  • the manufacturing process of the existing array substrate has the problems of complicated process and high manufacturing cost.
  • Embodiments of the present invention provide a method of fabricating an array substrate, wherein a common electrode and a pixel electrode are simultaneously formed by one process.
  • the manufacturing method includes:
  • the passivation layer Forming a pattern of a passivation layer on a substrate on which the data line, the source electrode, the drain electrode, and the conductive layer are formed, the passivation layer having a slit corresponding to the conductive layer Passivation layer slit;
  • the transparent conductive layer comprising two layers, one of which is located above the passivation layer to form a common electrode, and the other layer is located in the slit region and
  • the conductive layers are in the same layer and electrically connected to form a pixel electrode.
  • the pattern of the data lines, the source electrodes, and the drain electrodes is formed on the substrate on which the active layer is formed, and a pattern of a conductive layer including at least one slit is formed in the pixel region, specifically including :
  • a pattern of a conductive layer having at least one slit is formed in the pixel region.
  • the pattern of a passivation layer is formed on a substrate on which the data line, the source electrode, the drain electrode, and the conductive layer are formed, the passivation layer having the conductive
  • the slit of the layer - the corresponding passivation layer slit specifically includes:
  • a photoresist is coated on the passivation layer film, and a passivation layer slit of the pixel region is formed by one patterning process, and the passivation layer slits are in one-to-one correspondence with the slits of the conductive layer.
  • the transparent conductive layer is formed on the substrate on which the passivation layer is formed, and the transparent conductive layer comprises two layers, one of which is located above the passivation layer to form a common electrode, and the other layer Located in the slit region and in the same layer as the conductive layer and electrically connected to form a pixel electrode, specifically including:
  • a transparent conductive layer on the substrate on which the passivation layer is formed Forming a transparent conductive layer on the substrate on which the passivation layer is formed, a portion of the transparent conductive layer remaining over the passivation layer to form a first transparent electrode layer, the first transparent electrode layer being a common electrode; Another portion of the transparent conductive layer is filled into the slit of the conductive layer and is electrically conductive The layers are electrically connected to form a second transparent electrode layer, and the second transparent electrode layer is connected to the drain electrode to form the pixel electrode.
  • the manufacturing method includes:
  • the transparent conductive layer comprising two layers, one of which is located above the passivation layer to form a common electrode, and the other layer is located in the slit region and
  • the conductive layers are in the same layer and electrically connected to form a pixel electrode.
  • the pattern of the gate electrode and the gate line is formed on the substrate, and the pattern of the conductive layer having the at least one slit is formed in the pixel region, and specifically includes:
  • the gate electrode and the gate line are formed by one patterning process, and a pattern of the conductive layer composed of a gate metal layer having at least one slit is formed in the pixel region.
  • the gate insulating layer is formed on a substrate on which the gate electrode, the gate line, and the conductive layer are formed, and a gate insulating layer slit is formed in a pixel region by a patterning process, the gate
  • the insulating layer slits are in one-to-one correspondence with the slits of the conductive layer, and specifically include:
  • a photoresist is coated on the gate insulating film, and a gate insulating layer having a slit is formed in the pixel region by a patterning process, and the gate insulating layer slit corresponds to a slit of the conductive layer.
  • the passivation layer is formed on the substrate on which the source electrode, the drain electrode, and the data line are formed, and a passivation layer slit is formed in the pixel region by a patterning process, the blunt The slit of the layer is corresponding to the slit of the gate insulating layer, and specifically includes:
  • a photoresist is coated on the passivation layer film, and a passivation layer having a slit is formed in the pixel region by a patterning process, and the passivation layer slit corresponds to the gate insulating layer slit.
  • the transparent conductive layer is formed on the substrate on which the passivation layer is formed, and the transparent conductive layer comprises two layers, one of which is located above the passivation layer to form a common electrode, and the other layer Located in the slit region and in the same layer as the conductive layer and electrically connected to form a pixel electrode, specifically including:
  • a transparent conductive layer on the substrate on which the passivation layer is formed Forming a transparent conductive layer on the substrate on which the passivation layer is formed, a portion of the transparent conductive layer remaining over the passivation layer to form a first transparent electrode layer, the first transparent electrode layer being a common electrode; the transparent conductive Another portion of the layer is filled into the slit of the conductive layer and electrically connected to the conductive layer to form a second transparent electrode layer, and the second transparent electrode layer is connected to the drain electrode to form the pixel electrode.
  • the conductive layer is made of a transparent conductive material.
  • the embodiment of the present invention further provides an array substrate, wherein the array substrate comprises a common electrode and a pixel electrode formed by a single process; wherein the pixel electrode comprises a conductive layer having at least one slit, and the transparent conductive layer in the slit a layer connected to the conductive layer to form the pixel electrode;
  • the conductive layer is in the same layer as the gate line on the array substrate or in the same layer as the data line.
  • the array substrate comprises:
  • a drain electrode formed on the gate insulating layer, a source electrode, a data line, a pattern of a conductive layer having at least one slit, and a transparent conductive layer located in the slit, the transparent conductive layer and the conductive Layer connections constitute the pixel electrode;
  • the passivation layer Forming a passivation layer on the source electrode, the drain electrode, the data line, and the pixel electrode, the passivation layer having at least one slit, a slit of the passivation layer, and the conductive The slit of the layer - corresponding;
  • a common electrode composed of a transparent conductive layer formed on the passivation layer, the common electrode There is a slit structure corresponding to the slit of the passivation layer.
  • the array substrate comprises:
  • the pixel electrode
  • a gate insulating layer formed on the gate electrode, the gate line, and the pixel electrode, and the gate insulating layer of the pixel region has at least one slit, and a slit of the gate insulating layer and the conductive The slit of the layer - corresponding;
  • drain electrode a drain electrode, a source electrode, and a data line formed on the gate insulating layer
  • Forming a passivation layer on the drain electrode, the source electrode, and the data line, and the passivation layer corresponding to the pixel region has at least one slit, the slit of the passivation layer and the gate Slit of the insulating layer - corresponding;
  • a common electrode composed of a transparent conductive layer formed on the passivation layer, the common electrode having a slit structure corresponding to a slit of the passivation layer.
  • the conductive layer is made of a transparent conductive material.
  • the transparent conductive material is ZnMgO.
  • Embodiments of the present invention also provide a display device including the array substrate as described above.
  • An embodiment of the present invention further provides a method for fabricating an array substrate, including:
  • the fabrication method further includes the steps of fabricating a thin film transistor, a gate line, and a data line, wherein the conductive layer pattern, the source and drain of the thin film transistor, and the data line are in the same patterning process form. In one embodiment, the fabrication method further includes the steps of fabricating a thin film transistor, a gate line, and a data line, wherein the conductive layer pattern is formed in the same patterning process as the gate of the thin film transistor.
  • the method for fabricating the array substrate provided by the embodiment of the invention can simultaneously form the common electrode and the pixel electrode by one process, thereby simplifying the manufacturing process of the array substrate, improving the production efficiency of the product, and reducing the production cost of the product.
  • 1 is a schematic structural view of an array substrate of an existing ADS product
  • FIG. 2A is a schematic plan view of the corresponding array substrate after step 101 in Embodiment 1;
  • FIG. 2B is a schematic cross-sectional view of the array substrate in FIG. 2A along the A2-A2 direction;
  • FIG. 3A is a schematic plan view of the corresponding array substrate after step 102 in Embodiment 1;
  • FIG. 3B is a schematic cross-sectional view of the array substrate in FIG. 3A along the A3-A3 direction;
  • FIG. 4A is a schematic plan view of the corresponding array substrate after step 103 in Embodiment 1;
  • FIG. 4B is a schematic cross-sectional view of the array substrate in FIG. 4A along the A4-A4 direction;
  • FIG. 5A is a schematic plan view of the corresponding array substrate after the step 104 in the embodiment 1;
  • FIG. 5B is a schematic cross-sectional view of the array substrate in the direction of A5-A5 in FIG. 5A;
  • FIG. 6A is a schematic plan view of the corresponding array substrate after step 105 in Embodiment 1;
  • FIG. 6B is a schematic cross-sectional view of the array substrate in FIG. 6A along the A1-A1 direction;
  • Fig. 7 is a schematic cross-sectional view showing an array substrate produced by the fabrication method of Fig. 8. detailed description
  • Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device, which are used to solve The fabrication process of the existing array substrate has the problems of complicated process and high production cost.
  • the common electrode and the pixel electrode are simultaneously formed by one process.
  • the pattern of the conductive layer of the array substrate has at least one slit, and the transparent conductive layer in the slit is connected with the conductive layer of the array substrate to form a pixel electrode. Therefore, the method for fabricating the array substrate of the present invention can be formed by depositing a transparent conductive layer at a time. Two transparent conductive layers, wherein one transparent conductive layer forms a common electrode, and the other layer is located in the slit region and is in the same layer as the conductive layer and is electrically connected to form a pixel electrode.
  • An embodiment of the present invention further provides an array substrate, the array substrate comprising a common electrode and a pixel electrode formed by a single process; wherein the pixel electrode comprises a conductive layer having at least one slit, and the transparent in the slit
  • the conductive layer is connected to the conductive layer to form the pixel electrode; the conductive layer is in the same layer as the gate line on the array substrate or in the same layer as the data line.
  • the embodiments of the present invention can simultaneously form the common electrode and the pixel electrode by one process, thereby simplifying the fabrication process of the array substrate, improving the production efficiency of the product, and reducing the production cost of the product.
  • Step 101 sequentially forming a gate metal layer and a gate insulating layer on the base substrate, wherein the gate metal layer includes a pattern of a gate electrode and a gate line;
  • Step 102 forming a pattern of an active layer on a substrate on which a gate insulating layer is formed;
  • Step 103 forming a pattern of a data line, a source electrode, and a drain electrode on a substrate on which an active layer is formed, and forming a pattern of a conductive layer including at least one slit in the pixel region;
  • Step 104 forming a pattern of a passivation layer on a substrate on which a data line, a source electrode, a drain electrode and a conductive layer are formed, the passivation layer having a passivation layer slit corresponding to the slit of the conductive layer;
  • Step 105 forming a transparent conductive layer on the substrate on which the passivation layer is formed.
  • the transparent conductive layer comprises two layers, one of which is located above the passivation layer to form a common electrode, and the other layer is located in the slit region and is in the same layer as the conductive layer. Electrically connected to form a pixel electrode.
  • the array substrate of the present embodiment can be formed through the above steps. As shown in FIG. 6A and FIG. 6B, the array substrate of the embodiment includes:
  • Substrate substrate 1 a gate electrode 2 and a gate line 10 formed on the base substrate 1;
  • a drain electrode 52 formed on the gate insulating layer 3, a source electrode 51, a data line 11, a pattern of the conductive layer 12 having at least one slit, and a transparent conductive layer 7, a transparent conductive layer 7 and a conductive layer in the slit 12 connected to form a pixel electrode;
  • a passivation layer 6 formed on the source electrode 51, the drain electrode 52, the data line 11, and the pixel electrode, the passivation layer 6 having at least one slit, and the slit of the passivation layer 6 corresponding to the slit of the conductive layer 12
  • a common electrode composed of a transparent conductive layer 8 formed on the passivation layer 6 having a slit structure corresponding to the slit of the passivation layer 6.
  • the conductive layer 12 may be made of a transparent conductive material.
  • the transparent conductive material may be ZnM g O.
  • Step 101 sequentially forming a gate metal layer and a gate insulating layer on the base substrate, wherein the gate metal layer includes a pattern of a gate electrode and a gate line.
  • a gate metal layer is first formed on the base substrate 1 by a patterning process, and the gate metal layer includes a pattern of the gate electrode 2 and the gate line 10 connected to the gate electrode 2 (FIG. 2A, 2B). Shown).
  • the base substrate 1 may be a glass substrate or a quartz substrate.
  • a gate metal layer may be deposited on the base substrate 1 by sputtering or thermal evaporation.
  • the material of the gate metal layer may be a metal such as Cr, W, Ti, Ta, Mo, Al, Cu or the like and an alloy thereof, and the gate metal layer may also be composed of a plurality of metal thin films.
  • a photoresist is coated on the gate metal layer, and a pattern of the gate electrode 2 and the gate line 10 is formed by a photolithography process (for example, a process of exposure, development, etching, etc., using a conventional mask).
  • a gate insulating layer 3 is formed on the substrate on which the gate electrode 2 and the gate line 10 are formed.
  • Step 102 forming a pattern of the active layer 4 on the substrate on which the gate insulating layer 3 is formed (Fig. 3A,
  • An active layer may be deposited on the substrate 1 on which the gate insulating layer 3 is formed.
  • the active layer material may be a composite layer of an a-Si (amorphous silicon) layer and an n+ a-Si layer.
  • a photoresist is coated on the active layer, and a pattern of the active layer 4 is formed by a patterning process such as exposure, development, etching, or the like using a conventional mask.
  • Step 103 forming a pattern of the data line 11, the source electrode 51, and the drain electrode 52 on the substrate on which the active layer 4 is formed, and forming a pattern of the conductive layer 12 including at least one slit in the pixel region (FIG. 5A, 5B)).
  • a source/drain metal layer is first formed on the substrate on which the active layer pattern is formed; then, a data line, a source electrode and a drain electrode located above the active layer are formed by a patterning process, A gap is formed between the source electrode and the drain electrode (forming a channel at the interval corresponding to the active layer), and at least one narrow is formed in the pixel region defined by the intersection of the data line and the gate line The pattern of the stitched conductive layer.
  • a source/drain metal layer is formed on the substrate 1 on which the active layer 4 is formed, and a data line 11 perpendicularly intersecting the gate line 10 is formed on the substrate 1 by one patterning process.
  • the source electrode 51 and the drain electrode 52 which are spaced apart from each other are formed over the active layer 4 (n+ a-Si etching is also required at the interval between the source electrode 51 and the drain electrode 52), and the data line 11 and the gate line 10 are crossed.
  • the defined pixel area forms a pattern of conductive layers 12 having a plurality of slits (as shown in Figures 4A, 4B).
  • the conductive layer 12 may be made of a transparent conductive material, for example, a transparent conductive oxide ZnMgO, or other transparent conductive material.
  • the source/drain metal layer may also be made of a transparent conductive material.
  • Step 104 forming a pattern of the passivation layer 6 on the substrate 1 on which the data line 11, the source electrode 51, the drain electrode 52 and the conductive layer 12 are formed, the passivation layer 6 having a blunt corresponding to the slit of the conductive layer 12.
  • a passivation layer film is formed on the substrate on which the data line, the source electrode, the drain electrode, and the conductive layer are formed; then, the passivation layer film is coated with light.
  • the passivation layer slit is formed by one patterning process, and the passivation layer slits are in one-to-one correspondence with the slits of the conductive layer.
  • a passivation layer film may be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) method, and the passivation layer film may be an oxide, a nitride or an oxynitride.
  • the reaction gas may be Si3 ⁇ 4, N3 ⁇ 4, N 2 or a mixed gas Si3 ⁇ 4Cl 2, Li 3, N 2 gas mixture.
  • a photoresist is coated on the passivation layer film, and a pattern of the passivation layer 6 having a plurality of slits is formed on the pixel region defined by the intersection of the data line 11 and the gate line 10 by a normal mask patterning process, and the passivation layer a plurality of slits on the 6 and a plurality of slit positions on the conductive layer 12 Same, - corresponding.
  • Step 105 Form a transparent conductive layer on the substrate 1 on which the passivation layer 6 is formed.
  • the transparent conductive layer includes two layers, one of which is located above the passivation layer 6 to form a common electrode, and the other layer is located in the slit region and is opposite to the conductive layer. 12 is in the same layer and electrically connected to form a pixel electrode.
  • a transparent conductive layer is deposited on the substrate on which the passivation layer is formed, and a portion of the transparent conductive layer remains above the passivation layer to form a first transparent electrode layer, and the first transparent electrode layer is a common electrode; another portion of the transparent conductive layer is filled into the slit of the conductive layer, and electrically connected to the conductive layer to form a second transparent electrode layer, and the second transparent electrode layer is connected with the drain electrode The pixel electrode.
  • a transparent conductive layer is deposited by sputtering or thermal evaporation on the substrate on which the passivation layer 6 is formed. Due to the difference in height and slope of the passivation layer 6, the transparent conductive layer is deposited. A portion of the transparent conductive layer 7 formed in the slit region is connected to the conductive layer 12 to form a pixel electrode; a portion remains above the passivation layer, and the transparent conductive layer 8 formed on the passivation layer 6 is naturally formed with a narrow Sewn common electrode.
  • the transparent conductive layer when the transparent conductive layer is deposited, since the conductive layer 12 of the pixel region and the slit of the passivation layer 6 correspond to each other, two layers are naturally formed, that is, one layer is formed in the slit region and is in the same layer as the conductive layer 12. And electrically connected to the conductive layer 12 to form a pixel electrode, and the other layer is formed above the passivation layer to form a common electrode.
  • the pixel electrode is connected to the drain electrode 51 (as shown in Figs. 7A, 7B).
  • ITO Indium Tin Oxide
  • ITO Indium Tin Oxide
  • the transparent conductive layer 7 and the transparent conductive layer 8 in Figs. 6A, 6B are produced in the same process of depositing a transparent conductive layer, but only in the position of the height. Due to the height difference and slope of the passivation layer 6, the first transparent electrode layer and the second transparent electrode layer are naturally disconnected, and there is no electrical connection.
  • the technical solution of the embodiment forms a pattern of a conductive layer having at least one slit on the gate insulating layer, and forms a passivation layer having at least one slit on the conductive layer, and the slit of the passivation layer and the narrowness of the conductive layer Slot-corresponding; when a transparent conductive layer is deposited on the passivation layer, a portion of the transparent conductive layer remaining above the passivation layer forms a common electrode, and another portion of the transparent conductive layer is filled into the slit of the conductive layer, and is electrically conductive
  • the layer connection forms a pixel electrode connected to the drain electrode. Due to the height difference and the slope of the passivation layer, the common electrode and the pixel electrode are naturally disconnected, and there is no electrical connection.
  • the embodiments of the present invention can simultaneously form the common electrode and the pixel electrode by one process, thereby simplifying the fabrication process of the array substrate, improving the production efficiency of the product, and reducing the production cost of the product.
  • Example 2 Example 2
  • Step 801 forming a pattern of a gate electrode and a gate line on the base substrate, and forming a pattern of the conductive layer having at least one slit in the pixel region;
  • Step 802 Form a gate insulating layer on the substrate on which the gate electrode, the gate line and the conductive layer are formed, and form a gate insulating layer slit in the pixel region by a patterning process, and the gate insulating layer slit and the slit of the conductive layer correspond to ;
  • Step 803 forming a pattern of an active layer on a substrate on which a gate insulating layer is formed;
  • Step 804 forming a pattern of a source electrode, a drain electrode, and a data line on a substrate on which an active layer is formed;
  • Step 805 forming a passivation layer on the substrate on which the active electrode, the drain electrode and the data line are formed, and forming a passivation layer slit in the pixel region by a patterning process, wherein the passivation layer slit and the gate insulating layer slit correspond one-to-one ;
  • Step 806 forming a transparent conductive layer on the substrate on which the passivation layer is formed.
  • the transparent conductive layer comprises two layers, one of which is located above the passivation layer to form a common electrode, and the other layer is located in the slit region and is in the same layer as the conductive layer. Electrically connected to form a pixel electrode.
  • the array substrate of this embodiment can be formed through the above steps. As shown in FIG. 7, the array substrate of this embodiment includes:
  • Substrate substrate 01 Substrate substrate 01 ;
  • a gate insulating layer 03 formed on the gate electrode 02, the gate line, and the pixel electrode, and the gate insulating layer 03 of the pixel region has at least one slit, and the slit of the gate insulating layer 03 corresponds to the slit of the conductive layer 012 ;
  • drain electrode 052 a drain electrode 052, a source electrode 051, and a data line formed on the gate insulating layer 03;
  • a passivation layer 06 is formed on the drain electrode 052, the source electrode 051, and the data line, and the passivation layer 06 corresponding to the pixel region has at least one slit, and the slit of the passivation layer 06 and the slit of the gate insulating layer 03 One correspondence
  • a common electrode composed of a transparent conductive layer 08 formed on the passivation layer 06, the common electrode having A slit structure corresponding to the slit of the passivation layer.
  • the conductive layer 012 may be made of a transparent conductive material; for example, the transparent conductive material may be ZnM g O.
  • Step 801 A pattern of the gate electrode 02 and the gate line is formed on the base substrate 01, and a pattern of the conductive layer 012 having at least one slit is formed in the pixel region.
  • a gate metal layer is formed on the base substrate; the gate electrode and the gate line are formed by one patterning process, and a pattern of the conductive layer composed of a gate metal layer is formed in the pixel region,
  • the conductive layer has at least one slit.
  • a gate metal layer is first deposited on the base substrate 01, and then a gate electrode 02 is formed on the base substrate 01 and connected to the gate electrode 02 by a gate metal layer by a patterning process (such as a general reticle process).
  • the gate line forms a pattern of the conductive layer 012 having a plurality of slits on the pixel region by the gate metal layer.
  • the gate electrode 02, the gate line and the conductive layer 012 may be made of a transparent conductive material, for example, a transparent conductive oxide ZnMgO, or other transparent conductive materials. .
  • Step 802 Form a gate insulating layer 03 on the substrate 01 on which the gate electrode 02, the gate line and the conductive layer 012 are formed, and form a gate insulating layer slit in the pixel region by a patterning process, and the slit of the gate insulating layer and the narrowness of the conductive layer Sew - corresponding.
  • a gate insulating film is formed on the substrate on which the gate electrode, the gate line and the conductive layer are formed; a photoresist is coated on the gate insulating film, and a patterning process is performed.
  • the pixel region forms a gate insulating layer having a slit, and the gate insulating layer slit corresponds to a slit of the conductive layer.
  • a gate insulating film is formed on the substrate 01 on which the gate electrode 02, the gate line and the conductive layer 012 are formed, a photoresist is coated on the gate insulating film, and a plurality of stripes are formed in the pixel region by a patterning process.
  • the gate insulating layer 03 of the slit, and the slit of the gate insulating layer 03 corresponds to the slit of the conductive layer 012.
  • Step 803 A pattern of the active layer 04 is formed on the substrate 01 on which the gate insulating layer 03 is formed.
  • a layer of active material may be deposited on the substrate 01 on which the gate insulating layer 03 is formed, which The active material layer may be a composite layer of an a-Si layer and an n+ a-Si layer.
  • a pattern of the active layer 04 is formed on the gate insulating layer 03 by a pattern of active material by a patterning process (e.g., using a conventional mask).
  • Step 804 A pattern of the source electrode 051, the drain electrode 052, and the data line is formed on the substrate 01 on which the active layer 04 is formed.
  • a source/drain metal layer is deposited on the substrate 01 on which the active layer 04 is formed, and the source and drain metal layers may be made of a conventional opaque metal such as Mo, AlNd, or A1. Then, by using a patterning process (for example, using a normal reticle), a source line perpendicularly intersecting the gate line is formed on the substrate 01, and a source electrode 051 having a space between the active layer 04 is formed by using the source/drain metal layer. It is also necessary to perform n+ a-Si etching at the interval between the source electrode 051 and the drain electrode 052 with the drain electrode 052.
  • Step 805 forming a passivation layer 06 on the substrate 01 on which the active electrode 051, the drain electrode 052, and the data line are formed, and forming a passivation layer slit in the pixel region by a patterning process, and the passivation layer slit and the gate insulating layer are narrow One-to-one correspondence.
  • a passivation layer film is formed on the substrate on which the source electrode, the drain electrode and the data line are formed; a photoresist is coated on the passivation layer film, and a patterning process is performed.
  • the pixel region forms a passivation layer having a slit, and the passivation layer slit has a one-to-one correspondence with the gate insulating layer slit.
  • a passivation layer film is formed on the substrate 01 on which the active electrode 051, the drain electrode 052, and the data line are formed, and a photoresist is coated on the passivation layer film, and a plurality of strips are formed in the pixel region by a patterning process.
  • the passivation layer 06 of the slit, and the slit of the passivation layer 06 corresponds to the slit of the gate insulating layer 03.
  • Step 806 forming a transparent conductive layer on the substrate 01 on which the passivation layer 06 is formed.
  • the transparent conductive layer comprises two layers, one of which is formed above the passivation layer 06 to form a common electrode, and the other layer is located in the slit region and the conductive layer 012 is in the same layer and electrically connected to form a pixel electrode.
  • a transparent conductive layer is formed on the substrate on which the passivation layer is formed, a portion of the transparent conductive layer remains above the passivation layer to form a first transparent electrode layer, and the first transparent electrode layer is a common electrode Another portion of the transparent conductive layer is filled into the slit of the conductive layer, and electrically connected to the conductive layer to form a second transparent electrode layer, and the second transparent electrode layer is connected to the drain electrode to form the Pixel electrode.
  • a transparent conductive layer may be deposited on the substrate 01 on which the passivation layer 06 is formed by sputtering or thermal evaporation, wherein the transparent conductive layer may be made of ITO (Indium Tin Oxide). Indium tin). Due to the height difference and slope of the passivation layer 06, the transparent conductive layer can naturally form different sections, and a portion 08 of the transparent conductive layer remains above the passivation layer 06 to form a first transparent electrode layer.
  • ITO Indium Tin Oxide
  • the first transparent layer The electrode layer is a common electrode; another portion 07 of the transparent conductive layer is filled into the slit of the conductive layer 012, and is electrically connected to the conductive layer 012 to form a second transparent electrode layer, and the second transparent electrode layer is connected to the drain electrode 052 to form a pixel. electrode. Due to the height difference and the slope of the passivation layer 06, the first transparent electrode layer and the second transparent electrode layer are naturally disconnected, and there is no electrical connection.
  • a method for fabricating an array substrate includes: forming a first conductive layer on a substrate, and patterning the first conductive layer to form a conductive layer pattern having at least one slit; An insulating film is formed on the conductive layer pattern, and the insulating film is patterned to form an insulating layer pattern having slits of the insulating layer, wherein the insulating layer slits are in one-to-one correspondence with the slits of the conductive layer pattern; Forming a second conductive layer thereon, wherein the portion of the second conductive layer corresponding to the slit falls into the slit and is disconnected from a portion of the second conductive layer above the insulating layer pattern, A portion of the second conductive layer that falls into the slit is connected to the conductive layer pattern to form a first electrode, and a portion of the second conductive layer that is on the insulating layer pattern forms a second electrode.
  • the fabrication method may further include the steps of fabricating a thin film transistor, a gate line, and a data line, wherein the conductive layer pattern, the source and drain of the thin film transistor, and the data line are formed in the same patterning process;
  • the insulating layer pattern may be formed in the same patterning process as the passivation layer pattern.
  • the conductive layer pattern is formed in the same patterning process as the gate of the thin film transistor; in this case, the insulating layer pattern may include upper and lower layers, and the lower layer is simultaneously patterned with the gate insulating film of the thin film transistor Formed while the pattern of the upper layer and the passivation layer are formed in the same patterning process.
  • One of the first electrode and the second electrode described above is a pixel electrode, and the other is a common electrode.
  • the material selection of each part mentioned above reference may be made to the examples in the above various embodiments, and details are not described herein again.
  • the technical solution of the embodiment forms a pattern of a conductive layer having at least one slit on the substrate, and forms a gate insulating layer having at least one slit, a slit of the gate insulating layer and a slit of the conductive layer on the conductive layer.
  • a transparent conductive layer is deposited thereon, a portion of the transparent conductive layer remaining above the passivation layer forms a common electrode.
  • Another portion of the transparent conductive layer is filled into the slit of the conductive layer, and is connected with the conductive layer to form a pixel electrode connected to the drain electrode. Due to the height difference and the slope of the passivation layer, the common electrode and the pixel electrode are naturally disconnected, There will be an electrical connection.
  • the embodiments of the present invention can simultaneously form the common electrode and the pixel electrode by one process, thereby simplifying the fabrication process of the array substrate, improving the production efficiency of the product, and reducing the production cost of the product.
  • the embodiment of the invention further provides a display device comprising the array substrate according to any of the above embodiments.
  • the display device may be: a product or a component having any display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.

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Abstract

提供了一种阵列基板及其制作方法和显示装置。该阵列基板的制作方法是通过一次工艺同时形成公共电极（08）和像素电极。由此能够解决现有阵列基板的制作工艺复杂、成本高的问题。

Description

阵列基板及其制作方法和显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制作方法和显示装置。 背景技术
随着 TFT产业的进步及工艺的改善， 高级超维场转换 ( ADvanced Super Dimension Switch, AD-ADS , 简称 ADS )广视角技术已被应用到越来越多的 产品当中，其优良的显示特性已被越来越多的用户所推崇，市场竟争力很强。
ADS 技术是通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极 层与板状电极层间产生的电场形成多维电场， 使液晶盒内狭缝电极间、 电极 正上方所有取向液晶分子都能够产生旋转， 从而提高了液晶工作效率并增大 了透光效率。 高级超维场转换技术可以提高 TFT-LCD产品的画面品质， 具 有高分辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低色差、 无挤压水波 故 ( ush Mura )等优点。
由于 ADS自身的特点， 其 Array阵列工艺较传统的 TN产品复杂， 构图 及单件工时（Tact Time ) 均有所增加， 因此成本较高。 例如， 图 1 为现有 ADS产品的阵列基板的结构示意图 ,制作该阵列基板需要 6次构图工艺，即： Gate构图、 active构图、 S/D构图、 IstlTO构图（形成板状电极）、 PVX构 图以及 2nd ITO构图 （形成狭缝电极） ， 构图工艺复杂， 制作成本较高。 发明内容
本发明实施例提供了一种阵列基板及其制作方法和显示装置， 例如可以 解决现有阵列基板的制作工艺存在工艺复杂、 制作成本较高的问题。
本发明实施例提供了一种阵列基板的制作方法， 通过一次工艺同时形成 公共电极和像素电极。
在一个实施例中， 所述制作方法包括：
在衬底基板上依次形成栅金属层和栅绝缘层， 所述栅金属层包括栅电极 和栅线的图形； 在形成有所述栅绝缘层的基板上形成有源层的图形；
在形成有所述有源层的基板上形成数据线、 源电极和漏电极的图形， 并 在像素区域形成包含有至少一条狭缝的导电层的图形；
在形成有所述数据线、 所述源电极、 所述漏电极和所述导电层的基板上 形成钝化层的图形， 所述钝化层具有与所述导电层的狭缝——对应的钝化层 狭缝；
在形成有所述钝化层的基板上形成透明导电层， 所述透明导电层包括两 层， 其中一层位于所述钝化层上方形成公共电极， 另一层位于所述狭缝区域 且与所述导电层同层并电连接以形成像素电极。
在一个实施例中， 所述在形成有所述有源层的基板上形成数据线、 源电 极和漏电极的图形，并在像素区域形成包含有至少一条狭缝的导电层的图形， 具体包括：
在形成有有源层图形的基板上形成一层源漏金属层；
通过构图工艺， 形成数据线、 位于所述有源层上方的源电极和漏电极， 所述源电极和漏电极之间形成有间隔， 以及在所述数据线与所述栅线交叉定 义的所述像素区域内形成具有至少一条狭缝的导电层的图形。
在一个实施例中， 所述在形成有所述数据线、 所述源电极、 所述漏电极 和所述导电层的基板上形成钝化层的图形， 所述钝化层具有与所述导电层的 狭缝——对应的钝化层狭缝， 具体包括：
在形成有所述数据线、 所述源电极、 所述漏电极和所述导电层的基板上 形成一层钝化层薄膜；
在钝化层薄膜上涂覆光刻胶， 通过一次构图工艺形成所述像素区域的钝 化层狭缝， 并且所述钝化层狭缝与所述导电层的狭缝一一对应。
在一个实施例中， 所述在形成有所述钝化层的基板上形成透明导电层， 所述透明导电层包括两层， 其中一层位于所述钝化层上方形成公共电极， 另 一层位于所述狭缝区域且与所述导电层同层并电连接以形成像素电极， 具体 包括：
在形成有所述钝化层的基板上形成透明导电层， 所述透明导电层的一部 分保留在所述钝化层上方形成第一透明电极层， 该第一透明电极层为公共电 极； 所述透明导电层的另一部分填充到所述导电层的狭缝中， 并与所述导电 层电连接形成第二透明电极层， 该第二透明电极层与所述漏电极相连形成所 述像素电极。
在一个实施例中， 所述制作方法包括：
在衬底基板上形成栅电极和栅线的图形， 并在像素区域形成具有至少一 条狭缝的导电层的图形；
在形成有所述栅电极、 所述栅线和所述导电层的基板上形成栅绝缘层， 且利用构图工艺在像素区域形成栅绝缘层狭缝， 所述栅绝缘层狭缝与所述导 电层的狭缝——对应；
在形成有所述栅绝缘层的基板上形成有源层的图形；
在形成有所述有源层的基板上形成源电极、 漏电极和数据线的图形； 在形成有所述源电极、 所述漏电极和所述数据线的基板上形成钝化层， 且利用构图工艺在像素区域形成钝化层狭缝， 所述钝化层狭缝与所述栅绝缘 层狭缝——对应；
在形成有所述钝化层的基板上形成透明导电层， 所述透明导电层包括两 层， 其中一层位于所述钝化层上方形成公共电极， 另一层位于所述狭缝区域 且与所述导电层同层并电连接以形成像素电极。
在一个实施例中， 所述在衬底基板上形成栅电极和栅线的图形， 并在像 素区域形成具有至少一条狭缝的导电层的图形， 具体包括：
在衬底基板上形成栅金属层；
通过一次构图工艺， 形成所述栅电极和栅线， 并在所述像素区域形成由 栅金属层构成的所述导电层的图形， 所述导电层具有至少一条狭缝。
在一个实施例中， 所述在形成有所述栅电极、 所述栅线和所述导电层的 基板上形成栅绝缘层， 且利用构图工艺在像素区域形成栅绝缘层狭缝， 所述 栅绝缘层狭缝与所述导电层的狭缝一一对应， 具体包括：
在形成有所述栅电极、 所述栅线和所述导电层的基板上形成一层栅绝缘 层薄膜；
在栅绝缘层薄膜上涂覆光刻胶， 通过构图工艺， 在所述像素区域形成具 有狭缝的栅绝缘层， 且所述栅绝缘层狭缝与所述导电层的狭缝——对应。
在一个实施例中， 所述在形成有所述源电极、 所述漏电极和所述数据线 的基板上形成钝化层， 且利用构图工艺在像素区域形成钝化层狭缝， 所述钝 化层狭缝与所述栅绝缘层狭缝——对应， 具体包括：
在形成有所述源电极、 所述漏电极和所述数据线的基板上形成一层钝化 层薄膜；
在钝化层薄膜上涂覆光刻胶， 通过构图工艺， 在所述像素区域形成具有 狭缝的钝化层， 且所述钝化层狭缝与所述栅绝缘层狭缝——对应。
在一个实施例中， 所述在形成有所述钝化层的基板上形成透明导电层， 所述透明导电层包括两层， 其中一层位于所述钝化层上方形成公共电极， 另 一层位于所述狭缝区域且与所述导电层同层并电连接以形成像素电极， 具体 包括：
在形成有钝化层的基板上形成透明导电层， 所述透明导电层的一部分保 留在所述钝化层上方形成第一透明电极层， 该第一透明电极层为公共电极； 所述透明导电层的另一部分填充到所述导电层的狭缝中， 并与所述导电层电 连接形成第二透明电极层， 该第二透明电极层与所述漏电极相连形成所述像 素电极。
在一个实施例中， 所述导电层釆用透明导电材料。
本发明实施例还提供了一种阵列基板， 所述阵列基板包含由一次工艺形 成的公共电极和像素电极； 其中， 所述像素电极包含具有至少一条狭缝的导 电层， 狭缝中的透明导电层与所述导电层连接组成所述像素电极；
所述导电层与所述阵列基板上的栅线同层或者与数据线同层。
在一个实施例中， 所述阵列基板包括：
衬底基板；
形成在所述衬底基板上的栅电极和栅线；
形成在上述衬底基板上的栅绝缘层；
形成在所述栅绝缘层上的漏电极、 源电极、 数据线、 具有至少一条狭缝 的导电层的图形， 以及位于所述狭缝中的透明导电层， 所述透明导电层与所 述导电层连接组成所述像素电极；
形成在所述源电极、 所述漏电极、 所述数据线和所述像素电极上的钝化 层， 所述钝化层具有至少一条狭缝， 所述钝化层的狭缝与所述导电层的狭缝 ——对应；
形成在所述钝化层上的由透明导电层组成的公共电极， 所述公共电极具 有与所述钝化层的狭缝——对应的狭缝结构。
在一个实施例中， 所述阵列基板包括：
衬底基板；
形成在所述衬底基板上的栅电极、 栅线、 具有至少一条狭缝的导电层的 图形， 以及位于所述狭缝中的透明导电层， 所述透明导电层与所述导电层连 接组成所述像素电极；
形成在所述栅电极、 所述栅线和所述像素电极上的栅绝缘层， 且像素区 域的所述栅绝缘层具有至少一条狭缝， 且所述栅绝缘层的狭缝与所述导电层 的狭缝——对应；
形成在所述栅绝缘层上的漏电极、 源电极和数据线；
形成在所述漏电极、 所述源电极和所述数据线上的钝化层， 且对应像素 区域的所述钝化层具有至少一条狭缝， 所述钝化层的狭缝与所述栅绝缘层的 狭缝——对应；
形成在所述钝化层上的由透明导电层组成的公共电极， 所述公共电极具 有与所述钝化层的狭缝——对应的狭缝结构。
在一个实施例中， 所述导电层釆用透明导电材料。
在一个实施例中， 所述透明导电材料为 ZnMgO。
本发明实施例还提供了一种显示装置， 包括如上所述的阵列基板。
本发明的实施例还提供一种阵列基板的制作方法， 包括：
在基板上形成第一导电层， 对该第一导电层进行构图以形成具有至少一 条狭缝的导电层图案；
在所述导电层图案上形成绝缘膜， 对该绝缘膜进行构图以形成具有绝缘 层狭缝的绝缘层图案， 所述绝缘层狭缝与所述导电层图案的狭缝一一对应； 在所述绝缘层图案上形成第二导电层， 所述第二导电层对应于所述狭缝 的部分落入所述狭缝中且与所述第二导电层位于所述绝缘层图案之上的部分 断开， 所述第二导电层的落入所述狭缝中的部分与所述导电层图案连接以形 成第一电极，所述第二导电层的位于所述绝缘层图案上的部分形成第二电极。
在一个实施例中， 该制作方法还包括制作薄膜晶体管、 栅线和数据线的 步骤， 其中所述导电层图案、 所述薄膜晶体管的源极和漏极以及所述数据线 在同一构图工艺中形成。 在一个实施例中， 该制作方法还包括制作薄膜晶体管、 栅线和数据线的 步骤，其中所述导电层图案与所述薄膜晶体管的栅极在同一构图工艺中形成。
本发明实施例提供的阵列基板的制作方法， 能够通过一次工艺同时形成 公共电极和像素电极， 从而能够简化阵列基板的制作工艺， 提高产品的生产 效率， 降低产品的生产成本。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有 ADS产品的阵列基板的结构示意图；
图 2A为实施例 1中步骤 101后对应的阵列基板的平面示意图； 图 2B为图 2A中阵列基板沿 A2-A2方向的截面示意图；
图 3A为实施例 1中步骤 102后对应的阵列基板的平面示意图； 图 3B为图 3A中阵列基板沿 A3-A3方向的截面示意图；
图 4A为实施例 1中步骤 103后对应的阵列基板的平面示意图； 图 4B为图 4A中阵列基板沿 A4-A4方向的截面示意图；
图 5A为实施例 1中步骤 104后对应的阵列基板的平面示意图； 图 5B为图 5A中阵列基板沿 A5-A5方向的截面示意图；
图 6A为实施例 1中步骤 105后对应的阵列基板的平面示意图； 图 6B为图 6A中阵列基板沿 A1-A1方向的截面示意图； 以及
图 7为执行图 8中制作方法制作的阵列基板的截面示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例提供了一种阵列基板及其制作方法和显示装置， 用以解决 现有阵列基板的制作工艺存在工艺复杂、 制作成本较高的问题。
本发明的阵列基板的制作方法， 通过一次工艺同时形成公共电极和像素 电极。
阵列基板的导电层的图形具有至少一条狭缝， 狭缝中的透明导电层与阵 列基板的导电层连接组成像素电极， 因此， 本发明的阵列基板的制作方法通 过一次沉积透明导电层即可形成两层透明导电层， 其中一层透明导电层形成 公共电极， 另一层位于狭缝区域且与导电层同层并电连接以形成像素电极。
本发明的实施例还提供了一种阵列基板， 所述阵列基板包含由一次工艺 形成的公共电极和像素电极； 其中， 所述像素电极包含具有至少一条狭缝的 导电层， 狭缝中的透明导电层与所述导电层连接组成所述像素电极； 所述导 电层与所述阵列基板上的栅线同层或者与数据线同层。
本发明的实施例能够通过一次工艺同时形成公共电极和像素电极， 从而 能够简化阵列基板的制作工艺，提高产品的生产效率，降低产品的生产成本。
下面结合具体的实施例对本发明的阵列基板及其制作方法进行进一步地 介绍：
实施例 1
本实施例的阵列基板的制作方法包括：
步骤 101 : 在衬底基板上依次形成栅金属层和栅绝缘层， 栅金属层包括 栅电极和栅线的图形；
步骤 102: 在形成有栅绝缘层的基板上形成有源层的图形；
步骤 103: 在形成有有源层的基板上形成数据线、 源电极和漏电极的图 形， 并在像素区域形成包含有至少一条狭缝的导电层的图形；
步骤 104: 在形成有数据线、 源电极、 漏电极和导电层的基板上形成钝 化层的图形， 钝化层具有与导电层的狭缝一一对应的钝化层狭缝；
步骤 105: 在形成有钝化层的基板上形成透明导电层， 透明导电层包括 两层， 其中一层位于钝化层上方形成公共电极， 另一层位于狭缝区域且与导 电层同层并电连接以形成像素电极。
经过上述步骤可形成本实施例的阵列基板，如图 6A和图 6B所示， 本实 施例的阵列基板包括：
衬底基板 1 ; 形成在衬底基板 1上的栅电极 2和栅线 10;
形成在上述衬底基板 1上的栅绝缘层 3;
形成在栅绝缘层 3上的漏电极 52、 源电极 51、 数据线 11、 具有至少一 条狭缝的导电层 12的图形， 以及位于狭缝中的透明导电层 7, 透明导电层 7 与导电层 12连接组成像素电极；
形成在源电极 51、 漏电极 52、 数据线 11和像素电极上的钝化层 6, 钝 化层 6具有至少一条狭缝， 钝化层 6的狭缝与导电层 12的狭缝——对应； 形成在钝化层 6上的由透明导电层 8组成的公共电极， 公共电极具有与 钝化层 6的狭缝——对应的狭缝结构。
进一步地，为了提高阵列基板的开口率，导电层 12可以釆用透明导电材 料， 例如， 透明导电材料可以为 ZnMgO。
下面结合具体的工艺流程对本实施例的阵列基板的制作方法进行进一步 地介绍：
步骤 101、 在衬底基板上依次形成栅金属层和栅绝缘层， 栅金属层包括 栅电极和栅线的图形。
在本实施例的步骤 101中， 首先通过一次构图工艺在衬底基板 1上形成 栅金属层，栅金属层包括栅电极 2和与栅电极 2连接的栅线 10的图形（如图 2A、 2B所示） 。 例如， 衬底基板 1可为玻璃基板或石英基板。
例如，可以釆用溅射或热蒸发的方法在衬底基板 1上沉积一层栅金属层。 栅金属层的材料可以是 Cr、 W、 Ti、 Ta、 Mo、 Al、 Cu等金属及其合金， 栅 金属层也可以是由多层金属薄膜组成。 在栅金属层上涂覆一层光刻胶， 通过 一次光刻工艺 （如釆用普通掩模板进行曝光、 显影、 刻蚀等工艺形成）形成 栅电极 2和栅线 10的图形。
然后， 在形成有栅电极 2和栅线 10的基板上形成栅绝缘层 3。
步骤 102、在形成有栅绝缘层 3的基板上形成有源层 4的图形（如图 3A、
3B所示） 。
可以在形成有栅绝缘层 3的基板 1上沉积一层有源层， 例如， 有源层材 料可为 a-Si (非晶硅）层和 n+ a-Si层的复合层。 在有源层上涂覆光刻胶， 通 过一次构图工艺 （如釆用普通掩模板进行曝光、 显影、 刻蚀等工序）形成有 源层 4的图形。 步骤 103、在形成有有源层 4的基板上形成数据线 11、源电极 51和漏电 极 52的图形，并在像素区域形成包含有至少一条狭缝的导电层 12的图形（如 图 5A、 5B所示 ) 。
在该步骤中， 首先在形成有有源层图形的基板上形成一层源漏金属层； 然后，通过构图工艺， 形成数据线、位于所述有源层上方的源电极和漏电极， 所述源电极和漏电极之间形成有间隔 （在有源层的对应于该间隔处形成沟 道） ， 以及在所述数据线与所述栅线交叉定义的所述像素区域内形成具有至 少一条狭缝的导电层的图形。
结合图 4A、 4B所示， 在形成有有源层 4图形的基板 1上形成一层源漏 金属层， 通过一次构图工艺， 在基板 1上形成与栅线 10垂直交叉的数据线 11 , 在有源层 4的上方形成彼此间隔的源电极 51与漏电极 52 (源电极 51和 漏电极 52之间的间隔处也需要进行 n+ a-Si刻蚀 ) , 在数据线 11和栅线 10 交叉定义的像素区域形成具有多条狭缝的导电层 12的图形（如图 4A、 4B所 示） 。
进一步地，为了提高阵列基板的开口率，导电层 12可以釆用透明导电材 料， 例如， 可为透明的导电氧化物 ZnMgO, 亦可为其它透明的导电材料。
进一步地， 源漏金属层也可以釆用透明导电材料。
步骤 104、 在形成有数据线 11、 源电极 51、 漏电极 52和导电层 12的基 板 1上形成钝化层 6的图形，钝化层 6具有与导电层 12的狭缝——对应的钝 化层狭缝；
在本步骤中， 首先在形成有所述数据线、 所述源电极、 所述漏电极和所 述导电层的基板上形成一层钝化层薄膜； 然后，在钝化层薄膜上涂覆光刻胶， 通过一次构图工艺形成所述像素区域的钝化层狭缝， 并且所述钝化层狭缝与 所述导电层的狭缝一一对应。
例如， 结合图 5A、 5B所示， 可以在基板上通过等离子体增强化学气相 沉积（PECVD )方法沉积一层钝化层薄膜， 钝化层薄膜可以釆用氧化物、 氮 化物或者氮氧化合物， 对应的反应气体可以为 Si¾、 N¾、 N2的混合气体或 Si¾Cl2、 丽 3、 N2的混合气体。 在钝化层薄膜上涂覆光刻胶， 通过普通掩模 构图工艺， 在数据线 11和栅线 10交叉定义的像素区域上形成具有多条狭缝 的钝化层 6的图形，钝化层 6上的多条狭缝与导电层 12上的多条狭缝位置相 同， ——对应。
步骤 105、 在形成有钝化层 6的基板 1上形成透明导电层， 透明导电层 包括两层， 其中一层位于钝化层 6上方形成公共电极， 另一层位于狭缝区域 且与导电层 12同层并电连接以形成像素电极。
在本步骤中， 在形成有所述钝化层的基板上沉积透明导电层， 所述透明 导电层的一部分保留在所述钝化层上方形成第一透明电极层， 该第一透明电 极层为公共电极； 所述透明导电层的另一部分填充到所述导电层的狭缝中， 并与所述导电层电连接形成第二透明电极层， 该第二透明电极层与所述漏电 极相连形成所述像素电极。
结合图 6A、 6B所示， 在形成有钝化层 6的基板上通过溅射或热蒸发的 方法沉积透明导电层， 由于钝化层 6的高度差及坡度， 上述透明导电层在沉 积时， 一部分沉积到狭缝区域， 形成在狭缝区域的透明导电层 7与导电层 12 连接形成像素电极； 一部分保留在钝化层上方， 形成在钝化层 6上的透明导 电层 8自然形成具有狭缝的公共电极。 也就是说， 透明导电层在沉积时由于 像素区域的导电层 12和钝化层 6的狭缝——对应，会自然形成两层， 即一层 形成在狭缝区域且与导电层 12同层并与导电层 12电连接从而形成像素电极， 另一层位于钝化层上方形成公共电极。 像素电极与漏电极 51 相连接（如图 7A, 7B所示） 。 其中， 透明导电层可以釆用 ITO ( Indium Tin Oxide, 氧化 铟锡） 。
图 6A、 6B中的透明导电层 7和透明导电层 8是在同一次的沉积透明导 电层过程中制作出来的， 只是位置上的高低之分。 由于钝化层 6的高度差及 坡度， 使得第一透明电极层和第二透明电极层自然断开， 不会有电连接。
本实施例的技术方案在栅绝缘层上形成具有至少一条狭缝的导电层的图 形， 并在导电层上形成具有至少一条狭缝的钝化层， 钝化层的狭缝与导电层 的狭缝——对应； 在钝化层上沉积透明导电层时， 透明导电层保留在钝化层 的上方的部分形成公共电极,透明导电层的另一部分填充到导电层的狭缝中， 并与导电层连接形成与漏电极相连的像素电极，由于钝化层的高度差及坡度， 使得公共电极和像素电极自然断开， 不会有电连接。 本发明的实施例能够通 过一次工艺同时形成公共电极和像素电极， 从而能够简化阵列基板的制作工 艺， 提高产品的生产效率， 降低产品的生产成本。 实施例 2
本实施例的阵列基板的制作方法包括：
步骤 801 : 在衬底基板上形成栅电极和栅线的图形， 并在像素区域形成 具有至少一条狭缝的导电层的图形；
步骤 802: 在形成有栅电极、 栅线和导电层的基板上形成栅绝缘层， 且 利用构图工艺在像素区域形成栅绝缘层狭缝， 栅绝缘层狭缝与导电层的狭缝 ——对应；
步骤 803: 在形成有栅绝缘层的基板上形成有源层的图形；
步骤 804: 在形成有有源层的基板上形成源电极、 漏电极和数据线的图 形；
步骤 805: 在形成有源电极、 漏电极和数据线的基板上形成钝化层， 且 利用构图工艺在像素区域形成钝化层狭缝， 钝化层狭缝与栅绝缘层狭缝一一 对应；
步骤 806: 在形成有钝化层的基板上形成透明导电层， 透明导电层包括 两层， 其中一层位于钝化层上方形成公共电极， 另一层位于狭缝区域且与导 电层同层并电连接以形成像素电极。
经过上述步骤可形成本实施例的阵列基板， 如图 7所示， 本实施例的阵 列基板包括：
衬底基板 01 ;
形成在衬底基板 01上的栅电极 02、 栅线、 具有至少一条狭缝的导电层
012的图形， 以及位于狭缝中的透明导电层 07, 透明导电层 07与导电层 012 连接组成像素电极；
形成在栅电极 02、栅线和像素电极上的栅绝缘层 03 ,且像素区域的栅绝 缘层 03具有至少一条狭缝， 且栅绝缘层 03的狭缝与导电层 012的狭缝—— 对应；
形成在栅绝缘层 03上的漏电极 052、 源电极 051和数据线；
形成在漏电极 052、 源电极 051和数据线上的钝化层 06 , 且对应像素区 域的钝化层 06具有至少一条狭缝,钝化层 06的狭缝与栅绝缘层 03的狭缝一 一对应；
形成在钝化层 06上的由透明导电层 08组成的公共电极， 公共电极具有 与钝化层的狭缝——对应的狭缝结构。
进一步地， 为了提高阵列基板的开口率， 导电层 012可以釆用透明导电 材料； 例如， 透明导电材料可以为 ZnMgO。
下面结合具体的工艺流程对本实施例的阵列基板的制作方法进行进一步 地介绍：
步骤 801 : 在衬底基板 01上形成栅电极 02和栅线的图形， 并在像素区 域形成具有至少一条狭缝的导电层 012的图形。
在本步骤中， 在衬底基板上形成栅金属层； 通过一次构图工艺， 形成所 述栅电极和栅线， 并在所述像素区域形成由栅金属层构成的所述导电层的图 形， 所述导电层具有至少一条狭缝。
例如，在衬底基板 01上先沉积一层栅金属层，然后利用一次构图工艺（如 普通掩模版工艺） ， 利用栅金属层在衬底基板 01上形成栅电极 02和与栅电 极 02 连接的栅线， 利用栅金属层在像素区域上形成具有多条狭缝的导电层 012的图形。
优选地， 为了保证阵列基板的开口率， 栅电极 02、 栅线和导电层 012都 可以釆用透明导电材料制成， 例如， 可为透明的导电氧化物 ZnMgO, 亦可为 其它透明的导电材料。
步骤 802:在形成有栅电极 02、栅线和导电层 012的基板 01上形成栅绝 缘层 03 , 且利用构图工艺在像素区域形成栅绝缘层狭缝， 栅绝缘层狭缝与导 电层的狭缝——对应。
在本步骤中， 在形成有所述栅电极、 所述栅线和所述导电层的基板上形 成一层栅绝缘层薄膜； 在栅绝缘层薄膜上涂覆光刻胶， 通过构图工艺， 在所 述像素区域形成具有狭缝的栅绝缘层， 且所述栅绝缘层狭缝与所述导电层的 狭缝——对应。
例如， 在形成有栅电极 02、 栅线和导电层 012的基板 01上形成一层栅 绝缘层薄膜， 在栅绝缘层薄膜上涂覆光刻胶， 通过构图工艺， 在像素区域形 成具有多条狭缝的栅绝缘层 03 , 且栅绝缘层 03的狭缝与导电层 012的狭缝 ——对应。
步骤 803: 在形成有栅绝缘层 03的基板 01上形成有源层 04的图形。 例如， 可以在形成有栅绝缘层 03的基板 01上沉积一层有源材料层， 该 有源材料层可为 a-Si层和 n+ a-Si层的复合层。 通过一次构图工艺 （如釆用 普通掩模板） ， 利用有源材料层在栅绝缘层 03上形成有源层 04的图形。
步骤 804: 在形成有有源层 04的基板 01上形成源电极 051、 漏电极 052 和数据线的图形。
例如， 在形成有有源层 04的基板 01上沉积一层源漏金属层， 源漏金属 层可釆用常规的不透明的 Mo、 AlNd、 A1等金属。之后通过一次构图工艺（如 釆用普通掩模版）， 利用源漏金属层， 在基板 01上形成与栅线垂直交叉的数 据线、 在有源层 04的上方形成之间有间隔的源电极 051与漏电极 052 (源电 极 051和漏电极 052之间的间隔处也需要进行 n+ a-Si刻蚀 ) 。
步骤 805: 在形成有源电极 051、 漏电极 052和数据线的基板 01上形成 钝化层 06, 且利用构图工艺在像素区域形成钝化层狭缝， 钝化层狭缝与栅绝 缘层狭缝一一对应。
在本步骤中， 在形成有所述源电极、 所述漏电极和所述数据线的基板上 形成一层钝化层薄膜； 在钝化层薄膜上涂覆光刻胶， 通过构图工艺， 在所述 像素区域形成具有狭缝的钝化层， 且所述钝化层狭缝与所述栅绝缘层狭缝一 一对应。
例如， 在形成有源电极 051、 漏电极 052和数据线的基板 01上形成一层 钝化层薄膜， 在钝化层薄膜上涂覆光刻胶， 通过构图工艺， 在像素区域形成 具有多条狭缝的钝化层 06,且钝化层 06的狭缝与栅绝缘层 03的狭缝——对 应。
步骤 806: 在形成有钝化层 06的基板 01上形成透明导电层， 透明导电 层包括两层，其中一层位于钝化层 06上方形成公共电极，另一层位于狭缝区 域且与导电层 012同层并电连接以形成像素电极。
在本步骤中， 在形成有钝化层的基板上形成透明导电层， 所述透明导电 层的一部分保留在所述钝化层上方形成第一透明电极层， 该第一透明电极层 为公共电极； 所述透明导电层的另一部分填充到所述导电层的狭缝中， 并与 所述导电层电连接形成第二透明电极层， 该第二透明电极层与所述漏电极相 连形成所述像素电极。
例如， 可以通过溅射或热蒸发的方法在形成有钝化层 06的基板 01上沉 积一层透明导电层， 其中， 透明导电层可以釆用 ITO ( Indium Tin Oxide, 氧 化铟锡）。 由于钝化层 06的高度差及坡度， 这一层透明导电层可以自然地形 成高低不同的断面， 透明导电层的一部分 08保留在钝化层 06上方形成第一 透明电极层，该第一透明电极层为公共电极；透明导电层的另一部分 07填充 到导电层 012的狭缝中， 并与导电层 012电连接形成第二透明电极层， 该第 二透明电极层与漏电极 052相连形成像素电极。由于钝化层 06的高度差及坡 度， 使得第一透明电极层和第二透明电极层自然断开， 不会有电连接。
综合以上描述， 本发明实施例提供的阵列基板的制作方法， 包括： 在基 板上形成第一导电层， 对该第一导电层进行构图以形成具有至少一条狭缝的 导电层图案； 在所述导电层图案上形成绝缘膜， 对该绝缘膜进行构图以形成 具有绝缘层狭缝的绝缘层图案， 所述绝缘层狭缝与所述导电层图案的狭缝一 一对应； 所述绝缘层图案上形成第二导电层， 所述第二导电层对应于所述狭 缝的部分落入所述狭缝中且与所述第二导电层位于所述绝缘层图案之上的部 分断开， 所述第二导电层的落入所述狭缝中的部分与所述导电层图案连接以 形成第一电极， 所述第二导电层的位于所述绝缘层图案上的部分形成第二电 极。
该制作方法还可包括制作薄膜晶体管、 栅线和数据线的步骤， 其中所述 导电层图案、 所述薄膜晶体管的源极和漏极以及所述数据线在同一构图工艺 中形成； 在这种情况下， 绝缘层图案可以与钝化层图案在同一构图工艺中形 成。
或者，所述导电层图案与所述薄膜晶体管的栅极在同一构图工艺中形成； 在这种情况下， 上述绝缘层图案可以包括上下两层， 下层与薄膜晶体管的栅 极绝缘膜的图案同时形成， 而上层与钝化层的图案在同一构图工艺中形成。
以上所述的第一电极和第二电极其中之一为像素电极， 而另一者为公共 电极。 对于上述各部分的材料选择， 均可以参考以上各种实施例中的示例， 这里不再赘述。
本实施例的技术方案在基板上形成具有至少一条狭缝的导电层的图形， 并在导电层上形成具有至少一条狭缝的栅绝缘层， 栅绝缘层的狭缝与导电层 的狭缝——对应， 之后形成有源层、 漏电极、 源电极和数据线， 并形成具有 至少一条狭缝的钝化层， 钝化层的狭缝与导电层的狭缝一一对应， 在钝化层 上沉积透明导电层时，透明导电层保留在钝化层的上方的部分形成公共电极， 透明导电层的另一部分填充到导电层的狭缝中， 并与导电层连接形成与漏电 极相连的像素电极， 由于钝化层的高度差及坡度， 使得公共电极和像素电极 自然断开， 不会有电连接。 本发明的实施例能够通过一次工艺同时形成公共 电极和像素电极，从而能够简化阵列基板的制作工艺，提高产品的生产效率， 降低产品的生产成本。
本发明实施例还提供了一种显示装置， 包括如上任一实施例所述的阵列 基板。 所述显示装置可以为： 液晶面板、 电子纸、 OLED面板、 液晶电视、 液晶显示器、数码相框、手机、平板电脑等具有任何显示功能的产品或部件。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、一种阵列基板的制作方法， 其中，通过一次工艺同时形成公共电极和 像素电极。
2、 根据权利要求 1所述的阵列基板的制作方法， 包括：
在衬底基板上依次形成栅金属层和栅绝缘层， 所述栅金属层包括栅电极 和栅线的图形；
在形成有所述栅绝缘层的基板上形成有源层的图形；
在形成有所述有源层的基板上形成数据线、 源电极和漏电极的图形， 并 在像素区域形成包含有至少一条狭缝的导电层的图形；
在形成有所述数据线、 所述源电极、 所述漏电极和所述导电层的基板上 形成钝化层的图形， 所述钝化层具有与所述导电层的狭缝——对应的钝化层 狭缝；
在形成有所述钝化层的基板上形成透明导电层， 所述透明导电层包括两 层， 其中一层位于所述钝化层上方形成公共电极， 另一层位于所述狭缝区域 且与所述导电层同层并电连接以形成像素电极。
3、根据权利要求 2所述的阵列基板的制作方法， 其中， 所述在形成有所 述有源层的基板上形成数据线、 源电极和漏电极的图形， 并在像素区域形成 包含有至少一条狭缝的导电层的图形包括：
在形成有有源层图形的基板上形成一层源漏金属层；
通过构图工艺， 形成数据线、 位于所述有源层上方的源电极和漏电极， 所述源电极和漏电极之间形成有间隔， 以及在所述数据线与所述栅线交叉定 义的所述像素区域内形成具有至少一条狭缝的导电层的图形。
4、根据权利要求 2或 3所述的阵列基板的制作方法， 其中， 所述在形成 有所述数据线、 所述源电极、 所述漏电极和所述导电层的基板上形成钝化层 的图形， 所述钝化层具有与所述导电层的狭缝一一对应的钝化层狭缝包括： 在形成有所述数据线、 所述源电极、 所述漏电极和所述导电层的基板上 形成一层钝化层薄膜；
在钝化层薄膜上涂覆光刻胶， 通过一次构图工艺形成所述像素区域的钝 化层狭缝， 并且所述钝化层狭缝与所述导电层的狭缝——对应。
5、 根据权利要求 2-4中任一项所述的阵列基板的制作方法， 其中， 所述 在形成有所述钝化层的基板上形成透明导电层， 所述透明导电层包括两层， 其中一层位于所述钝化层上方形成公共电极， 另一层位于所述狭缝区域且与 所述导电层同层并电连接以形成像素电极包括：
在形成有所述钝化层的基板上形成透明导电层， 所述透明导电层的一部 分保留在所述钝化层上方形成第一透明电极层， 该第一透明电极层为公共电 极； 所述透明导电层的另一部分填充到所述导电层的狭缝中， 并与所述导电 层电连接形成第二透明电极层， 该第二透明电极层与所述漏电极相连形成所 述像素电极。
6、 根据权利要求 1所述的阵列基板的制作方法， 包括：
在衬底基板上形成栅电极和栅线的图形， 并在像素区域形成具有至少一 条狭缝的导电层的图形；
在形成有所述栅电极、 所述栅线和所述导电层的基板上形成栅绝缘层， 且利用构图工艺在像素区域形成栅绝缘层狭缝， 所述栅绝缘层狭缝与所述导 电层的狭缝——对应；
在形成有所述栅绝缘层的基板上形成有源层的图形；
在形成有所述有源层的基板上形成源电极、 漏电极和数据线的图形； 在形成有所述源电极、 所述漏电极和所述数据线的基板上形成钝化层， 且利用构图工艺在像素区域形成钝化层狭缝， 所述钝化层狭缝与所述栅绝缘 层狭缝——对应；
在形成有所述钝化层的基板上形成透明导电层， 所述透明导电层包括两 层， 其中一层位于所述钝化层上方形成公共电极， 另一层位于所述狭缝区域 且与所述导电层同层并电连接以形成像素电极。
7、根据权利要求 6所述的阵列基板的制作方法， 其中， 所述在衬底基板 上形成栅电极和栅线的图形， 并在像素区域形成具有至少一条狭缝的导电层 的图形包括：
在衬底基板上形成栅金属层；
通过一次构图工艺， 形成所述栅电极和栅线， 并在所述像素区域形成由 栅金属层构成的所述导电层的图形， 所述导电层具有至少一条狭缝。
8、根据权利要求 6或 7所述的阵列基板的制作方法， 其中， 所述在形成 有所述栅电极、 所述栅线和所述导电层的基板上形成栅绝缘层， 且利用构图 工艺在像素区域形成栅绝缘层狭缝， 所述栅绝缘层狭缝与所述导电层的狭缝 ——对应包括：
在形成有所述栅电极、 所述栅线和所述导电层的基板上形成一层栅绝缘 层薄膜；
在栅绝缘层薄膜上涂覆光刻胶， 通过构图工艺， 在所述像素区域形成具 有狭缝的栅绝缘层， 且所述栅绝缘层狭缝与所述导电层的狭缝——对应。
9、 根据权利要求 6-8中任一项所述的阵列基板的制作方法， 其中， 所述 在形成有所述源电极、 所述漏电极和所述数据线的基板上形成钝化层， 且利 用构图工艺在像素区域形成钝化层狭缝， 所述钝化层狭缝与所述栅绝缘层狭 缝——对应包括：
在形成有所述源电极、 所述漏电极和所述数据线的基板上形成一层钝化 层薄膜；
在钝化层薄膜上涂覆光刻胶， 通过构图工艺， 在所述像素区域形成具有 狭缝的钝化层， 且所述钝化层狭缝与所述栅绝缘层狭缝——对应。
10、 根据权利要求 6-9中任一项所述的阵列基板的制作方法， 其中， 所 述在形成有所述钝化层的基板上形成透明导电层，所述透明导电层包括两层， 其中一层位于所述钝化层上方形成公共电极， 另一层位于所述狭缝区域且与 所述导电层同层并电连接以形成像素电极包括：
在形成有钝化层的基板上形成透明导电层， 所述透明导电层的一部分保 留在所述钝化层上方形成第一透明电极层， 该第一透明电极层为公共电极； 所述透明导电层的另一部分填充到所述导电层的狭缝中， 并与所述导电层电 连接形成第二透明电极层， 该第二透明电极层与所述漏电极相连形成所述像 素电极。
11、 根据权利要求 2或 6所述的阵列基板的制作方法， 其中， 所述导电 层釆用透明导电材料。
12、 一种阵列基板， 包括由一次工艺形成的公共电极和像素电极， 其中， 所述像素电极包含具有至少一条狭缝的导电层， 狭缝中的透明导电层与所述 导电层连接组成所述像素电极；
所述导电层与所述阵列基板上的栅线同层或者与数据线同层。
13、 根据权利要求 12所述的阵列基板， 其中， 所述阵列基板包括： 衬底基板；
形成在所述衬底基板上的栅电极和栅线；
形成在上述衬底基板上的栅绝缘层；
形成在所述栅绝缘层上的漏电极、 源电极、 数据线、 具有至少一条狭缝 的导电层的图形， 以及位于所述狭缝中的透明导电层， 所述透明导电层与所 述导电层连接组成所述像素电极；
形成在所述源电极、 所述漏电极、 所述数据线和所述像素电极上的钝化 层， 所述钝化层具有至少一条狭缝， 所述钝化层的狭缝与所述导电层的狭缝 ——对应；
形成在所述钝化层上的由透明导电层组成的公共电极， 所述公共电极具 有与所述钝化层的狭缝——对应的狭缝结构。
14、 根据权利要求 12所述的阵列基板， 其中， 所述阵列基板包括： 衬底基板；
形成在所述衬底基板上的栅电极、 栅线、 具有至少一条狭缝的导电层的 图形， 以及位于所述狭缝中的透明导电层， 所述透明导电层与所述导电层连 接组成所述像素电极；
形成在所述栅电极、 所述栅线和所述像素电极上的栅绝缘层， 且像素区 域的所述栅绝缘层具有至少一条狭缝， 且所述栅绝缘层的狭缝与所述导电层 的狭缝——对应；
形成在所述栅绝缘层上的漏电极、 源电极和数据线；
形成在所述漏电极、 所述源电极和所述数据线上的钝化层， 且对应像素 区域的所述钝化层具有至少一条狭缝， 所述钝化层的狭缝与所述栅绝缘层的 狭缝——对应；
形成在所述钝化层上的由透明导电层组成的公共电极， 所述公共电极具 有与所述钝化层的狭缝——对应的狭缝结构。
15、 根据权利要求 13或 14所述的阵列基板， 其中， 所述导电层釆用透 明导电材料。
16、根据根据权利要求 15所述的阵列基板， 其中， 所述透明导电材料为 ZnMgO„
17、 一种显示装置， 其中， 包括如权利要求 12-16中任一项所述的阵列 基板。
18、 一种阵列基板的制作方法， 包括：
在基板上形成第一导电层， 对该第一导电层进行构图以形成具有至少一 条狭缝的导电层图案；
在所述导电层图案上形成绝缘膜， 对该绝缘膜进行构图以形成具有绝缘 层狭缝的绝缘层图案， 所述绝缘层狭缝与所述导电层图案的狭缝一一对应； 在所述绝缘层图案上形成第二导电层， 所述第二导电层对应于所述狭缝 的部分落入所述狭缝中且与所述第二导电层位于所述绝缘层图案之上的部分 断开， 所述第二导电层的落入所述狭缝中的部分与所述导电层图案连接以形 成第一电极，所述第二导电层的位于所述绝缘层图案上的部分形成第二电极。
19、如权利要求 18所述的制作方法，还包括制作薄膜晶体管、栅线和数 据线的步骤， 其中所述导电层图案、 所述薄膜晶体管的源极和漏极以及所述 数据线在同一构图工艺中形成。
20、如权利要求 18所述的制作方法，还包括制作薄膜晶体管、栅线和数 据线的步骤， 其中所述导电层图案与所述薄膜晶体管的栅极在同一构图工艺 中形成。
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