WO2013171996A1 - 電力用半導体モジュール - Google Patents
電力用半導体モジュール Download PDFInfo
- Publication number
- WO2013171996A1 WO2013171996A1 PCT/JP2013/002941 JP2013002941W WO2013171996A1 WO 2013171996 A1 WO2013171996 A1 WO 2013171996A1 JP 2013002941 W JP2013002941 W JP 2013002941W WO 2013171996 A1 WO2013171996 A1 WO 2013171996A1
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- WIPO (PCT)
- Prior art keywords
- frame
- metal conductor
- transistor
- conductor island
- disposed
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 210
- 229910052751 metal Inorganic materials 0.000 claims description 329
- 239000002184 metal Substances 0.000 claims description 329
- 239000004020 conductor Substances 0.000 claims description 236
- 239000012212 insulator Substances 0.000 claims description 59
- 239000011347 resin Substances 0.000 claims description 27
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- 239000000463 material Substances 0.000 claims description 22
- 229910010293 ceramic material Inorganic materials 0.000 claims description 3
- 230000000694 effects Effects 0.000 description 28
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- 239000010949 copper Substances 0.000 description 12
- 239000000919 ceramic Substances 0.000 description 11
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- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
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- 229910052802 copper Inorganic materials 0.000 description 4
- 238000010292 electrical insulation Methods 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
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- 238000007789 sealing Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
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- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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Definitions
- the present invention relates to the structure of a power semiconductor module.
- the power semiconductor module that converts power is required to be highly efficient from the viewpoint of energy saving.
- an insulated gate bipolar transistor IGBT
- a transistor using a wide bandgap power semiconductor element SiC, GaN
- an insulated gate transistor using silicon carbide SiC can achieve a high breakdown voltage and a low on-resistance, can operate at high speed because of a unipolar device, and is expected to be put to practical use.
- the switching loss can be greatly reduced, so that the high frequency operation with the same loss becomes possible.
- the size of the reactor and the capacity can be reduced, and the power conversion device can be configured to be small. Therefore, since the volume of the inverter itself can be significantly reduced, the configuration of the device itself can be miniaturized and integrated.
- the inductance from the power source side of the smoothing capacitor to the ground side through each phase of the module it is an important factor to reduce the inductance from the power source side of the smoothing capacitor to the ground side through each phase of the module.
- the power supply voltage is increased, the current is increased, and the speed of the device is increased, if the inductance value is increased, the device is adversely affected. More specifically, a through current is a problem when turned on, and a jumping voltage when turned off. In the worst case, the element is destroyed.
- the package size increases, and the increase in current and the inductance value are in a contradictory relationship.
- Patent Document 1 discloses a conventional technique for realizing a low inductance of a module when a plurality of power semiconductor chips are mounted.
- FIG. 10 shows a plan view of a conventional power semiconductor module described in Patent Document 1.
- the chips are arranged in parallel in the arm, the bus bar is arranged in the center, and the high side element group 73 and the low side element group 74 sandwich the bus bar. It is configured.
- the positive electrode side internal electrode 71 of the bus bar and the negative electrode side internal electrode 72 of the bus bar are arranged so as to face each other, and an effect of reducing inductance is achieved by adopting a configuration in which currents flow in opposite directions.
- a low inductance is achieved by utilizing the principle (mutual inductance effect) that cancels out the magnetic field by arranging the bus bars in which current flows in the opposite direction nearby.
- the module size is increased, and the inductance component cannot be sufficiently reduced.
- An object of the present invention is to provide a power semiconductor module that can reduce the wiring inductance by reducing the module size in consideration of the conventional problems.
- the first aspect of the present invention provides: A first frame in which a plurality of first transistors and first diodes are disposed; A second frame in which a plurality of second transistors and second diodes are disposed; A first intermediate frame adjacent to the first frame; A second intermediate frame adjacent to the second frame; A third frame electrically connected to the first intermediate frame and disposed above the first frame; A fourth frame electrically connected to the second intermediate frame and disposed above the second frame; A power supply terminal provided on an extension of the first frame; A ground terminal provided on an extension of the fourth frame; An output terminal provided on an extension in which the second frame and the third frame are electrically connected; A drain electrode of the first transistor is connected to the first frame; A source electrode of the first transistor and an anode electrode of the first diode are connected to the first intermediate frame by a first metal connection line; A drain electrode of the second transistor is connected to the second frame; A source electrode of the second transistor and an anode electrode of the second diode are connected to the second intermediate
- a foot of the third frame is connected to the first intermediate frame;
- the foot of the fourth frame is connected to the second intermediate frame;
- the legs of the third frame are disposed between the plurality of first connection lines,
- the leg of the fourth frame is a power semiconductor module according to the first aspect of the present invention, wherein the leg of the fourth frame is disposed between the plurality of second connection lines.
- the third aspect of the present invention is arranged to cover the first transistor and the first diode
- the power semiconductor module according to the first aspect of the present invention is characterized in that the fourth frame is disposed so as to cover the second transistor and the second diode.
- the fourth aspect of the present invention is A gate electrode of the first transistor is disposed on a side opposite to the first intermediate frame;
- the power semiconductor module according to the first aspect of the present invention is characterized in that the gate electrode of the second transistor is disposed on the opposite side of the second intermediate frame.
- the fifth aspect of the present invention provides A first metal conductor island in which a plurality of first transistors and a first diode are disposed; A second metal conductor island in which a plurality of second transistors and second diodes are disposed; A first intermediate metal conductor island adjacent to the first metal conductor island; A second intermediate metal conductor island adjacent to the second metal conductor island; A fifth frame electrically connected to the first intermediate metal conductor island and disposed above the first metal conductor island; A sixth frame electrically connected to the second intermediate metal conductor island and disposed above the second metal conductor island; A power supply terminal provided on an extension of the first metal conductor island; A ground terminal provided on an extension of the sixth frame; The second metal conductor island and the fifth frame are electrically connected, and includes an output terminal connected to the second metal conductor island; A drain electrode of the first transistor is connected to the first metal conductor island; A source electrode of the first transistor and an anode electrode of the first diode are connected to the first intermediate metal conductor island by a first metal connection line; A
- the fifth frame and the sixth frame are arranged in parallel with each other, and the power supply terminal, the ground terminal, and the ground terminal are arranged so that induced voltages generated in the fifth frame and the sixth frame are opposite to each other.
- the power semiconductor module is characterized in that the output terminal is disposed.
- the sixth aspect of the present invention provides A foot of the fifth frame is connected to the first intermediate metal conductor island; A foot of the sixth frame is connected to the second intermediate metal conductor island; The legs of the fifth frame are disposed between the plurality of first connection lines, The foot of the sixth frame is a power semiconductor module according to the fifth aspect of the present invention, which is arranged between the plurality of second connection lines.
- the seventh aspect of the present invention The fifth frame is arranged to cover the first transistor and the first diode,
- the sixth frame is a power semiconductor module according to the fifth aspect of the present invention, wherein the sixth frame is disposed so as to cover the second transistor and the second diode.
- the eighth aspect of the present invention In the power semiconductor module according to the first or fifth aspect of the present invention, the first connection line and the second connection line are formed of a ribbon.
- the ninth aspect of the present invention provides In the power semiconductor module according to the first or fifth aspect of the present invention, the first connection line and the second connection line are configured by clips.
- the tenth aspect of the present invention is A gate electrode of the first transistor is disposed on a side opposite to the first intermediate metal conductor island;
- the gate electrode of the second transistor is disposed on the side opposite to the second intermediate metal conductor island, and is the power semiconductor module according to the fifth aspect of the present invention.
- the present invention it is possible to provide a power semiconductor module that can reduce the wiring inductance by reducing the module size.
- FIG. 1 A plan view of the power semiconductor module according to the first embodiment of the present invention, (b) a cross-sectional view of the power semiconductor module according to the first embodiment of the present invention taken along the line AA ′ of FIG. (C) Sectional drawing of the modification of the power semiconductor module in Embodiment 1 of this invention (A)-(f) Top view which shows the assembly flow of the power semiconductor module of Embodiment 1 of this invention (A) A plan view of the power semiconductor module according to the second embodiment of the present invention, (b) a cross-sectional view of the power semiconductor module according to the second embodiment of the present invention at BB ′ in FIG.
- FIG. 1A shows a module configuration 101 that is a plan view of a resin-encapsulated power semiconductor module according to the first embodiment of the present invention.
- FIG. 1B shows a cross-sectional configuration 102 of the power semiconductor module of the first embodiment cut along AA ′ in FIG.
- FIGS. 2A to 2F show assembly flow diagrams of the power semiconductor module according to the first embodiment.
- 2 (a) to 2 (f) show plan views of the power semiconductor module according to the first embodiment when assembled.
- FIG. 2A shows the first lead frame 1, the second frame 2, the first intermediate frame 5, the second intermediate frame 6, the high-side gate terminal 7, the low-side source terminal 20, and the high-level lead frame.
- 4 is a plan view of a side source terminal 8 and a low side gate terminal 21.
- FIG. actually, these leads are fixed to the frame so as not to fall apart, and are separated from the frame after the final molding is completed, but detailed description of this part is omitted.
- the transistor chip 11 and the diode chip 12 which are semiconductor elements are mounted on the lead frame described in FIG. 2A by die bonding.
- a transistor such as IGBT or SiC-MOSFET is mounted.
- the drain electrode or collector electrode of the transistor chip 11 mounted on the first frame 1 and the second frame 2 is connected to the first frame 1 and the second frame 2, and is connected to the first frame 1 and the second frame 2.
- the cathode electrode of the diode chip 12 to be mounted is also connected to the first frame 1 and the second frame 2.
- the source electrode or emitter electrode of the transistor chip 11 mounted on the first frame 1 is wire-connected to the first intermediate frame 5, and the source electrode or emitter electrode of the transistor chip 11 mounted on the second frame 2 is second. Wire-connected to the intermediate frame 6.
- the gate pad 13 of the transistor chip 11 mounted on the first frame 1 and the gate terminal 7 on the high side of the lead frame are connected by wire, and the source pad of the transistor chip 11 and the source terminal 8 on the high side of the lead frame are connected. Are connected by wire.
- the gate pad 13 of the transistor chip 11 mounted on the second frame 2 and the gate terminal 21 on the low side of the lead frame are connected by wire, and the source pad of the transistor chip 11 and the source terminal 20 on the low side of the lead frame are connected. Wire connected.
- a third frame 3 on the positive electrode side and a fourth frame 4 on the negative electrode side that function as a bus bar are prepared.
- the fourth frame 4 is arranged above the second frame 2, and the legs of the fourth frame 4 are metal-bonded to the second intermediate frame 6.
- the third frame 3 is disposed above the first frame 1, and the third frame 3 is metal-bonded to the second frame 2 at the bonding point 50. Further, the legs of the third frame 3 are metal-bonded to the first intermediate frame 5.
- the module is fixed by molding with the insulating resin 18 and sealing the whole with a shape defined by the outer frame 19 of the insulating resin.
- the power semiconductor module according to the first embodiment is completed through such an assembly flow.
- a plurality of semiconductor chips are mounted on the first frame 1 and the second frame 2 by bonding them with a die bond material. These semiconductor chips are composed of a transistor chip 11 and a diode chip 12.
- the first frame 1 and the second frame 2 are disposed on the heat sink 17 via an insulator 16.
- the heat radiating plate 17 is preferably made of a material having a high thermal conductivity such as Cu or Al.
- the insulator 16 is preferably made of a material having good thermal conductivity and good electrical insulation.
- the entire wiring is molded with the insulating resin 18 and the shape of the module is defined by the outer frame 19 of the insulating resin.
- the configuration of the power semiconductor module according to the first embodiment using SiC-MOSFET as the transistor chip 11 corresponds to an example of the power semiconductor module of the present invention.
- the transistor chip 11 and the diode chip 12 mounted on the first frame 1 correspond to examples of the first transistor and the first diode of the present invention, respectively.
- the transistor chip 11 and the diode chip 12 mounted on the second frame 2 correspond to examples of the second transistor and the second diode of the present invention, respectively.
- first intermediate frame 5 and the second intermediate frame 6 which are narrower than these frames, are substantially parallel to the side closer to the first frame 1.
- the second intermediate frame 6 is disposed substantially parallel to the side close to the second frame 2.
- the first intermediate frame 5 and the second intermediate frame 6 are centered on the center line of the power semiconductor module, that is, on the basis of the line that bisects the module configuration 101 in the plan view of FIG. It is arrange
- the source or emitter electrode of the transistor chip 11 on the first frame 1 is connected to the first intermediate frame 5 by the metal connection line 9, and the anode electrode of the diode chip 12 on the first frame 1 is connected to the first intermediate frame 5.
- 5 is connected to a metal connection line 10.
- the legs of the third frame 3 disposed above the first frame 1 are connected to the first intermediate frame 5 where there are no metal connection lines 9, 10.
- the source or emitter electrode of the transistor chip 11 on the second frame 2 is connected to the second intermediate frame 6 by a metal connection line 9, and the anode electrode of the diode chip 12 on the second frame 2 is connected to the second intermediate frame 6. 6 is connected by a metal connection line 10.
- the leg of the fourth frame 4 disposed above the second frame 2 is connected to the second intermediate frame 6 where there are no metal connection lines 9, 10.
- the metal connection lines 9 and 10 connecting the transistor chip 11 and the diode chip 12 on the first frame 1 and the first intermediate frame 5 correspond to an example of the metal first connection line of the present invention. Further, the metal connection lines 9 and 10 connecting the transistor chip 11 and the diode chip 12 on the second frame 2 and the second intermediate frame 6 correspond to an example of the metal second connection line of the present invention.
- the third frame 3 covers at least the semiconductor chip mounting area of the first frame 1, that is, the area above which the three transistor chips 11 and the three diode chips 12 are mounted.
- the fourth frame 4 covers at least the semiconductor chip mounting area of the second frame 2.
- the metal connection line 9 used to connect from the source electrode or emitter electrode of the transistor chip 11 on the first frame 1 to the first intermediate frame 5 is usually composed of a plurality of Al wires, It also supports large currents.
- the metal connection line 10 used to connect the anode electrode of the diode chip 12 to the first intermediate frame 5 is the same as described above.
- metal connection lines 9 and 10 used for connecting the transistor chip 11 and the diode chip 12 on the second frame 2 and the second intermediate frame 6 are the same as described above.
- the power supply terminal portion 22 on the extension of the first frame 1 has a function as an electrode and functions as a P (power supply) terminal.
- the ground terminal portion 23 on the extension of the fourth frame 4 has a function as an electrode and functions as an N (ground) terminal.
- the third frame 3 and the second frame 2 are connected by a metal junction 50 arranged on the opposite side to the P terminal and the N terminal, and the output terminal portion 24 on the extension of the third frame 3 is an electrode. And functions as an O (output) terminal.
- the third frame 3 and the fourth frame 4 are arranged in parallel to each other, and the O terminal is arranged on the opposite side of the P terminal and the N terminal.
- the currents of the third frame 3 and the fourth frame 4 that is the negative electrode side bus bar flow in opposite directions, and the inductance can be reduced by the effect of mutual inductance.
- the power supply terminal portion 22 (P terminal), the ground terminal portion 23 (N terminal), and the output terminal portion 24 is arranged.
- the first intermediate frame 5, the second intermediate frame 6, the third frame 3, and the fourth frame 4 are used in combination so that the wiring on the semiconductor chip can realize a wide and low inductance ( Since it can be used as a bus bar), it is possible to reduce the size of the power semiconductor module, and the arrangement of the first frame 1 and the second frame 2 on which the semiconductor chip is mounted can be made closer. It is possible to achieve low inductance.
- the gate wiring it is advantageous to configure the distance from the gate driver as short as possible. Accordingly, the high-side gate terminal 7 and the low-side gate terminal 21 are formed as gate wiring leads, and the high-side source terminal 8 and the low-side source terminal 20 are formed as source wiring leads in the vicinity of each transistor. It is good to keep.
- a configuration in which a gate driver is arranged in each transistor chip 11 is desirable, but a configuration in which gates and sources of a plurality of transistor chips are combined into one lead may be used particularly in applications where high-speed operation is not required.
- a metal gate wiring 14 is formed from the gate pad 13 of the transistor chip 11 on the high-side gate terminal 7 and the low-side gate terminal 21 which are leads for the gate wiring.
- a metal source wiring 15 is formed on the high-side source terminal 8 and the low-side source terminal 20 which are leads for the source wiring.
- the transistor chip 11 and the lead for the gate wiring and the lead for the source wiring are electrically connected by the metal wiring.
- the gate electrode of the transistor chip 11 on the first frame 1 is arranged on the side opposite to the first intermediate frame 5 in the center of the power semiconductor module, as shown in FIG. It is advantageous that the gate electrode of the transistor chip 11 on the second frame 2 is arranged on the side opposite to the second intermediate frame 6 in the center of the power semiconductor module because the wiring is shortened.
- an insulator 16 is disposed on a heat radiating plate 17 disposed on the lower surface side, each frame is disposed thereon, and an insulating resin It is desirable to adopt a configuration in which molding is performed with an insulating resin 18 as defined by the outer frame 19.
- the present invention is not limited to the example shown here, and the number and arrangement of the semiconductor chips are not particularly specified because they are determined by an arbitrary combination according to the current rating of the power semiconductor module.
- the minimum structural unit of the number of semiconductor chips is only one transistor chip, or one transistor chip and one diode chip. Even in such a configuration, inductance reduction is required to achieve high-speed operation of the device. Therefore, the effect of applying the configuration of the power semiconductor module of the first embodiment is great.
- FIG. 3A shows a module configuration 103 which is a plan view of a metal insulating substrate type power semiconductor module.
- FIG. 3B shows a cross-sectional configuration 104 of the power semiconductor module according to the second embodiment taken along the line BB ′ in FIG.
- FIGS. 4A to 4F show assembly flow diagrams of the power semiconductor module according to the second embodiment.
- 4 (a) to 4 (f) show plan views of the power semiconductor module according to the second embodiment at the time of assembly.
- FIG. 4A is a wiring pattern diagram on the underlying ceramic substrate.
- a side gate terminal 37, a low side source terminal 25, a high side source terminal 38, and a low side gate terminal 26 are formed on the substrate. This ceramic substrate is attached to the case 49.
- the ceramic substrate shown as the insulator 46 in FIG. 3B is configured to be mounted on the heat sink 47 via the adhesive layer 63, the detailed description of this part is omitted.
- the transistor chip 41 and the diode chip 42 which are semiconductor elements are mounted on the first metal conductor island 31 and the second metal conductor island 33 which are lead frames by die bonding.
- a transistor such as IGBT or SiC-MOSFET is mounted.
- the drain electrode or collector electrode of the transistor chip 41 mounted on the first metal conductor island 31 and the second metal conductor island 33 is connected to the first metal conductor island 31 and the second metal conductor island 33.
- the cathode electrode of the diode chip 42 mounted on the first metal conductor island 31 and the second metal conductor island 33 is also connected to the first metal conductor island 31 and the second metal conductor island 33.
- the source electrode or emitter electrode of the transistor chip 41 mounted on the first metal conductor island 31 is wire-connected to the first intermediate metal conductor island 35, and the transistor chip 41 mounted on the second metal conductor island 33. Are connected to the second intermediate metal conductor island 36 by wire.
- the gate pad of the transistor chip 41 mounted on the first metal conductor island 31 and the gate terminal 37 on the high side of the lead frame are connected by wire, and the source pad of the transistor chip 41 and the source on the high side of the lead frame are connected.
- the terminal 38 is wire-connected.
- the gate pad of the transistor chip 41 mounted on the second metal conductor island 33 and the gate terminal 26 on the low side of the lead frame are wire-connected, and the source pad of the transistor chip 41 and the source terminal on the low side of the lead frame are connected. 25 is wire-connected.
- a fifth frame 32 on the positive electrode side and a sixth frame 34 on the negative electrode side that function as a bus bar are prepared.
- the sixth frame 34 is disposed above the second metal conductor island 33, and the legs of the sixth frame 34 are metal-bonded to the second intermediate metal conductor island 36.
- the fifth frame 32 is disposed above the first metal conductor island 31, and the fifth frame 32 is metal-bonded to the second metal conductor island 33 at the junction point 51. Further, the legs of the fifth frame 32 are metal-bonded to the first intermediate metal conductor island 35.
- FIGS. 3A and 3B the configuration of the power semiconductor module of the second embodiment manufactured through the assembly flow shown in FIGS. 4A to 4F is used. Will be described.
- the insulator 46 is composed of a ceramic substrate.
- a ceramic substrate For example, an aluminum nitride (AlN) substrate or a silicon nitride (SiN) substrate is optimal, and an alumina (Al 2 O 3 ) substrate is also often used, and a thick metal wiring capable of flowing a large current is formed on the surface. .
- the first intermediate metal conductor island 35 is substantially parallel to the side close to the first metal conductor island 31, and the second intermediate metal conductor island 36 is the second metal conductor. It is arranged substantially parallel to the side close to the island 33.
- the first intermediate metal conductor island 35 and the second intermediate metal conductor island 36 are center lines of the power semiconductor module, that is, a line that bisects the outer shape of the case 49 in the plan view of FIG. With the center line as a reference, they are arranged at opposite positions.
- a plurality of semiconductor chips are mounted on the first metal conductor island 31 and the second metal conductor island 33 by bonding them with a die bond material.
- These semiconductor chips include a transistor chip 41 and a diode chip 42.
- the first metal conductor island 31 and the second metal conductor island 33 are disposed on the heat sink 47 via an insulator 46.
- the first metal conductor island 31 and the second metal conductor island 33 are fixed to the insulator 46 by the adhesive layer 62.
- the heat radiating plate 47 is preferably made of a material having a high thermal conductivity such as Cu or Al.
- the insulator 46 is fixed to the heat sink 47 with an adhesive layer 63.
- the insulator 46 is preferably made of a material having good thermal conductivity and good electrical insulation.
- the configuration of the power semiconductor module according to the second embodiment using SiC-MOSFET as the transistor chip 41 corresponds to an example of the power semiconductor module of the present invention.
- the transistor chip 41 and the diode chip 42 mounted on the first metal conductor island 31 correspond to examples of the first transistor and the first diode of the present invention, respectively.
- the transistor chip 41 and the diode chip 42 mounted on the second metal conductor island 33 correspond to examples of the second transistor and the second diode of the present invention, respectively.
- the entire power semiconductor module according to the second embodiment has an outer shape determined by the case 49 and is filled with the high heat-resistant silicone gel 48 or the like to ensure a withstand voltage or the like.
- a diode chip on the first metal conductor island 31 is connected to the first intermediate metal conductor island 35 from the source electrode or emitter electrode of the transistor chip 41 on the first metal conductor island 31 by a metal connection line 39.
- the anode connection electrode 42 is connected to the first intermediate metal conductor island 35 by a metal connection line 40.
- the leg of the fifth frame 32 disposed above the first metal conductor island 31 is connected to a place on the first metal conductor island 31 where the metal connection lines 39 and 40 are not present.
- the diode chip on the second metal conductor island 33 is connected from the source electrode or emitter electrode of the transistor chip 41 on the second metal conductor island 33 to the second intermediate metal conductor island 36 by a metal connection line 39.
- the anode electrode 42 is connected to the second intermediate metal conductor island 36 by a metal connection line 40.
- the foot of the sixth frame 34 disposed above the second metal conductor island 33 is connected to the second intermediate metal conductor island 36 where there are no metal connection lines 39, 40.
- the metal connection lines 39 and 40 connecting the transistor chip 41 and the diode chip 42 on the first metal conductor island 31 and the first intermediate metal conductor island 35 are the metal first connection lines of the present invention.
- the metal connection lines 39 and 40 connecting the transistor chip 41 and the diode chip 42 on the second metal conductor island 33 and the second intermediate metal conductor island 36 are the metal second connection lines of the present invention.
- the fifth frame 32 cover at least the semiconductor chip mounting area of the first metal conductor island 31, that is, the area where the three transistor chips 41 and the three diode chips 42 are mounted.
- the sixth frame 34 covers at least the semiconductor chip mounting region of the second metal conductor island 33.
- the metal connection line 39 used to connect from the source electrode or emitter electrode of the transistor chip 41 on the first metal conductor island 31 to the first intermediate metal conductor island 35 is usually an Al wire. It consists of a plurality of cables and can handle large currents.
- the metal connection line 40 used to connect the anode electrode of the diode chip 42 to the first intermediate metal conductor island 35 is the same as described above.
- the extended portion of the first metal conductor island 31 has a function as an electrode and functions as a P (power source) terminal 27.
- the extended portion of the sixth frame 34 has a function as an electrode and is connected to an N (ground) terminal 28.
- N ground terminal
- the fifth frame 32 and the second metal conductor island 33 are connected by a metal junction point 51 disposed on the opposite side to the P terminal 27 and the N terminal 28, and an extended portion of the second metal conductor island 33.
- the space on the semiconductor chip can be configured as a bus bar, and therefore, at least the semiconductor chip occupies the bus bar. As a result, it is possible to reduce the inductance by using a wide wiring.
- the size of the power semiconductor module can be greatly reduced. Accordingly, the wiring length is shortened and the inductance can be further reduced, so that the effect is great.
- a high-side gate terminal 37 and a low-side gate terminal 26 are formed as gate wiring leads, and a high-side source terminal 38 and a low-side source terminal 25 are formed as source wiring leads in the vicinity of each transistor. It is good to keep.
- a configuration in which a gate driver is arranged in each transistor chip 41 is desirable, but a configuration in which gates and sources of a plurality of transistor chips are combined into one lead may be used particularly in applications where high-speed operation is not required.
- the transistor chip 41 and the lead for the gate wiring and the lead for the source wiring are electrically connected by the metal wiring.
- the gate electrode of the transistor chip 41 on the first metal conductor island 31 is arranged on the opposite side to the first intermediate metal conductor island 35 in the center of the power semiconductor module, as shown in FIG.
- the gate electrode of the transistor chip 41 on the second metal conductor island 33 is arranged on the side opposite to the second intermediate metal conductor island 36 in the center of the power semiconductor module.
- the wiring is also shortened, which is advantageous.
- an insulator 46 is arranged on a heat radiating plate 47 arranged on the lower surface side, each frame is arranged thereon, and sealed with a silicone gel 48. desirable.
- the present invention is not limited to the example shown here, and the number and arrangement of the semiconductor chips are not particularly specified because they are determined by an arbitrary combination according to the current rating of the power semiconductor module.
- the minimum structural unit of the number of semiconductor chips is only one transistor chip, or one transistor chip and one diode chip. Even in such a configuration, inductance reduction is required to achieve high-speed operation of the device. Therefore, the effect of applying the configuration of the power semiconductor module of the second embodiment is great.
- the number of transistor chips and the number of diode chips need not be equal.
- the positive bus bar and the negative bus bar are configured by arranging the wide lead frame in the space on the semiconductor element.
- the module size can be reduced.
- the bus bar is not directly connected to the semiconductor element, the junction reliability can be remarkably improved.
- connection can be realized by metal bonding between the frame and the frame instead of bonding between the semiconductor chip and the frame, it is possible to apply larger heat and vibration stress. Strong bonding can be realized.
- bonding between the semiconductor chip and the intermediate frame even if temperature distribution occurs between the semiconductor chips by using wiring for each semiconductor chip, if the reliability between each semiconductor chip and the frame can be secured individually, the overall reliability Can be improved. It has been found that such a configuration can solve the conventional problems described above.
- the positive frame is obtained by combining the intermediate frame and the wide bus bar frame. Since both the side bus bar and the negative electrode side bus bar can be arranged in the space on the semiconductor chip, a wide configuration can be realized, so that the wiring inductance can be greatly reduced as compared with the prior art. This makes it possible to provide a power semiconductor module that is robust against noise and has high reliability as a whole module. Further, since it is not necessary to secure the bus bar area at the same time, the module size can be reduced.
- FIG. 1B shows the case where the first intermediate frame 5 and the second intermediate frame 6 are arranged between the first frame 1 and the second frame 2 as shown in FIG.
- the first intermediate frame 5 and the second intermediate frame 6 may be disposed outside the first frame 1 and the second frame 2 as shown in FIG.
- FIG.1 (c) shows the cross-sectional structure 102 'of the power semiconductor module as a modification of the power semiconductor module shown in FIG.1 (a), (b) in Embodiment 1 of this invention. It is sectional drawing.
- the first intermediate metal conductor island 35 and the second intermediate metal conductor island 36 are disposed between the first metal conductor island 31 and the second metal conductor island 33.
- the present invention is not limited to this.
- the first intermediate metal conductor island 35 and the second intermediate metal conductor island 36 are It may be arranged outside the first metal conductor island 31 and the second metal conductor island 33.
- FIG.3 (c) shows the cross-sectional structure 104 'of the power semiconductor module as a modification of the power semiconductor module shown in FIG.3 (a), (b) in Embodiment 1 of this invention. It is sectional drawing.
- FIG. 5A shows a module configuration 1101 that is a plan view of the resin-encapsulated power semiconductor module according to the third embodiment of the present invention.
- FIG. 5B shows a cross-sectional configuration 1102 of the power semiconductor module according to the third embodiment, taken along AA ′ in FIG.
- FIGS. 6A to 6E show assembly flow diagrams of the power semiconductor module according to the third embodiment.
- FIGS. 6A to 6E are plan views showing the power semiconductor module according to the third embodiment when assembled.
- FIG. 6A shows the first lead frame 301, the second frame 302, the first intermediate frame 305, the second intermediate frame 306, the high-side gate terminal 307, the low-side source terminal 320, and the high-level lead frame.
- 4 is a plan view of a side-side source terminal 308 and a low-side side gate terminal 321.
- FIG. actually, these leads are fixed to the frame so as not to fall apart, and are separated from the frame after the final molding is completed, but detailed description of this part is omitted.
- the transistor chip 311 and the diode chip 312 which are semiconductor elements are mounted on the lead frame described in FIG. 6A by die bonding.
- a transistor such as an IGBT or a SiC-MOSFET is mounted as the transistor chip 311.
- the drain electrode or collector electrode of the transistor chip 311 mounted on the first frame 301 and the second frame 302 is connected to the first frame 301 and the second frame 302, and is connected to the first frame 301 and the second frame 302.
- the cathode electrode of the mounted diode chip 312 is also connected to the first frame 301 and the second frame 302.
- the source electrode or emitter electrode of the transistor chip 311 mounted on the first frame 301 is wire-connected to the first intermediate frame 305, and the source electrode or emitter electrode of the transistor chip 311 mounted on the second frame 302 is second. Wire-connected to the intermediate frame 306.
- the gate pad 313 of the transistor chip 311 mounted on the first frame 301 and the gate terminal 307 on the high side of the lead frame are connected by wire, and the source pad of the transistor chip 311 and the source terminal 308 on the high side of the lead frame are connected. Are connected by wire.
- the gate pad 313 of the transistor chip 311 mounted on the second frame 302 and the gate terminal 321 on the low side of the lead frame are connected by wire, and the source pad of the transistor chip 311 and the source terminal 320 on the low side of the lead frame are connected. Wire connected.
- a third frame 303 on the positive electrode side that functions as a bus bar and a fourth frame 304 on the negative electrode side are prepared.
- the shapes of the third frame 303 and the fourth frame 304 are processed, and the insulator 1200 is disposed and bonded between the lead frames. In this manner, a composite in which the third frame 303 and the fourth frame 304 are arranged in parallel via the insulator 1200 is formed.
- the composite of the third frame 303 and the fourth frame 304 formed in FIG. 6C is arranged above the first frame 301 and the second frame 302, and the third frame 303 is obtained.
- the legs of the fourth frame 304 are metal-bonded to the first intermediate frame 305, and the legs of the fourth frame 304 are metal-bonded to the second intermediate frame 306.
- the legs of the third frame 303 are metal-bonded to the second frame 302 at the bonding point 350.
- the module is fixed by molding with the insulating resin 318 and sealing the whole with a shape defined by the outer frame 319 of the insulating resin.
- a plurality of semiconductor chips are mounted on the first frame 301 and the second frame 302 by bonding them with a die bond material. These semiconductor chips include a transistor chip 311 and a diode chip 312.
- the first frame 301 and the second frame 302 are disposed on the heat sink 317 via an insulator 316.
- the heat radiating plate 317 is preferably made of a material such as Cu or Al having a high thermal conductivity.
- the insulator 316 is preferably formed using a material having good thermal conductivity and good electrical insulation.
- the entire wiring is molded with insulating resin 318, and the shape of the module is defined by outer frame 319 of insulating resin.
- the configuration of the power semiconductor module according to the third embodiment using SiC-MOSFET as the transistor chip 311 corresponds to an example of the power semiconductor module of the present invention.
- the transistor chip 311 and the diode chip 312 mounted on the first frame 301 correspond to examples of the first transistor and the first diode of the present invention, respectively.
- the transistor chip 311 and the diode chip 312 mounted on the second frame 302 are examples of the second transistor and the second diode of the present invention, respectively.
- the insulator 316 corresponds to an example of the first insulator of the present invention.
- first intermediate frame 305 and a second intermediate frame 306 which are narrower than these frames, are substantially parallel to the side closer to the first frame 301.
- the second intermediate frame 306 is disposed substantially parallel to the side close to the second frame 302.
- the source or emitter electrode of the transistor chip 311 on the first frame 301 is connected to the first intermediate frame 305 by a metal connection line 309, and the anode electrode of the diode chip 312 on the first frame 301 is connected to the first intermediate frame.
- a metal connection line 310 is connected to 305.
- the leg of the third frame 303 disposed above the first frame 301 is connected to the first intermediate frame 305 where there are no metal connection lines 309 and 10.
- the source electrode or the emitter electrode of the transistor chip 311 on the second frame 302 is connected to the second intermediate frame 306 by a metal connection line 309, and the anode electrode of the diode chip 312 on the second frame 302 is connected to the second intermediate frame.
- a metal connection line 310 is connected to 306.
- the leg of the fourth frame 304 disposed above the second frame 302 is connected to the second intermediate frame 306 where there are no metal connection lines 309 and 10.
- the metal connection lines 309 and 10 connecting the transistor chip 311 and the diode chip 312 on the first frame 301 and the first intermediate frame 305 correspond to an example of the first metal connection line of the present invention.
- the metal connection lines 309 and 10 connecting the transistor chip 311 and the diode chip 312 on the second frame 302 and the second intermediate frame 306 correspond to an example of the metal second connection line of the present invention.
- the third frame 303 is arranged so as to overlap with the fourth frame 304 in the vertical direction, and has a closest structure with a dielectric strength secured by sandwiching an insulator 1200 between them, It is desirable to cover the transistor chip 311 and the diode chip 312 disposed on the second frame 302.
- the insulator 1200 is an example of the second insulator of the present invention.
- the insulator 1200 is provided for the purpose of securing the distance between the third frame 303 and the fourth frame 304, if there is another means for securing the distance between these frames, it is necessary to provide the insulator 1200.
- the inter-frame distance may be secured by using another means.
- the insulator 1200 between the third frame 303 and the fourth frame 304 is made of insulating resin or ceramic.
- the thickness of the insulator 1200 is appropriately set in accordance with the trade-off relationship between the withstand voltage and the electrical characteristics. The closer the distance between the frames, the lower the inductance but the lower the withstand voltage. As the distance between the frames increases, the withstand voltage can be improved, but the magnetic field canceling effect is reduced and the inductance is increased.
- the maximum electric field strength is set to about 1 MV / cm or less.
- a thickness of 10 ⁇ m is required.
- an electric field higher than this it will not be destroyed immediately, but if it is intended to ensure a life of 20 years or more in a high temperature environment of 300 ° C. or higher, it is set to about 1 MV / cm or lower. Is preferred.
- the actual thickness of the insulator 1200 depends on the withstand voltage, but it is desirable to set the thinnest setting to (withstand voltage / (1 MV / cm)). By setting in this way, the inductance reduction effect can be maximized.
- a withstand voltage required for an actual power semiconductor module a minimum of 1 kV or more is required. Therefore, the thinnest configuration of the insulator 1200 is 10 ⁇ m or more.
- the upper limit of the thickness of the insulator 1200 it is desirable to set the upper limit of the thickness of the insulator 1200 to about 1 mm or less. By setting in this way, the inductance reduction effect can be exhibited.
- FIG. 7 shows an equivalent circuit diagram of the power semiconductor module according to the third embodiment.
- L1, L2, L3, L5, L6, and L7 indicate inductances between the transistor chip 311 and the first intermediate frame 305 and the second intermediate frame 306, respectively.
- L4 and L8 are wiring inductances of the third frame 303 and the fourth frame 304, respectively. These can be reduced by using a wide bus bar.
- the P (power) terminal and the N (ground) terminal are connected to the same side of the power semiconductor module.
- the O (output) terminal is arranged on the opposite side surface side so that the direction of the current flowing through the third frame 303 and the direction of the current flowing through the fourth frame 304 are opposite to each other.
- the inductance (L1, L2, L3, L5, L6, and L7) of the wiring connecting the source electrode and the intermediate lead has a substantial inductance value, but the current amount per chip is the entire amount. Since it is smaller than the amount of current, the electrical characteristics of the entire power semiconductor module can realize a good operation.
- the vertical positional relationship between the third frame 303 and the fourth frame 304 positioned on the first frame 301 and the second frame 302 does not affect the effect of reducing the inductances L4 and L8 described above. Therefore, if the distance between the first frame 301 and the second frame 302 and the third frame 303 and the fourth frame 304 is sufficiently secured, the upper and lower arrangement configurations of the third frame 303 and the fourth frame 304 are: Either configuration is possible. However, when the legs of the third frame 303 and the fourth frame 304 are shortened, there is a configuration in which an adverse effect appears in the upper and lower arrangement configurations of the third frame 303 and the fourth frame 304.
- the legs of the third frame 303 and the fourth frame 304 can be shortened, the inductance can be further reduced, and these frames can also function as a heat radiating plate.
- the configuration in which the third frame 303 is arranged above the fourth frame 304 is used.
- the fourth frame 304 is grounded, it is possible to make a structure resistant to noise by fixing the potential.
- the configuration has an adverse effect.
- the third frame 303 and the gate wiring 314 have capacitive coupling, and the voltage of the third frame 303 varies from 0 V to the power supply voltage. More specifically, at the moment when the low-side transistor chip 311 is turned off, the voltage of the third frame 303 rises to the power supply voltage. At this time, the gate wiring is raised to a positive voltage regardless of the low-side transistor chip 311 being off.
- the power source of the driver that drives the transistor chip 311 on the low side is often driven in common, and as a result, the driver input signal line distance becomes long, so noise resistance is weaker than that on the high side. Therefore, in order to improve noise resistance of the low-side element, it is preferable from the viewpoint of noise resistance that the bus bar immediately above the transistor chip 311 mounted on the second frame 302 is the grounded fourth frame 304. .
- the metal connection line 309 used to connect from the source electrode or the emitter electrode of the transistor chip 311 on the first frame 301 to the first intermediate frame 305 normally includes a plurality of Al wires, It also supports large currents.
- the metal connection line 310 used to connect the anode electrode of the diode chip 312 to the first intermediate frame 305 is the same as described above.
- the metal connection lines 309 and 10 used to connect the transistor chip 311 and the diode chip 312 on the second frame 302 and the second intermediate frame 306 are also the same as described above.
- the power supply terminal portion 322 on the extension of the first frame 301 has a function as an electrode and functions as a P (power supply) terminal.
- the ground terminal portion 323 on the extension of the fourth frame 304 has a function as an electrode and functions as an N (ground) terminal.
- the third frame 303 and the second frame 302 are connected by a metal junction 350 arranged on the opposite side to the P terminal and the N terminal, and the output terminal portion 324 on the extension of the second frame 302 is an electrode. And functions as an O (output) terminal.
- the space on the semiconductor chip is effectively used as a wide wiring (bus bar) arrangement. Therefore, further miniaturization of the power semiconductor module can be realized, and the structure becomes more advantageous for low inductance. Since the first frame 301 and the second frame 302 on which the semiconductor chip is mounted can be brought close to each other, the wiring length is shortened, and further reduction in inductance can be realized.
- the gate wiring 314 is connected by a metal wire between the high-side gate terminal 307 and the low-side gate terminal 321 and the gate pad 313 of the corresponding transistor chip 311.
- the source wiring 315 is connected by a metal wire between the high-side source terminal 308 and the low-side source terminal 320 and the source electrode of the corresponding transistor chip 311.
- an insulator 316 is disposed on a heat sink 317 disposed on the lower surface side, and each frame is disposed thereon, It is desirable to mold with the insulating resin 318 so that is defined by the outer frame 319 of the insulating resin.
- the present invention is not limited to the example shown here, and the number and arrangement of the semiconductor chips are not particularly specified because they are determined by an arbitrary combination according to the current rating of the power semiconductor module.
- the minimum structural unit of the number of semiconductor chips is only one transistor chip, or one transistor chip and one diode chip. Even in such a configuration, inductance reduction is required to achieve high-speed operation of the device. Therefore, the effect of applying the configuration of the power semiconductor module of the third embodiment is great.
- the third frame 303 and the fourth frame 304 which are wide lead frames, are arranged so as to overlap each other using the space on the semiconductor element.
- the wiring inductance can be reduced, and the module size can be reduced.
- each part is arranged so that the induced voltages generated in the third frame 303 and the fourth frame 304 are in opposite directions.
- FIG. 8 (a) shows a module configuration 1103 as a plan view of a metal insulating substrate type power semiconductor module as a fourth embodiment of the present invention.
- FIG. 8B shows a cross-sectional configuration 1104 of the power semiconductor module according to the fourth embodiment cut along BB ′ in FIG.
- FIGS. 9A to 9E show assembly flow diagrams of the power semiconductor module according to the fourth embodiment.
- FIGS. 9A to 9E are plan views showing the power semiconductor module according to the fourth embodiment when assembled.
- FIG. 9A is a wiring pattern diagram on the underlying ceramic substrate.
- a side gate terminal 337, a low side source terminal 325, a high side source terminal 338, and a low side gate terminal 326 are formed on the substrate.
- the high side gate terminal 337 and the high side source terminal 338 are leads for sending electric signals to the gate pad and the source pad, respectively.
- the low-side gate terminal 326 and the low-side source terminal 325 are also patterns in which leads for sending electric signals to the gate pad and the source pad are formed.
- the ceramic substrate on which these wiring patterns are formed is attached to the case 349.
- the ceramic substrate shown as the insulator 346 in FIG. 8B is configured to be mounted on the heat radiating plate 347 with the adhesive layer 363 interposed therebetween, but a detailed description of this part is omitted.
- a transistor chip 341 and a diode chip 342, which are semiconductor elements, are mounted on the first metal conductor island 331 and the second metal conductor island 333, which are lead frames, by die bonding. .
- a transistor such as IGBT or SiC-MOSFET is mounted.
- the drain electrode or collector electrode of the transistor chip 341 mounted on the first metal conductor island 331 and the second metal conductor island 333 is connected to the first metal conductor island 331 and the second metal conductor island 333.
- the cathode electrode of the diode chip 342 mounted on the first metal conductor island 331 and the second metal conductor island 333 is also connected to the first metal conductor island 331 and the second metal conductor island 333.
- the source electrode or emitter electrode of the transistor chip 341 mounted on the first metal conductor island 331 is wire-connected to the first intermediate metal conductor island 335, and the transistor chip 341 mounted on the second metal conductor island 333.
- Source electrode or emitter electrode is wire-connected to the second intermediate metal conductor island 336.
- the gate pad of the transistor chip 341 mounted on the first metal conductor island 331 and the gate terminal 337 on the high side of the lead frame are wire-connected, and the source pad of the transistor chip 341 and the source on the high side of the lead frame are connected.
- the terminal 338 is wire-connected.
- the gate pad of the transistor chip 341 mounted on the second metal conductor island 333 and the gate terminal 326 on the low side of the lead frame are wire-connected, and the source pad of the transistor chip 341 and the source terminal on the low side of the lead frame are connected. 325 is wired.
- a fifth frame 332 on the positive electrode side that functions as a bus bar and a sixth frame 334 on the negative electrode side are prepared.
- the shapes of the fifth frame 332 and the sixth frame 334 are processed, and the insulator 1201 is disposed and bonded between the lead frames. In this way, a composite in which the fifth frame 332 and the sixth frame 334 are arranged in parallel via the insulator 1201 is formed.
- the composite of the fifth frame 332 and the sixth frame 334 formed in FIG. 9C is disposed above the first metal conductor island 331 and the second metal conductor island 333.
- the legs of the fifth frame 332 are metal bonded to the first intermediate metal conductor island 335, and the legs of the sixth frame 334 are metal bonded to the second intermediate metal conductor island 336.
- the legs of the fifth frame 332 are metal-bonded to the second metal conductor island 333 at the bonding point 351.
- the insulator 346 is formed of a ceramic substrate.
- a ceramic substrate For example, an aluminum nitride (AlN) substrate or a silicon nitride (SiN) substrate is optimal, and an alumina (Al 2 O 3 ) substrate is also often used, and a thick metal wiring capable of flowing a large current is formed on the surface. .
- first intermediate metal conductor island 335 is substantially parallel to the side closer to the first metal conductor island 331
- second intermediate metal conductor island 336 is the second metal conductor. It is arranged substantially parallel to the side close to the island 333.
- a plurality of semiconductor chips are mounted on the first metal conductor island 331 and the second metal conductor island 333 by bonding them with a die bond material. These semiconductor chips include a transistor chip 341 and a diode chip 342.
- 1st metal conductor island 331 and 2nd metal conductor island 333 are arrange
- the first metal conductor island 331 and the second metal conductor island 333 are fixed to the insulator 346 by the adhesive layer 362.
- the heat sink 347 is preferably made of a material such as Cu or Al having a high thermal conductivity.
- the insulator 346 is fixed to the heat sink 347 with an adhesive layer 363.
- the insulator 346 is preferably formed using a material having good thermal conductivity and good electrical insulation.
- the configuration of the power semiconductor module according to the fourth embodiment using SiC-MOSFET as the transistor chip 341 corresponds to an example of the power semiconductor module of the present invention.
- the transistor chip 341 and the diode chip 342 mounted on the first metal conductor island 331 are examples of the first transistor and the first diode of the present invention, respectively.
- the transistor chip 341 and the diode chip 342 mounted on the second metal conductor island 333 are examples of the second transistor and the second diode of the present invention, respectively.
- the insulator 346 is an example of the first insulator of the present invention.
- the whole power semiconductor module according to the fourth embodiment has an outer shape determined by a case 349 and is filled with a high heat-resistant silicone gel 348 or the like to ensure a withstand voltage or the like.
- a diode chip on the first metal conductor island 331 is connected from the source electrode or emitter electrode of the transistor chip 341 on the first metal conductor island 331 to the first intermediate metal conductor island 335 by a metal connection line 339.
- a metal connection line 40 connects the anode electrode 342 to the first intermediate metal conductor island 335.
- a leg of a fifth frame 332 disposed above the first metal conductor island 331 is connected to a place on the first intermediate metal conductor island 335 where the metal connection lines 339 and 340 are not present.
- a diode chip on the second metal conductor island 333 is connected from the source electrode or emitter electrode of the transistor chip 341 on the second metal conductor island 333 to the second intermediate metal conductor island 336 by a metal connection line 339.
- a metal connection line 40 connects the anode electrode 342 to the second intermediate metal conductor island 336.
- the leg of the sixth frame 334 disposed above the second metal conductor island 333 is connected to a place where the metal connection lines 339 and 340 are not present on the second intermediate metal conductor island 336.
- the metal connection lines 339 and 340 connecting the transistor chip 341 and the diode chip 342 on the first metal conductor island 331 and the first intermediate metal conductor island 335 are the first metal connection lines of the present invention.
- the metal connection lines 339 and 340 connecting the transistor chip 341 and the diode chip 342 and the second intermediate metal conductor island 336 on the second metal conductor island 333 are the metal second connection lines of the present invention.
- the fifth frame 332 is disposed so as to sandwich the insulator 1201 between the sixth frame 334 and the transistor chip 341 and the diode disposed on the first metal conductor island 331 and the second metal conductor island 333. It is desirable to configure so as to cover the chip 342.
- the insulator 1201 corresponds to an example of the second insulator of the present invention.
- the insulator 1201 between the fifth frame 332 and the sixth frame 334 is made of insulating resin or ceramic.
- the thickness of the insulator 1201 is appropriately set in the relationship between the withstand voltage and the electrical characteristics, as described in the third embodiment, and thus detailed description thereof is omitted. As described in Embodiment 3, the thickness of the insulator 1201 is set to 10 ⁇ m or more and 1 mm or less in order to exhibit the inductance reduction effect.
- the metal connection line 339 used to connect from the source electrode or emitter electrode of the transistor chip 341 on the first metal conductor island 331 to the first intermediate metal conductor island 335 is usually an Al wire. It consists of a plurality of cables and can handle large currents.
- the metal connection line 40 used to connect the anode electrode of the diode chip 342 to the first intermediate metal conductor island 335 is the same as described above.
- metal connection lines 339 and 340 used for connecting the transistor chip 341 and the diode chip 342 on the second metal conductor island 333 and the second intermediate metal conductor island 336 are the same as described above. .
- the extended portion of the first metal conductor island 331 has a function as an electrode and functions as a P (power source) terminal 327.
- the extended portion of the sixth frame 334 has a function as an electrode and is connected to an N terminal (ground terminal) 328.
- N ground terminal
- the fifth frame 332 and the second metal conductor island 333 are connected by a metal junction 351 disposed on the opposite side of the P terminal (power supply terminal) 327 and the N terminal (ground terminal) 328, and the second An extended portion of the metal conductor island 333 has a function as an electrode and functions as an O terminal (output terminal) 329.
- the first intermediate metal conductor island 335, the second intermediate metal conductor island 336, the fifth frame 332, and the sixth frame 334 are used in combination, so that the space on the semiconductor chip is wide and has a low inductance. Therefore, the power semiconductor module can be miniaturized, and the first metal conductor island 331 and the second metal conductor island 333 on which the semiconductor chip is mounted can be realized. Since the arrangement can be made close, it is possible to achieve further reduction in inductance.
- the size of the power semiconductor module can be greatly reduced. Accordingly, the wiring length is shortened and the inductance can be further reduced, so that the effect is great.
- a metal wire is connected between the high-side gate terminal 337 and the low-side gate terminal 326 and the gate pad of the corresponding transistor chip 341.
- a metal wire is connected between the high-side source terminal 338 and the low-side source terminal 325 and the source electrode of the corresponding transistor chip 341.
- Insulator 346 is arranged on heat sink 347 arranged on the lower surface side, and each frame is arranged thereon, and silicone gel 348 or the like is injected into case 349 defined by the outer frame for insulation. By securing, the power semiconductor module of the fourth embodiment is completed.
- the present invention is not limited to the example shown here, and the number and arrangement of the semiconductor chips are not particularly specified because they are determined by an arbitrary combination according to the current rating of the power semiconductor module.
- the minimum structural unit of the number of semiconductor chips is only one transistor chip, or one transistor chip and one diode chip. Even in such a configuration, inductance reduction is required to achieve high-speed operation of the device. Therefore, the effect of applying the configuration of the power semiconductor module of the fourth embodiment is great.
- the number of transistor chips and the number of diode chips need not be equal.
- connection can be realized by metal bonding between the frame and the frame instead of bonding between the semiconductor chip and the frame, it is possible to apply larger heat and vibration stress. Strong bonding can be realized.
- bonding between the semiconductor chip and the intermediate frame even if temperature distribution occurs between the semiconductor chips by using wiring for each semiconductor chip, if the reliability between each semiconductor chip and the frame can be secured individually, the overall reliability Can be improved. It has been found that such a configuration can solve the conventional problems described above.
- the configuration of the power semiconductor module of the present invention even if it is difficult to realize the strong bonding between the semiconductor chip and the bus bar, which is difficult, the wide positive bus bar and the negative electrode using the intermediate frame
- the closest configuration By adopting the closest configuration by overlapping the side bus bars in the space on the semiconductor chip, it becomes possible to significantly reduce the wiring inductance compared to the prior art. This makes it possible to provide a power semiconductor module that is robust against noise and has high reliability as a whole module.
- a foot of the third frame is connected to the first intermediate frame;
- the foot of the fourth frame is connected to the second intermediate frame;
- the legs of the third frame are disposed between the plurality of first connection lines,
- the legs of the fourth frame are arranged between the plurality of second connection lines.
- the fourth frame is disposed above the first frame and the second frame,
- the third frame is disposed above the fourth frame.
- the power terminal and the ground terminal are arranged on the same side of the power semiconductor module,
- the output terminal is disposed on a side surface of the power semiconductor module opposite to the power supply terminal and the ground terminal.
- a foot of the fifth frame is connected to the first intermediate metal conductor island;
- a foot of the sixth frame is connected to the second intermediate metal conductor island;
- the legs of the fifth frame are disposed between the plurality of first connection lines,
- the legs of the sixth frame are disposed between the plurality of second connection lines.
- the fifth frame is disposed above the sixth frame.
- the first connection line and the second connection line are constituted by ribbons.
- the first connection line and the second connection line are constituted by clips.
- the module size can be reduced, the wiring inductance can be reduced, and a power semiconductor module resistant to noise can be provided.
- the power semiconductor module according to the present invention has an effect of reducing the wiring inductance by reducing the module size, and is used when a higher power supply voltage, a higher current, a higher device speed, or the like is required. It is useful as a power semiconductor module.
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Abstract
Description
複数の第1トランジスタ及び第1ダイオードが配置された第1フレームと、
複数の第2トランジスタ及び第2ダイオードが配置された第2フレームと、
前記第1フレームに隣接する第1中間フレームと、
前記第2フレームに隣接する第2中間フレームと、
前記第1中間フレームに電気的に接続されて、前記第1フレームの上方に配置された第3フレームと、
前記第2中間フレームに電気的に接続されて、前記第2フレームの上方に配置された第4フレームと、
前記第1フレームの延長上に設けられた電源端子と、
前記第4フレームの延長上に設けられた接地端子と、
前記第2フレーム及び前記第3フレームが電気的に繋がれた延長上に設けられた出力端子とを備え、
前記第1トランジスタのドレイン電極は、前記第1フレームに接続され、
前記第1トランジスタのソース電極及び前記第1ダイオードのアノード電極は、前記第1中間フレームに金属の第1接続線で接続され、
前記第2トランジスタのドレイン電極は、前記第2フレームに接続され、
前記第2トランジスタのソース電極及び前記第2ダイオードのアノード電極は、前記第2中間フレームに金属の第2接続線で接続され、
前記第1トランジスタ及び前記第2トランジスタの近傍に、ゲート端子及びソース端子が配置され、
全ての前記フレームは、放熱板の上に、樹脂系材料で構成された絶縁体を介して配置され、全ての前記フレームの少なくとも一部が、モールド樹脂で覆われており、
前記第3フレーム及び前記第4フレームは、互いに平行に配置されており、前記第3フレーム及び前記第4フレームに発生する誘起電圧が互いに逆方向となるように、前記電源端子、前記接地端子及び前記出力端子が配置されていることを特徴とする電力用半導体モジュールである。
前記第1中間フレームに前記第3フレームの足が接続され、
前記第2中間フレームに前記第4フレームの足が接続され、
前記第3フレームの足は、複数の前記第1接続線の間に配置され、
前記第4フレームの足は、複数の前記第2接続線の間に配置されていることを特徴とする、第1の本発明の電力用半導体モジュールである。
前記第3フレームは、前記第1トランジスタ及び前記第1ダイオードの上方を覆うように配置されており、
前記第4フレームは、前記第2トランジスタ及び前記第2ダイオードの上方を覆うように配置されている、ことを特徴とする、第1の本発明の電力用半導体モジュールである。
前記第1トランジスタのゲート電極は、前記第1中間フレームとは反対の側に配置され、
前記第2トランジスタのゲート電極は、前記第2中間フレームとは反対の側に配置されていることを特徴とする、第1の本発明の電力用半導体モジュールである。
複数の第1トランジスタ及び第1ダイオードが配置された第1金属導電体島と、
複数の第2トランジスタ及び第2ダイオードが配置された第2金属導電体島と、
前記第1金属導電体島に隣接する第1中間金属導電体島と、
前記第2金属導電体島に隣接する第2中間金属導電体島と、
前記第1中間金属導電体島に電気的に接続されて、前記第1金属導電体島の上方に配置された第5フレームと、
前記第2中間金属導電体島に電気的に接続されて、前記第2金属導電体島の上方に配置された第6フレームと、
前記第1金属導電体島の延長上に設けられた電源端子と、
前記第6フレームの延長上に設けられた接地端子と、
前記第2金属導電体島及び前記第5フレームが電気的に繋がり、前記第2金属導電体島に接続された出力端子とを備え、
前記第1トランジスタのドレイン電極は、前記第1金属導電体島に接続され、
前記第1トランジスタのソース電極及び前記第1ダイオードのアノード電極は、前記第1中間金属導電体島に金属の第1接続線で接続され、
前記第2トランジスタのドレイン電極は、前記第2金属導電体島に接続され、
前記第2トランジスタのソース電極及び前記第2ダイオードのアノード電極は、前記第2中間金属導電体島に金属の第2接続線で接続され、
前記第1トランジスタ及び前記第2トランジスタの近傍に、ゲート端子及びソース端子が配置され、
全ての前記金属導電体島は、放熱板の上に、セラミック材料で構成された絶縁体を介して配置され、全ての前記金属導電体島の少なくとも一部が、ゲル状の樹脂で覆われており、
前記第5フレーム及び前記第6フレームは、互いに平行に配置されており、前記第5フレーム及び前記第6フレームに発生する誘起電圧が互いに逆方向となるように、前記電源端子、前記接地端子及び前記出力端子が配置されていることを特徴とする電力用半導体モジュールである。
前記第1中間金属導電体島に前記第5フレームの足が接続され、
前記第2中間金属導電体島に前記第6フレームの足が接続され、
前記第5フレームの足は、複数の前記第1接続線の間に配置され、
前記第6フレームの足は、複数の前記第2接続線の間に配置されていることを特徴とする、第5の本発明の電力用半導体モジュールである。
前記第5フレームは、前記第1トランジスタ及び前記第1ダイオードの上方を覆うように配置されており、
前記第6フレームは、前記第2トランジスタ及び前記第2ダイオードの上方を覆うように配置されている、ことを特徴とする、第5の本発明の電力用半導体モジュールである。
前記第1接続線及び前記第2接続線は、リボンで構成されていることを特徴とする、第1または第5の本発明の電力用半導体モジュールである。
前記第1接続線及び前記第2接続線は、クリップで構成されていることを特徴とする、第1または第5の本発明の電力用半導体モジュールである。
前記第1トランジスタのゲート電極は、前記第1中間金属導電体島とは反対の側に配置され、
前記第2トランジスタのゲート電極は、前記第2中間金属導電体島とは反対の側に配置されていることを特徴とする、第5の本発明の電力用半導体モジュールである。
本発明の実施の形態1の樹脂封止型の電力用半導体モジュールの平面図であるモジュール構成101を図1(a)に示す。
実施の形態1では、樹脂封止型のモジュールで本発明を説明してきたが、本発明のコンセプトは、これに限るものではなく、金属絶縁基板上に形成するモジュールに適用しても同様の効果が得られる。その他の形態でも、同様の効果が得られる。
本発明の実施の形態3の樹脂封止型の電力用半導体モジュールの平面図であるモジュール構成1101を図5(a)に示す。
設定されるのが適切である。1kVの耐電圧を確保する為には10μmの厚みが必要になる。実際には、これ以上の電界を印加しても即座に破壊ということにはならないが、300℃以上の高温環境で20年以上のライフを確保しようとすれば1MV/cm程度以下に
設定するのが好ましい。
実施の形態3では、樹脂封止型のモジュールで本発明を説明してきたが、本発明のコンセプトは、これに限るものではなく、金属絶縁基板上に形成するモジュールに適用しても同様の効果が得られる。その他の形態でも、同様の効果が得られる。
複数の第1トランジスタ及び第1ダイオードが配置された第1フレームと、
複数の第2トランジスタ及び第2ダイオードが配置された、前記第1フレームに隣接する第2フレームと、
前記第1フレーム及び前記第2フレームの外側に配置され、前記第1フレームに隣接する第1中間フレームと、
前記第1フレーム及び前記第2フレームの外側に配置され、前記第2フレームに隣接する第2中間フレームと、
前記第1中間フレームに電気的に接続されて、前記第1フレームの上方に配置された第3フレームと、
前記第2中間フレームに電気的に接続されて、前記第2フレームの上方に配置された第4フレームと、
前記第1フレームの延長上に設けられた電源端子と、
前記第4フレームの延長上に設けられた接地端子と、
前記第2フレーム及び前記第3フレームが電気的に繋がれた延長上に設けられた出力端子とを備え、
前記第1トランジスタのドレイン電極は、前記第1フレームに接続され、
前記第1トランジスタのソース電極及び前記第1ダイオードのアノード電極は、前記第1中間フレームに金属の第1接続線で接続され、
前記第2トランジスタのドレイン電極は、前記第2フレームに接続され、
前記第2トランジスタのソース電極及び前記第2ダイオードのアノード電極は、前記第2中間フレームに金属の第2接続線で接続され、
前記第1中間フレーム及び前記第2中間フレームの近傍に、ゲート端子及びソース端子が配置され、
全ての前記フレームは、放熱板の上に、樹脂系材料で構成された第1絶縁体を介して配置され、全ての前記フレームの少なくとも一部が、モールド樹脂で覆われており、
第2絶縁体が、前記第3フレーム及び前記第4フレームの間に挟まれており、前記第3フレーム及び前記第4フレームには、上下方向に互いに重なっている部分があり、
前記第3フレーム及び前記第4フレームを流れる各電流が互いに逆方向に流れるように構成されていることを特徴とする。
前記第1中間フレームに前記第3フレームの足が接続され、
前記第2中間フレームに前記第4フレームの足が接続され、
前記第3フレームの足は、複数の前記第1接続線の間に配置され、
前記第4フレームの足は、複数の前記第2接続線の間に配置されていることを特徴とする。
前記第4フレームは、前記第1フレーム及び前記第2フレームの上方に配置され、
前記第3フレームは、前記第4フレームの上方に配置されている。
前記電源端子及び前記接地端子は、前記電力用半導体モジュールの側面のうち同じ側面側に配置されており、
前記出力端子は、前記電力用半導体モジュールの側面のうち、前記電源端子及び前記接地端子とは反対側の側面側に配置されている。
複数の第1トランジスタ及び第1ダイオードが配置された第1金属導電体島と、
複数の第2トランジスタ及び第2ダイオードが配置された、前記第1金属導電体島に隣接する第2金属導電体島と、
前記第1金属導電体島及び前記第2金属導電体島の外側に配置され、前記第1金属導電体島に隣接する第1中間金属導電体島と、
前記第1金属導電体島及び前記第2金属導電体島の外側に配置され、前記第2金属導電体島に隣接する第2中間金属導電体島と、
前記第1中間金属導電体島に電気的に接続されて、前記第1金属導電体島の上方に配置された第5フレームと、
前記第2中間金属導電体島に電気的に接続されて、前記第2金属導電体島の上方に配置された第6フレームと、
前記第1金属導電体島の延長上に設けられた電源端子と、
前記第6フレームの延長上に設けられた接地端子と、
前記第2金属導電体島及び前記第5フレームが電気的に繋がり、前記第2金属導電体島に接続された出力端子とを備え、
前記第1トランジスタのドレイン電極は、前記第1金属導電体島に接続され、
前記第1トランジスタのソース電極及び前記第1ダイオードのアノード電極は、前記第1中間金属導電体島に金属の第1接続線で接続され、
前記第2トランジスタのドレイン電極は、前記第2金属導電体島に接続され、
前記第2トランジスタのソース電極及び前記第2ダイオードのアノード電極は、前記第2中間金属導電体島に金属の第2接続線で接続され、
前記第1中間金属導電体島及び前記第2中間金属導電体島の近傍に、ゲート端子及びソース端子が配置され、
全ての前記金属導電体島は、放熱板の上に、セラミック材料で構成された第1絶縁体を介して配置され、全ての前記金属導電体島の少なくとも一部が、ゲル状の樹脂で覆われており、
第2絶縁体が、前記第5フレーム及び前記第6フレームの間に挟まれており、前記第5フレーム及び前記第6フレームには、上下方向に互いに重なっている部分があり、
前記第5フレーム及び前記第6フレームを流れる各電流が互いに逆方向に流れるように構成されていることを特徴とする。
前記第1中間金属導電体島に前記第5フレームの足が接続され、
前記第2中間金属導電体島に前記第6フレームの足が接続され、
前記第5フレームの足は、複数の前記第1接続線の間に配置され、
前記第6フレームの足は、複数の前記第2接続線の間に配置されている。
前記第5フレームは、前記第6フレームの上方に配置されている。
前記第1接続線及び前記第2接続線は、リボンで構成されている。
前記第1接続線及び前記第2接続線は、クリップで構成されている。
2 第2フレーム
3 第3フレーム
4 第4フレーム
5 第1中間フレーム
6 第2中間フレーム
7 ハイサイド側ゲート端子
8 ハイサイド側ソース端子
9、10 金属の接続線
11 トランジスタチップ
12 ダイオードチップ
13 ゲートパッド
14 ゲート配線
15 ソース配線
16 絶縁体
17 放熱板
18 絶縁樹脂
19 絶縁樹脂の外枠
20 ローサイド側ソース端子
21 ローサイド側ゲート端子
22 電源端子部(P)
23 接地端子部(N)
24 出力端子部(O)
25 ローサイド側ソース端子
26 ローサイド側ゲート端子
27 電源端子(P)
28 接地端子(N)
29 出力端子(O)
31 第1金属導電体島
32 第5フレーム
33 第2金属導電体島
34 第6フレーム
35 第1中間金属導電体島
36 第2中間金属導電体島
37 ハイサイド側ゲート端子
38 ハイサイド側ソース端子
39、40 金属の接続線
41 トランジスタチップ
42 ダイオードチップ
43 接合点
44 接地端子(N)形成用島
46 絶縁体
47 放熱板
48 シリコーンゲル
49 ケース
50、51 接合点
62、63 接着層
71 バスバーの正極側内部電極
72 バスバーの負極側内部電極
73 ハイサイド側素子群
74 ローサイド側素子群
101 モジュール構成
102 モジュール断面構成
103 モジュール構成
104 モジュール断面構成
301 第1フレーム
302 第2フレーム
303 第3フレーム
304 第4フレーム
305 第1中間フレーム
306 第2中間フレーム
307 ハイサイド側ゲート端子
308 ハイサイド側ソース端子
309、310 金属の接続線
311 トランジスタチップ
312 ダイオードチップ
313 ゲートパッド
314 ゲート配線
315 ソース配線
316 絶縁体
317 放熱板
318 絶縁樹脂
319 絶縁樹脂の外枠
320 ローサイド側ソース端子
321 ローサイド側ゲート端子
322 電源端子部(P)
323 接地端子部(N)
324 出力端子部(O)
325 ローサイド側ソース端子
326 ローサイド側ゲート端子
327 電源端子(P)
328 接地端子(N)
329 出力端子(O)
331 第1金属導電体島
332 第5フレーム
333 第2金属導電体島
334 第6フレーム
335 第1中間金属導電体島
336 第2中間金属導電体島
337 ハイサイド側ゲート端子
338 ハイサイド側ソース端子
339、340 金属の接続線
341 トランジスタチップ
342 ダイオードチップ
343 接合点
344 接地端子(N)形成用島
346 絶縁体
347 放熱板
348 シリコーンゲル
349 ケース
350、351 接合点
362、363 接着層
1101 モジュール構成
1102 モジュール断面構成
1103 モジュール構成
1104 モジュール断面構成
1200、1201 絶縁体
Claims (10)
- 複数の第1トランジスタ及び第1ダイオードが配置された第1フレームと、
複数の第2トランジスタ及び第2ダイオードが配置された第2フレームと、
前記第1フレームに隣接する第1中間フレームと、
前記第2フレームに隣接する第2中間フレームと、
前記第1中間フレームに電気的に接続されて、前記第1フレームの上方に配置された第3フレームと、
前記第2中間フレームに電気的に接続されて、前記第2フレームの上方に配置された第4フレームと、
前記第1フレームの延長上に設けられた電源端子と、
前記第4フレームの延長上に設けられた接地端子と、
前記第2フレーム及び前記第3フレームが電気的に繋がれた延長上に設けられた出力端子とを備え、
前記第1トランジスタのドレイン電極は、前記第1フレームに接続され、
前記第1トランジスタのソース電極及び前記第1ダイオードのアノード電極は、前記第1中間フレームに金属の第1接続線で接続され、
前記第2トランジスタのドレイン電極は、前記第2フレームに接続され、
前記第2トランジスタのソース電極及び前記第2ダイオードのアノード電極は、前記第2中間フレームに金属の第2接続線で接続され、
前記第1トランジスタ及び前記第2トランジスタの近傍に、ゲート端子及びソース端子が配置され、
全ての前記フレームは、放熱板の上に、樹脂系材料で構成された絶縁体を介して配置され、全ての前記フレームの少なくとも一部が、モールド樹脂で覆われており、
前記第3フレーム及び前記第4フレームは、互いに平行に配置されており、前記第3フレーム及び前記第4フレームに発生する誘起電圧が互いに逆方向となるように、前記電源端子、前記接地端子及び前記出力端子が配置されていることを特徴とする電力用半導体モジュール。 - 前記第1中間フレームに前記第3フレームの足が接続され、
前記第2中間フレームに前記第4フレームの足が接続され、
前記第3フレームの足は、複数の前記第1接続線の間に配置され、
前記第4フレームの足は、複数の前記第2接続線の間に配置されていることを特徴とする、請求項1に記載の電力用半導体モジュール。 - 前記第3フレームは、前記第1トランジスタ及び前記第1ダイオードの上方を覆うように配置されており、
前記第4フレームは、前記第2トランジスタ及び前記第2ダイオードの上方を覆うように配置されている、ことを特徴とする、請求項1に記載の電力用半導体モジュール。 - 前記第1トランジスタのゲート電極は、前記第1中間フレームとは反対の側に配置され、
前記第2トランジスタのゲート電極は、前記第2中間フレームとは反対の側に配置されていることを特徴とする、請求項1に記載の電力用半導体モジュール。 - 複数の第1トランジスタ及び第1ダイオードが配置された第1金属導電体島と、
複数の第2トランジスタ及び第2ダイオードが配置された第2金属導電体島と、
前記第1金属導電体島に隣接する第1中間金属導電体島と、
前記第2金属導電体島に隣接する第2中間金属導電体島と、
前記第1中間金属導電体島に電気的に接続されて、前記第1金属導電体島の上方に配置された第5フレームと、
前記第2中間金属導電体島に電気的に接続されて、前記第2金属導電体島の上方に配置された第6フレームと、
前記第1金属導電体島の延長上に設けられた電源端子と、
前記第6フレームの延長上に設けられた接地端子と、
前記第2金属導電体島及び前記第5フレームが電気的に繋がり、前記第2金属導電体島に接続された出力端子とを備え、
前記第1トランジスタのドレイン電極は、前記第1金属導電体島に接続され、
前記第1トランジスタのソース電極及び前記第1ダイオードのアノード電極は、前記第1中間金属導電体島に金属の第1接続線で接続され、
前記第2トランジスタのドレイン電極は、前記第2金属導電体島に接続され、
前記第2トランジスタのソース電極及び前記第2ダイオードのアノード電極は、前記第2中間金属導電体島に金属の第2接続線で接続され、
前記第1トランジスタ及び前記第2トランジスタの近傍に、ゲート端子及びソース端子が配置され、
全ての前記金属導電体島は、放熱板の上に、セラミック材料で構成された絶縁体を介して配置され、全ての前記金属導電体島の少なくとも一部が、ゲル状の樹脂で覆われており、
前記第5フレーム及び前記第6フレームは、互いに平行に配置されており、前記第5フレーム及び前記第6フレームに発生する誘起電圧が互いに逆方向となるように、前記電源端子、前記接地端子及び前記出力端子が配置されていることを特徴とする電力用半導体モジュール。 - 前記第1中間金属導電体島に前記第5フレームの足が接続され、
前記第2中間金属導電体島に前記第6フレームの足が接続され、
前記第5フレームの足は、複数の前記第1接続線の間に配置され、
前記第6フレームの足は、複数の前記第2接続線の間に配置されていることを特徴とする、請求項5に記載の電力用半導体モジュール。 - 前記第5フレームは、前記第1トランジスタ及び前記第1ダイオードの上方を覆うように配置されており、
前記第6フレームは、前記第2トランジスタ及び前記第2ダイオードの上方を覆うように配置されている、ことを特徴とする、請求項5に記載の電力用半導体モジュール。 - 前記第1接続線及び前記第2接続線は、リボンで構成されていることを特徴とする、請求項1または5に記載の電力用半導体モジュール。
- 前記第1接続線及び前記第2接続線は、クリップで構成されていることを特徴とする、請求項1または5に記載の電力用半導体モジュール。
- 前記第1トランジスタのゲート電極は、前記第1中間金属導電体島とは反対の側に配置され、
前記第2トランジスタのゲート電極は、前記第2中間金属導電体島とは反対の側に配置されていることを特徴とする、請求項5に記載の電力用半導体モジュール。
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JP2014515487A JP5919511B2 (ja) | 2012-05-16 | 2013-05-07 | 電力用半導体モジュール |
EP13790413.2A EP2851950B1 (en) | 2012-05-16 | 2013-05-07 | Power semiconductor module |
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Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20150064991A (ko) * | 2013-12-04 | 2015-06-12 | 삼성전자주식회사 | 반도체소자 패키지 및 그 제조방법 |
WO2017169134A1 (ja) * | 2016-03-30 | 2017-10-05 | 三菱電機株式会社 | パワーモジュール及びその製造方法並びにパワーエレクトロニクス機器及びその製造方法 |
WO2018142863A1 (ja) * | 2017-02-06 | 2018-08-09 | 富士電機株式会社 | 半導体モジュール、電気自動車、及びパワーコントロールユニット |
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WO2021182569A1 (ja) * | 2020-03-12 | 2021-09-16 | 住友電気工業株式会社 | 半導体装置 |
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EP4064346A1 (en) | 2021-03-25 | 2022-09-28 | Hitachi Energy Switzerland AG | Power module comprising switch elements and diodes |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20150002219U (ko) * | 2013-12-03 | 2015-06-11 | 엘에스산전 주식회사 | 버스바 절연 결합 장치 어셈블리 |
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FR3082369B1 (fr) * | 2018-06-08 | 2021-02-19 | Valeo Equip Electr Moteur | Circuit electrique, bras de commutation et convertisseur de tension |
JP7359581B2 (ja) | 2019-07-10 | 2023-10-11 | 株式会社デンソー | 半導体装置 |
WO2021029150A1 (ja) * | 2019-08-13 | 2021-02-18 | 富士電機株式会社 | 半導体装置 |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004022960A (ja) | 2002-06-19 | 2004-01-22 | Mitsubishi Electric Corp | 電力用半導体装置 |
JP2005347561A (ja) * | 2004-06-03 | 2005-12-15 | Toshiba Corp | パワー半導体モジュールおよび電力変換装置 |
JP2007329427A (ja) * | 2006-06-09 | 2007-12-20 | Honda Motor Co Ltd | 半導体装置 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3312034B2 (ja) | 1991-05-24 | 2002-08-05 | 株式会社東芝 | 音量調整装置 |
JP2732767B2 (ja) * | 1992-12-22 | 1998-03-30 | 株式会社東芝 | 樹脂封止型半導体装置 |
JP4286465B2 (ja) * | 2001-02-09 | 2009-07-01 | 三菱電機株式会社 | 半導体装置とその製造方法 |
JP3629222B2 (ja) | 2001-06-14 | 2005-03-16 | 株式会社日立製作所 | 半導体装置 |
JP4046623B2 (ja) * | 2003-02-19 | 2008-02-13 | 三菱電機株式会社 | パワー半導体モジュールおよびその固定方法 |
JP2007220976A (ja) * | 2006-02-17 | 2007-08-30 | Toyota Motor Corp | 半導体モジュールおよびそれを備えるハイブリッド車両の駆動装置 |
EP2202792B1 (en) * | 2006-06-09 | 2016-11-23 | Honda Motor Co., Ltd. | Semiconductor device |
US7750447B2 (en) | 2007-06-11 | 2010-07-06 | Alpha & Omega Semiconductor, Ltd | High voltage and high power boost converter with co-packaged Schottky diode |
US9363894B2 (en) | 2010-09-24 | 2016-06-07 | Semiconductor Components Industries, Llc | Circuit device |
JP5947537B2 (ja) * | 2011-04-19 | 2016-07-06 | トヨタ自動車株式会社 | 半導体装置及びその製造方法 |
-
2013
- 2013-05-07 US US14/401,556 patent/US9520344B2/en active Active
- 2013-05-07 JP JP2014515487A patent/JP5919511B2/ja not_active Expired - Fee Related
- 2013-05-07 CN CN201380025535.8A patent/CN104303297B/zh not_active Expired - Fee Related
- 2013-05-07 WO PCT/JP2013/002941 patent/WO2013171996A1/ja active Application Filing
- 2013-05-07 EP EP13790413.2A patent/EP2851950B1/en not_active Not-in-force
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004022960A (ja) | 2002-06-19 | 2004-01-22 | Mitsubishi Electric Corp | 電力用半導体装置 |
JP2005347561A (ja) * | 2004-06-03 | 2005-12-15 | Toshiba Corp | パワー半導体モジュールおよび電力変換装置 |
JP2007329427A (ja) * | 2006-06-09 | 2007-12-20 | Honda Motor Co Ltd | 半導体装置 |
Non-Patent Citations (1)
Title |
---|
See also references of EP2851950A4 |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20150064991A (ko) * | 2013-12-04 | 2015-06-12 | 삼성전자주식회사 | 반도체소자 패키지 및 그 제조방법 |
KR102153041B1 (ko) | 2013-12-04 | 2020-09-07 | 삼성전자주식회사 | 반도체소자 패키지 및 그 제조방법 |
WO2017169134A1 (ja) * | 2016-03-30 | 2017-10-05 | 三菱電機株式会社 | パワーモジュール及びその製造方法並びにパワーエレクトロニクス機器及びその製造方法 |
JPWO2017169134A1 (ja) * | 2016-03-30 | 2018-12-06 | 三菱電機株式会社 | パワーモジュール及びその製造方法並びにパワーエレクトロニクス機器及びその製造方法 |
US10784214B2 (en) | 2017-02-06 | 2020-09-22 | Fuji Electric Co., Ltd. | Semiconductor module, electric automobile and power control unit |
WO2018142863A1 (ja) * | 2017-02-06 | 2018-08-09 | 富士電機株式会社 | 半導体モジュール、電気自動車、及びパワーコントロールユニット |
JPWO2018142863A1 (ja) * | 2017-02-06 | 2019-06-27 | 富士電機株式会社 | 半導体モジュール、電気自動車、及びパワーコントロールユニット |
JP2018137283A (ja) * | 2017-02-20 | 2018-08-30 | 株式会社東芝 | 半導体装置 |
WO2021182569A1 (ja) * | 2020-03-12 | 2021-09-16 | 住友電気工業株式会社 | 半導体装置 |
JP2021168319A (ja) * | 2020-03-12 | 2021-10-21 | 住友電気工業株式会社 | 半導体装置 |
WO2022059250A1 (ja) * | 2020-09-18 | 2022-03-24 | 住友電気工業株式会社 | 半導体装置 |
EP4064346A1 (en) | 2021-03-25 | 2022-09-28 | Hitachi Energy Switzerland AG | Power module comprising switch elements and diodes |
WO2022200512A1 (en) | 2021-03-25 | 2022-09-29 | Hitachi Energy Switzerland Ag | Power semiconductor module comprising switch elements and diodes |
Also Published As
Publication number | Publication date |
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US9520344B2 (en) | 2016-12-13 |
EP2851950A4 (en) | 2015-07-15 |
CN104303297A (zh) | 2015-01-21 |
EP2851950A1 (en) | 2015-03-25 |
CN104303297B (zh) | 2017-05-17 |
JPWO2013171996A1 (ja) | 2016-01-12 |
US20150115423A1 (en) | 2015-04-30 |
JP5919511B2 (ja) | 2016-05-18 |
EP2851950B1 (en) | 2019-02-06 |
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