WO2013099189A1 - Appareil d'affichage - Google Patents

Appareil d'affichage Download PDF

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Publication number
WO2013099189A1
WO2013099189A1 PCT/JP2012/008203 JP2012008203W WO2013099189A1 WO 2013099189 A1 WO2013099189 A1 WO 2013099189A1 JP 2012008203 W JP2012008203 W JP 2012008203W WO 2013099189 A1 WO2013099189 A1 WO 2013099189A1
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WO
WIPO (PCT)
Prior art keywords
wiring
gate
lead
display
source
Prior art date
Application number
PCT/JP2012/008203
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English (en)
Japanese (ja)
Inventor
慎司 貞光
孝司 上野
Original Assignee
シャープ株式会社
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Publication of WO2013099189A1 publication Critical patent/WO2013099189A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13456—Cell terminals located on one side of the display only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0285—Improving the quality of display appearance using tables for spatial correction of display data

Definitions

  • the present invention relates to a display device that performs image display.
  • a display device that performs image display.
  • display quality due to variation in effective voltage applied by pixel electrodes between pixels, which is the minimum unit of an image. This is related to measures for lowering
  • red (R), green (G), and blue (B) pixels constituting each pixel are arranged in a scanning direction, so-called triple.
  • a technique for driving by a scanning method is known.
  • the number of gate wirings formed in the display region is three times that of normal driving, and correspondingly, each gate wiring is framed around the display region.
  • the number of gate lead-out lines for leading over the area (non-display area) and leading to the signal input terminal area provided on one end side thereof also increases.
  • Patent Document 1 discloses that a plurality of gate lead-out lines are formed using a metal film for forming a gate line and a metal film for forming a source line, and adjacent gate lead-out lines are gate lines and source lines.
  • a two-layer wiring structure formed so as to be positioned above and below an insulating film interposed therebetween is disclosed. That is, this two-layer wiring structure has a lower lead wiring formed from a metal film for forming a gate wiring and an upper lead wiring formed from a metal film for forming a source wiring as the gate lead wiring. Lead wires are arranged alternately.
  • the present invention has been made in view of such a point, and an object of the present invention is to realize a pixel driven through the same kind of lead wiring formed in different layers while realizing a narrow frame structure. It is to improve display quality by suppressing variations in effective voltage applied by the pixel electrodes.
  • the signal voltage supplied to the source lead wiring is corrected in consideration of the difference in stray capacitance between the pixel electrode in the lower lead wiring and the upper lead wiring. I made it.
  • the present invention is directed to an active matrix drive type display device, and has the following solutions.
  • the first invention is the above display device, A base substrate; A display area provided on the base substrate; A frame area provided around the display area; A plurality of gate lines provided in the display area so as to extend in parallel to each other; A plurality of source lines provided in the display region so as to extend in parallel with each other in a direction intersecting with the gate lines; An insulating film that is interposed between each of the gate wirings and the source wirings and insulates the wirings; A thin film transistor (TFT) provided at each intersection of each gate line and each source line and connected to the corresponding gate line and source line and a pixel connected to the TFT.
  • TFT thin film transistor
  • Electrodes A plurality of gate lead wires connected to the gate wires and drawn on the frame region from the display region side to one end side of the frame region; A plurality of source lead lines connected to the source lines and drawn on the frame area from the display area side to one end side of the frame area; A drive circuit that is electrically connected to the leading end of each of the gate lead-out wiring and the source lead-out wiring and that receives a display signal including a display data signal corresponding to an image to be displayed from an external circuit;
  • the display area is configured by providing a plurality of pixels having the TFT and the pixel electrode in a predetermined arrangement, At least one of the plurality of gate lead wires and the plurality of source lead wires includes a lower lead wire covered with the insulating film, and an upper lead wire provided on the insulating film, A memory unit for storing luminance correction data for suppressing or eliminating a luminance difference in display based on the same display data signal between a pixel driven by the lower layer lead line and a pixel driven by the upper layer
  • At least one of the plurality of gate lead-out lines and the plurality of source lead-out lines that lead the display wiring (each gate lead-out wiring or each source lead-out wiring) to one end side of the frame region is formed of the insulating film.
  • a two-layer wiring structure including a covered lower lead wiring and an upper lead wiring provided on the insulating film is provided. According to this two-layer wiring structure, it is possible to narrow the pitch between the lead-out wirings at the location where the lower-layer lead-out wiring and the upper-layer lead-out wiring are adjacent to each other, thereby narrowing the width of the frame region.
  • a memory unit for storing luminance correction data for suppressing or eliminating a luminance difference in display based on the same display data between the pixels driven by the lower layer lead lines and the pixels driven by the upper layer lead lines. Since the drive circuit corrects the level of the signal voltage supplied to each source lead-out line based on the brightness correction data stored in the memory unit, the lower layer is caused by being formed from a separate conductive film.
  • a second invention is the display device of the first invention, wherein The plurality of pixels are pixels of a plurality of colors arranged periodically,
  • the memory unit stores the luminance correction data for each color of the pixel.
  • the effect of the present invention is concretely exerted, and a narrow frame structure is realized, but applied by the pixel electrodes between the pixels. It is possible to improve display quality by suppressing variations in effective voltage.
  • a third invention is the display device of the second invention, wherein The plurality of pixels are arranged in a matrix so that pixels of the same color are aligned in the row direction and pixels of different colors are aligned in the column direction, Each of the gate wirings is connected to a TFT included in each pixel of the same color aligned in the row direction, Each of the source wirings is connected to a TFT included in each pixel of different colors aligned in the column direction.
  • each gate wiring is connected to a TFT of the same color pixel and driven in a triple scan mode.
  • the total number of gate wirings and source wirings is reduced, and the number of gate driver circuits having a relatively simple circuit configuration is increased, while the number of source driver circuits having a complicated circuit configuration compared to the gate driver circuit.
  • COG Chip On Glass
  • a driver IC (Integrated Circuit) chip can be integrated into one chip, and the manufacturing cost can be reduced.
  • a fourth invention is the display device according to any one of the first to third inventions,
  • the memory unit stores the luminance correction data for a display data signal input from the outside to the driving circuit,
  • the drive circuit includes a luminance correction circuit that corrects the display data signal based on luminance correction data stored in the memory unit.
  • a fifth invention is the display device according to any one of the first to third inventions,
  • the drive circuit has a gradation voltage generation circuit for generating gradation voltages of a plurality of levels used when digitally converting a display data signal input from the outside,
  • the memory unit stores the luminance correction data for the gradation voltage generated by the gradation voltage generation circuit,
  • the gradation voltage generation circuit adjusts the gradation voltage based on luminance correction data stored in the memory unit.
  • a sixth invention is the display device according to any one of the first to fifth inventions,
  • the lower layer lead wires and the upper layer lead wires are arranged alternately without overlapping each other in plan view.
  • the lower wiring layer and the upper wiring layer are alternately arranged in plan view.
  • the lower layer lead wiring and the upper layer lead wiring are arranged so as to overlap each other. An increase in power consumption due to a decrease in display quality due to signal delay and an increase in impedance can be suppressed.
  • a seventh invention is the display device according to any one of the first to sixth inventions, A TFT substrate having a base substrate provided with each gate wiring, each source wiring, insulating film, each TFT, each gate lead wiring and each source lead wiring; A counter substrate disposed to face the TFT substrate; And a liquid crystal layer provided between the TFT substrate and the counter substrate.
  • the display device according to the present invention is a liquid crystal display device, and in the liquid crystal display device, the variation in effective voltage applied by the pixel electrode between the pixels is achieved while realizing a narrow frame structure. It is possible to suppress and improve the display quality.
  • the luminance correction data has a two-layer wiring structure, and suppresses or eliminates the luminance difference between the pixel driven by the lower lead wiring and the pixel driven by the upper lead wiring in the structure. And the level of the signal voltage that the drive circuit supplies to each source lead-out line based on the luminance correction data stored in the memory unit, so that a narrow frame structure can be realized. In addition, it is possible to improve display quality by suppressing variations in effective voltage applied by the pixel electrode between pixels driven through the same kind of lead wiring formed in different layers.
  • FIG. 1 is a plan view schematically showing the configuration of the liquid crystal display device according to the first embodiment.
  • 2 is a cross-sectional view showing a cross-sectional structure taken along the line II-II in FIG.
  • FIG. 3 is a plan view showing a partially enlarged display area in the first embodiment.
  • FIG. 4 is a plan view showing a lead-out configuration of the display wiring of the TFT substrate in the first embodiment.
  • FIG. 5 is an equivalent circuit diagram illustrating a configuration of one pixel in the first embodiment.
  • FIG. 6 is a cross-sectional view showing a cross-sectional structure of the TFT.
  • FIG. 7 is a plan view showing a partially enlarged configuration of the TFT substrate in the first embodiment.
  • FIG. 8 is a cross-sectional view showing a cross-sectional structure taken along line VIII-VIII in FIG.
  • FIG. 9 is a cross-sectional view showing a connection structure between the gate wiring and the upper lead wiring.
  • FIG. 10 is a plan view schematically showing a connection relationship between each pixel and the gate lead wiring for driving them in the first embodiment.
  • FIG. 11 is a block diagram schematically showing the configuration of the driver IC chip in the first embodiment.
  • FIG. 12 is a block diagram illustrating a configuration of a unit driver IC that constitutes the source driver according to the first embodiment.
  • FIG. 13 is a block diagram illustrating a configuration of a luminance correction circuit included in the unit driver IC according to the first embodiment.
  • FIG. 14 is a conceptual diagram schematically showing a look-up table (LUT) included in the memory unit according to the first embodiment.
  • FIG. 15 is a block diagram illustrating a configuration of a unit driver IC that constitutes a source driver according to the second embodiment.
  • FIG. 16 is a circuit diagram illustrating a configuration of a grayscale voltage generation circuit according to the second embodiment.
  • FIG. 17 is a conceptual diagram schematically illustrating a lookup table (LUT) included in the memory unit according to the second embodiment.
  • FIG. 18 is a plan view showing a configuration for routing display wiring on a TFT substrate in another embodiment.
  • Embodiment 1 of the Invention an active matrix liquid crystal display device S that performs full color display will be described as an example of the display device according to the present invention.
  • FIG. 1 shows a schematic configuration of the liquid crystal display device S of the present embodiment.
  • 2 is a cross-sectional view showing a cross-sectional structure taken along the line II-II in FIG.
  • the liquid crystal display device S includes a liquid crystal display panel 10, a driver IC chip 50 for driving the liquid crystal display panel, and a wiring substrate 100 with respect to the driver IC chip 50.
  • a controller 80 which is an external circuit that supplies a display signal including a display data signal DS corresponding to an image to be displayed, and a liquid crystal driving power supply 90 are provided, and a driving circuit is provided on one end side of the liquid crystal display panel S.
  • the driver IC chip 50 has a COG structure that is mounted as a single chip.
  • the liquid crystal display panel 10 is a display element that generates a display image by selectively applying a voltage from the liquid crystal driving power source 90 by driving the driver IC chip 50 in response to an output from the controller 80. Scanning driving is possible.
  • the liquid crystal display panel 10 includes a TFT substrate 11 and a counter substrate 12 that are arranged so as to face each other, a frame-shaped sealing material 13 that bonds the outer peripheral edges of the substrates 11 and 12, and the TFT substrate 11 A liquid crystal layer 14 surrounded and sealed by a sealing material 13 is provided between the counter substrate 12 and the counter substrate 12.
  • the liquid crystal display panel 10 has a display area D for displaying an image in an area where the TFT substrate 11 and the counter substrate 12 overlap and inside the sealing material 13, that is, an area where the liquid crystal layer 14 is provided. Further, the liquid crystal display panel 10 has a frame region F which is a non-display region around the display region D. Then, on one side of the frame region F (lower side in FIG. 1, left side in FIG. 2), the TFT substrate 11 protrudes from the counter substrate 12 and the surface of the counter substrate 12 side is exposed to the outside. 11a is provided.
  • the driver IC chip 50 is mounted near the display area D in the terminal area 11a.
  • the wiring board 100 is mounted on the outer side of the driver IC chip 50 in the terminal region 11a.
  • the driver IC chip 50 and the wiring substrate 100 are connected to the terminal region 11a via a connecting material such as ACF (Anisotropic Conductive Film).
  • the TFT substrate 11 and the counter substrate 12 are formed, for example, in a rectangular shape, and as shown in FIG. 2, alignment films 15 and 16 for controlling the alignment of liquid crystal molecules are provided on the inner surfaces facing each other, and the outer surface. Are respectively provided with polarizing plates 17 and 18.
  • the polarizing plate 17 on the TFT substrate 11 and the polarizing plate 18 on the counter substrate 12 have different light transmission axes by 90 °.
  • the liquid crystal layer 14 is made of a nematic liquid crystal material having electro-optical characteristics.
  • FIG. 3 shows an enlarged plan view of a part of the display area D.
  • the display area D includes a plurality of pixel units P arranged in a matrix.
  • Each of these pixel units P is composed of pixels p1 of three colors of red (R), green (G), and blue (B).
  • the pixels p1 (R), p1 (G), and p1 (B) of these three colors are arranged in parallel in a striped manner in a juxtaposed manner along the scanning direction (Y-axis direction) in the same order in all the pixel units P. .
  • pixels p1 of the same color are aligned in the horizontal direction (X-axis direction) in FIG. 3 to form a pixel row PL for each color, and three colors in the vertical direction (Y-axis direction) in FIG.
  • a plurality of pixel rows PL are periodically arranged, and a plurality of pixel unit rows UL are configured with a set of three color pixel rows PL.
  • pixel units P are arranged in the vertical direction (Y-axis direction) in FIG. 3 to form a pixel unit row UC.
  • the pixel unit rows are arranged in the horizontal direction (X-axis direction).
  • a plurality of UCs are lined up.
  • FIG. 4 is a plan view showing a lead-out configuration of the display wirings 21 and 23 on the TFT substrate 11.
  • FIG. 5 is an equivalent circuit diagram showing the configuration of one pixel p1.
  • FIG. 6 is a cross-sectional view showing a cross-sectional structure of the TFT 24.
  • FIG. 7 is an enlarged plan view showing a two-layer wiring structure portion of the TFT substrate 11.
  • 8 is a cross-sectional view showing a cross-sectional structure taken along line VIII-VIII in FIG.
  • FIG. 9 is a cross-sectional view showing a connection structure between the gate wiring 21 and the upper layer extraction wiring 31B.
  • the TFT substrate 11 includes an insulating substrate 20 such as a glass substrate as a base substrate, as shown in FIG.
  • an insulating substrate 20 such as a glass substrate as a base substrate, as shown in FIG.
  • a plurality of gate wirings 21 are provided so as to extend in parallel to each other in the row direction (lateral direction in FIG. 4; X-axis direction).
  • Each of these gate wirings 21 is covered with a gate insulating film 22 described later.
  • a plurality of source lines 23 are provided on the gate insulating film 22 in the display region D so as to extend in parallel to each other in a column direction (vertical direction in FIG. 4; Y-axis direction) orthogonal to each gate line 21. ing.
  • Each gate wiring 21 and each source wiring 23 are insulated by interposing a gate insulating film 22 between these wirings 21 and 23.
  • the gate wiring 21 and the source wiring 23 are formed in a lattice shape so as to partition each pixel p1 as a whole.
  • Each pixel p1 is provided with a TFT 24 and a pixel electrode 30 connected thereto as shown in FIG.
  • the TFT 24 is provided at each intersection of each gate line 21 and each source line 23 and is connected to the corresponding gate line 21 and source line 23 that form the intersection.
  • the TFT 24 is a bottom gate type (also referred to as an inverted staggered type) TFT, and is provided so as to cover the gate electrode 25 provided on the insulating substrate 20 and the gate electrode 25.
  • the gate electrode 25 is connected to the gate wiring 21.
  • the source electrode 27 is connected to the source wiring 23.
  • the pixel electrode 30 is provided on the interlayer insulating film 29 and is connected to the drain electrode 28 through a contact hole formed in the interlayer insulating film 29 (not shown).
  • a stray capacitance C ′ shown in FIG. 5 is formed between the corresponding pixel electrode 30 and the gate wiring 21.
  • the TFTs 24 are connected to the same gate wiring 21 separately for each pixel row PL. Each TFT 24 is connected to the same source wiring 23 separately for each pixel unit UC column.
  • a plurality of gate lead wires 31 connected to the gate wires 21 and drawn from the display region D side to the terminal region 11a side.
  • a plurality of source lead lines 35 connected to the respective source lines 23 and led from the display area D side to the terminal area 11a side.
  • Chip connection terminals (not shown) for connection to the driver IC chip 50 are formed along the edge of the TFT substrate 1 at the leading ends of the gate lead lines 31 and the source lead lines 35. Yes.
  • the plurality of gate lead-out lines 31 are alternately drawn out to one side and the other side of the display area D to constitute a double-side lead-out wiring structure.
  • Each gate lead-out line 31 connected to the odd-numbered gate lines 21 from the upper side of the display area D is drawn from one side (left side in FIG. 4) of the display area D to form a first wiring group 32.
  • each gate lead-out line 31 connected to the even-numbered gate lines 21 from the upper side of the display area D is drawn out from the other side (right side in FIG. 4) of the display area D to form the second wiring group 33.
  • the display region D can be formed without increasing the size of the TFT substrate 1 as compared with the case of adopting the single-side lead-out wiring structure in which all the gate lead wires 31 are drawn from only one side of the display region D.
  • the substrate 1 can be arranged at the center position of the outer shape.
  • the first wiring group 32 and the second wiring group 33 are composed of the same number of groups of gate lead-out wirings 31, the widths of both frame regions B where the wiring groups 32 and 33 are provided are balanced. It can be narrowed well.
  • the first wiring group 32 and the second wiring group 33 include a lower layer wiring 31 ⁇ / b> A covered with the gate insulating film 22 and an upper layer wiring provided on the gate insulating film 22. 31B.
  • the lower layer lead wiring 31A and the upper layer lead wiring 31B are three-dimensionally arranged via the gate insulating film 22 to form a two-layer wiring structure.
  • the lower layer lead wiring 31A and the upper layer lead wiring 31B are alternately arranged without overlapping each other in a plan view to constitute an alternate wiring structure.
  • this alternate wiring structure compared to the case where the lower layer wiring 31A and the upper layer wiring 31B are arranged so as to overlap each other, the adverse effect of the capacitance formed between the both wirings 31A and 31B, specifically, Can suppress a decrease in display quality due to signal delay and an increase in power consumption due to an increase in impedance.
  • the lower lead wiring 31 ⁇ / b> A is formed of the same metal film as the gate wiring 21 and is provided integrally with the gate wiring 21.
  • the upper lead line 31B is formed of the same metal film as the source line 23 and is connected to one end of the gate line 21 through a contact hole 22a formed in the gate insulating film 22, as shown in FIG. Has been.
  • the upper lead line 31B is covered with an interlayer insulating film 29.
  • FIG. 10 shows a schematic plan view of the connection relationship between the pixels p1 of the respective colors and the gate lead-out wiring 31 that drives them in the present embodiment.
  • “GL” is placed on the lead-out side of the gate lead-out line 31 of the pixel row PL including the pixel p1 having the TFT 24 to which the lower-layer lead line 31A is electrically connected, and the upper-layer lead line 31B is electrically connected.
  • “SL” is attached to the lead-out side of the gate lead-out wiring 31 of the pixel row PL including the pixel p1 having the TFT 24 connected thereto.
  • a pixel row PL composed of pixels p1 of the same color.
  • the lower layer lead wiring 31A is connected and a case where the upper layer lead wire 31B is connected.
  • the stray capacitance C ′ formed between the lower layer lead line 31 ⁇ / b> A and the upper layer lead line 31 ⁇ / b> B via the gate line 21 and the pixel electrode 30.
  • the counter substrate 12 includes a black matrix provided in a lattice shape so as to correspond to the gate wiring 21 and the source wiring 23 on an insulating substrate such as a glass substrate as a base substrate, and a lattice of the black matrix.
  • a plurality of color filters composed of a red layer, a green layer, and a blue layer that are periodically arranged corresponding to the pixels p1 (R), p1 (G), and p1 (B) of each color in between, the black matrix,
  • a common electrode 19 is provided so as to cover the color filter and is opposed to the group of pixel electrodes 30, and a photo spacer is provided on the common electrode 19 in a columnar shape.
  • the driver IC chip 50 supplies a source signal to the gate driver 51 that drives each gate line 21 via each gate lead line 31 and each source line 23 via each source lead line 35.
  • a memory unit 65 made of a nonvolatile memory such as an EEPROM (Electrically Erasable Programmable Read-Only Memory).
  • the gate driver 51 has a known configuration in which a plurality of unit driver ICs each having a shift register circuit, a level shifter circuit, and an output circuit are cascade-connected, and one gate wiring 21 is selected from all the gate wirings 21. Are sequentially selected, a selection voltage (for example, a high level voltage) is applied to the selected gate wiring 21, and a non-selection voltage (for example, a low level voltage) is applied to the other gate wirings 21. It is configured. Thereby, the gate driver 51 makes each TFT 24 connected to the selected gate wiring 21 conductive, and makes the pixel electrode 30 connected to each TFT 24 in the conductive state ready for potential writing. .
  • a selection voltage for example, a high level voltage
  • a non-selection voltage for example, a low level voltage
  • the source driver 52 has a configuration in which a plurality of unit driver ICs 53 to be described later are cascade-connected.
  • the source driver 52 is configured to perform dot inversion driving of the display region D, and one source wiring 23 for each source wiring 23.
  • the voltage polarity (positive voltage / negative voltage) is switched every time and the voltage polarity (positive voltage / negative voltage) is inverted for each pixel unit row UL to apply a signal voltage corresponding to the display data signal DS.
  • the source driver 52 writes a potential corresponding to the display data signal DS to each pixel electrode 30 in a potential writable state.
  • the controller 80 outputs a gate pulse signal GSP, a gate clock signal GCLK, and a gate ON signal as a control signal S1 for controlling the driving of the driver 51 to the gate driver 51.
  • the gate clock signal GCLK and the gate ON signal are input to each unit driver IC constituting the gate driver 51, but the gate start pulse signal GSP is one of the gate driver ICs (for example, a unit located at one end). It is input only to the driver IC).
  • the controller 80 controls each source driver 52 as a control signal S2 for controlling the driver 52, such as a source start pulse signal SSP, a source clock signal SCLK, a horizontal synchronization signal (latch signal) LS, and a polarity inversion signal. and REV, as digitized display data DS, red, green, and blue pixels p1 (R), p1 (G ), each signal inputted to p1 (B) D R, D G, and D B Output.
  • the source clock signal SCLK, the horizontal synchronization signal LS, the display data signal DS, and the polarity inversion signal REV are input to each unit driver IC 53 constituting the source driver 52, but the source start pulse signal SSP is any one of them. It is input only to the unit driver IC 53 (for example, the unit driver IC 53 located at one end).
  • the liquid crystal driving power supply 90 supplies an analog voltage for causing the gate driver 51 and the source driver 52 to display an image on the liquid crystal display panel 10, for example, a reference voltage VR for causing the source driver 52 to generate a gradation voltage. It is a circuit to supply.
  • FIG. 12 is a block diagram showing the configuration of the unit driver IC 53 that constitutes the source driver 52 of the present embodiment.
  • Each unit driver IC 53 constituting the source driver 52 includes a shift register circuit 54, a data latch circuit 55, a sampling memory circuit 56, a hold memory circuit 57, a level shifter circuit 58, a gradation voltage generation circuit 59, a digital analog (Digital-Analog).
  • a conversion circuit (DA conversion circuit) 60 and an output circuit 61 are provided.
  • the shift register circuit 54 is an n-stage shift register, and sequentially shifts the source start pulse signal SPP in synchronization with the source clock signal SCLK input from the controller 80, and a pulse signal based on the source start pulse signal SPP is transmitted from each stage. It is a circuit that outputs to the sampling memory circuit 56 in order. The output signal of the shift register circuit 54 determines the sampling position of the display data signal DS (D R , D G , D B ).
  • the source start pulse signal SSP is a signal synchronized with the horizontal synchronization signal LS, and after being shifted to the final stage in the shift register circuit 54, the source start pulse signal SSP is supplied to the shift register circuit 54 in the adjacent unit driver IC 53. It is input as a pulse signal SSP and similarly shifted. Then, the data is transferred to the shift register circuit 54 in the outermost unit driver IC 53.
  • Data latch circuit 55 s bits (e.g. D R, D G, D B total of 18 bits of each 6-bit) input to the serial display data signal DS (D R, D G, D B) of the source clock signal
  • bits e.g. D R, D G, D B total of 18 bits of each 6-bit
  • This is a circuit that temporarily latches in accordance with SCLK and outputs the latched display data signals DS (D R , D G , D B ) to the sampling memory circuit 56.
  • the sampling memory circuit 56 is an s-bit display data signal DS (D R , D G) sent in a time-sharing manner from the data latch circuit 55 to a position specified by an output signal from each stage of the shift register circuit 54. , D B ), and stores each display data signal DS until n display data signals DS (D R , D G , D B ) for one horizontal synchronization period are obtained.
  • the hold memory circuit 57 collectively holds the n display data signals DS (D R , D G , D B ) stored in the sampling memory circuit 56 based on the horizontal synchronization signal LS, that is, at the rising edge of the latch pulse. Circuit.
  • the level shifter circuit 58 is adapted to a DA conversion circuit that processes the voltage level applied to the source line 23, and the n display data signals DS (D R , D G , D B ) stored in the hold memory circuit 57 are used. This circuit converts the signal level by boosting or the like.
  • the gradation voltage generation circuit 59 includes a resistance dividing circuit, and uses this to generate a ⁇ -corrected gradation voltage of 2 S level (for example, 64 levels) based on the reference voltage VR input from the liquid crystal driving power supply 90. It is a circuit that generates and outputs to the DA converter circuit 60.
  • the DA conversion circuit 60 uses the 2 S level gradation generated by the gradation voltage generation circuit 59 for each of the n display data signals DS (D R , D G , D B ) input from the level shifter circuit 58. In this circuit, one gradation voltage is selected from the voltages, and the selected gradation voltage is converted into an analog signal by switching the voltage polarity according to the polarity inversion signal REV, and then output to the output circuit 61.
  • the output circuit 61 includes n voltage followers composed of, for example, an operational amplifier and an output buffer.
  • the output circuit 61 amplifies an analog signal input from the DA converter circuit 60 using the voltage follower and converts the amplified analog signal into a low impedance output to generate a source signal. Is output to each source line 23.
  • each unit driver IC 53 constituting the source driver 52 in the present embodiment includes a luminance correction circuit 70 in addition to the various circuits 54, 55, 56, 57, 58, 59, 60, 61 described above.
  • the luminance correction circuit 70 is provided between the controller 80 and the data latch circuit 55, based on the luminance correction data stored in the memory unit 65, the display of s bits input from the controller 80 the data signal DS (D R , D G , D B ) is a circuit for correcting the signal level so as to compensate for the difference in the stray capacitance C ′ between the pixel electrode 30 in the lower layer extraction wiring 31A and the upper layer extraction wiring 31B.
  • FIG. 14 shows a conceptual diagram of a data structure that the memory unit 65 has.
  • “**” is predetermined brightness correction data. The same applies to FIG. 17 referred later.
  • the memory unit 65 has a lookup table (LUT) shown in FIG.
  • the look-up table (LUT) includes predetermined luminance correction data (*) for correcting the signal level of the display data signal DS (D R , D G , D B ) input from the controller 80 to the data latch circuit 55. *) Is stored.
  • the lookup table (LUT) since the double-sided lead wiring structure is adopted, the lookup table (LUT) includes an upper layer lead wiring 31B (4k + third gate lead wiring 31, where k is a natural number including 0) in the first wiring group 32. ) And lower layer lead wire 31A (4k + 1 gate lead wire 31), upper layer lead wire 31B (4k + fourth gate lead wire 31) and lower layer lead wire 31A (4k + second gate lead wire 31) of the second wiring group 33.
  • the luminance correction data for the four patterns are stored. This luminance correction data is data for suppressing or eliminating a luminance difference in display based on the same display data signal DS, and displays 0 (00000000) to 255 (11111111) for each color of each pixel p1.
  • Data signals DS (D R , D G , D B ) are prepared.
  • the brightness correction data stored in the lookup table (LUT) drives the liquid crystal display panel 10 from the minimum drive (0; 00000000) to the maximum drive (255; 11111111) for each single color display. It is calculated from the luminance difference between the four patterns.
  • the configuration of the luminance correction circuit 70 is shown in FIG.
  • the luminance correction circuit 70 includes an LUT register 71 and a correction unit 72.
  • the LUT register 71 reads necessary brightness correction data from the look-up table (LUT) of the memory unit 65 and temporarily stores it.
  • the correction unit 72 corrects the signal level of the display data signal DS (D R , D G , D B ) based on the luminance correction data stored in the LUT register 71, and the corrected display data signal DS (D R , D G , D B ) are output to the data latch circuit 55.
  • the display data signal DS (D R , D G , D B ) input to the data latch circuit 55 is corrected, and as a result, the signal voltage supplied to each source lead wiring 35 Level is corrected.
  • the line width and the film thickness of the lower layer lead wiring 31A and the upper layer lead wiring 31B become non-uniform due to the fact that they are formed from separate metal films, and the gate wiring between these two lead wirings 31A and 31B.
  • the stray capacitance C ′ formed between the pixel electrode 30 and the pixel electrode 30, the difference in the stray capacitance C ′ is compensated by the corrected signal voltage supplied to the source wiring 23.
  • Variations in the effective voltage applied to the liquid crystal layer 14 by the pixel electrode 30 can be suppressed between the pixel p1 driven by the lower lead line 31A and the pixel p1 driven by the upper lead line 31B.
  • a two-layer wiring structure is provided, and in this structure, the luminance difference between the pixel p1 driven by the lower lead line 31A and the pixel p1 driven by the upper lead line 31B is suppressed or eliminated.
  • luminance correction data comprises a memory unit 65 for storing, based on the stored luminance correction data in the memory unit 65, the display data signals DS (D R the luminance correction circuit 70 is inputted to the data latch circuit 55 for , D G , D B ) are corrected so as to compensate for the difference in the stray capacitance C ′ between the pixel electrode 30 in the lower-layer lead-out wiring 31A and the upper-layer lead-out wiring 31B, so that a narrow frame structure is realized.
  • the effective voltage applied to the liquid crystal layer 14 by the pixel electrode 30 between the pixels p1 driven through the lower lead wire 31A and the upper lead wire 31B formed in different layers. The flicker can be suppressed and the display quality can be improved.
  • the upper layer lead wiring 31B (4k + third gate lead wiring 31) and the lower layer lead wiring 31A (4k + 1) gate lead wiring in the first wiring group 32 are stored in the lookup table (LUT) of the memory unit 65. 31) and brightness correction data for four patterns of the upper layer lead line 31B (4k + fourth gate lead line 31) and the lower layer lead line 31A (4k + second gate lead line 31) of the second wiring group 33 are stored.
  • the display data signal DS (D R , D G , D B ) is corrected using these, so that the upper layer leading wiring 31B of the first wiring group 32 and the upper layer leading wiring 31B of the second wiring group 33 are corrected.
  • Embodiment 2 of the Invention the configuration of the unit driver IC 53 and the memory unit 65 constituting the source driver 52 is the same as that of the first embodiment except for the configuration of the liquid crystal display device S except for the configuration of the first embodiment. Only the different unit driver IC 53 will be described, and the same components will be left to the description of the first embodiment based on FIGS. 1 to 14, and the detailed description thereof will be omitted.
  • FIG. 15 shows the configuration of the unit driver IC 53 that constitutes the source driver 52 according to the present embodiment.
  • the unit driver IC 53 of the present embodiment also has a shift register circuit 54, a data latch circuit 55, a sampling memory circuit 56, a hold memory circuit 57, a level shifter circuit 58, a gradation, as in the first embodiment.
  • a voltage generation circuit 59, a DA conversion circuit 60, and an output circuit 61 are provided.
  • the unit driver IC 53 has the luminance correction circuit 70 in addition to the various circuits 54, 55, 56, 57, 58, 59, 60, 61, and thereby the display input to the data latch circuit 55.
  • the data signal DS (D R , D G , D B ) is corrected.
  • the gradation voltage generation circuit 59 of the unit driver IC 53 is used to correct the luminance stored in the memory unit 65. Based on the data, each gradation voltage to be generated is adjusted so as to compensate for the difference in the stray capacitance C ′ between the pixel electrode 30 in the lower layer lead line 31A and the upper layer lead line 31B.
  • FIG. 16 shows a schematic configuration of the gradation voltage generation circuit 59 in the present embodiment.
  • the gradation voltage generation circuit 59 has two voltage input terminals, ie, the lowest voltage input terminal Vss and the highest voltage input terminal Vdd, and x (for example, eight) for correcting the level of the generated gradation voltage.
  • a variable resistor 77 (R1 to Rx) and an LUT register 76 are provided.
  • the x variable resistors 77 (R1 to Rx) are connected in series between the highest voltage input terminal Vss and the highest voltage input terminal Vdd.
  • the variable resistor 77 (R1) located at one end is connected to the highest voltage input terminal Vdd, and the variable resistor 77 (Rx) located at the other end is connected to the lowest voltage input terminal Vss.
  • y for example, 8 in series between the lowest voltage input terminal Vss and the variable resistor 77 (Rx) connected thereto and between the variable resistors 77 (R1 to Rx).
  • a total of x ⁇ y (for example, 64) resistors (not shown) connected one by one are provided.
  • FIG. 17 shows a conceptual diagram of the data structure of the memory unit 65 of this embodiment.
  • the memory unit 65 has a lookup table (LUT) shown in FIG.
  • This look-up table (LUT) stores predetermined brightness correction data (**) for adjusting the resistance values of the variable resistors 77 (R1 to Rx).
  • the lookup table (LUT) includes an upper layer lead wire 31B (4k + third gate lead wire 31) and a lower layer lead wire 31A (4k + 1 gate lead wire 31) of the first wiring group 32, and
  • the brightness correction data for the four patterns of the upper layer lead line 31B (4k + fourth gate lead line 31) and the lower layer lead line 31A (4k + second gate lead line 31) of the second wiring group 33 are stored.
  • the brightness correction data is data for suppressing or eliminating a brightness difference in display based on the same display data signal DS, and is prepared for each variable resistor 77.
  • the brightness correction data stored in the lookup table (LUT) is the same for the liquid crystal display panel 10 from the minimum drive (0; 00000000) to the maximum drive (255; 11111111) for each single color. It is calculated from the luminance difference of the four patterns at that time.
  • the LUT register 76 reads necessary brightness correction data from the look-up table (LUT) of the memory unit 65 and temporarily stores it.
  • Each variable resistor 77 (R1 to Rx) is configured such that the resistance value is adjusted based on the luminance correction data stored in the LUT register 76.
  • the level of each gradation voltage to be generated is adjusted by each variable resistor 77 (R1 to Rx), and the adjusted gradation voltages are further added to the x ⁇ y resistors.
  • the level of each gradation voltage is adjusted by each variable resistor 77 (R1 to Rx), so that the level of the signal voltage supplied to each source lead line 35 is corrected.
  • the source wiring 23 is supplied.
  • the difference in the stray capacitance C ′ is compensated by the corrected signal voltage, and the liquid crystal layer is formed by the pixel electrode 30 between the pixel p1 driven by the lower lead line 31A and the pixel p1 driven by the upper lead line 31B. 14 can suppress variations in effective voltage applied to.
  • the level of the grayscale voltage generated by the grayscale voltage generation circuit 59 is adjusted based on the brightness correction data stored in the memory unit 65, whereby the lower layer lead-out wiring 31A and the upper layer lead-out wiring 31B are adjusted.
  • the signal voltage supplied to each source line 23 is corrected so as to compensate for the difference in the stray capacitance C ′ between the pixel electrode 30 and the pixel electrode 30, so that the narrow frame structure is realized but formed in different layers.
  • the display quality can be improved by suppressing variations in the effective voltage applied to the liquid crystal layer 14 by the pixel electrode 30 between the pixels p1 driven via the lower lead line 31A and the upper lead line 31B.
  • FIG. 18 is a plan view showing a routing configuration of the display wirings 21 and 23 of the TFT substrate 11 in another embodiment.
  • the gate lead-out wiring 31 forms a double-side lead-out wiring structure.
  • each gate lead-out wiring 31 has a display area as shown in FIG. It may be drawn from only one side of D (right side in FIG. 18) to form a one-side lead wiring structure.
  • the liquid crystal display panel 10 is configured to be capable of triple scan driving.
  • the present invention is not limited to this, and the liquid crystal display panel may be driven by a so-called single scan driving ( (Normal driving) may be possible.
  • the pixels p1 of a plurality of colors that constitute each pixel unit P are arranged in parallel in a striped manner along a direction orthogonal to the scanning direction.
  • a group of source lead wirings 35 includes a lower lead wiring covered by the gate insulating film 22 and an upper lead wiring provided on the gate insulating film 22. These two lead wires constitute a two-layer wiring structure.
  • the lower layer lead wiring and the upper layer lead wiring are respectively formed from the same metal film as the gate wiring 21 or the source wiring 23 as in the first embodiment.
  • the group of source lead lines 35 may form a two-layer wiring structure, and each of the group of gate lead lines 31 and the group of source lead lines 35 has two layers.
  • a wiring structure may be configured.
  • the three-color pixels p1 of red (R), green (G), and blue (B) are arranged in a stripe pattern in a juxtaposed manner, but these three-color pixels p1 (R ), P1 (G), and p1 (B) have other arrangements, the gist of this patent is not affected.
  • the pixel unit P may be composed of four color pixels in which white (W) or yellow (Y) pixels are added to the above three color pixels.
  • the lookup table (LUT) includes an upper layer lead line 31B (4k + third gate lead line 31) and a lower layer lead line 31A (4k + 1th gate lead line 31) in the first wiring group 32. ) And the upper layer lead wiring 31B (4k + fourth gate lead wiring 31) and the lower layer lead wiring 31A (4k + second gate lead wiring 31) of the second wiring group 33 are stored.
  • the present invention is not limited to this.
  • the liquid crystal display device S includes a lower layer lead wire 31A (4k + 1 gate lead wire 31, 4k + second gate lead wire 31) and an upper layer lead wire 31B (4k + third gate lead wire 31, 4k + fourth gate lead wire 31).
  • the luminance correction circuit 70 or the gradation voltage generation circuit 59 uses the lower layer lead wiring 31A and the upper layer lead wiring 31B.
  • the level of the signal voltage supplied to each source lead wiring 35 is corrected so as to compensate for the stray capacitance C ′ formed between the pixel electrode 30 and the pixel electrode 30 via the gate wiring 21. Good.
  • the TFT 24 included in each pixel p1 is a bottom gate type TFT.
  • each TFT 24 is a top gate type (referred to as a stagger type). May be.
  • the liquid crystal display device S having the COG structure in which the driver IC chip including the gate driver and the source driver is mounted in the terminal region of the liquid crystal display panel has been described, but the present invention is not limited to this.
  • the gate driver and the source driver may be divided into unit ICs and mounted on the liquid crystal display panel as TCPs. These two drivers are integrated with the TFTs and display wirings constituting each pixel on the TFT substrate. It may be built as a monolithic circuit.
  • the liquid crystal display device S that performs full-color display has been described as an example.
  • the present invention is not limited to this, and other types such as an organic EL (Electro-Luminescence) display device and a plasma display device are used.
  • the present invention can also be applied to a display device.
  • the present invention can be applied not only to a display device that performs full-color display but also to a display device that performs monochromatic display, and can be widely applied to any display device having a two-layer wiring structure.
  • the present invention is useful for a display device.
  • the pixel electrode is used between pixels driven through the same kind of lead wiring formed in different layers while realizing a narrow frame structure. It is suitable for a display device that is desired to improve display quality by suppressing variations in applied effective voltage.
  • Display area F Frame area S Liquid crystal display device p1 Pixel 10 Liquid crystal display panel 11 TFT substrate 12 Counter substrate 14 Liquid crystal layer 20 Insulating substrate (base substrate) 21 Gate wiring 22 Gate insulating film 23 Source wiring 24 TFT 30 pixel electrode 31 gate lead wire 31A lower layer lead wire 31B upper layer lead wire 35 source lead wire 50 driver IC chip (drive circuit) 51 Gate Driver 52 Source Driver 59 Gradation Voltage Generation Circuit 65 Memory Unit 70 Brightness Correction Circuit 80 Controller (External Circuit)

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Abstract

L'appareil d'affichage selon l'invention dispose d'une structure de câblage à double couche et d'une unité de mémoire (65), qui stocke les données de correction de luminance afin de supprimer ou d'éliminer, dans la structure, une différence entre la luminance d'un pixel (p1) transmise au moyen d'une ligne câblée de sortie de couche inférieure (31A) et la luminance d'un pixel (p1) transmise au moyen d'une ligne câblée de sortie de couche supérieure (31B). Sur la base des données de correction de la luminance stockées dans l'unité de mémoire (65), une puce de CI de commande (50) corrige les niveaux de tension des signaux à desservir aux lignes source câblées de sortie respectives (35).
PCT/JP2012/008203 2011-12-28 2012-12-21 Appareil d'affichage WO2013099189A1 (fr)

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CN104882102A (zh) * 2014-02-27 2015-09-02 三星显示有限公司 液晶显示器及其驱动方法
WO2016080290A1 (fr) * 2014-11-21 2016-05-26 シャープ株式会社 Dispositif d'affichage
WO2021121095A1 (fr) * 2019-12-19 2021-06-24 京东方科技集团股份有限公司 Substrat matriciel, panneau d'affichage et dispositif d'affichage

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JP2007219046A (ja) * 2006-02-15 2007-08-30 Epson Imaging Devices Corp 液晶表示パネル
JP2007248999A (ja) * 2006-03-17 2007-09-27 Epson Imaging Devices Corp 液晶装置及び電子機器
JP2008077005A (ja) * 2006-09-25 2008-04-03 Casio Comput Co Ltd 表示駆動装置及びそれを備える表示装置
JP2009236937A (ja) * 2008-03-07 2009-10-15 Casio Comput Co Ltd 液晶表示装置及びその駆動方法

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JPH07134572A (ja) * 1993-11-11 1995-05-23 Nec Corp アクティブマトリクス型液晶表示装置の駆動回路
JP2007219046A (ja) * 2006-02-15 2007-08-30 Epson Imaging Devices Corp 液晶表示パネル
JP2007248999A (ja) * 2006-03-17 2007-09-27 Epson Imaging Devices Corp 液晶装置及び電子機器
JP2008077005A (ja) * 2006-09-25 2008-04-03 Casio Comput Co Ltd 表示駆動装置及びそれを備える表示装置
JP2009236937A (ja) * 2008-03-07 2009-10-15 Casio Comput Co Ltd 液晶表示装置及びその駆動方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104882102A (zh) * 2014-02-27 2015-09-02 三星显示有限公司 液晶显示器及其驱动方法
CN104882102B (zh) * 2014-02-27 2019-04-02 三星显示有限公司 液晶显示器及其驱动方法
WO2016080290A1 (fr) * 2014-11-21 2016-05-26 シャープ株式会社 Dispositif d'affichage
CN107003580A (zh) * 2014-11-21 2017-08-01 夏普株式会社 显示装置
JPWO2016080290A1 (ja) * 2014-11-21 2017-08-31 シャープ株式会社 表示装置
CN107003580B (zh) * 2014-11-21 2020-11-10 夏普株式会社 显示装置
WO2021121095A1 (fr) * 2019-12-19 2021-06-24 京东方科技集团股份有限公司 Substrat matriciel, panneau d'affichage et dispositif d'affichage

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