WO2013035300A1 - 半導体素子、半導体装置、およびその製造方法 - Google Patents
半導体素子、半導体装置、およびその製造方法 Download PDFInfo
- Publication number
- WO2013035300A1 WO2013035300A1 PCT/JP2012/005565 JP2012005565W WO2013035300A1 WO 2013035300 A1 WO2013035300 A1 WO 2013035300A1 JP 2012005565 W JP2012005565 W JP 2012005565W WO 2013035300 A1 WO2013035300 A1 WO 2013035300A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- region
- silicon carbide
- semiconductor layer
- body region
- impurity
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 359
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 268
- 210000000746 body region Anatomy 0.000 claims abstract description 264
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 207
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 206
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000002347 injection Methods 0.000 claims abstract description 12
- 239000007924 injection Substances 0.000 claims abstract description 12
- 238000002513 implantation Methods 0.000 claims description 86
- 230000002441 reversible effect Effects 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 27
- 230000000630 rising effect Effects 0.000 claims description 20
- 230000005669 field effect Effects 0.000 claims description 11
- 238000009826 distribution Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 142
- 230000015556 catabolic process Effects 0.000 description 27
- 238000011084 recovery Methods 0.000 description 17
- 238000005468 ion implantation Methods 0.000 description 15
- 230000008569 process Effects 0.000 description 13
- 230000004913 activation Effects 0.000 description 10
- 230000005684 electric field Effects 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 230000002093 peripheral effect Effects 0.000 description 9
- 239000013078 crystal Substances 0.000 description 8
- 238000006731 degradation reaction Methods 0.000 description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 6
- 230000007423 decrease Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000003763 carbonization Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000010992 reflux Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 230000001846 repelling effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
Definitions
- This application relates to semiconductor elements.
- the present invention relates to a silicon carbide semiconductor element (power semiconductor device) used for high breakdown voltage and large current.
- Silicon carbide (silicon carbide: SiC) is a high-hardness semiconductor material with a larger band gap than silicon (Si), and is applied to various semiconductor devices such as power elements, environmental elements, high-temperature operating elements, and high-frequency elements. Has been. Among these, application to power elements such as switching elements and rectifying elements has attracted attention.
- a power element using SiC has advantages such as a significant reduction in power loss compared to a Si power element. Further, the SiC power element can realize a smaller semiconductor device as compared with the Si power element by utilizing such characteristics.
- a typical semiconductor element among power elements using SiC is a metal-insulator-semiconductor field-effect transistor (MISFET).
- MISFET metal-insulator-semiconductor field-effect transistor
- MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
- Such a pn junction exists in the semiconductor element constituting the SiC-FET and functions as a diode, so that it is called a “body diode”.
- a pn junction diode body diode
- a freewheeling diode a current flows in the forward direction through the body diode that is a pn junction.
- crystal degradation of the SiC-FET increase in stacking faults at the pn junction
- proceeds due to bipolar operation by the body diode for example, Patent Document 1).
- the on-voltage of the body diode may increase. Further, when the body diode is used as a free-wheeling diode, a reverse recovery current flows when the diode transitions from the on state to the off state due to the bipolar operation of the pn junction diode. The reverse recovery current causes a recovery loss and also reduces the switching speed.
- One non-limiting exemplary embodiment of the present application provides a SiC semiconductor element that can maintain high reliability by suppressing the progress of crystal degradation of a SiC semiconductor device without increasing the number of components. There is.
- a method for manufacturing a semiconductor device comprising: forming a first conductivity type first silicon carbide semiconductor layer on a semiconductor substrate; and defining a body region on the first silicon carbide semiconductor layer.
- Forming a first body implantation region in the first silicon carbide semiconductor layer by forming an impurity implantation region in the semiconductor layer and implanting a second conductivity type impurity; and the first carbonization; Heat treatment of silicon semiconductor layer
- an impurity region and a first body region are formed from the impurity implantation region and the first body implantation region, respectively, and a second region is formed in the region other than the impurity implantation region and the first body implantation region in the body implantation region.
- a semiconductor element includes a first conductivity type semiconductor substrate, a first conductivity type first silicon carbide semiconductor layer located on a main surface of the semiconductor substrate, and the first silicon carbide semiconductor layer.
- a second conductivity type body region located; a first conductivity type impurity region located within the body region; and at least a portion of the body region and the impurity region on the first silicon carbide semiconductor layer.
- a first conductivity type second silicon carbide semiconductor layer disposed in contact with each other, a gate insulating film on the second silicon carbide semiconductor layer, a gate electrode on the gate insulating film, and the impurity region electrically
- the second body region is in contact with the bottom surface of the body region, and the impurity concentration of the first body region is higher than the impurity concentration of the second body region, and the impurity of the second conductivity type impurity in the impurity region The concentration is lower than the impurity concentration of the second conductivity type impurity in the first body region.
- FIG. 2 is a diagram showing the relationship between the threshold value Vth of semiconductor element 100 and the rising voltage
- (A) to (h) are process cross-sectional views for explaining a method for manufacturing the semiconductor element 100.
- FIGS. 4A to 4D are process cross-sectional views for explaining another method for manufacturing the semiconductor element 100.
- (A) to (e) are process cross-sectional views for explaining a method for manufacturing the semiconductor element 100.
- (A) is a top view showing a semiconductor device
- (b) is a sectional view of a unit cell 100u
- (c) is a sectional view taken along line EF in (a).
- 1 is a circuit diagram showing a configuration of a typical inverter circuit 1000.
- FIG. 1 is a cross-sectional view of a semiconductor element (SiC-MISFET) 1100.
- FIG. It is a graph for demonstrating the rising voltage of a SiC body diode.
- FIG. 10 It is the circuit diagram which took out one phase part of the three-phase inverter of the inverter circuit shown in FIG. 10 is a timing chart showing operation waveforms of the circuit shown in FIG. 9. It is a graph for demonstrating the reverse recovery current of a pn junction diode.
- FIG. 6 shows the configuration of a typical inverter circuit 1000 having such a freewheeling diode element.
- the inverter circuit 1000 is a circuit for driving a load 1500 such as a motor, and includes a plurality of semiconductor elements 1100 made of SiC-FETs.
- a semiconductor element 1100 and a free wheel diode element 1200 are connected in antiparallel.
- An on-current (IF) flows through the semiconductor element 1100, and a reflux current (IR) flows through the free-wheeling diode element 1200.
- One set is constituted by two semiconductor elements 1100 connected in series, and three sets are provided in parallel to the DC power supply 2000.
- the gate potential of each semiconductor element 1100 is controlled by the controller.
- FIG. 7 shows a configuration of the semiconductor element (SiC-FET) 1100.
- the semiconductor element 1100 is made of a silicon carbide (SiC) semiconductor, and has a structure in which an n ⁇ drift region 120 is stacked on an n + substrate (SiC substrate) 119.
- a p body region 130 is formed on the n ⁇ drift region 120, and a p body contact region 132 and an n + impurity region 140 are formed on the p body region 130.
- a first ohmic electrode 145 is formed on p body contact region 132 and n + impurity region 140.
- a channel epitaxial layer 150 is formed on the surfaces of n ⁇ drift region 120, p body region 130 and n + impurity region 140. Further, a gate insulating film 160 and a gate electrode 165 are formed on the channel epitaxial layer 150. A channel region is formed in a portion of channel epitaxial layer 150 in contact with the upper surface of p body region 130. A second ohmic electrode 170 is formed on the back surface of the n + substrate 119.
- the semiconductor element 1100 has a body diode 180 built therein. That is, body diode 180 is formed by a pn junction between p body region 130 and n ⁇ drift region 120.
- the rising voltage Vf of the body diode 180 at room temperature (the potential Vsd of the first ohmic electrode 145 with respect to the second ohmic electrode 170) is around 3V (about 2.7V). ) And relatively high, loss is large.
- FIG. 8 shows the current-voltage characteristics and the rising voltage of the body diode 180 at different operating temperatures.
- the rising voltage Vf obtained by tangential approximation from the curve indicating the current-voltage characteristics is as high as about 2.8 V at 25 ° C., and such a diode having a high rising voltage is not practical.
- Vf decreases.
- the body diode 180 is used as a freewheeling diode, there is a problem that the crystal degradation of the semiconductor element 1100 proceeds, the electrical resistance in the body diode 180 increases and the loss increases.
- the body diode 180 is a pn junction diode and is a bipolar operation element.
- a reverse recovery current flows and therefore a recovery loss occurs.
- a period in which a reverse recovery current flows is generated, and it is extremely difficult to perform high-speed switching of the semiconductor element 1100. Further, since the switching loss increases, it is difficult to increase the switching frequency.
- FIG. 9 is a circuit diagram showing a part of the configuration shown in FIG. 6 for explanation.
- a DC power supply 2000 supplies power to an inductive load 2100 such as a motor.
- a high side MISFET H and a low side MISFET L are connected in series.
- the controller 2200 for driving the high side MISFET H and the low side MISFET L outputs the gate drive voltage Vg1 of the high side MISFET H and the gate drive voltage Vg2 of the low side MISFET L.
- the controller 2200 together with the DC power supply 2000, functions as a “potential setting unit” that sets the potential of each MOSFET (semiconductor element), and the semiconductor device illustrated is driven by this potential setting unit.
- 10 (a) to 10 (e) are operation waveforms of the circuit shown in FIG. 9, and are timing charts showing the voltages and currents of the respective parts when current is supplied to the inductive load 2100.
- the gate drive voltage Vg1 of the high side MISFET H and the gate drive voltage Vg2 of the low side MISFET L are exclusively turned on and off.
- dead times Td1 and Td2 are provided between Vg1 and Vg2.
- the initial state in the timing chart of FIG. 10 shows a state in which Vg2 is turned on and a current is flowing through a path indicated by an arrow 96 shown in FIG.
- Vg2 is turned off, and during the dead time Td1, a current flows through the path of the arrow 97 shown in FIG. 9, that is, the freewheeling diode element connected in antiparallel to the low-side MISFET L.
- the current I1 shows a negative value.
- the reverse recovery current passing through the freewheeling diode element connected in antiparallel from the high-side MISFET H to the low-side MISFET L is transient as indicated by the peak current 98. Flowing into. Although this reverse recovery current does not flow to the inductive load 2100, it is superimposed on the current flowing to the high-side MISFET H as indicated by an arrow 95 in FIG. 9, increasing switching loss, element destruction due to overcurrent, and noise generation It causes cause.
- the low-side MISFET L is turned on while the current is flowing through the freewheeling diode element connected in reverse parallel to the low-side MISFET L, and the current flows through the path of the arrow 96 shown in FIG. 9, ie, the channel of the low-side MISFET L. Return to the initial state.
- the on / off operation timing differs between the high-side MISFET H and the low-side MISFET L. However, since the reverse recovery current also occurs on the high side, current also flows through the high-side freewheeling diode element.
- Curves (a) and (b) in FIG. 11 show measurement results of current change of a pn junction diode (Si-PND) using Si.
- the pn junction diode has a period in which a reverse recovery current is generated, thereby deteriorating the characteristics of the inverter circuit 1000 (for example, hindering switching speed and switching loss) Increase).
- the reverse recovery current is larger in the curve (b) at 150 ° C. than in the curve (a) at 25 ° C. Therefore, the characteristics of the Si-pn junction diode deteriorate as the temperature increases.
- the curve (c) in FIG. 11 shows the measurement result of the current change of the Schottky barrier diode (SiC-SBD) using SiC.
- the reverse recovery current is small compared to the curves (a) and (b).
- Curve (c) is the result of both 25 ° C. and 150 ° C., so it can be seen that the SiC-SBD hardly generates reverse recovery current even at high temperatures. Therefore, it is preferable to use SiC-SBD as the free-wheeling diode element 1200 as compared to Si-PND.
- the rising voltage of SBD is lower than that of the body diode of SiC-FET.
- SiC SBD is used as the freewheeling diode element
- the silicon carbide semiconductor material is still expensive, so SiC SBD is also expensive, resulting in an increase in circuit cost.
- SiC-FET of Patent Document 2 when the SiC-FET of Patent Document 2 is used for a power converter, when a reflux current flows through the body diode, the failure rate such as breakdown voltage degradation of the SiC-FET increases, resulting in a low-reliability power converter. There is also a problem.
- the number of parts increases by the amount of SiC-SBD mounted, so that the power converter becomes larger by that amount, which goes against the demand for a power converter that is desired to be reduced in size and weight.
- the present inventors have conceived of a novel semiconductor element, semiconductor device, and manufacturing method thereof in view of such problems.
- a method for manufacturing a semiconductor element comprising: a step (A) of forming a first conductivity type first silicon carbide semiconductor layer on a semiconductor substrate; and a body region on the first silicon carbide semiconductor layer.
- an impurity region and a first body region are formed from the impurity implantation region and the first body implantation region, respectively, and a second region is formed in the region other than the impurity implantation region and the first body implantation region in the body implantation region.
- the second conductivity type impurity may be implanted so that the second conductivity type impurity is located in a region deeper than the impurity implantation region in the body implantation region.
- the first body region and the second body region each include a bottom portion and a wall portion, and the impurity region is located in a surface region of the first silicon carbide semiconductor layer in the first silicon carbide semiconductor layer.
- the bottom portion of the first body region is located below the impurity region, the wall portion of the first body region is located on the side of the impurity region, and on the surface of the first silicon carbide semiconductor layer.
- the bottom portion of the second body region is located below the bottom portion of the first body region, and the wall portion of the second body region is located outside the wall portion of the first body region. You may do it.
- the method for manufacturing a semiconductor device further includes a step of forming a contact implantation region reaching at least a bottom portion of the first body region in the impurity implantation region before the step (F), and the step (F)
- the contact region may be formed from the contact implantation region.
- the method of manufacturing the semiconductor element includes a step of forming a second silicon carbide semiconductor layer on the surface of the first silicon carbide semiconductor layer after the step (F), and a gate insulating film on the second silicon carbide semiconductor layer. Forming a gate electrode on the gate insulating film, and part of the gate insulating film and the second silicon carbide semiconductor layer so that a part of the impurity region and the contact region are exposed. In contact with a surface of the semiconductor substrate that is not in contact with the first silicon carbide semiconductor layer, and a step of forming a first ohmic electrode so as to contact a part of the exposed impurity region and the contact region. A step of forming the second ohmic electrode may be further included.
- the method for manufacturing the semiconductor element includes performing the steps (A), (B), (D), (E), (C), and (F) in this order, and the steps (E) and (C).
- the method may further include a step of removing the sidewall.
- a semiconductor element includes a first conductive type semiconductor substrate, a first conductive type first silicon carbide semiconductor layer located on a main surface of the semiconductor substrate, and the first silicon carbide.
- a first conductivity type second silicon carbide semiconductor layer disposed in contact with at least a part of the first conductivity type, a gate insulating film on the second silicon carbide semiconductor layer, a gate electrode on the gate insulating film, and the impurity
- a first ohmic electrode electrically connected to the region, and a second ohmic electrode provided on the back surface of the semiconductor substrate, wherein the body region includes a first body region and at least a portion below the first body region.
- the second body region is in contact with the bottom surface of the body region, and the impurity concentration of the first body region is higher than the impurity concentration of the second body region, and the second conductivity type impurity in the impurity region
- the impurity concentration of is lower than the impurity concentration of the second conductivity type impurity in the first body region.
- the first body region and the second body region have a thickness of at least 15 nm and 100 nm, respectively, in a direction perpendicular to the main surface of the semiconductor substrate, and the impurity concentration of the first body region is the second body region. It may be twice or more the impurity concentration of the body region.
- the first body region is located below the bottom of the impurity region and on the side of the impurity region, and may be in contact with the surface of the first silicon carbide semiconductor layer on the side of the impurity region. Good.
- the portion of the first body region in contact with the second silicon carbide layer may be disposed at a position shallower than the portion of the first body region located below the impurity region.
- the first body region and the second body region each include a bottom portion and a wall portion, and the impurity region is located in a surface region of the first silicon carbide semiconductor layer in the first silicon carbide semiconductor layer.
- the bottom portion of the first body region is located below the impurity region, the wall portion of the first body region is located on the side of the impurity region, and on the surface of the first silicon carbide semiconductor layer.
- the bottom portion of the second body region is located below the bottom portion of the first body region, and the wall portion of the second body region is located outside the wall portion of the first body region. You may do it.
- the potentials applied to the second ohmic electrode and the gate electrode with respect to the first ohmic electrode are Vds and Vgs, respectively, the gate threshold voltage is Vth, and when Vgs ⁇ Vth, the second silicon carbide
- Vth when Vgs ⁇ Vth, the second silicon carbide
- the first silicon carbide semiconductor is moved from the body region to the first ohmic electrode.
- the current may flow from the first ohmic electrode to the second ohmic electrode through the second silicon carbide semiconductor layer.
- the semiconductor substrate, the first silicon carbide semiconductor layer, the body region, the impurity region, the second silicon carbide semiconductor layer, the gate insulating film, the gate electrode, the first ohmic electrode, and the second ohmic electrode are Forming a metal-insulator-semiconductor field effect transistor, wherein the potential of the second ohmic electrode with reference to the potential of the first ohmic electrode is Vds, and the gate of the gate with reference to the potential of the first ohmic electrode The potential of the electrode is Vgs, the gate threshold voltage of the metal-insulator-semiconductor field effect transistor is Vth, the direction of the current flowing from the second ohmic electrode to the first ohmic electrode is forward, and the first ohmic electrode to the When the direction of the current flowing to the second ohmic electrode is defined as the reverse direction, when Vgs ⁇ Vth, the metal-insulation The semiconductor field effect transistor conducts between the second ohmic electrode and the first ohmic electrode
- the impurity concentration of the first body region is 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less
- the impurity concentration of the second body region is 1 ⁇ 10 17 cm ⁇ 3 or more and 1 ⁇ 10 It may be 19 cm ⁇ 3 or less.
- the second silicon carbide semiconductor layer is electrically connected to a region adjacent to the second body region in the impurity region and the first silicon carbide semiconductor layer, and is disposed on the first body region. Also good.
- the second silicon carbide semiconductor layer may be formed by epitaxial growth.
- a semiconductor device is a semiconductor device including a plurality of any of the semiconductor elements described above, and the semiconductor substrate and the first silicon carbide semiconductor layer of the plurality of semiconductor elements are each A ring region of a second conductivity type that is connected and surrounds the plurality of semiconductor elements in a plane parallel to the main surface of the semiconductor substrate is disposed in the first silicon carbide semiconductor layer,
- the impurity concentration distribution in the depth direction is equal to the impurity concentration distribution in the depth direction of the body region.
- the concentration of the second body region that forms the pn junction between the first body region that adjusts the threshold value of the semiconductor element and the drift region is configured by configuring the body region in two regions. Can be controlled independently. Accordingly, it is possible to suppress a breakdown voltage failure or a leakage failure of the semiconductor element. Further, since the impurity concentration of the second conductivity type impurity in the first conductivity type impurity region is lower than the impurity concentration of the second conductivity type impurity in the first body region, the effective first conductivity type in the impurity region.
- the impurity concentration of the first conductivity type is suppressed from being affected by the second conductivity type impurity, and the concentration of the first conductivity type impurity region is hardly lowered. Further, the controllability of the impurity concentration of the first conductivity type in the impurity region is enhanced, and the variation in impurity concentration can be reduced. Therefore, an increase in on-resistance of the semiconductor element can be suppressed, and variations in element characteristics can be suppressed.
- the semiconductor element of the following embodiment includes a silicon carbide semiconductor layer that functions as a channel region, a gate electrode that controls a current flowing in the silicon carbide semiconductor layer, a first ohmic electrode that is electrically connected to the silicon carbide semiconductor layer, and MISFET comprised by a 2nd ohmic electrode is included.
- This MISFET has a current flowing from the first ohmic electrode to the second ohmic electrode through the channel region when the potential of the gate electrode relative to the potential of the first ohmic electrode is zero or more and lower than the threshold voltage Vth of the transistor. It operates as a diode that flows.
- the potential of the second ohmic electrode D based on the potential of the first ohmic electrode S is Vds
- the potential of the gate electrode G based on the potential of the first ohmic electrode S is Vgs
- the second ohmic electrode The direction of current flowing from D to the first ohmic electrode S is defined as “forward direction”
- the direction of current flowing from the first ohmic electrode S to the second ohmic electrode D is defined as “reverse direction”.
- the unit of potential and voltage is volt (V).
- FIG. 1A schematically shows a cross section of the semiconductor element 100 of the present embodiment.
- FIG. 1A shows a cross section of two semiconductor elements 100 positioned on the right and left sides of the alternate long and short dash line. These constitute unit cell 100u, and a commercially available semiconductor device includes a plurality of unit cells.
- the semiconductor element 100 includes a first conductivity type semiconductor substrate 101 and a first conductivity type first silicon carbide semiconductor layer 102 ′ located on the main surface of the semiconductor substrate 101.
- the first conductivity type is n-type and the second conductivity type is p-type.
- the first conductivity type may be p-type and the second conductivity type may be n-type.
- Semiconductor substrate 101 has n + type conductivity and is made of silicon carbide.
- First silicon carbide semiconductor layer 102 ′ is n ⁇ type.
- the “+” or “ ⁇ ” on the right shoulder of the n or p conductivity type represents the relative concentration of impurities.
- N + means that the n-type impurity concentration is higher than “n”
- n ⁇ means that the n-type impurity concentration is lower than “n”.
- a second conductivity type body region 103 is provided in the first silicon carbide semiconductor layer 102 ′.
- a region other than the body region 103 of the first silicon carbide semiconductor layer 102 ′ is called a drift region 102.
- the first conductivity type impurity region 104 is located in contact with the surface 102's of the first silicon carbide semiconductor layer 102 '.
- the body region 103 includes a second conductivity type first body region 103a and a second conductivity type second body region 103b.
- First body region 103 a has a bottom portion 103 ab located below impurity region 104 and a wall portion 103 aw located on the side of impurity region 104. That is, first body region 103a is located below and to the side of impurity region 104, and in contact with surface 102's of the first silicon carbide semiconductor layer on the side of impurity region 104.
- Second body region 103b is in contact with bottom surface 103u of body region 103, and is located on the side of bottom portion 103bb located below bottom portion 103ab of first body region 103a and wall portion 103aw of first body region 103a. It has wall part 103bw.
- first body region 103 a and the second body region 103 b have a thickness of at least 15 nm and 100 nm in a direction perpendicular to the main surface of the semiconductor substrate 101.
- second body region 103b extends from below impurity region 104 to surface 102 ′s of first silicon carbide semiconductor layer 102 ′ so as to cover first body region 103a and impurity region 104. It has a wall portion 103bw. The thickness of wall portion 103bw decreases from the bottom of impurity region 104 toward the surface 102's of first silicon carbide semiconductor layer 102 '.
- First body region 103a has wall portion 103aw extending from below impurity region 104 to surface 102 'of first silicon carbide semiconductor layer 102' so as to cover impurity region 104.
- the first body region 103a is surrounded by the wall portion 103bw of the second body region 103b and is located in the second body region 103b, and the first body region 103a is not in contact with the drift region 102.
- the impurity region 104 is surrounded by the wall 13aw of the first body region 103a and is located in the first body region 103a.
- the outer periphery of the first body region 103a has a distribution that spreads closer to the surface inside the second body region 103b.
- the region 102 a in contact with the surface 102 ′ s of the first silicon carbide semiconductor layer 102 ′ and the side surface of the impurity region 104 is located between the wall portion 103 aw of the first body region 103 a and the impurity region 104.
- the region 102a has the same second conductivity type as the drift region 102, and contains the second conductivity type impurity at the same concentration.
- the region 102a may contain impurities of the second conductivity type as much as the first body region 103a.
- the first body region 103a is p + type
- the second body region 103b is p type.
- the impurity concentration of the first body region 103a may be twice or more the impurity concentration of the second body region 103b.
- the impurity concentrations of the first body region 103a and the second body region 103b are compared at positions where the first body region 103a and the second body region 103b are adjacent to each other.
- first body region 103a is formed by implanting an impurity deeper than impurity region 104 using a mask for forming impurity region 104 having a sidewall. . Therefore, the impurity concentration of the second conductivity type impurity in the impurity region 104 is lower than the impurity concentration of the second conductivity type impurity in the first body region 103a.
- the impurity concentration of the second conductivity type impurity in the impurity region 104 and the first body region 103a is compared at the same depth in the first silicon carbide semiconductor layer 102 '.
- an impurity for forming the first body region 103a is located shallower in the first silicon carbide semiconductor layer 102 'below the side wall as much as it passes through the side wall. Thereby, wall portion 103aw of first body region 103a in contact with surface 102's of first silicon carbide semiconductor layer 102 'is formed.
- the impurity region 104 Since the impurity concentration of the second conductivity type impurity in the impurity region 104 is lower than the impurity concentration of the second conductivity type impurity in the first body region, the impurity region 104 is offset to become the first conductivity type. The amount of impurities of one conductivity type is small. For this reason, it becomes easy to form the high concentration impurity region 104. In addition, the controllability of the impurity concentration of the first conductivity type is enhanced, and variations in element characteristics can be suppressed.
- the semiconductor element 100 may have a second conductivity type contact region 105 that penetrates the first body region 103a and is in contact with the second body region 103b.
- Contact region 105 may be p + -type.
- a first ohmic electrode 109 is formed on the impurity region 104.
- First ohmic electrode 109 is formed on the surfaces of impurity region 104 and contact region 105, and is in electrical contact with both impurity region 104 and contact region 105. When the impurity concentration of the first body region 103a is sufficiently high, the contact region 105 may not be provided.
- a contact trench exposing the first body region 103a is provided in the impurity region 104, and the first ohmic electrode 109 is formed in the trench so that the first body region 103a and the first ohmic electrode 109 are in direct contact with each other. May be.
- the region 102j adjacent to the body region 103 that is, the region 102j sandwiched between the body regions 103 of the two adjacent unit cells is described with a JFET (Junction Field-Effect Transistor). It will be called an area. Since this region is composed of the first silicon carbide semiconductor layer 102 ′, the impurity concentration may be the same as that of the first silicon carbide semiconductor layer 102 ′. However, in order to reduce the resistance in the JFET region 102j, the first conductivity type impurity (Here, n-type) may be introduced by ion implantation or the like to make the impurity concentration higher than that of the first silicon carbide semiconductor layer 102 ′.
- the first conductivity type impurity (Here, n-type) may be introduced by ion implantation or the like to make the impurity concentration higher than that of the first silicon carbide semiconductor layer 102 ′.
- first conductivity type second silicon carbide semiconductor layer 106 that is in contact with at least part of the body region 103 and the impurity region 104 is provided.
- Second silicon carbide semiconductor layer 106 is electrically connected to JFET region 102j adjacent to second body region 103b among impurity region 104 and first silicon carbide semiconductor layer 102 ', and is also connected to first body region. It may be formed on 103a. Specifically, in first body region 103 a, part of wall portion 103 aw is in contact with second silicon carbide semiconductor layer 106. Wall portion 103aw is arranged at a shallower position in first silicon carbide semiconductor layer 102 'than bottom portion 103ab.
- the second silicon carbide semiconductor layer 106 is formed by epitaxial growth.
- Second silicon carbide semiconductor layer 106 includes a channel region 106c in a region in contact with first body region 103a.
- the length of the channel region 106c corresponds to the length indicated by the two bidirectional arrows shown in FIG. That is, the “channel length” of the MISFET is defined by the horizontal size of the upper surface (surface in contact with the second silicon carbide semiconductor layer 106) of the first body region 103a in the drawing.
- a gate insulating film 107 is formed on the second silicon carbide semiconductor layer 106.
- a gate electrode 108 is formed on the gate insulating film 107. The gate electrode 108 is located at least above the channel region 106c.
- An interlayer insulating film 111 is formed so as to cover the gate electrode 108, and an upper wiring electrode 112 is formed on the interlayer insulating film 111.
- the upper wiring electrode 112 is connected to the first ohmic electrode 109 through a contact hole 111 c provided in the interlayer insulating film 111.
- a second ohmic electrode 110 is formed on the back surface of the semiconductor substrate 101.
- a back surface wiring electrode 113 is further formed on the back surface of the second ohmic electrode 110.
- the unit cell 100u of the semiconductor element 100 has, for example, a square shape.
- the unit cell 100u may have a rectangular shape or a polygonal shape other than a quadrangular shape.
- FIG. 1B shows the arrangement of the unit cells 100u.
- the unit cells 100u are two-dimensionally arranged in the x and y directions, for example, and the arrangement in the y direction is alternately shifted by 1 ⁇ 2.
- the unit cells 100u have a shape that is long in one direction, they may be arranged in parallel as shown in FIG.
- a semiconductor device is constituted by the plurality of unit cells 100u arranged in this way.
- the second silicon carbide semiconductor layer 106, the gate electrode 108 for controlling the current flowing through the second silicon carbide semiconductor layer 106, the gate insulating film 107, and the second silicon carbide semiconductor layer 106 are electrically connected.
- the first ohmic electrode 109 and the second ohmic electrode 110 thus formed constitute a MISFET.
- the threshold voltage of the MISFET is Vth
- the MISFET is turned on when Vgs ⁇ Vth, and when Vds> 0 V
- the second ohmic electrode is interposed via the second silicon carbide semiconductor layer 106.
- Vgs ⁇ Vth the transistor is turned off.
- the second silicon carbide semiconductor layer 106 functions as a diode that allows current to flow from the first ohmic electrode 109 to the second ohmic electrode 110 via the second silicon carbide semiconductor layer 106.
- a diode that causes a current to flow from the first ohmic electrode 109 to the second ohmic electrode 110 via the second silicon carbide semiconductor layer 106 is referred to as a “channel diode”.
- the direction from the second ohmic electrode 110 to the first ohmic electrode 109 is defined as “forward direction”, and the direction from the first ohmic electrode 109 to the second ohmic electrode 110 is defined as “reverse direction”.
- the direction of flowing is “reverse direction”.
- This channel diode having a channel region of the MISFET as a current path has a characteristic that does not flow a current of 1 mA or more when Vds> Vf0 (Vf0 is a negative value) and flows a current of 1 mA or more when Vds ⁇ Vf0.
- Vf0 is a negative value
- Vds the current flowing through this diode is almost zero (less than 1 mA) when Vds> Vf0 (Vf0 is a negative value), but gradually decreases Vds from zero (increases the absolute value of Vds).
- Vf0 corresponds to the “rising voltage” in the current-voltage characteristics of the diode.
- the rising voltage Vf0 of the diode and the threshold voltage Vth of the transistor are both determined mainly by the impurity concentration of the first body region 103a, the impurity concentration and film thickness of the second silicon carbide semiconductor layer 106, and the thickness of the gate insulating film 107. Is done.
- FIG. 2A shows, as an example, the second silicon carbide semiconductor layer 106 when the thickness of the gate insulating film 107 is set to 70 nm and the impurity concentration of the first body region 103a is set to 1 ⁇ 10 19 cm ⁇ 3 .
- Vth and Vf0 2A
- Vth of the semiconductor element 100 is about 3.5V. If the impurity concentration of the second silicon carbide semiconductor layer 106 is about 1.5 ⁇ 10 18 cm ⁇ 3 and the thickness of the second silicon carbide semiconductor layer 106 is set to about 30 nm,
- the Vth of the semiconductor element 100 can be set to about 6.1V while maintaining.
- Semiconductor device 100 can increase both the impurity concentration on the surface side of body region 103 (that is, first body region 103a) and the impurity concentration of second silicon carbide semiconductor layer 106.
- the absolute value of Vf0 can be set smaller than the absolute value of Vf at which current starts to flow in the body diode formed by the drift region 102 and the second body region 103b, and 0V ⁇ Vgs ⁇ Vth and Vds ⁇ 0V
- the current can be passed through the channel diode before the current starts to flow through the body diode.
- the breakdown voltage of the semiconductor element 100 is mainly determined by a pn junction constituted by the second body region 103b and the drift region 102 (first silicon carbide semiconductor layer 102 ').
- the impurity concentration of the body region 103 is high, when a positive bias is applied to the second ohmic electrode 110 with respect to the first ohmic electrode 109, a reverse voltage is applied to the pn junction composed of the body region 103 and the drift region 102. As a result, electric field concentration occurs at the interface. As the concentration of the body region 103 is higher, the electric field concentration is more likely to occur. In particular, as shown in FIG. 1A, the electric field becomes stronger at the corner 103c of the body region 103, and the breakdown voltage of the semiconductor element 100 is determined. That is, the lower the p-type impurity concentration at the corner 103c, the higher the breakdown voltage of the semiconductor element 100 is maintained.
- body region 103 is mainly formed by ion implantation into silicon carbide, and impurities implanted into silicon carbide are incompletely activated as compared with Si semiconductor.
- the concentration of the region in contact with the drift region 102 of the body region 103 is low to some extent.
- the first body region 103a having a high impurity concentration is located in the second body region 103b, and only the second body region 103b having a low concentration can be in contact with the drift region 102. For this reason, it is possible to remarkably suppress problems caused by the high concentration of the body region.
- the body region 103 is divided into a first body region 103a and a second body region 103b, and the impurity concentrations of these regions can be controlled independently. That is, on the one hand, the rising voltage Vf0 of the diode can be controlled by adjusting the impurity concentration of the first body region 103a, and on the other hand, the breakdown voltage of the semiconductor element 100 can be adjusted by adjusting the impurity concentration of the second body region 103b. Can be controlled by.
- the impurity concentration of the first body region 103a is 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less
- the impurity concentration of the second body region 103b is 1 ⁇ 10 17 cm ⁇ 3 or more and 1 ⁇ 10 19 cm ⁇ 3 or less
- the impurity concentration of the first body region 103a is set to be twice or more the impurity concentration of the second body region 103b.
- the impurity concentrations of the first body region 103a and the second body region 103b are compared at positions where the first body region 103a and the second body region 103b are adjacent to each other.
- the second silicon carbide semiconductor layer 106 is formed on the impurity region 104 and the JFET region 102j. In other words, the second silicon carbide semiconductor layer 106 is in contact with the upper surface of the drift region 102.
- the current flowing through the channel diode when the second ohmic electrode 110 is negative (reverse direction) with respect to the first ohmic electrode 109 is positive (forward) with respect to the first ohmic electrode 109.
- an amount of current comparable to the on-current of the transistor (1/5 or more and 2 or less of the rated on-current of the transistor) can be secured.
- a so-called free-wheeling diode connected in reverse parallel to a MISFET mounted on a general inverter circuit can function as a channel diode of the semiconductor element 100. That is, the semiconductor element 100 includes a free wheel diode.
- the absolute value of the rising voltage Vf0 of the channel diode can be made smaller than the absolute value of the rising voltage of the body diode, power loss in the inverter circuit can be reduced. Furthermore, since the current flowing through the body diode can be drastically reduced, the crystal degradation of the semiconductor element 100 can be suppressed, and the high breakdown voltage characteristics can be maintained. Therefore, the semiconductor element 100 has high reliability.
- the impurity concentration of the second conductivity type impurity in the impurity region 104 is lower than the impurity concentration of the second conductivity type impurity in the first body region.
- 2B and 2C show transistor characteristics of an example of the semiconductor device 100 according to the present embodiment.
- 2B and 2C show the forward characteristic and the reverse characteristic of the semiconductor element 100, respectively.
- the characteristics of the conventional semiconductor element shown in FIG. 7 are also shown.
- the semiconductor device 100 of the present embodiment since the on-resistance is small, a large forward current can flow.
- the sheet resistances of the impurity regions 104 of the example and the conventional example shown in FIG. 2B are 1.7 k ⁇ / ⁇ and 12.56 k ⁇ / ⁇ , respectively, and the sheet resistance is reduced to 1/7 compared to the conventional example. .
- FIG. 2C when the reverse bias is applied, the source / drain current flows in the reverse direction, and it can be seen that the semiconductor device 100 according to the present embodiment has a function as a free-wheeling diode.
- the semiconductor substrate 101 is prepared.
- the semiconductor substrate 101 is, for example, an n-type 4H—SiC offcut substrate having a low resistance (resistivity 0.02 ⁇ cm).
- a high-resistance first silicon carbide semiconductor layer 102 ′ is epitaxially grown on a semiconductor substrate 101.
- a buffer layer made of SiC having a high impurity concentration may be deposited on the semiconductor substrate 101.
- the impurity concentration of the buffer layer is, for example, 1 ⁇ 10 18 cm ⁇ 3 and the thickness is 1 ⁇ m.
- the first silicon carbide semiconductor layer 102 ′ is made of, for example, n-type 4H—SiC, and has an impurity concentration and a film thickness of, for example, 1 ⁇ 10 16 cm ⁇ 3 and 10 ⁇ m, respectively.
- a base oxide film 129 having a thickness of, for example, 50 nm is deposited on the first silicon carbide semiconductor layer 102 ′, and then a mask 201 made of SiN having a thickness of 350 nm is formed. .
- Mask 201 defines body region 103. Using this mask 201, for example, Al ions are implanted into the first silicon carbide semiconductor layer 102 '.
- the ion implantation region formed here is a second body implantation region 103b 'formed at a lower concentration than the first body implantation region 103a'.
- a mask made of SiO 2 having a thickness of, for example, 500 nm is newly deposited without removing the mask 201, and then etching back is performed.
- Sidewalls 202 are formed on the side surfaces, and a mask 202 ′ is formed on a region to be the contact region 105 in the first silicon carbide semiconductor layer 102 ′.
- impurity implantation region 104 ′ is formed by ion implantation of, for example, nitrogen into second body implantation region 103b ′ using mask 201 with sidewall 202.
- the first body implantation region 103a ′ is formed by implanting, for example, Al ions through the same opening.
- the first body implantation region 103 a ′, the second body implantation region 103 b ′, and the impurity implantation region 104 ′ become the first body region 103 a, the second body region 103 b, and the impurity region 104 after activation of the implanted ions.
- regions other than the first body region 103 a, the second body region 103 b, and the impurity region 104 become the drift region 102.
- the impurity concentration (dopant concentration) and the ion implantation profile are strictly different, and the impurity concentration is often lower than the ion implantation profile. This is due to the activation rate of the implanted impurities. If the activation rate is 100%, the ion implantation profile and the impurity concentration are almost equal. If the activation rate is ⁇ %, for example, the dose during ion implantation may be multiplied by 1 / ( ⁇ / 100) so that the designed impurity concentration is obtained.
- the ion implantation energy and implantation amount are selected so that a desired impurity concentration profile is obtained after the activation rate and diffusion coefficient are known in advance. In the following description, it is assumed that the activation rate is 100% and the impurity concentration and the ion implantation profile are substantially the same.
- the second body implantation region 103b ′ can be obtained by implanting Al with the following implantation energy and dose, for example.
- the first body implantation region 103a ′ formed using the mask 202 ′ and the mask 201 with the sidewalls 202 is obtained by implanting Al with the following implantation energy and dose, for example. 250 keV: 5.0 ⁇ 10 14 cm ⁇ 2
- the impurity implantation region 104 ′ can be obtained by implanting nitrogen with the following implantation energy and dose, for example. 30 keV: 1.5 ⁇ 10 14 cm ⁇ 2 50 keV: 2.0 ⁇ 10 14 cm ⁇ 2 90 keV: 5.0 ⁇ 10 14 cm ⁇ 2
- the depth of the impurity region 104 in the second body region 103b is about 200 nm, the range of 200 nm from the surface is the n-type region, and the deeper region is the p-type region.
- the first body region 103a formed by using the mask 202 ′ and the mask 201 with the sidewall 202 has a range (Rp) of 250 nm in the opening without the sidewall 202, and considered range and range variation ( (Rp ⁇ 3 ⁇ ⁇ Rp) implantation depth is 210 nm, which is deeper than the boundary between the second body region 103b and the impurity region 104. That is, the first body implantation region 103a ′ is not implanted into the impurity implantation region 104 ′ (0.3% or less of the dose amount even if implanted) and does not affect the concentration of the impurity implantation region 104 ′. .
- the side wall 202 becomes an implantation mask, and the implantation profile becomes shallow.
- the entire range of the first body implantation region 103 a ′ is present in the first silicon carbide semiconductor layer 102, and the range does not remain on the mask 201 and the sidewall 202.
- the range of the first body implantation region 103a ′ is shallower as the sidewall 202 is thicker, the range of the first body implantation region 103a ′ is deeper as it is closer to the impurity implantation region 104 ′ and closer to the drift region 102. In the vicinity of the drift region 102, Rp becomes as shallow as about 30 nm.
- the first body region 103 a is formed in the second body region 103 b between the drift region 102 and the impurity region 104.
- the impurity concentrations of the first body implantation region 103a ′ and the second body implantation region 103b ′ are about 1 ⁇ 10 19 cm ⁇ 3 and about 1 ⁇ 10 19 cm ⁇ 3 respectively. 2 ⁇ 10 18 cm ⁇ 3 . If the activation rate is 100%, these values are the maximum impurity concentrations of the first body region 103a and the second body region 103b.
- the average impurity concentrations are about 9.7 ⁇ 10 18 cm ⁇ 3 and about 1.5 ⁇ 10 18 cm ⁇ 3 , respectively.
- the impurity concentration of the first body region 103a is desirably not less than 2 times and not more than 100 times the impurity concentration of the second body region 103b.
- the thickness (depth) of the first body region 103a is determined according to the rising voltage Vf0 of the channel diode, the concentration and thickness of the second silicon carbide semiconductor layer 106, and the thickness of the gate insulating film.
- the thickness of the first body region 103a may be 15 nm or more.
- the thickness of the second body region 103b may be 100 nm or more.
- the order of forming the first body implantation region 103a ', the second body implantation region 103b', and the impurity implantation region 104 ' is not limited to the above example.
- the first body implantation region 103a 'and the impurity implantation region 104' may be formed before the second body implantation region 103b '.
- FIG. 3B (a) after a high resistance first silicon carbide semiconductor layer 102 ′ is epitaxially grown on the semiconductor substrate 101, a base oxide is formed on the first silicon carbide semiconductor layer 102 ′.
- a film 129 is formed, and a mask 202 ′ for forming the mask 201, the sidewall 202, and the contact region 105 is further formed.
- nitrogen is implanted into the first silicon carbide semiconductor layer 102 ′ using the mask 201, the sidewall 202, and the mask 202 ′ to form an impurity implanted region 104 ′.
- Al ions are implanted into the first silicon carbide semiconductor layer 102 ', thereby forming a first body implantation region 103a'.
- Al ions are implanted into the first silicon carbide semiconductor layer 102 'to form a second body implantation region 103b'.
- a contact implantation region 105 ′ is formed by implanting Al after forming the mask 203.
- the contact implantation region 105 ′ may reach the second body implantation region 103 b ′.
- the mask 203 is removed and activation annealing is performed, so that as shown in FIG. 3A (e), the first body region 103a, the second body region 103b, the impurity region 104, and the contact region 105. Is formed.
- the ion implantation profile is determined so that the depth of the first body region 103a is, for example, 300 nm and the average impurity concentration is about 1 ⁇ 10 19 cm ⁇ 3 .
- the depth of the entire body region 103 including the first body region 103a and the second body region 103b is, for example, 550 nm, and the average impurity concentration of the second body region 103b is about 2 ⁇ 10 18 cm ⁇ 3. Adjust the injection profile.
- the ion implantation profile is adjusted so that the depth of the impurity region 104 is, for example, 250 nm and the average impurity concentration is about 5 ⁇ 10 19 cm ⁇ 3 .
- the depth (bottom position) of the first body region 103 a is defined by the depth at which the Al impurity concentration has a minimum value in the body region 103.
- the depth of the second body region 103b is set to a depth at which, for example, an impurity concentration of 5 ⁇ 10 17 cm ⁇ 3 is obtained.
- the depth of the impurity region 104 is set to a depth at which an impurity concentration of 5 ⁇ 10 17 cm ⁇ 3 is obtained, for example.
- the depth of the contact region 105 is, for example, 400 nm, the average impurity concentration is about 1 ⁇ 10 20 cm ⁇ 3 , and the depth is, for example, a depth at which an impurity concentration of 5 ⁇ 10 17 cm ⁇ 3 is obtained.
- the surface layer of the first silicon carbide semiconductor layer 102 ′ may be removed in order to clean the surface of the first silicon carbide semiconductor layer 102 ′ after the activation annealing.
- the depths of the first body region 103a, the entire body region 103, the impurity region 104, and the contact region 105 are all reduced by about 50 nm, and 250 nm, 500 nm, 200 nm, and 350 nm.
- second silicon carbide semiconductor layer 106 is epitaxially grown on the entire surface of first silicon carbide semiconductor layer 102 ′ including first body region 103a, impurity region 104, and contact region 105.
- a gate insulating film 107 is formed on the surface of the second silicon carbide semiconductor layer 106 by, for example, thermal oxidation.
- the gate insulating film 107 is formed by thermal oxidation, a part of the second silicon carbide semiconductor layer 106 becomes the gate insulating film 107. Therefore, after the gate insulating film 107 is formed in consideration of the thickness lost by thermal oxidation.
- the thickness of second silicon carbide semiconductor layer 106 to be formed is adjusted so as to have the thickness d.
- the second silicon carbide semiconductor layer 106 is formed with a thickness of about 50 nm with respect to d, and the cleaning process of the second silicon carbide semiconductor layer 106 before the gate insulating film is formed, After the formation process, the thickness becomes the above-mentioned thickness d.) Thereafter, a polycrystalline silicon film doped with about 7 ⁇ 10 20 cm ⁇ 3 of phosphorus is deposited on the surface of the gate insulating film 107. The thickness of the polycrystalline silicon film is, for example, about 500 nm.
- the polycrystalline silicon film is dry-etched using a mask (not shown) to form a gate electrode 108 in a desired region.
- a mask not shown
- an interlayer insulating film 111 using, for example, SiO 2 is deposited by CVD so as to cover the surface of the gate electrode 108 and the surface of the first silicon carbide semiconductor layer 102 ′.
- the thickness of the interlayer insulating film 111 is, for example, 1.5 ⁇ m.
- the interlayer insulating film 111 on the surface of the contact region 105 and a part of the surface of the impurity region 104 is removed by dry etching using a mask (not shown). As a result, a contact hole 111c is formed.
- a nickel film 109 ′ having a thickness of about 50 nm is formed on the interlayer insulating film 111.
- the first ohmic structure made of nickel silicide is obtained by reacting the nickel film 109 'with the silicon carbide surface by heat treatment in an inert atmosphere at a temperature of, for example, 950 ° C. for 5 minutes.
- An electrode 109 is formed.
- FIG. 4D after the nickel film 109 ′ on the interlayer insulating film 111 is removed by etching, for example, nickel is deposited on the entire back surface of the semiconductor substrate 101, and similarly by heat treatment.
- the second ohmic electrode 110 is formed by reacting with silicon carbide.
- an aluminum film having a thickness of about 4 ⁇ m is deposited on the interlayer insulating film 111 and in the contact hole 111c, and etched into a desired pattern, whereby the upper wiring electrode 112 is formed as shown in FIG. can get.
- a gate wiring (or gate pad) in contact with the gate electrode is also formed in another region at the chip end.
- Ti / Ni / Ag is deposited on the back surface of the second ohmic electrode 110 as the back wiring electrode 113 for die bonding. (The Ti side is in contact with the second ohmic electrode 110.) In this way, the semiconductor element 100 shown in FIG. 1 is obtained.
- the first body region that affects Vf0 can be controlled independently. For this reason, a channel diode can be used as a free-wheeling diode, and a semiconductor element having high breakdown voltage and reliability can be realized. Further, when forming the first body region for adjusting the threshold value, the second conductivity type impurity ions are not implanted into the region to be the first conductivity type impurity region (source region).
- the impurity region of the first conductivity type can be formed without repelling the impurity, the decrease in the concentration of the impurity region of the first conductivity type can be suppressed, and the variation can be reduced. Therefore, the low-resistance first-conductivity-type impurity region can be reliably formed, an increase in on-resistance of the semiconductor element can be suppressed, and variation in characteristics can be suppressed.
- the impurity concentration of the second body region may be made lower than the impurity concentration of the first body region.
- the impurity concentrations of the first body region and the second body region are compared at the same depth in the first silicon carbide layer.
- the rise voltage of the channel diode is designed to be 1 V or less, it is possible to substitute for a Schottky diode made of SiC, which is a candidate for a freewheeling diode, and if the rise voltage of the channel diode is designed to be 0.6 V or less, it is fast made of Si.
- a recovery diode can be substituted. That is, without using these free-wheeling diodes, only the semiconductor element 100 can function as a free-wheeling diode.
- the threshold voltage Vth of the forward current may be 2 V or more.
- a semiconductor element (MISFET) generally used in an inverter circuit which is a power circuit may be normally off (Vth> 0 V).
- the threshold voltage of the MISFET decreases as the temperature rises.
- the temperature is lowered by about 1 V with a temperature rise of 100 ° C.
- Vth at room temperature may be set to 2 V (1 V + 1 V) or more.
- the threshold voltage is practically 8 V or less. May be.
- the process design of the electric field concentration relaxation structure at the peripheral edge portion in the semiconductor element is facilitated. This will be described below.
- FIG. 5A is a schematic view of a semiconductor device 100c including a plurality of semiconductor elements 100 as unit cells as viewed from the upper wiring electrode 112 side.
- the semiconductor element 100 is often cut into a square as shown in FIG.
- the semiconductor device 100c includes a unit cell arrangement part 100ul and a peripheral end part 100fl.
- the unit cells shown in FIGS. 1B and 1C are arranged in the unit cell arrangement unit 100ul.
- the peripheral end portion 100fl is arranged so as to surround the periphery of the unit cell arrangement portion 100ul.
- FIG. 5B shows the unit cell 100u of the semiconductor element 100 already shown in FIG.
- FIG. 5C is a cross-sectional view taken along the line EF of FIG.
- the semiconductor device 100c includes a second conductivity type injection region 115 disposed at the peripheral end portion 100fl.
- the injection region 115 is mainly disposed on the outermost periphery of the unit cell 100u, and is defined by a planar shape similar to that of the unit cell 100u (for example, a quadrangle shown in FIG. 1B).
- the semiconductor device further includes a second conductivity type ring region (FLR) 116.
- the ring region 116 surrounds the unit cell placement portion 100ul and the injection region 115 in a ring shape on a plane parallel to the main surface of the semiconductor substrate 101, and is composed of one or a plurality of rings.
- a depletion suppression region 104 f of the first conductivity type is provided outside the ring region 116 and further surrounds the ring region 116.
- the injection region 115 and the ring region 116 affect the device breakdown voltage and have a role of relaxing electric field concentration at the end portion of the device.
- an anti-conductivity type (p-type in this case) injection region 115 or ring region 116 may be provided for the drift region 102 prepared to have a desired breakdown voltage. Good.
- the manufacturing process of the semiconductor device can be simplified, and the process cost can be reduced.
- the implantation region 115 and the ring region are simultaneously formed. 116 can be formed.
- the first implantation region 103ad and the second implantation region 103bd in the implantation region 115 can be formed by the same process as the first body region 103a and the second body region 103b, respectively.
- the first ring region 103af and the second ring region 103bf in the ring region 116 can be formed in the same process as the first body region 103a and the second body region 103b.
- the first ring region 103af is formed on the surface of the first silicon carbide semiconductor layer 102 ′ without providing a mask, the same depth as that of the first body region 103a located below the impurity region 104, that is, the first carbonization is performed.
- first silicon carbide semiconductor layer 102 ′ It is formed inside from the surface of the silicon semiconductor layer 102 '.
- a mask having the same function as the sidewall 202 shown in FIG. 3A (c) is used as the first silicon carbide semiconductor layer 102'.
- the first conductivity type impurity may be implanted near the surface of the first silicon carbide semiconductor layer 102 ′.
- the first body region / second body region in the unit cell arrangement portion 100ul and the implantation region 115 and the ring region 116 in the peripheral end portion 100fl are simultaneously formed to facilitate the process design. It is also effective for suppression. In order to suppress element breakdown voltage degradation, it is effective to alleviate electric field concentration at the peripheral end portion 100fl.
- element design of the implantation region 115 and the ring region 116 is important. For example, the width and interval of the rings formed in the ring region 116, the number of rings, and the impurity concentration of the second ring region 103bf Are optimally designed, and based on this element design, a mask set for realizing a semiconductor process is produced.
- the injection region 115 and the ring region 116 of the peripheral end portion 100fl can be formed simultaneously with the first and second body regions 103a and 103b in the unit cell arrangement portion 100ul.
- the impurity concentration of the second body region 103b, the second implantation region 103bd, and the second ring region 103bf that affect the device breakdown voltage is fixed on the one hand, and the impurity concentration of the first body region 103a is arbitrarily designed on the other hand.
- can be realized while suppressing the breakdown voltage of the element.
- the element design mask re-fabrication
- a semiconductor device capable of suppressing a breakdown voltage failure and a leakage failure while avoiding the progress of crystal deterioration of a semiconductor device including a SiC pn junction.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
以下、図面を参照しながら、半導体素子の第1の実施形態を説明する。図1(a)は本実施形態の半導体素子100の断面を模式的に示している。図1(a)には、一点鎖線の右側および左側にそれぞれ位置する2つの半導体素子100の断面が示されている。これらは、ユニットセル100uを構成しており、市販される半導体装置は、複数のユニットセルを含む。
30keV:6.0×1012cm-2
70keV:1.2×1013cm-2
150keV:2.5×1013cm-2
350keV:6.0×1013cm-2
250keV:5.0×1014cm-2
30keV:1.5×1014cm-2
50keV:2.0×1014cm-2
90keV:5.0×1014cm-2
N=2×1018
d=30
101 半導体基板
102 ドリフト領域
102’ 第1炭化珪素半導体層
102j JFET領域
103a 第1ボディ領域
103b 第2ボディ領域
103ab、103bb 底部分
103aw、103bw 壁部分
104 不純物領域
105 コンタクト領域
106 第2炭化珪素半導体層
106c チャネル領域
107 ゲート絶縁膜
108 ゲート電極
109 第1オーミック電極
110 第2オーミック電極
111 層間絶縁膜
112 上部配線電極
113 裏面配線電極
Claims (17)
- 半導体基板上に第1導電型の第1炭化珪素半導体層を形成する工程(A)と、
前記第1炭化珪素半導体層上にボディ領域を規定する第1マスクを形成する工程(B)と、
前記第1マスクを用いて、第2導電型の不純物を注入することにより、前記第1炭化珪素半導体層中に、ボディ注入領域を形成する工程(C)と、
前記第1マスクの側面にサイドウォールを形成する工程(D)と、
前記第1マスクおよび前記サイドウォールを用いて、第1導電型の不純物を注入することにより、前記第1炭化珪素半導体層中に不純物注入領域を形成し、第2導電型の不純物を注入することにより、前記第1炭化珪素半導体層中に第1ボディ注入領域を形成する工程(E)と、
前記第1炭化珪素半導体層を熱処理することにより、前記不純物注入領域および前記第1ボディ注入領域からそれぞれ不純物領域および第1ボディ領域を形成し、前記ボディ注入領域の前記不純物注入領域および前記第1ボディ注入領域以外の領域に第2ボディ領域を画定し、前記第1炭化珪素半導体層のボディ注入領域以外の領域にドリフト領域を画定する工程(F)と、
を包含する半導体素子の製造方法。 - 前記工程(E)において、前記ボディ注入領域中の前記不純物注入領域よりも深い領域に前記第2導電型の不純物が位置するように、前記第2導電型不純物を注入する請求項1に記載の半導体素子の製造方法。
- 前記第1ボディ領域および前記第2ボディ領域はそれぞれ底部分および壁部分を含み、
前記第1炭化珪素半導体層中において、前記不純物領域は前記第1炭化珪素半導体層の表面領域に位置しており、
前記第1ボディ領域の底部分は前記不純物領域の下方に位置し、前記第1ボディ領域の壁部分は、前記不純物領域の側方に位置し、かつ前記第1炭化珪素半導体層の表面に接しており、
前記第2ボディ領域の底部分は前記第1ボディ領域の底部分の下方に位置し、前記第2ボディ領域の壁部分は、前記第1ボディ領域の壁部分よりも外側に位置している請求項1に記載の半導体素子の製造方法。 - 前記工程(F)の前に前記不純物注入領域中に前記第1ボディ領域の底部分に少なくとも達するコンタクト注入領域を形成する工程をさらに包含し、
前記工程(F)において、前記コンタクト注入領域からコンタクト領域を形成する請求項3に記載の半導体素子の製造方法。 - 前記工程(F)の後に、
前記第1炭化珪素半導体層の表面に第2炭化珪素半導体層を形成する工程と、
前記第2炭化珪素半導体層上にゲート絶縁膜を形成する工程と
前記ゲート絶縁膜上にゲート電極を形成する工程と、
前記不純物領域の一部および前記コンタクト領域が露出するように、前記ゲート絶縁膜および前記第2炭化珪素半導体層の一部を除去する工程と、
前記露出した不純物領域の一部および前記コンタクト領域に接するように第1オーミック電極を形成する工程と、
前記半導体基板の前記第1炭化珪素半導体層が接していない面に接するように第2オーミック電極を形成する工程と
をさらに包含する請求項4に記載の半導体素子の製造方法。 - 前記工程(A)、(B)、(D)、(E)、(C)、(F)の順に各工程を行い、
前記工程(E)と(C)との間に、前記サイドウォールを除去する工程をさらに包含する請求項1に記載の半導体素子の製造方法。 - 第1導電型の半導体基板と、
前記半導体基板の主面上に位置する第1導電型の第1炭化珪素半導体層と、
前記第1炭化珪素半導体層内に位置する第2導電型のボディ領域と、
前記ボディ領域内に位置する第1導電型の不純物領域と、
前記第1炭化珪素半導体層上であって、前記ボディ領域および前記不純物領域の少なくとも一部にそれぞれ接して配置された第1導電型の第2炭化珪素半導体層と、
前記第2炭化珪素半導体層上のゲート絶縁膜と、
前記ゲート絶縁膜上のゲート電極と、
前記不純物領域と電気的に接続された第1オーミック電極と、
前記半導体基板の裏面に設けられた第2オーミック電極と
を備え、
前記ボディ領域は、第1ボディ領域と、少なくとも前記第1ボディ領域の下方を含む位置に配置され前記ボディ領域の底面に接する第2ボディ領域とを含み、
前記第1ボディ領域の不純物濃度は、前記第2ボディ領域の不純物濃度よりも高く、
前記不純物領域における第2導電型不純物の不純物濃度は、前記第1ボディ領域における第2導電型不純物の不純物濃度よりも低い、半導体素子。 - 前記第1ボディ領域および前記第2ボディ領域は、それぞれ、前記半導体基板の主面と垂直な方向に少なくとも15nmおよび100nmの厚さを有し、
前記第1ボディ領域の不純物濃度は、前記第2ボディ領域の不純物濃度の2倍以上である、請求項7に記載の半導体素子。 - 前記第1ボディ領域は、前記不純物領域の底よりも下方および前記不純物領域の側方に位置しており、前記不純物領域の側方において、前記第1炭化珪素半導体層の表面に接している請求項7または8に記載の半導体素子。
- 前記第1ボディ領域のうち前記第2炭化珪素層に接する部分が前記第1ボディ領域のうち、前記不純物領域の下方に位置する部分よりも浅い位置に配置されている、請求項7または8に記載の半導体素子。
- 前記第1ボディ領域および前記第2ボディ領域はそれぞれ底部分および壁部分を含み、
前記第1炭化珪素半導体層中において、前記不純物領域は前記第1炭化珪素半導体層の表面領域に位置しており、
前記第1ボディ領域の底部分は前記不純物領域の下方に位置し、前記第1ボディ領域の壁部分は、前記不純物領域の側方に位置し、かつ前記第1炭化珪素半導体層の表面に接しており、
前記第2ボディ領域の底部分は前記第1ボディ領域の底部分の下方に位置し、前記第2ボディ領域の壁部分は、前記第1ボディ領域の壁部分よりも外側に位置している請求項7または8に記載の半導体素子。 - 前記第1オーミック電極を基準とする前記第2オーミック電極および前記ゲート電極に印加される電位はそれぞれVdsおよびVgsであり、ゲート閾値電圧はVthであり、
Vgs≧Vthの場合、前記第2炭化珪素半導体層を介して前記第2オーミック電極から前記第1オーミック電極へ電流が流れ、
0ボルト≦Vgs<Vthの場合、Vdsが0ボルトよりも小さくなるにつれて、前記ボディ領域から前記第1炭化珪素半導体層へ電流が流れ始める前に前記第1オーミック電極から前記第2炭化珪素半導体層を介して前記第2オーミック電極へ電流が流れる、請求項7から11のいずれかに記載の半導体素子。 - 前記半導体基板、前記第1炭化珪素半導体層、前記ボディ領域、前記不純物領域、前記第2炭化珪素半導体層、前記ゲート絶縁膜、前記ゲート電極、前記第1オーミック電極、および前記第2オーミック電極は、金属-絶縁体-半導体電界効果トランジスタを構成しており、
前記第1オーミック電極の電位を基準とする前記第2オーミック電極の電位をVds、
前記第1オーミック電極の電位を基準とする前記ゲート電極の電位をVgs、
前記金属-絶縁体-半導体電界効果トランジスタのゲート閾値電圧をVth、
前記第2オーミック電極から前記第1オーミック電極へ流れる電流の向きを順方向、
前記第1オーミック電極から前記第2オーミック電極へ流れる電流の向きを逆方向と定義すると、
Vgs≧Vthの場合、
前記金属-絶縁体-半導体電界効果トランジスタは、前記第2炭化珪素半導体層を介して前記第2オーミック電極と前記第1オーミック電極との間を導通し、
0ボルト≦Vgs<Vthの場合、
前記金属-絶縁体-半導体電界効果トランジスタは、前記順方向に電流を流さず、Vds<0ボルトのとき、前記第1オーミック電極から前記第2炭化珪素半導体層を介して前記第2オーミック電極へ前記逆方向に電流を流すダイオードとして機能し、
前記ダイオードの立ち上がり電圧の絶対値は、前記ボディ領域と前記第1炭化珪素半導体層とにより構成されるボディダイオードの立ち上がり電圧の絶対値よりも小さい、請求項7から11のいずれかに記載の半導体素子。 - 前記第1ボディ領域の不純物濃度が1×1018cm-3以上、1×1020cm-3以下であり、前記第2ボディ領域の不純物濃度が1×1017cm-3以上、1×1019cm-3以下である、請求項7から13のいずれかに記載の半導体素子。
- 前記第2炭化珪素半導体層は、前記不純物領域、および前記第1炭化珪素半導体層のうち前記第2ボディ領域に隣接する領域と電気的に接続され、前記第1ボディ領域上に配置されている、請求項7から14のいずれかに記載の半導体素子。
- 前記第2炭化珪素半導体層はエピタキシャル成長により形成されている請求項15に記載の半導体素子。
- 請求項7から16のいずれかに記載された半導体素子を複数含む半導体装置であって、
前記複数の半導体素子の前記半導体基板および前記第1炭化珪素半導体層は、それぞれ、互いに接続されており、
前記半導体基板の主面に平行な面において前記複数の半導体素子を囲む第2導電型のリング領域が、前記第1炭化珪素半導体層中に配置されており、
前記リング領域の深さ方向の不純物濃度分布は、前記ボディ領域の深さ方向の不純物濃度分布と等しい、半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013522045A JP5400252B2 (ja) | 2011-09-07 | 2012-09-03 | 半導体素子、半導体装置、およびその製造方法 |
US14/001,027 US8878194B2 (en) | 2011-09-07 | 2012-09-03 | Semiconductor element, semiconductor device, and semiconductor element manufacturing method |
CN201280009601.8A CN103548142B (zh) | 2011-09-07 | 2012-09-03 | 半导体元件、半导体装置、及其制造方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011-195208 | 2011-09-07 | ||
JP2011195208 | 2011-09-07 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2013035300A1 true WO2013035300A1 (ja) | 2013-03-14 |
Family
ID=47831772
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2012/005565 WO2013035300A1 (ja) | 2011-09-07 | 2012-09-03 | 半導体素子、半導体装置、およびその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8878194B2 (ja) |
JP (1) | JP5400252B2 (ja) |
CN (1) | CN103548142B (ja) |
WO (1) | WO2013035300A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012104856A (ja) * | 2009-04-30 | 2012-05-31 | Panasonic Corp | 半導体素子、半導体装置および電力変換器 |
JP2015060841A (ja) * | 2013-09-17 | 2015-03-30 | 三菱電機株式会社 | 炭化珪素半導体装置の製造方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112951922B (zh) * | 2021-03-25 | 2024-07-23 | 派恩杰半导体(杭州)有限公司 | 集成ESD的SiC功率MOSFET器件及制备方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003163351A (ja) * | 2001-11-27 | 2003-06-06 | Nec Kansai Ltd | 絶縁ゲート型半導体装置およびその製造方法 |
WO2008087763A1 (ja) * | 2007-01-16 | 2008-07-24 | Panasonic Corporation | 半導体装置およびその製造方法 |
JP2008227151A (ja) * | 2007-03-13 | 2008-09-25 | Denso Corp | 炭化珪素半導体装置およびその製造方法 |
JP2009194165A (ja) * | 2008-02-14 | 2009-08-27 | Sumitomo Electric Ind Ltd | 半導体装置およびその製造方法 |
WO2010125819A1 (ja) * | 2009-04-30 | 2010-11-04 | パナソニック株式会社 | 半導体素子、半導体装置および電力変換器 |
WO2011013364A1 (ja) * | 2009-07-28 | 2011-02-03 | パナソニック株式会社 | 半導体素子の製造方法 |
WO2011027540A1 (ja) * | 2009-09-02 | 2011-03-10 | パナソニック株式会社 | 半導体素子およびその製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5744994A (en) * | 1996-05-15 | 1998-04-28 | Siliconix Incorporated | Three-terminal power mosfet switch for use as synchronous rectifier or voltage clamp |
JP4197400B2 (ja) | 2001-03-29 | 2008-12-17 | 三菱電機株式会社 | 炭化珪素半導体からなる半導体装置 |
US6940110B2 (en) * | 2002-11-29 | 2005-09-06 | Matsushita Electric Industrial Co., Ltd. | SiC-MISFET and method for fabricating the same |
JP4903439B2 (ja) | 2005-05-31 | 2012-03-28 | 株式会社東芝 | 電界効果トランジスタ |
JP2008017237A (ja) * | 2006-07-07 | 2008-01-24 | Mitsubishi Electric Corp | 電子部品およびその電子部品を用いた電力変換器 |
US7598567B2 (en) | 2006-11-03 | 2009-10-06 | Cree, Inc. | Power switching semiconductor devices including rectifying junction-shunts |
JP2008159927A (ja) * | 2006-12-25 | 2008-07-10 | Toyota Motor Corp | Iii族窒化物半導体装置とその製造方法 |
US8772788B2 (en) * | 2011-05-30 | 2014-07-08 | Panasonic Corporation | Semiconductor element and method of manufacturing thereof |
-
2012
- 2012-09-03 US US14/001,027 patent/US8878194B2/en active Active
- 2012-09-03 CN CN201280009601.8A patent/CN103548142B/zh active Active
- 2012-09-03 WO PCT/JP2012/005565 patent/WO2013035300A1/ja active Application Filing
- 2012-09-03 JP JP2013522045A patent/JP5400252B2/ja active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003163351A (ja) * | 2001-11-27 | 2003-06-06 | Nec Kansai Ltd | 絶縁ゲート型半導体装置およびその製造方法 |
WO2008087763A1 (ja) * | 2007-01-16 | 2008-07-24 | Panasonic Corporation | 半導体装置およびその製造方法 |
JP2008227151A (ja) * | 2007-03-13 | 2008-09-25 | Denso Corp | 炭化珪素半導体装置およびその製造方法 |
JP2009194165A (ja) * | 2008-02-14 | 2009-08-27 | Sumitomo Electric Ind Ltd | 半導体装置およびその製造方法 |
WO2010125819A1 (ja) * | 2009-04-30 | 2010-11-04 | パナソニック株式会社 | 半導体素子、半導体装置および電力変換器 |
WO2011013364A1 (ja) * | 2009-07-28 | 2011-02-03 | パナソニック株式会社 | 半導体素子の製造方法 |
WO2011027540A1 (ja) * | 2009-09-02 | 2011-03-10 | パナソニック株式会社 | 半導体素子およびその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012104856A (ja) * | 2009-04-30 | 2012-05-31 | Panasonic Corp | 半導体素子、半導体装置および電力変換器 |
JP2015060841A (ja) * | 2013-09-17 | 2015-03-30 | 三菱電機株式会社 | 炭化珪素半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN103548142A (zh) | 2014-01-29 |
CN103548142B (zh) | 2016-05-04 |
JPWO2013035300A1 (ja) | 2015-03-23 |
JP5400252B2 (ja) | 2014-01-29 |
US8878194B2 (en) | 2014-11-04 |
US20130328065A1 (en) | 2013-12-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5015361B2 (ja) | 半導体素子および半導体装置 | |
JP6926869B2 (ja) | 半導体装置 | |
JP5592997B2 (ja) | 半導体素子およびその製造方法 | |
US8933466B2 (en) | Semiconductor element | |
JP7357713B2 (ja) | 炭化珪素半導体装置および電力変換装置 | |
JP6678810B2 (ja) | 炭化珪素半導体装置および電力変換装置 | |
JP6617292B2 (ja) | 炭化珪素半導体装置 | |
JP4955128B2 (ja) | 半導体素子、半導体装置および電力変換器 | |
JP6737401B2 (ja) | 炭化珪素半導体装置および電力変換装置 | |
US20140231828A1 (en) | Semiconductor device | |
WO2018037701A1 (ja) | 半導体装置 | |
JP2012099630A (ja) | 半導体装置および電力変換器 | |
JP5400252B2 (ja) | 半導体素子、半導体装置、およびその製造方法 | |
WO2013146329A1 (ja) | 高耐圧半導体装置 | |
JP7410478B2 (ja) | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 | |
JP6976489B2 (ja) | 炭化珪素半導体装置および電力変換装置 | |
KR20210114569A (ko) | 900v급 초접합 모스펫 및 그 제조방법 | |
JP7396000B2 (ja) | 炭化珪素半導体装置 | |
JP7333509B2 (ja) | 炭化珪素半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 201280009601.8 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 12829756 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2013522045 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 14001027 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 12829756 Country of ref document: EP Kind code of ref document: A1 |