WO2011058688A1 - 半導体装置及びノイズ抑制方法 - Google Patents
半導体装置及びノイズ抑制方法 Download PDFInfo
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- WO2011058688A1 WO2011058688A1 PCT/JP2010/005391 JP2010005391W WO2011058688A1 WO 2011058688 A1 WO2011058688 A1 WO 2011058688A1 JP 2010005391 W JP2010005391 W JP 2010005391W WO 2011058688 A1 WO2011058688 A1 WO 2011058688A1
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- Prior art keywords
- conductor
- semiconductor chip
- semiconductor device
- semiconductor
- conductor pattern
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 217
- 238000000034 method Methods 0.000 title claims description 9
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- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present invention relates to a semiconductor device having a semiconductor chip mounted on an object to be mounted and a noise suppression method.
- a semiconductor chip mounting method there is a method in which a semiconductor chip is flip-chip mounted on an interposer substrate.
- the surface of the semiconductor chip on which the wiring layer is formed faces the interposer, and the interposer substrate and the semiconductor chip are connected using bumps.
- Japanese Patent Laid-Open No. 2008-270363 discloses that an EBG is provided on a dielectric substrate in a high-frequency package in which a high-frequency semiconductor is flip-chip mounted on a dielectric substrate. According to this technology, it is said that electromagnetic waves can be attenuated by through holes constituting the EBG, thereby improving high frequency isolation characteristics between the input and output of the high frequency semiconductor.
- connection members such as bumps.
- the connecting member is located in a space between the semiconductor chip and the mounted object. For this reason, the electromagnetic waves radiated
- An object of the present invention is to provide a semiconductor device and a noise suppression method capable of suppressing leakage of electromagnetic waves to the outside through a space between a semiconductor chip and a mounted object.
- a first semiconductor chip mounted on the mounted object A plurality of first conductors repeatedly provided on one of the first semiconductor chip and the mounted object; A second conductor provided on the other of the first semiconductor chip and the mounted object and facing the plurality of first conductors; A plurality of connecting members provided in a space between the mounted object and the first semiconductor chip, and electrically connecting the plurality of first conductors and the second conductor; With A semiconductor device in which the plurality of first conductors are electrically connected to each other via the plurality of connection members and the second conductor is provided.
- a first semiconductor chip mounted on the mounted object A plurality of first conductors repeatedly provided on one of the mounted object and the first semiconductor chip; A second conductor provided on the one side and facing the plurality of first conductors; A plurality of vias connecting the plurality of first conductors to the second conductor; With A semiconductor device in which the plurality of first conductors are electrically connected to each other via the plurality of vias and the second conductor is provided.
- the first conductor is provided on the mounted object on which the semiconductor chip is mounted,
- the semiconductor chip is provided with a second conductor located in a region facing the first conductor,
- an EBG (Electromagnetic Band Gap) structure is formed using the first conductor and the second conductor, and the mounted object
- a noise suppression method for suppressing noise leakage from the space between the first semiconductor chips.
- electromagnetic waves can be prevented from leaking to the outside through the space between the semiconductor chip and the mounted object.
- FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to a first embodiment. It is an expanded sectional view for demonstrating the structure of the connection part of an upper semiconductor chip and a lower semiconductor chip. It is a plane schematic diagram showing the positional relationship between the first region and the EBG structure. It is sectional drawing which shows the structure of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 4th Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 5th Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 6th Embodiment.
- FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment.
- This semiconductor device includes an interposer substrate 400, a plurality of semiconductor chips 600, a semiconductor chip 620, and solder balls 630 as external connection terminals.
- the plurality of semiconductor chips 600 are memory chips and are stacked on one surface of the interposer substrate 400.
- the semiconductor chip 620 is a system LSI and is mounted on the other surface of the interposer substrate 400.
- the semiconductor chip 600 and the semiconductor chip 620 overlap each other in plan view.
- the semiconductor chip 600 is laminated in a direction in which an active surface, that is, a surface on which an element such as a transistor, a multilayer wiring layer, and a rewiring layer are formed faces away from the interposer substrate 400.
- the semiconductor chip 600 has a through electrode (shown in FIG. 2), and is connected to the other semiconductor chip 600 or the interposer substrate 400 located below through the through electrode.
- the through electrode of the lowermost semiconductor chip 600 is connected to the semiconductor chip 620 through a via and a wiring provided in the interposer substrate 400.
- the solder ball 630 is an external connection terminal for connecting the semiconductor device to a mother board or the like, and is provided on the surface of the interposer substrate 400 on which the semiconductor chip 620 is mounted.
- the solder ball 630 and the semiconductor chip 620 are connected to the solder ball 630 through vias and wirings provided in the interposer substrate 400.
- the plurality of semiconductor chips 600 are sealed on one surface of the interposer substrate 400 with a sealing resin 640, and the semiconductor chip 620 is sealed on the other surface of the interposer substrate 400 with a sealing resin 642.
- FIG. 2 is an enlarged cross-sectional view for explaining a configuration of a connection portion between the first semiconductor chip 200 that is the upper semiconductor chip 600 and the second semiconductor chip 100 that is the lower semiconductor chip 600.
- the first semiconductor chip 200 is mounted on the second semiconductor chip 100.
- the first semiconductor chip 200 has a first conductor pattern 222 that is a conductor piece
- the second semiconductor chip 100 has a conductor pattern 122 that is connected to the first conductor pattern 222 that is a conductor piece.
- the conductor pattern 122 is formed in a region overlapping the first conductor pattern 222 that is a conductor piece in plan view.
- the first conductor pattern 222 and conductor pattern 122 that are conductor pieces has a repetitive structure, for example, a periodic structure.
- the first conductor pattern 222 and the second conductor pattern 122 constitute at least a part of an EBG (Electromagnetic Band Band Gap) structure 20. That is, in the present embodiment, the conductor pattern 122 and the first conductor pattern 222 that is a conductor piece have a repeated structure in a region facing each other, and this repeated structure is the second semiconductor chip in the thickness direction. 100 extending from 100 to the first semiconductor chip 200.
- the repetitive structure is connected to the conductor pattern 122 and the first conductor pattern 222 that is a conductor piece having one of them.
- the first conductor pattern 222 which is a conductor piece is formed on the surface of the first semiconductor chip 200 facing the second semiconductor chip 100, and the conductor pattern 122 is the second semiconductor chip 100. Of these, it is formed on the surface facing the first semiconductor chip 200.
- the second semiconductor chip 100 has a multilayer wiring layer 110 and a rewiring layer as a stacked structure in which a conductor layer and an insulating layer are repeatedly stacked on the surface facing the first semiconductor chip 200.
- the rewiring layer has a plurality of island-shaped conductor patterns which are the conductor patterns 122.
- the multilayer wiring layer 110 has a sheet-like first conductor plane 112 and a plurality of vias 114.
- the plurality of island-shaped conductor patterns which are the conductor patterns 122 are periodically arranged.
- the first conductor plane 112 is positioned below the conductor pattern 122 and extends in a region overlapping the conductor pattern 122 in plan view.
- the plurality of vias 114 connect the plurality of island-shaped conductor patterns, which are the conductor patterns 122, to the first conductor plane 112.
- the first conductor plane 112 is connected to either the power line or the ground line, for example, the power line.
- the first conductor pattern 222 which is a conductor piece is an island-like conductor pattern provided in an island shape at each position overlapping with the plurality of island-like conductor patterns which are the conductor patterns 122 in plan view.
- the meaning of the island shape means that the first conductor patterns 222 which are conductor pieces are separated from each other in the layer, and the shape of the first conductor pattern 222 which is the conductor pieces is simple.
- the shape is not limited to a quadrangle or a circle, but may be a shape such as a line or a flat coil around which the wire is wound.
- the first semiconductor chip 200 has an insulating layer 210.
- the insulating layer 210 is located between the first conductor pattern 222 that is a conductor piece and the substrate.
- the insulating layer 210 is provided on the back surface of the substrate of the first semiconductor chip 200.
- the first conductor pattern 222 that is a conductor piece is formed on the insulating layer 210.
- the insulating layer 210 is, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.
- the semiconductor device shown in FIG. 2 includes a plurality of bumps 302 as connection members.
- the bump 302 connects each of the plurality of island-shaped conductor patterns which are the conductor patterns 122 to any of the plurality of island-shaped conductor patterns which are the first conductor patterns 222 which are conductor pieces.
- the first conductor pattern 222 is electrically independent from other conductors included in the first semiconductor chip 200 when viewed in the first semiconductor chip 200. In the present embodiment, the first conductor pattern 222 is not directly connected to other conductors included in the first semiconductor chip 200.
- the plurality of first conductor patterns 222 are electrically connected to each other through the plurality of bumps 302, the plurality of conductor patterns 122, the plurality of vias 114, and the conductor pattern 112.
- the first semiconductor chip 200 has a through electrode 230
- the second semiconductor chip 100 has a through electrode 130.
- One end of the through electrode 230 is connected to the electrode pad 220 as the first external connection terminal, and one end of the through electrode 130 is connected to the electrode pad 120 as the second external connection terminal.
- the electrode pad 220 is formed on the surface of the first semiconductor chip 200 facing the second semiconductor chip 100, that is, the rewiring layer, and is located in the same layer as the first conductor pattern 222 that is a conductor piece.
- the electrode pad 120 is formed on the surface of the second semiconductor chip 100 that faces the first semiconductor chip 200, and is located in the same layer as the conductor pattern 122.
- the electrode pads 220 and 120 are connected to each other via bumps 300 as connection members.
- the through electrodes 230 and 130, the electrode pads 220 and 120, and the bumps 300 are located in the first region 10 that is a region where the EBG structure 20 is not formed.
- the unit cell 50 of the EBG structure 20 includes one island-like conductor pattern of the first conductor pattern 222, which is a conductor piece, one island-like conductor pattern of the bump 302, the conductor pattern 122, and
- the first conductor plane 112 and the substrate of the first semiconductor chip 200 are formed by regions overlapping with the first conductor pattern 222 which is a conductor piece in plan view.
- the unit cells 50 are two-dimensionally repeated in plan view, and are periodically arranged, for example.
- the interval between the same vias is within 1 ⁇ 2 of the wavelength ⁇ of the electromagnetic wave assumed as noise. It is preferable to do so.
- “repetition” includes a case where a part of the configuration is missing in any unit cell 50. When the unit cell 50 has a two-dimensional array, “repetition” includes a case where the unit cell 50 is partially missing. Further, “periodic” includes a case where some of the constituent elements are deviated in some unit cells 50 and a case where the arrangement of some unit cells 50 themselves is deviated.
- the EBG structure 20 is a so-called mushroom type EBG, and the first conductor plane 112 corresponds to a conductor plane connected to the mushroom.
- the via 114, the conductor pattern 122, and the bump 302 correspond to the mushroom inductance portion, and the first conductor pattern 222, which is a conductor piece, corresponds to the mushroom head portion.
- the substrate (third conductor) of the first semiconductor chip 200 corresponds to the second conductor plane facing the mushroom and serves as a ground line.
- the size of each capacitor of the EBG structure 20 is controlled by the distance between the first semiconductor chip 200 and the second semiconductor chip 100 and the size and arrangement of the first conductor pattern 222 which is a conductor piece.
- the inductance component of the EBG structure 20 is controlled by the length and thickness of the via 114. By adjusting these, the band gap band of the EBG structure 20 can be adjusted.
- FIG. 3 is a schematic plan view showing the positional relationship between the first region and the EBG structure 20.
- the first region 10 is provided with through electrodes 230 and 130, electrode pads 220 and 120, and bumps 300.
- the first region 10 is located closer to the center side of the first semiconductor chip 200 than the EBG structure 20.
- the EBG structure 20 is provided so as to surround the first region 10. 2 corresponds to a cross-sectional view taken along the line AA ′ of FIG.
- the EBG structure 20 is formed by using the first conductor pattern 222 and the conductor pattern 122 which are conductor pieces.
- the first conductor pattern 222 that is a conductor piece is formed on the first semiconductor chip 200, and the conductor pattern 122 is formed on the second semiconductor chip 100.
- the EBG structure 20 is formed in the space between the first semiconductor chip 200 and the second semiconductor chip 100. Therefore, noise is prevented from propagating through the space and radiated to the outside.
- this noise for example, there is a bump 300.
- a large number of semiconductor chips 600 are stacked close to each other as in the present embodiment, a plurality of semiconductor chips 600 may be switched at the same time, so that noise radiated from the bumps 300 increases.
- the EBG structure 20 is designed so that the frequency of noise radiated from the bump 300 is included in the band gap of the EBG structure 20, the noise radiated from the bump 300 is reduced to the first semiconductor chip 200 and the second semiconductor chip. Leakage from the space between 100 is suppressed.
- the first conductor pattern 222 that is a conductor piece faces the substrate of the first semiconductor chip 200 that becomes the second conductor plane with the insulating layer 210 interposed therebetween. Therefore, the capacitance component that mainly determines the band gap frequency band in the EBG structure 20 is calculated as a simple parallel plate capacitance formed by the first conductor pattern 222 that is a conductor piece and the substrate of the first semiconductor chip 200. As a result, the capacity of the EBG structure 20 can be easily designed. In particular, in this embodiment, there is a degree of freedom in adjusting the thickness and material of the insulating layer 210, and this effect is increased.
- FIG. 4 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment. This figure corresponds to FIG. 2 in the first embodiment.
- the semiconductor device according to the present embodiment is the first implementation except that the substrate of the first semiconductor chip 200 has an impurity region 202 (third conductor) on the surface facing the second semiconductor chip 100.
- the configuration is similar to that of the semiconductor device according to the embodiment.
- the impurity region 202 extends to a region overlapping with a plurality of island-shaped conductor patterns constituting the first conductor pattern 222 that is a conductor piece in plan view.
- the impurity region 202 corresponds to the second conductor plane in the mushroom type EBG in the EBG structure 20.
- the effective capacitance can be adjusted by adjusting the impurity concentration of the impurity region 202, and the band gap frequency band of the EBG structure 20 can be controlled. Particularly, by reducing the resistance, the capacitance per unit area can be increased, and the band gap frequency band of the EBG structure 20 can be shifted to the low frequency side even in the same area.
- FIG. 5 is a cross-sectional view showing the configuration of the semiconductor device according to the third embodiment. This figure corresponds to FIG. 2 in the first embodiment.
- the semiconductor device according to the present embodiment has the same configuration as the semiconductor device according to the first embodiment except for the following points.
- the second semiconductor chip 100 does not have the via 114.
- the first semiconductor chip 200 has a plurality of vias 212.
- the plurality of vias 212 are provided in the insulating layer 210, and connect the first conductor pattern 222, which is a plurality of island-shaped conductor patterns and conductor pieces, to the substrate of the first semiconductor chip 200.
- the second conductor pattern 122 is not directly connected to other conductors included in the second semiconductor chip 100.
- the EBG structure 20 is a so-called mushroom type EBG, and has a structure that is upside down from the EBG structure 20 shown in the first embodiment. That is, the first conductor plane 112 (third conductor) has a structure facing the mushroom head.
- the substrate of the first semiconductor chip 200 corresponds to a conductor plane connected to the mushroom, the via 212, the first conductor pattern 222, and the bump 302 correspond to an inductance portion of the mushroom, and a second conductor pattern that is a conductor piece. 122 corresponds to the head portion of the mushroom.
- the plurality of second conductor patterns 122 are electrically connected to each other through the plurality of bumps 302, the plurality of first conductor patterns 222, the plurality of vias 212, and the substrate of the first semiconductor chip 200.
- FIG. 6 is a cross-sectional view showing the configuration of the semiconductor device according to the fourth embodiment. This figure corresponds to FIG. 5 in the third embodiment.
- the semiconductor device according to the present embodiment is the same as the semiconductor device according to the third embodiment except that the substrate of the first semiconductor chip 200 has an impurity region 202 on the surface facing the second semiconductor chip 100. It is the same composition as.
- the impurity region 202 extends in a region overlapping with a plurality of island-shaped conductor patterns that constitute the first conductor pattern 222 in plan view.
- the impurity region 202 corresponds to a lower conductor plane in the mushroom type EBG in the EBG structure 20.
- the plurality of second conductor patterns 122 are electrically connected to each other via the plurality of bumps 302, the plurality of first conductor patterns 222, the plurality of vias 212, and the impurity region 202.
- the same effect as that of the third embodiment can be obtained by this embodiment. Further, the resistance of the lower conductor plane in the mushroom-type EBG can be lowered. Thereby, the rise and fall of the band gap frequency band of the EBG structure 20 can be made steep.
- FIG. 7 is a cross-sectional view showing the configuration of the semiconductor device according to the fifth embodiment. This figure corresponds to FIG. 2 in the first embodiment.
- the semiconductor device according to the present embodiment has the same configuration as the semiconductor device according to the first embodiment except for the following points.
- the first semiconductor chip 200 has a conductor pattern 250 (third conductor) and an insulating layer 240.
- the conductor pattern 250 has a sheet shape and is formed on the insulating layer 210.
- the insulating layer 240 is formed on the conductor pattern 250.
- a plurality of island-like conductor patterns constituting the first conductor pattern 222 which is a conductor piece are formed on the insulating layer 240.
- the through electrode 230 is a power supply line or a ground line, and is connected to the electrode pad 220 via the conductor pattern 250 and the conductor pattern 242 provided in the insulating layer 240. That is, the conductor pattern 250 is connected to the through electrode 230.
- the EBG structure 20 is a so-called mushroom type EBG, as in the first embodiment.
- the conductor pattern 250 corresponds to the upper conductor plane.
- the same effect as that of the first embodiment can be obtained. Further, since the capacitance formed by the first conductor pattern 222 and the conductor pattern 250 can be controlled also by the material and thickness of the insulating layer 240, the control of the band gap frequency band becomes easier.
- FIG. 8 is a cross-sectional view showing the configuration of the semiconductor device according to the sixth embodiment. This figure corresponds to FIG. 7 in the seventh embodiment.
- the semiconductor device according to the present embodiment has the same configuration as the semiconductor device according to the seventh embodiment except for the following points.
- the second semiconductor chip 100 does not have the via 114.
- the first semiconductor chip 200 has a plurality of vias 244.
- the plurality of vias 244 are provided in the insulating layer 240, and the second conductor pattern 122 that is a conductor piece is connected to the sheet-like conductor pattern 250 through the bump 302 and the conductor pattern 222.
- the EBG structure 20 is a so-called mushroom-type EBG, and has a structure that is upside down from the EBG structure 20 shown in the first embodiment, as in the third embodiment. That is, the first conductor plane 112 corresponds to a conductor plane facing the mushroom head.
- the conductor pattern 250 of the first semiconductor chip 200 corresponds to the lower conductor plane, and the via 244, the conductor pattern 222, and the bump 302 correspond to the inductance portion of the mushroom, and the second conductor pattern 122 is a conductor piece. Corresponds to the head part of the mushroom.
- the plurality of second conductor patterns 122 are electrically connected to each other via the plurality of bumps 302, the plurality of first conductor patterns 222, the plurality of vias 244, and the conductor pattern 250.
- the same effect as that of the first embodiment can be obtained. Further, it is not necessary to change the multilayer wiring of the second semiconductor chip 100, and an EBG structure can be formed even for a semiconductor chip that is not designed for stacking.
- FIG. 9 is a cross-sectional view showing the configuration of the semiconductor device according to the seventh embodiment.
- This semiconductor device is one of the first to sixth embodiments except that the EBG structure 22 is also provided between the lowermost semiconductor chip 602 of the semiconductor chips 600 and the interposer substrate 400.
- the configuration is the same as that of the semiconductor device shown in FIG.
- the semiconductor chip 602 has the same configuration as that of the first semiconductor chip 200, and includes an insulating layer 210, an electrode pad 220, a first conductor pattern 222 serving as a conductor piece, and a through electrode 230. ing.
- the interposer substrate 400 includes a second conductor pattern 422, a via 414, a plain-shaped conductor pattern 412, and an electrode pad 420.
- the electrode pad 420 is connected to the electrode pad 220 through the bump 300.
- the second conductor pattern 422, the via 414, and the conductor pattern 412 have the same layout as the conductor pattern 122, the via 114, and the first conductor plane 112 in the first embodiment in plan view.
- the conductor pattern 412 is connected to either the power line or the ground line, for example, the power line.
- the unit cell 52 of the EBG structure 22 has a mushroom structure similar to that of the unit cell 50 in the first embodiment.
- the conductor pattern 412 corresponds to a conductor plane connected to the mushroom structure.
- the via 414, the second conductor pattern 422, and the bump 302 correspond to the mushroom inductance portion
- the first conductor pattern 222 which is a conductor piece, corresponds to the mushroom head portion.
- the substrate of the first semiconductor chip 200 corresponds to a conductor plane facing the mushroom head.
- the EBG structure 22 is formed so as to surround the first region 10.
- the plurality of first conductor patterns 222 are electrically connected to each other via the plurality of bumps 302, the plurality of conductor patterns 412, the plurality of vias 414, and the conductor pattern 412.
- the EBG structure 22 is formed by using the first conductor pattern 222 and the second conductor pattern 422 which are conductor pieces.
- the first conductor pattern 222 that is a conductor piece is formed on the semiconductor chip 602, and the second conductor pattern 422 is formed on the interposer substrate 400.
- the EBG structure 22 is formed in the space between the semiconductor chip 602 and the interposer substrate 400. Therefore, noise is prevented from propagating through the space and radiated to the outside.
- FIG. 10 is a cross-sectional view showing the configuration of the semiconductor device according to the eighth embodiment.
- This semiconductor device has the same configuration as the semiconductor device according to the third embodiment shown in FIG. 5 except for the following points.
- the first semiconductor chip 200 and the second semiconductor chip 100 communicate between an inductor (not shown) formed in the first semiconductor chip 200 and an inductor 124 formed in the second semiconductor chip 100.
- an inductor not shown
- the through electrodes 130 and 230 and the bumps 300 shown in FIG. 5 are not formed. Accordingly, the bump 302 is not formed. That is, no conductor that connects the first conductor pattern 222 and the first conductor plane 112 is provided in the space between the first semiconductor chip 200 and the second semiconductor chip 100.
- the EBG structure 20 does not have the second conductor pattern 122 and the via 114.
- the EBG structure 20 is a mushroom-type EBG, but the first conductor plane 112 corresponds to a conductor plane facing the head of the mushroom.
- the substrate of the first semiconductor chip 200 corresponds to a conductor plane connected to the mushroom, the via 212 corresponds to the inductance portion of the mushroom, and the first conductor pattern 222 that is a conductor piece corresponds to the head portion of the mushroom. ing.
- the plurality of first conductor patterns 222 are electrically connected to each other through the plurality of vias 212 and the substrate of the first semiconductor chip 200.
- FIG. 11 is a cross-sectional view showing the configuration of the semiconductor device according to the ninth embodiment.
- This semiconductor device has the same configuration as that of the semiconductor device according to the eighth embodiment shown in FIG. 10 except for the configuration of the EBG structure 20.
- the EBG structure 20 does not have the via 212 and the first conductor pattern 222. Instead, the impurity region 202, the second conductor pattern 122 serving as a conductor piece, and the via 114 are provided.
- the structure of the impurity region 202, the second conductor pattern 122 serving as a conductor piece, and the via 114 is as shown in FIG. 4 in the second embodiment.
- the EBG structure 20 is a mushroom type EBG, and the impurity region 202 corresponds to a conductor plane facing the head of the mushroom.
- the first conductor plane 112 corresponds to a conductor plane connected to the mushroom
- the via 114 corresponds to an inductance portion of the mushroom
- the second conductor pattern 122 which is a conductor piece corresponds to the head portion of the mushroom.
- the plurality of second conductor patterns 122 are electrically connected to each other through the plurality of vias 114 and the conductor pattern 112.
- the same effect as that in the eighth embodiment can be obtained.
- the effective capacitance can be adjusted by the impurity region 202, and the band gap frequency band of the EBG structure 20 can be controlled. Particularly, by reducing the resistance, the capacitance per unit area can be increased, and the band gap frequency band of the EBG structure 20 can be shifted to the low frequency side even in the same area.
- the impurity region 202 may not be provided.
- the substrate of the first semiconductor chip 200 corresponds to the upper conductor plane in the mushroom-type EBG.
- FIG. 12 is a cross-sectional view showing the configuration of the semiconductor device according to the tenth embodiment. This semiconductor device has the same configuration as that of the semiconductor device according to the first embodiment except for the configuration of the EBG structure 20.
- the first conductor pattern 222 (third conductor) is not an island shape but a sheet-like conductor pattern.
- the bump 302 is not provided.
- the EBG structure 20 is a mushroom type EBG, and the first conductor pattern 222 having a plane shape corresponds to a conductor plane facing the head of the mushroom.
- the first conductor plane 112 corresponds to the lower conductor plane, the via 114 corresponds to the mushroom inductance portion, and the second conductor pattern 122 that is a conductor piece corresponds to the mushroom head portion.
- the same effect as that of the first embodiment can be obtained. Moreover, since there are few bump connection parts, the yield of a semiconductor device can be made high.
- FIG. 15 is a cross-sectional view showing the configuration of the semiconductor device according to the eleventh embodiment.
- a semiconductor chip 610 is flip-chip mounted on an interposer substrate 400.
- the semiconductor chip 610 is mounted on the interposer substrate 400 with the surface on which the multilayer wiring layer 650 and the rewiring layer are formed facing downward.
- the electrode pad 628 of the redistribution layer is connected to the electrode pad 420 of the interposer substrate 400 through the bump 300.
- the electrode pad 628, the bump 300 and the electrode pad 420 are located in the first region 14.
- the rewiring layer is provided with a plurality of island-like conductor patterns as the conductor pieces 626.
- the plurality of island-shaped conductor patterns are connected to the island-shaped second conductor pattern 422 of the interposer substrate 400 through the bumps 302.
- the configuration of the interposer substrate 400 is as shown in the seventh embodiment.
- the multilayer wiring layer 650 has a sheet-like conductor plane 616.
- the conductor plane 616 is formed in a wiring layer below the conductor piece 626 and is located in a region overlapping the conductor plane 616 in plan view.
- the unit cell 56 of the EBG structure 24 has the same mushroom structure as the unit cell 50 in the first embodiment.
- the conductor pattern 412 corresponds to a conductor plane connected to the mushroom.
- the via 414, the second conductor pattern 422, and the bump 302 correspond to the mushroom inductance portion
- the conductor piece 626 corresponds to the mushroom head portion.
- the conductor plane 616 corresponds to the conductor plane facing the mushroom head.
- the EBG structure 24 is formed so as to surround the first region 14.
- the EBG structure 24 is formed using the conductor piece 626 and the second conductor pattern 422.
- the conductor piece 626 is formed on the semiconductor chip 610, and the second conductor pattern 422 is formed on the interposer substrate 400.
- the EBG structure 24 is formed in the space between the semiconductor chip 610 and the interposer substrate 400. Therefore, noise is prevented from propagating through the space and radiated to the outside.
- the configuration of the EBG structures 20 to 24 is not limited to the above-described embodiment, and any structure that exhibits characteristics as an EBG can be applied as the EBG structures 20 to 24.
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Abstract
Description
前記被搭載物上に搭載された第1半導体チップと、
前記第1半導体チップ及び前記被搭載物の一方に繰り返し設けられた複数の第1導体と、
前記第1半導体チップ及び前記被搭載物の他方に設けられ、前記複数の第1導体と対向している第2導体と、
前記被搭載物と前記第1半導体チップの間の空間に設けられ、前記複数の第1導体と前記第2導体とを電気的に接続する複数の接続部材と、
を備え、
前記複数の第1導体は、前記複数の接続部材及び前記第2導体を介して互いに導通している半導体装置が提供される。
前記被搭載物上に搭載された第1半導体チップと、
前記被搭載物と前記第1半導体チップの一方に繰り返し設けられた複数の第1導体と、
前記一方に設けられ、前記複数の第1導体と対向している第2導体と、
前記複数の第1導体を前記第2導体に接続する複数のビアと、
を備え、
前記複数の第1導体は、前記複数のビア及び前記第2導体を介して互いに導通している半導体装置が提供される。
前記半導体チップに、前記第1導体と対向する領域に位置する第2導体を設け、
前記第1導体及び前記第2導体の少なくとも一方に繰り返し構造を持たせることにより、前記第1導体及び前記第2導体を用いてEBG(Electromagnetic Band Gap)構造を形成して、前記被搭載物と前記第1半導体チップの間の空間からノイズが漏洩することを抑制するノイズ抑制方法が提供される。
Claims (14)
- 被搭載物と、
前記被搭載物上に搭載された第1半導体チップと、
前記第1半導体チップ及び前記被搭載物の一方に繰り返し設けられた複数の第1導体と、
前記第1半導体チップ及び前記被搭載物の他方に設けられ、前記複数の第1導体と対向している第2導体と、
前記被搭載物と前記第1半導体チップの間の空間に設けられ、前記複数の第1導体と前記第2導体とを電気的に接続する複数の接続部材と、
を備え、
前記複数の第1導体は、前記複数の接続部材及び前記第2導体を介して互いに導通している半導体装置。 - 請求項1に記載の半導体装置において、
前記一方に設けられ、前記第1導体より前記一方の内層側に位置し、前記複数の第1導体と対向しており、前記一方の中において前記第1導体とは電気的に接続していない第3導体と、
を備える半導体装置。 - 請求項1又は2に記載の半導体装置において、
前記第2導体は前記他方の内層に形成されており、
前記他方に設けられ、前記第2導体と前記接続部材とを電気的に接続するビアを供える半導体装置。 - 請求項1~3のいずれか一つに記載の半導体装置において、
前記他方は前記第1半導体チップであり、
前記第2導体は、前記第1半導体チップの基板である半導体装置。 - 請求項1~4のいずれか一つに記載の半導体装置において、
前記第1導体及び前記第2導体は、一方が電源に接続されており、他方がグラウンドに接続されている半導体装置。 - 被搭載物と、
前記被搭載物上に搭載された第1半導体チップと、
前記被搭載物と前記第1半導体チップの一方に繰り返し設けられた複数の第1導体と、
前記一方に設けられ、前記複数の第1導体と対向している第2導体と、
前記複数の第1導体を前記第2導体に接続する複数のビアと、
を備え、
前記複数の第1導体は、前記複数のビア及び前記第2導体を介して互いに導通している半導体装置。 - 請求項6に記載の半導体装置において、
前記一方は第1半導体チップであり、
前記第2導体は、前記第1半導体チップの基板である半導体装置。 - 請求項6または7に記載の半導体装置において、
前記被搭載物と前記第1半導体チップの他方に設けられ、前記複数の第1導体に対向する第3導体を備える半導体装置。 - 請求項1~8のいずれか一つに記載の半導体装置において、
前記第1半導体チップのうち前記被搭載物に対向する面に形成された第1外部接続端子と、
前記被搭載物のうち前記第1半導体チップに対向する面に形成された第2外部接続端子と、
前記第1外部接続端子と前記第2外部接続端子を接続する接続部材と、
をさらに備え、
平面視において前記第1導体及び前記第2導体は、前記第1外部接続端子、前記第2外部接続端子、及び前記接続部材を取り囲むように形成されている半導体装置。 - 請求項1~9のいずれか一つに記載の半導体装置において、
前記第1導体は、前記第1半導体チップのうち前記被搭載物に対向する面に形成されている半導体装置。 - 請求項1~9のいずれか一つに記載の半導体装置において、
前記第1導体は、前記被搭載物のうち前記第1半導体チップに対向する面に形成されている半導体装置。 - 請求項1~11のいずれか一つに記載の半導体装置において、
前記被搭載物はインターポーザ基板である半導体装置。 - 請求項1~11のいずれか一つに記載の半導体装置において、
前記被搭載物は第2半導体チップである半導体装置。 - 半導体チップが搭載される被搭載物に第1導体を設け、
前記半導体チップに、前記第1導体と対向する領域に位置する第2導体を設け、
前記第1導体及び前記第2導体の少なくとも一方に繰り返し構造を持たせることにより、前記第1導体及び前記第2導体を用いてEBG(Electromagnetic Band Gap)構造を形成して、前記被搭載物と前記第1半導体チップの間の空間からノイズが漏洩することを抑制するノイズ抑制方法。
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JP2011540394A JPWO2011058688A1 (ja) | 2009-11-10 | 2010-09-01 | 半導体装置及びノイズ抑制方法 |
CN2010800509774A CN102598262A (zh) | 2009-11-10 | 2010-09-01 | 半导体装置和噪声抑制方法 |
US13/508,073 US20120217653A1 (en) | 2009-11-10 | 2010-09-01 | Semiconductor device and noise suppressing method |
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US8866024B1 (en) * | 2012-06-22 | 2014-10-21 | Altera Corporation | Transceiver power distribution network |
US10468326B2 (en) * | 2013-06-10 | 2019-11-05 | Purdue Research Foundation | Metamaterial systems and methods for their use |
CN103414316B (zh) * | 2013-08-07 | 2016-09-28 | 华进半导体封装先导技术研发中心有限公司 | 一种带电源噪声隔离的芯片封装结构 |
US9355960B2 (en) * | 2013-12-13 | 2016-05-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Electromagnetic bandgap structure for three dimensional ICS |
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