WO2011027465A1 - スイッチドキャパシタ回路およびad変換回路 - Google Patents
スイッチドキャパシタ回路およびad変換回路 Download PDFInfo
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- WO2011027465A1 WO2011027465A1 PCT/JP2009/065528 JP2009065528W WO2011027465A1 WO 2011027465 A1 WO2011027465 A1 WO 2011027465A1 JP 2009065528 W JP2009065528 W JP 2009065528W WO 2011027465 A1 WO2011027465 A1 WO 2011027465A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/44—Sequential comparisons in series-connected stages with change in value of analogue signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
- H03M1/162—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in a single stage, i.e. recirculation type
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
- H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
- H03M1/167—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters
- H03M1/168—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters and delivering the same number of bits
Definitions
- the embodiment referred to in this application relates to a switched capacitor circuit and an AD converter circuit.
- Switched capacitor circuits are widely applied to highly accurate and low power consumption AD (Analog-to-Digital) converters, DA (Digital-to-Analog) converters, filters, and the like.
- AD Analog-to-Digital
- DA Digital-to-Analog
- the switched capacitor circuit has a capacitor, a switch, and an amplifier, and is applied to, for example, an MDAC (Multiplying DAC) as a basic cell of a pipelined AD converter circuit or a cyclic comparison AD converter circuit.
- MDAC Multiplying DAC
- an AD converter circuit and a switched capacitor circuit (MDAC) applied to the AD converter circuit will be described as an example.
- the switched capacitor circuit is also used for a DA converter, a filter, and the like. Can be applied.
- the switched capacitor circuit is applied to, for example, an MDAC of a pipeline type AD converter circuit.
- AD conversion circuits capable of high-precision and high-speed processing have become increasingly important.
- further low power operation and reduction in the area occupied by a circuit are required.
- a switched capacitor circuit having two or more types of operation modes including a first operation mode and a second operation mode in a circuit having a switched capacitor circuit and a load circuit is provided.
- the switched capacitor circuit has two or more internal capacitors, one or more amplifiers, and two or more internal switches.
- the load circuit includes a sampling capacitor provided at a subsequent stage of the switched capacitor circuit and a sampling switch for controlling on / off of connection of the sampling capacitor.
- next-stage sampling switch In the first operation mode of the first half, the next-stage sampling switch is turned off to separate the output voltage of the switched-capacitor circuit from the next-stage sampling capacitor, and the switched-capacitor circuit performs an operation.
- next-stage sampling switch is turned on to sample the output voltage of the switched capacitor circuit into the next-stage sampling capacitor.
- the switched capacitor circuit disconnects one or more internal capacitors by the internal switch in the first operation mode.
- the disclosed switched capacitor circuit and AD conversion circuit can achieve an effect that it is possible to realize high-speed operation, low power consumption of the amplifier, reduction of the area occupied by the circuit, and the like.
- FIG. 1B is a diagram (part 1) for explaining the operation of the AD conversion circuit in FIG. 1A
- FIG. 2B is a diagram (part 2) for explaining the operation of the AD conversion circuit in FIG. 1A
- FIG. 3 is a diagram (part 1) for explaining an example of MDAC and its operation
- FIG. 4 is a diagram (part 2) for explaining an example of MDAC and its operation
- FIG. 3 is a diagram for explaining an example of MDAC and its operation (No. 3).
- FIG. 3B is a diagram (part 1) for explaining the operation of the MDAC in FIG. 3A;
- FIG. 3B is a diagram (part 1) for explaining the operation of the MDAC in FIG. 3A;
- FIG. 3B is a diagram (part 1) for explaining the operation of the MDAC in FIG. 3A;
- FIG. 3B is a diagram (part 1) for explaining the operation of the MDAC in FIG.
- FIG. 3B is a diagram (part 2) for explaining the operation of the MDAC in FIG. 3A;
- FIG. 3C is a diagram (part 3) for explaining the operation of the MDAC in FIG. 3A; It is a circuit diagram which shows an example of MDAC of a 2.5b structure separately at the time of sampling and holding.
- FIG. 4B is a diagram (part 1) for explaining the operation of the MDAC in FIG. 4A;
- FIG. 4B is a second diagram for explaining the operation of the MDAC in FIG. 4A; It is a figure for demonstrating the relationship between the operating speed at the time of the calculation of MDAC, and the consumption current of an operational amplifier. It is a figure which compares and shows the performance at the time of no load of the AD converter circuit of a MDAC system.
- FIG. 3 is a diagram (No. 1) for explaining the MDAC of the first embodiment and its operation
- FIG. 6 is a diagram (No. 2) for explaining the MDAC of the first embodiment and its operation
- FIG. (1) for demonstrating MDAC of 2nd Example, and its operation
- FIG. (2) for demonstrating MDAC of 2nd Example, and its operation
- FIG. 14A It is FIG. (1) for demonstrating MDAC of 3rd Example, and its operation
- FIG. (2) for demonstrating MDAC of 3rd Example, and its operation
- FIG. 3 is a diagram (part 1) for explaining the MDAC of the first embodiment described above and its operation;
- FIG. 6 is a diagram (No.
- FIG. 20B is a diagram (part 1) for explaining the operation of the MDAC in FIG. 20A;
- FIG. 20B is a diagram (part 2) for explaining the operation of the MDAC in FIG. 20A;
- FIG. 20B is a diagram (No. 3) for explaining the operation of the MDAC in FIG. 20A;
- FIG. 21B is a diagram (No. 1) for explaining the operation of the MDAC in FIG.
- FIG. 21A; FIG. 21B is a diagram (part 2) for explaining the operation of the MDAC in FIG. 21A; FIG. 21B is a diagram (No. 3) for explaining the operation of the MDAC in FIG. 21A;
- FIG. 10 is a diagram (No. 1) for describing a basic operation of the MDAC of the second configuration example.
- FIG. 11 is a diagram (No. 2) for describing a basic operation of the MDAC of the second configuration example. It is FIG. (1) for demonstrating MDAC of 4th Example, and its operation
- FIG. 11 is a diagram (No. 1) for describing a basic operation of the MDAC of the second configuration example in the parallel MDAC.
- FIG. 10 is a diagram (No. 2) for describing a basic operation of the MDAC of the second configuration example in the parallel MDAC.
- FIG. (1) for demonstrating MDAC of 5th Example, and its operation
- FIG. (2) for demonstrating MDAC of 5th Example, and its operation
- FIG. 28A shows an example of MDAC of 5th Example.
- FIG. 22A and FIG. 26A It is a figure which compares and shows the performance of MDAC of 4th Example and 5th Example, and MDAC shown to FIG. 22A and FIG. 26A. It is a block diagram which shows roughly an example of the pipeline type AD converter circuit to which MDAC of each Example is applied. It is a block diagram which shows roughly an example of the cyclic comparison type AD converter circuit to which MDAC of each Example is applied.
- FIG. 1A is a block diagram showing an example of an AD conversion circuit
- FIGS. 1B and 1C are diagrams for explaining the operation of the AD conversion circuit of FIG. 1A.
- the AD conversion circuit described with reference to FIGS. 1A to 1C is a pipelined AD conversion circuit.
- MDAC Multiplying DAC: switched capacitor circuit
- a pipelined AD converter circuit 1 includes a sample hold (S / H) circuit 11, an N ⁇ 1 stage circuit (STG-1 to STG- (N-1)) 10-1 ⁇ 10- (N ⁇ 1), a final stage flash AD converter (flash ADC) 12 and a digital correction circuit (code conversion circuit) 13.
- the sample hold circuit 11 samples and holds the input voltage VIN, and the flash ADC 12 outputs the AD converted signal DON to the digital correction circuit 13 as it is.
- the digital correction circuit 13 receives the output signal DON from the flash ADC 12 and the output signals DO1 to DO (N-1) from the respective stage circuits 10-1 to 10- (N-1), and AD converts the input voltage VIN. Output the digital signal DO.
- Each stage circuit 10 includes an MDAC 100 and a sub AD converter (ADC) 110, and the MDAC 100 includes a sub DA converter (DAC) 101 and an analog operation unit 102.
- the sub DAC 101 outputs voltages + VR, 0 (SG), and ⁇ VR to the analog calculation unit 102 in accordance with the signal DA (i) from the sub ADC 110.
- the MDAC100 has a switched capacitor circuit including two or more capacitors (internal capacitors), an amplifier, and a switch (internal switch), and the result of amplifying the input signal VIN (i) and the input signal are AD converted As a result, an analog operation is performed by adding / subtracting a constant multiple of the reference voltage VR using DA (i).
- each MDAC100 (each stage circuit 10-1 to 10- (N-1)) is the next stage circuit (the next stage circuit 10-2 to 10- (N-1) or the flash ADC12. ) As an input signal.
- the signal DO3 (1) is output in the period T (3), and the signal DO4 (1) of the least significant bit (LSB) is output in the period T (4).
- the digital output ADCO (1) binarized by the digital correction circuit 13 is output.
- the most significant bit signal DO1 (2) is output in the period T (2), and the signal DO2 (2) is output in the period T (3).
- the signal DO3 (2) is output in the period T (4), and the least significant bit signal DO4 (2) is output in the period T (5).
- the digital output ADCO (2) binarized by the digital correction circuit 13 is output.
- VO (i) m * [VIN (i) ⁇ ⁇ DA (i) / m ⁇ * VR], and as shown in FIG.
- DO4 is “1, 0, ⁇ 1, 1”
- the digital correction 13 outputs a binarized digital output ADCO “0111”.
- m represents a signal amplification factor.
- Pipelined AD converter circuit 1 can cascade the MDAC 100 and proceed with a plurality of processes in one clock, thereby increasing the delay from the input to the output (latency) but increasing the conversion speed.
- pipeline type AD converter circuit can be designed flexibly with respect to required performance because it is only necessary to define the number of stages according to the required resolution for high accuracy.
- the pipeline AD conversion circuit has a wide coverage of accuracy and conversion speed, it is widely applied to various electronic devices such as digital AV devices and wireless communication circuits.
- FIGS. 2A, 2B, and 2C are diagrams for explaining an example of the MDAC and its operation, and are for explaining the operation of the MDAC in the AD conversion circuit of FIG. 1A.
- FIG. 2B shows the processing of MDAC1 and MDAC2
- FIG. 2C shows only the processing of MDAC1.
- reference symbols OP1 and OP2 indicate operational amplifiers (op amps: amplifiers).
- the conversion timing T is divided into four periods (1) to (4). This is to correspond to the description of each embodiment to be described later. It can be described as an operation in two periods of period (1) + (2) and period (3) + (4).
- MDAC1 and MDAC2 are illustrated in FIG. 2A, the basic operation will be described with respect to the preceding MDAC1, and the subsequent MDAC2 is used to facilitate understanding of the load state of the preceding MDAC1. .
- an MDAC that is an analog signal processing circuit is a switched capacitor (SC) circuit including a capacitor (C), a switch (SW), and an operational amplifier (OP: operational amplifier).
- SC switched capacitor
- SW switch
- OP operational amplifier
- an analog operation result VO1 is output by applying a DAC output voltage using a comparison result of the operational amplifier OP1, the capacitors C1 n1 and C1 n2, and ADC1.
- the hold capacitor C1 H (C1 n2 ) is connected between the output terminal and the negative input terminal of the operational amplifier OP1, and the operation capacitor C1 MDAC (C1 n1 ) is sub-DA converted. It is connected between the output terminal of the device (101) and the negative input terminal of the operational amplifier OP1. Then, the output terminal of the operational amplifier OP1, so that the sampling capacitor of the next stage MDAC2 C2 S (C2 n1 + C2 n2) is connected.
- FIG. 3A is a circuit diagram showing an example of an MDAC having a 1.5b configuration separately for sampling and holding
- FIGS. 3B, 3C, and 3D are diagrams for explaining the operation of the MDAC of FIG. 3A. is there.
- reference symbol SWC1 receives signals MCLK and SHSEL and outputs a switch control signal
- 101 is a sub DAC
- CMP1 and CMO2 are comparators
- DFF1 and DFF2 are flip-flops
- L01 is The logic part is shown.
- the switch control unit SWC1 The control signals for the switches SWS1A / 1B / 2A / 2B and SWADCIN are set to high level “H” to turn on these switches.
- the comparators CMP1 and CMP2 compare the input voltage VIN given as the comparison voltage V CMP with the reference voltages 1/4 * VR and ⁇ 1 / 4 * VR, respectively, and flip the comparison result.
- the comparatators CMP1 and CMP2 compare the input voltage VIN given as the comparison voltage V CMP with the reference voltages 1/4 * VR and ⁇ 1 / 4 * VR, respectively, and flip the comparison result.
- DFF1 and DFF2 To the input terminals of DFF1 and DFF2.
- the switch control unit SWC1 sets the control signal for the switch SWH1A / 1B / 2B and the CLKADC to low level “L”. As a result, the switches SWH1A / 1B / 2B are turned off, and the flip-flops DFF1 and DFF2 are disabled.
- the switch control unit during MDAC1 hold (H: calculation) SWC1 sets the control signals for the switches SWS1A / 1B / 2A / 2B and SWADCIN to “L” to turn off these switches.
- the switch control unit SWC1 sets the control signal for the switch SWH1A / 1B / 2B and the CLKADC to “H”.
- the switches SWH1A / 1B / 2B are turned on, and the flip-flops DFF1, DFF2 are enabled to latch and hold the input data.
- the output signals of the flip-flops DFF1 and DFF2 are supplied to the logic unit LO1, and the logic unit LO1 outputs the digital output DO and the addition / subtraction coefficient DA1.
- the addition / subtraction coefficient DA1 is supplied to the sub DAC 101.
- the hold capacitor C1 H (C1 n2 ) is connected between the output terminal and the negative input terminal of the operational amplifier OP1, and the operation capacitor C1 MDAC (C1 n1 ) is sub-DA converted. It is connected between the output terminal of the device (101) and the negative input terminal of the operational amplifier OP1.
- VIN is-(1/4) * VR ⁇ VIN ⁇ -VR
- DO is -01
- DA is -1
- VDA1 is -VR
- VO is 2 * VIN + VR.
- FIG. 4A is a circuit diagram showing an example of an MDAC having a 2.5b configuration separately at the time of sampling and at the time of holding
- FIGS. 4B and 4C are diagrams for explaining the operation of the MDAC of FIG. 4A.
- the capacitor C1 n1 in the MDAC having the 2.5b configuration is divided into two capacitors C1 n11 and C1 n12 , Sub DACs 101a and 101b and switches SWS11B and SWH11B; SWS12B and SWH12B are provided.
- the two comparators CMP1 and CMP2 in FIG. 3A are changed to six comparators CMP11 to CMP16, and the voltages 5/8 * VR, 3/8 * VR, and 1/8 * are divided by 6 for each of the comparators CMP11 to CMP16.
- VR, -1 / 8 * VR, -3 / 8 * VR, -5 / 8 * VR are applied and compared with the input voltage VIN (V CMP ).
- the output signals of the comparators CMP11 to CMP16 are supplied to the logic part LO1 via the flip-flops DFF11 to DFF16.
- the logic part LO1 outputs two addition / subtraction coefficients DA1 and DA2 and a digital output DO that are supplied to the sub DACs 101a and 101b. To do.
- the switch control unit SWC1 sets the control signals for the switches SWS1A / 2B / 11B / 12BB and SWADCIN to “H” and turns on these switches.
- the switch control unit SWC1 sets the control signal for the switch SWH1A / 2B / 11B / 12B and the CLKADC to “L” to turn off the switch SWH1A / 2B / 11B / 12B, and also the flip-flop Disable DFF11 to DFF16.
- the switch control unit SWC1 sets the control signals for the switches SWS1A / 2B / 11B / 12B and SWADCIN to “L” to turn off these switches. .
- the switch control unit SWC1 sets the control signal for the switch SWH1A / 2B / 11B / 12B and the CLKADC to “H”.
- the switches SWH1A / 2B / 11B / 12B are turned on, and the flip-flops DFF1 to DFF16 are enabled to latch and hold the input data.
- the flip-flops DFF1 to DFF16 capture and hold the output signals of the corresponding comparators CMP11 to CMP16.
- the output signals of the flip-flops DFF1 to DFF16 are supplied to the logic unit LO1, and the logic unit LO1 outputs the digital output DO and the addition / subtraction coefficients DA1 and DA2.
- the addition / subtraction coefficients DA1 and DA2 are supplied to the sub DACs 101b and 101a, respectively.
- the input voltage VIN (comparison voltage V CMP ), digital output DO, addition / subtraction coefficients DA1, DA2, output voltages VDA1 and VDA2 of the sub DACs 101b and 101a, and the output voltage VO of the operational amplifier OP1 are shown in FIGS. 4C and 4D, respectively. It becomes like this.
- FIG. 5 is a diagram for explaining the relationship between the operation speed at the time of MDAC calculation (at the time of hold) and the consumption current of the operational amplifier, and shows the relationship between the calculation operation speed at the calculation operation of MDAC1 and the consumption current of the amplifier. is there.
- the necessary conversion time T 1 has the following relationship (see Equation (5)).
- TL 1 * I AMP and T2 S * I AMP have the following relationship (see equations (7) and (8)).
- sampling capacitor C1 S of the MDAC is defined by thermal noise (kT / C)
- this is set to a constant value C0 as a reference value in FIGS. 3A to 3D and FIGS. 4A to 4C.
- the signal amplification factor (m) is expressed by C1 S / C1 H.
- the sampling capacitor C2 S of the next-stage MDAC may generally be (1 / m) times the signal amplification factor (m), but it is necessary to consider the limitation on the minimum capacitance value. That is, it is necessary to consider the following two types (A) and (B).
- the capacitance of MDAC is all equal in each stage.
- the conversion time (see T * I AMP ) is more than twice as long as there is a load compared to the case of no load.
- the capacity C2 S shown in FIG. 5 is not scaled. It can be seen that the speed reduction becomes extremely large.
- the conversion speed (calculation speed) is 6 times or more lower when the capacity C2 S is not scaled than when there is no load. That is, it can be seen that if the power supply current of the amplifier (op-amp) is made constant as compared with the non-added case, the time required for the conversion is more than twice (the conversion speed is less than half).
- the MDAC switched capacitor circuit
- a conversion (calculation) time more than twice as long as when there is no load is required.
- the speed decrease greatly increases without scaling, and the speed decrease increases as the number of bits increases.
- FIG. 7 is a diagram for explaining the operation of MDAC (switched capacitor circuit: SC circuit) at the time of analog operation and sampling at the next stage.
- MDAC switched capacitor circuit: SC circuit
- the operation at the time of the above-described analog operation (hold operation) will be described in a simplified manner. It is.
- the hold capacitor C1 H is connected between the output terminal and the negative input terminal of the operational amplifier OP1
- the operation capacitor C1 MDAC is connected to the output terminal of the sub DA converter (101) and the negative input of the operational amplifier OP1.
- the sampling capacitor C2 S of the SC circuit 12 at the next stage is connected to the output terminal of the operational amplifier OP1.
- the power supply current of the amplifier must be increased because the sampling capacitor C2 S of the SC circuit 12 at the next stage is connected as the load of the operational amplifier OP1.
- FIG. 8A is a diagram for explaining an analog calculation operation in the MDAC of the first embodiment
- FIG. 8B is a diagram for explaining a next-stage sampling operation in the MDAC of the first embodiment.
- the analog operation (hold operation) is divided into two modes, the first half operation mode and the second half operation mode. .
- the feedback capacitor ⁇ is set to “1” of all feedback by disconnecting the calculation capacitor C 1 MDAC, and the sampling capacitor C 2 of the SC circuit 12 in the next stage is set. Accumulate the output voltage of S.
- each embodiment basically realizes the high-speed operation of the SC circuit itself, and the SC circuit and the SC circuit. It can be widely applied to various circuits to which is applied.
- FIGS. 9A and 9B are diagrams for explaining the MDAC of the first embodiment and its operation, in which the conversion timing T is divided into four periods (1) to (4).
- MDAC1 and ADC1 are not yet connected.
- MDAC2 performs an operation (hold: H).
- the output of the operational amplifier OP2 of the MDAC2 is disconnected from the load (C3 S ) of the MDAC (MDAC3) at the next stage in the same manner as the operational amplifier OP1 of the MDAC1 in the period (3) described later, and is unloaded.
- ADC1 is used, MDAC1 performs sampling (S), and MDAC2 performs calculation (full feedback calculation).
- the operation of MDAC1 in the period (3) corresponds to the operation of SC11 (MDAC1) described with reference to FIG. 8A.
- the capacitor C1 n1 becomes the calculation capacitor C1 MDAC
- the capacitor C1 n2 becomes the hold capacitor C1 H.
- MDAC1 performs calculation (full feedback calculation), ADC2 is used, and MDAC2 performs sampling.
- the operation of MDAC1 in the period (4) corresponds to the operation of SC11 (MDAC1) described with reference to FIG. 8B.
- the MDAC of the first embodiment it is possible to speed up the operation, reduce the power consumption of the amplifier, reduce the occupied area of the circuit, and the like.
- the ratio of the period (1) and the period (2) (the period (3) and the period (4)) can be appropriately changed in consideration of the operation speed of the circuit, the size of the capacity to be used, and the like.
- the power supply current of the operational amplifier OP1 can be set to a different value.
- the control of the power supply current of the operational amplifier in is not limited to the first embodiment, and can also be performed in the following second to fifth embodiments.
- FIG. 10A is a circuit diagram showing an example of the MDAC of the first embodiment
- FIG. 10B is a diagram for explaining the operation of the MDAC of FIG. 10A.
- FIGS. 10A and 10B show an MDAC (MDAC1) having a 1.5b configuration.
- the MDAC1 circuit in each period (1) to (4) in FIG. 10B corresponds to the MDAC1 in (1) to (4) in FIG. 9A described above.
- reference symbol SWC1 receives signals MCLK and SHSEL and outputs a switch control signal
- 101 is a sub DAC
- CMP1 and CMO2 are comparators
- DFF1 and DFF2 are flip-flops
- L01 is The logic part is shown.
- the MDAC1 (switched capacitor circuit) includes capacitors C1 n1 and C1 n2 (two or more internal capacitors), an operational amplifier OP1 (one or more amplifiers), and a switch SWS1A / 1B / 2A / 2B. , SWH1A / 1B, SWH2A / 2B, SWADCIN (two or more internal switches).
- both MDAC1s are the same, but the control of each switch by the switch control unit SWC1 is different.
- the switch control unit SWC1 sets the control signals for the switches SWS1A / 1B / 2A / 2B, SWH1A / 1B, SWH2A / 2B and SWADCIN to low level “L”. Turn off.
- the signal CLKADC is “L”, and the flip-flops DFF1 and DFF2 are disabled.
- the switch control unit SWC1 sets the control signals for the switches SWS1A / 1B / 2A / 2B and SWADCIN to high level “H” and turns on these switches. Note that the control signal and the signal CLKADC for the switches SWH1A / 1B and SWH2A / 2B remain “L”.
- the switches SWS1A / 1B / 2A / 2B and SWADCIN are turned on, and the MDAC1 performs sampling (S). That is, the input voltage VIN (comparison voltage V CMP ) is compared with the reference voltages 1/4 * VR and ⁇ 1 / 4 * VR by the comparators CMP1 and CMP2, respectively, and the comparison result is the input terminal of the flip-flops DFF1 and DFF2. To be supplied.
- the input voltage VIN is sampled by the sampling capacitor C1 S (C1 n1 + C1 n2 ).
- the switch control unit SWC1 sets the control signals for the switches SWS1A / 1B / 2A / 2B and SWADCIN to “L” to turn off these switches, and switches SWH1A / 1B, SWH2A / Set the control signal for 2B to “H”.
- the signal CLKADC is set to “H”.
- the comparison results of the comparators CMP1 and CMP2 are captured and held in the flip-flops DFF1 and DFF2.
- the operational amplifier OP1 since the operational amplifier OP1 performs the same control for the next-stage MDAC2, the operational amplifier OP1 is disconnected from the load (C2 S ) of the next-stage MDAC2 and becomes a no-load state.
- the hold capacitor C1 H (C1 n2 ) is connected between the output terminal and the negative input terminal of the operational amplifier OP1
- the operation capacitor C1 MDAC (C1 n1 ) is connected to the output terminal of the sub DA converter 101 and the negative terminal of the operational amplifier OP1. Connected between input terminals.
- the operational amplifier OP1 operates in a no-load state with its output terminal disconnected from the sampling capacitor C2 S (C2 n1 + C2 n2 ) of the next stage MDAC2.
- the switch control unit SWC1 changes the control signal for the switch SWH1A / 1B from “H” to “L” to turn off the switch SWH1A / 1B, and the capacitor C1 n1 is disconnected.
- the other switches SWS1A / 1B / 2A / 2B, SWADCIN, and SWH2A / 2B are held in the same state as the period (3).
- MDAC1 performs full feedback calculation. Note that the operation of the MDAC 1 in the period (4) is as described with reference to FIGS. 8B, 9A, and 9B.
- the MDAC of the first embodiment is about 33% when scaling is present, compared to the MDAC of FIG. 3A.
- the speed can be increased by about 40% or the power consumption can be reduced.
- the operation speed (T) of the MDAC when the operation speed (T) of the MDAC is the same, the power consumption (the operational amplifier current is I AMP ) can be reduced, and the operational amplifier current (I AMP : power consumption) is made the same. In this case, the operation speed (T) of the MDAC can be increased.
- the switching timing (clock cycle) is changed so that the first or first half processing time by MDAC is lengthened and the last or second half processing time is shortened. It can also be designed as follows.
- the MDAC having the 2.5b configuration modified from the first embodiment is approximately 43% when the scaling is present and the scaling is compared with the MDAC in FIG. 4A. It can be seen that the speed can be increased by about 63% or the power consumption can be reduced when there is nothing.
- T * I AMP the size can be appropriately designed by paying attention to the operation speed (T) or the power consumption (I AMP ). Adjustment of the periods (1) to (4) can also be performed as appropriate.
- the time of the first half operation mode (period (3)) and the second half operation mode (period (4)) and the feedback amount ⁇ in the first half and second half operation modes at the time of analog calculation of MDAC (MDAC1) are expressed as TL.
- the value of the MDAC of the first embodiment is m. You can see that it is twice as fast.
- the switching timing of each switch is controlled by the switch control unit SWC1, but for example, the duty ratio of the periods (1), (2) (periods (3), (4)) is controlled, or By controlling the power supply current of the operational amplifier, the performance closer to the ideal value can be exhibited.
- FIG. 13A and FIG. 13B are diagrams for explaining the MDAC of the second embodiment and its operation, and the conversion timing T is divided into four periods (1) to (4) for explanation.
- MDAC1 is unused but ADC1 is used. It has become.
- MDAC2 performs an operation (hold: H).
- the ADC1 is used in the period (1), and the addition / subtraction coefficient DA1 is supplied to a sub DAC in the MDAC 1 (not shown) (see, for example, the sub DAC 101 in FIG. 3A).
- the supply of the addition / subtraction coefficient DA1 from the ADC1 to the sub DAC is performed in the period (2).
- MDAC1 performs sampling (S), and MDAC2 performs calculation (full feedback calculation). Note that ADC1 continues to operate during the period (1).
- ADC2 is used in period (3), and the addition / subtraction coefficient DA2 is supplied to the sub DAC in MDAC2 (not shown).
- MDAC1 performs calculation (full feedback calculation), and MDAC2 performs sampling. Note that ADC2 continues to operate in the period (3).
- the MDAC of the second embodiment uses, for example, the fact that the analog operation result of MDAC1 is output in two periods (1) and (2), and the comparator (for example, FIG. The conversion speed of the comparator CMP1, CMP2) at 10A is relaxed.
- the comparators CMP1 and CMP2 of the ADC1 may perform the comparison process using the final data of the period (1) over the entire period (2).
- the demand for high-speed operation for CMP2 can be relaxed.
- FIG. 14A is a circuit diagram showing an example of the MDAC of the second embodiment
- FIG. 14B is a diagram for explaining the operation of the MDAC of FIG. 14A.
- 14A and 14B show an MDAC (MDAC1) having a 1.5b configuration.
- circuit of MDAC1 in each period (1) to (4) in FIG. 14B corresponds to MDAC1 in (1) to (4) of FIG. 13A described above.
- the MDAC (MDAC1) of the second embodiment is provided between the switch SWASCIN and ADC1 with respect to the MDAC1 of the first embodiment, and the period In (1), a capacitor C S (CMP) that functions as the sampling capacitor C S is provided.
- CMP capacitor C S
- the MDAC1 (switched capacitor circuit) includes capacitors C1 n1 , C1 n2 , C S (CMP) (two or more internal capacitors), an operational amplifier OP1 (one or more amplifiers), and a switch SWS1A. / 1B / 2A / 2B, SWH1A / 1B, SWH2A / 2B, SWADCIN (two or more internal switches).
- the switch control unit SWC1 sets the control signals for the switches SWS1A / 1B / 2A / 2B, SWH1A / 1B, SWH2A / 2B to low level “L”, and turns off these switches.
- the signal CLKADC is “L”, and the flip-flops DFF1 and DFF2 are disabled.
- the switch SWADCIN is turned on in the period (1) and the comparison voltage V CMP (input voltage VIN) is applied to the sampling capacitor C S (CMP). ) Is the point to be sampled.
- the switch control unit SWC1 sets the control signals for the switches SWS1A / 1B / 2A / 2B to “H” to turn on these switches, and the control signal for the switch SWADCIN Set to “L” to turn off switch SWADCIN. Note that the control signal and the signal CLKADC for the switches SWH1A / 1B and SWH2A / 2B remain “L”.
- the comparators CMP1 and CMP2 of the ADC1 use the comparison voltage V CMP sampled in the capacitor C S (CMP) in the period (1) as the reference voltages 1/4 * VR and -1 //, respectively, from the beginning of the period (2). Compared with 4 * VR, the comparison result is supplied to the input terminals of flip-flops DFF1 and DFF2.
- the switch control unit SWC1 sets the control signals for the switches SWS1A / 1B / 2A / 2B and SWADCIN to “L” to turn off these switches, and switches SWH1A / 1B, SWH2A /
- the control signal for 2B is set to “H” to turn on these switches.
- the signal CLKADC is also set to “H”.
- the comparison results of the comparators CMP1 and CMP2 are captured and held in the flip-flops DFF1 and DFF2.
- the operational amplifier OP1 is disconnected from the load (C2 S ) of the next-stage MDAC2, but its output voltage VO1 is sampled by the sampling C S (CMP) of the next-stage ADC2.
- the switch control unit SWC1 changes the control signal for the switch SWH1A / 1B from “H” to “L” to turn off the switch SWH1A / 1B, and the capacitor C1 n1 is disconnected.
- FIGS. 15A and 15B are diagrams for explaining the MDAC of the third embodiment and its operation, in which the conversion timing T is divided into four periods (1) to (4). Further, FIG. 16A is a circuit diagram showing an example of the MDAC of the third embodiment, and FIG. 16B is a diagram for explaining the operation of the MDAC of FIG. 16A.
- the third embodiment is different from the comparator CMP1, in the first embodiment.
- CMP2 is shared by one comparator CMP0.
- two switches SELADC1 and 2SELADC2 are provided in ADAC1, and one comparator CMP0 is provided in periods (1) and (2).
- the comparators CMP1 and CMP2 of the first embodiment are used.
- the common signals CLKADC supplied to the clock terminals of the flip-flops DFF1 and 2DFF2 of the first embodiment are individually controlled as activation signals of the flip-flops DFF1 and DFF2 as separate signals CLKADC1 and CLKADC2.
- MDAC1 is not used but ADC1 is used, and MDAC2 performs an operation (H).
- the use of the ADC1 in the period (1) is, for example, for comparing the reference voltage 1/4 * VR with the input voltage VIN (comparison voltage V CMP ) and outputting it to the flip-flop DFF1.
- ADC1 is used, MDAC1 performs sampling (S), and MDAC2 performs operations.
- the use of the ADC1 in the period (2) is, for example, for comparing the reference voltage-1 / 4 * VR with the comparison voltage V CMP and outputting the comparison voltage to the flip-flop DFF2.
- the comparison between the reference voltage 1/4 * VR and the comparison voltage V CMP is performed by using the ADC1 in the period (1), and the reference voltage -1 // is compared by using the ADC1 in the period (2). 4 * VR and comparison voltage V CMP are compared. The same comparator is shared for comparison between the reference voltage and the comparison voltage in the periods (1) and (2).
- MDAC2 is unused but ADC2 is used, and MDAC1 performs computation.
- ADC2 is used, MDAC1 performs an operation, and MDAC2 performs sampling.
- periods (3) and (4) are for comparing a reference voltage different from the comparison voltage in the next stage, and the same comparator is shared.
- the comparison voltage V CMP is applied to one input of the comparator CMP0 of the ADC1, and the reference voltage 1/4 via the switch SELADC1 is applied to the other input.
- VR and the reference voltage -1 / 4 * VR via the switch SELADC2 are selectively applied.
- the switches SELADC1 and SELADC2 are controlled by signals from the switch control unit SWC1.
- MDAC1 switched capacitor circuit
- C1 n1 and C1 n2 two or more internal capacitors
- OP1 one or more amplifiers
- SWS1A / 1B / 2A / 2B switches
- SWH1A / 1B switches between SWH2A / 2B
- SWADCIN switches
- the switch control unit SWC1 sets the control signals for the switches SWS1A / 1B / 2A / 2B, SWH1A / 1B, SWH2A / 2B, SELADC2 to “L” and turns off these switches.
- the comparison voltage V CMP input voltage VIN
- the reference voltage 1/4 * VR via the switch SELADC1 are applied to the comparator CMP0, and these voltages are compared and the comparison result is output.
- the signals CLKADC1 and CLKADC2 are both “L”, and the flip-flops DFF1 and DFF2 are disabled.
- the switch control unit SWC1 sets the control signals for the switches SWS1A / 1B / 2A / 2B and SELADC2 to “H” to turn on these switches, and also controls the switch SELADC1. Set the signal to “L” to turn off the switch SELADC1. The other switches remain in section (1).
- the signal CLKADC1 changes from “L” to “H”, thereby enabling the flip-flop DFF1, and the comparison voltage V CMP by the comparator CMP0 and the reference voltage 1/4 * VR Capture and hold the comparison results.
- the switch SELADC1 is turned off and the switch SELADC2 is turned on, so that the comparator CMP0 is applied with the comparison voltage V CMP and the reference voltage applied via the switch SELADC1 ⁇ 1 / 4 *. VR will be compared.
- the switch control unit SWC1 sets the control signals for the switches SWS1A / 1B / 2A / 2B, SWADCIN, SELADC2 to “L” to turn off these switches, and switches SWH1A / 1B, Set the control signal for SWH2A / 2B to “H” to turn on these switches.
- the signal CLKADC2 changes from “L” to “H”, thereby enabling the flip-flop DFF2, and the comparison voltage V CMP by the comparator CMP0 and the reference voltage ⁇ 1 / 4 * VR Capture and hold the comparison result with.
- the logic unit L01 compares the comparison voltage V CMP held by the flip-flop DFF1 with the reference voltage 1/4 * VR, and the comparison voltage V CMP held by the flip-flop DFF2 and the reference voltage.
- the comparison result with -1 / 4 * VR is received and a predetermined logical operation is performed.
- the switch control unit SWC1 changes the control signal for the switch SWH1A / 1B from “H” to “L” and turns off the switch SWH1A / 1B. Since other operations in each of the periods (1) to (4) are clear from the description of the first and second embodiments, the description thereof is omitted.
- the hardware configuration can be reduced by sharing the comparator in ADC1.
- FIG. 17 is a diagram comparing the number of comparators required for the MDAC of the third embodiment and each of the MDACs shown in FIGS. 3A and 4A.
- the comparators CMP1 and CMP2 in the ADC can be made into one comparator CMP0, and the number of comparators can be reduced. It is possible to halve.
- the comparators CMP11 to CMP16 (six) in FIG. 14A are reduced to half by applying the third embodiment described above. be able to.
- FIG. 17 is merely an example, and the present invention is not limited to this example. If the signal amplification factor m becomes larger (multi-bit), the effect of reducing the number of comparators becomes larger.
- FIGS. 18A and 18B are diagrams for explaining another example of the MDAC and its operation, in which an operational amplifier is shared in order to reduce the area and power consumption of the pipelined AD converter circuit. .
- the operational amplifier (OP1) is used as the operational amplifier OP2 of the MDAC2, and the period (3) + ( In 4), the operational amplifier OP1 is used as the operational amplifier OP1 of MDAC1. It is possible to share the comparators of the sub A / D converters ADC1 and ADC2 (not shown).
- the capacity of the MDAC (the operation capacities C1 n1 and C1 n2 of the MDAC1 and the operation capacities C2 n1 and C2 n2 of the MDAC2) must be provided individually and cannot be shared.
- 19A and 19B are diagrams for explaining the MDAC of the first embodiment described above and its operation.
- one operational amplifier (OP1) is shared by the front and rear MDACs (for example, MDAC1 and MDAC2). Is possible.
- the MDAC of the third embodiment utilizes the fact that the operation output of MDAC is output twice (H (1) and H (2)). Thus, it was possible to reduce the number of comparators.
- C1 n1 is unused in the periods (1) and (4)
- C1 n2 is unused in the period (1)
- C2 n1 is unused in the period (2 )
- And (3) are unused
- C2 n2 is unused in period (3).
- the MDACs of the fourth and fifth embodiments to be described later use the unused periods of the MDAC capacitances (C1 n1 and C1 n2 of MDAC1 and C2 n1 and C2 n2 of MDAC2) to share the capacitance. It is.
- an MDAC having a 1.5b configuration may have two types of circuit configurations, a first configuration example (type I) and a second configuration example (type II).
- FIG. 20A is a circuit diagram showing a first configuration example (type I) of an MDAC having a 1.5b configuration separately for sampling and holding, and FIGS. 20B to 20D are for explaining the operation of the MDAC of FIG. 20A.
- FIG. 20A is a circuit diagram showing a first configuration example (type I) of an MDAC having a 1.5b configuration separately for sampling and holding, and FIGS. 20B to 20D are for explaining the operation of the MDAC of FIG. 20A.
- FIG. 21A is a circuit diagram showing a second configuration example (type II) of an MDAC having a 1.5b configuration separately for sampling and holding, and FIGS. 21B to 21D illustrate the operation of the MDAC of FIG. 21A. It is a figure for doing.
- FIGS. 20A to 20D correspond to FIGS. 3A to 3D described above, and correspond to those in which ADC1 (sub AD converter) and related signals in MDAC1 of FIGS. 3A to 3D are omitted.
- the MDACs of the first to third embodiments shown in FIGS. 8A to 17 are based on the type I circuit. However, the MDAC of the first to third embodiments is of type II. It is also possible to apply to a circuit.
- the switch control unit SWC1 The control signal for the switches SWS1A / 11B / 12B / 2B is set to high level “H” to turn on these switches.
- the switch control unit SWC1 sets the control signal for the switch SWH1A / 11B / 12B / 2B to the low level “L”. As a result, the switch SWH1A / 11B / 12B / 2B is turned off.
- the switch control unit during MDAC1 hold (H: calculation) SWC1 sets the control signal for the switches SWS1A / 11B / 12B / 2B to “L” and turns off these switches.
- the switch control unit SWC1 sets the control signal for the switch SWH1A / 11B / 12B / 2B to “H”. As a result, the switch SWH1A / 11B / 12B / 2B is turned on.
- VIN comparison voltage V CMP
- V CMP comparison voltage
- DA1 addition / subtraction coefficient
- FIG. 21D the output voltage VDA1 of the DAC 101 and the output voltage VO of the operational amplifier OP1 are as shown in FIG. 21D.
- 21C and 21D are the same as FIGS. 20C and 20D described above.
- FIG. 22A and 22B are diagrams for explaining the basic operation of the MDAC of the second configuration example (type II), and show the above-described FIG. 21A and FIG. 21B more easily.
- MDAC two MDACs
- OP1 operational amplifier
- C1 H C0 / m
- C2 H C0 / m.
- m represents a signal amplification factor.
- the operational amplifier (OP1: common operational amplifier) is shared by two MDACs (MDAC1, MDAC2).
- MDAC1, MDAC2 the operational amplifier
- the capacitance cannot be shared by MDAC1 and MDAC2.
- the capacitance is shared between MDAC1 and MDAC2, and the occupied area of the switched capacitor circuit or AD converter circuit is further reduced.
- the MDAC of the fourth embodiment is the MDAC of the second configuration example (type II), and the conversion timing T is set to four periods (1) to (1) in the same manner as the MDAC of the first to third embodiments. Control is divided into (4).
- the MDAC of the fourth embodiment not only the operational amplifier (OP1: common operational amplifier) is shared by two MDACs (MDAC1, MDAC2).
- the capacity (CSC: shared capacity) is also shared by the two MDACs.
- the capacitor CSC is used as C2 MDAC in the period (1), used as C1 S in the period (2), and used as C1 MDAC in the period (3). Then, it has come to be used as C2 S in the period (4).
- the hold capacitors C1 H and C2 H need to be provided exclusively for MDAC1 and MDAC2, but the sampling capacitors C1 S and C2 S of MDAC1 and MDAC2 and the operation are required. It can be seen that the capacitors C1 MDAC and C2 MDAC can be shared.
- the operational amplifier (shared operational amplifier OP1) is shared by MDAC1 and MDAC2, as described with reference to FIGS. 22A and 22B.
- the subsequent MDAC sampling capacitance (for example, the capacitance C2 S of MDAC2) is more than the sampling capacitance of the previous MDAC (for example, the capacitance C1 S of MDAC1).
- the value may be small. That is, the sampling capacitance (C2 S) in the subsequent stage of MDAC may be using a portion of the sampling volume of the preceding MDAC (C1 S).
- FIG. 24A is a circuit diagram showing an example of the MDAC of the fourth embodiment
- FIG. 24B is a diagram for explaining the operation of the MDAC of FIG. 24A.
- reference characters CSC11 and CSC12 indicate a shared capacity (CSC) used in common
- CH1 indicates a hold capacity (C1 H ) when used as the first MDAC (MDAC1)
- CH2 indicates The hold capacitance (C2 H ) when used as the second MDAC (MDAC2) is shown.
- the MDAC0 (switched capacitor circuit) includes capacitors CH1, CH2, CSC11, CSC12 (two or more internal capacitors) and an operational amplifier OP0 (one or more amplifiers). Further, MDAC0 has switches SWVIN1, SWVIN2, SWSC1A / 11B / 12B, SWHC1A / 11B / 12B, SWHH1A / 1B, SWSH2A / 2B, and SWHH2A / 2B (two or more internal switches).
- the switch control unit SWC1 sets the control signals for the switches SWVIN1, SWHC1A / 11B / 12B, and SWHH2A / 2B to high level “H” and turns on these switches.
- the switch control unit SWC1 sets the control signals for the switches SWVIN2, SWSC1A / 11B / 12B, SWSH1A / 1B, SWHH1A / 1B, SWSH2A / 2B to low level “L” and turns off these switches. To do.
- the capacitor CSC11 functions as the operation capacitor C2 MDAC of the second MDAC (MDAC2).
- the capacity CH2 will be connected as a hold capacitor C2 H of the second MDAC (MDAC2).
- the switch control unit SWC1 sets the control signals for the switches SWSC1A / 11B / 12B and SWSH1A / 1B to “H” to turn on these switches, and the switch SWHC1A / 11B Set the control signal for / 12B to "L” to turn off these switches.
- the control signals for the other switches SWVIN1, SWVIN2, SWHH1A / 1B, SWSH2A / 2B, SWHH2A / 2B are maintained at the same level as in the period (1).
- the capacitors CSC11 and CSC12 function as the sampling capacitor C1 S of the first MDAC (MDAC1).
- the capacity CH2 maintains a connection as a hold capacitor C2 H of the second MDAC (MDAC2), The capacitor CH1 will be reset.
- the switch control unit SWC1 sets the control signals for the switches SWVIN2, SWHC1A / 11B / 12B, and SWHH1A / 1B to “H” to turn on these switches. Further, the switch control unit SWC1 sets the control signal for the switches SWVIN1, SWSC1A / 11B / 12B, SWSH1A / 1B, SWSH2A / 2B to “L” and turns off these switches. Note that in the period (3), the control signal for the switch SWSH2A / 2B is maintained at the same level as in the period (2).
- the capacitor CSC11 functions as the operation capacitor C1 MDAC of the first MDAC (MDAC1).
- the capacitor CH1 is connected as the hold capacitor C1 H of the first MDAC (MDAC1).
- the switch control unit SWC1 sets the control signals for the switches SWSC1A / 11B / 12B and SWSH2A / 2B to “H” to turn on these switches, and the switch SWHC1A / 11B / The control signal for 12B is set to “L” to turn off these switches.
- the capacitors CSC11 and CSC12 function as the sampling capacitor C2 S of the second MDAC (MDAC2).
- the capacity CH1 maintains the connection of the hold capacitor C1 H of the first MDAC (MDAC1), The capacitor CH2 will be reset.
- the operational amplifier OP1 (shared operational amplifier) can be shared by MDAC1 and MDAC2, as described with reference to FIGS. 22A and 22B.
- the MDAC of the fourth embodiment not only the operational amplifier but also the capacitors (CSC: CSC11, CSC12) can be shared by the two MDACs, and the switched capacitor circuit or the AD conversion circuit is occupied. The area can be further reduced.
- the MDAC of the fourth embodiment can be scaled.
- the sampling capacitor C2 S in the subsequent MDAC2 may be smaller than the sampling capacitor C1 S in the preceding MDAC1.
- sampling capacitor C2 S of MDAC2 it is also possible to use a portion of the sampling capacitor C1 S of the preceding MDAC1.
- This double-sampling AD converter circuit provides two MDACs in parallel and operates in an interleaved manner, thereby doubling the conversion speed of the AD converter circuit with the same power consumption.
- FIG. 25 is a diagram for explaining the basic operation of the MDAC of the first configuration example (type I) in the parallel MDAC.
- the double-sampling MDAC parallel MDAC
- the double-sampling MDAC corresponds to, for example, the above-described processing in which two MDACs (MDAC1, MDAC2) that perform processing in time order are provided in parallel.
- the double-sampling MDAC shown in FIG. 25 has, for example, the relationship between MDAC1 and MDAC2 in FIG. 18A described above as MDAC1 (E: even mode) and It may be replaced with MDAC1 (O: odd (Odd) mode).
- MDAC1 (E) samples the input voltage VIN1 (E) with the sampling capacitance C1 n1 (E) + C1 n2 (E), and MDAC1 (O) performs an operation.
- the operation capacity in MDAC1 (O) is C1 n1 (O), and the hold capacity is C1 n2 (O).
- the operational amplifier OP1 (O) of MDAC1 (O) that performs the calculation is used, and the operational amplifier OP1 (E) of MDAC1 (E) that performs the sampling is not used.
- MDAC1 (E) performs calculation
- MDAC1 (O) performs sampling sampling with input voltage VIN1 (O) with sampling capacitance C1 n1 (O) + C1 n2 (O).
- MDAC1 (E) the computation capacity in MDAC1 (E) is C1 n1 (E), and the hold capacity is C1 n2 (E).
- the operational amplifier OP1 (E) of MDAC1 (E) that performs the calculation is used, and the operational amplifier OP1 (O) of MDAC1 (O) that performs the sampling is not used.
- the operational amplifiers (OP1 (E), OP1 (O)) are shared (OP1 (E)) divided into period (1) + (2) and period (3) + (4).
- the operational amplifier can be shared by MDAC1 (E) and MDAC1 (O), the capacity cannot be shared.
- FIG. 26A and FIG. 26B are diagrams for explaining the basic operation of the MDAC of the second configuration example (type II) in the parallel MDAC.
- the double sampling MDAC (parallel MDAC) of FIGS. 26A and 26B for example, the relationship between MDAC1 and MDAC2 in FIGS. 22A and 22B described above may be replaced with MDAC1 (E) and MDAC1 (O).
- the operational amplifier (OP1: common operational amplifier) is shared by two MDACs (MDAC1 (E), MDAC1 (O)).
- MDAC1 (E) MDAC1 (O)
- the capacitance cannot be shared by MDAC1 (E) and MDAC1 (O).
- FIGS. 27A and 27B are diagrams for explaining the MDAC of the fifth embodiment and its operation, and are the MDAC of the second configuration example (type II).
- the MDAC of the fifth embodiment is obtained by applying the MDAC of the fourth embodiment described above to a double sampling MDAC (parallel MDAC). That is, in FIGS. 27A to 28B, the relationship between MDAC1 and MDAC2 in FIGS. 23A to 24B described above may be replaced with MDAC1 (E) and MDAC1 (O).
- the capacitor CSC is used as C1 MDAC (O) in the period (1), is used as C1 S (E) in the period (2), and is used in the period (3). It is used as C1 MDAC (E), and is used as C1 S (O) in period (4).
- the hold capacitors C1 H (E) and C1 H (O) need to be provided exclusively for MDAC1 (E) and MDAC1 (O).
- the sampling capacitors C1 S (E) and C1 S (O) and the operation capacitors C1 MDAC (E) and C1 MDAC (O) of the MDAC1 (E) and MDAC1 (O) can be shared.
- the operational amplifier (shared operational amplifier OP1 (E)) is shared by MDAC1 (E) and MDAC1 (O) as described above.
- FIG. 28A is a circuit diagram showing an example of the MDAC of the fifth embodiment
- FIG. 28B is a diagram for explaining the operation of the MDAC of FIG. 28A.
- reference numerals CSC11 and CSC12 indicate a shared capacity (CSC) used in common, and CH1E indicates a hold capacity (C1 H (E)) when used as the first MDAC (MDAC1 (E)). CH1O indicates a hold capacitor (C1 H (O)) when used as the second MDAC (MDAC1 (O)).
- the MDAC0 (switched capacitor circuit) has capacitors CH1E, CH1O, CSC11, 2CSC12 (two or more internal capacitors) and an operational amplifier OP0 (one or more amplifiers). Further, MDAC0 includes switches SWVIN1E, SWVIN1O, SWSC1A / 11B / 12B, SWHC1A / 11B / 12B, SWSH1A / 1B, SWHH1A / 1B, SWSH2A / 2B, and SWHH2A / 2B (two or more internal switches).
- the switch control unit SWC1 sets the control signals for the switches SWVIN1E, SWHC1A / 11B / 12B, SWHH2A / 2B to high level “H” and turns on these switches.
- the switch control unit SWC1 sets the control signals for the switches SWVIN1O, SWSC1A / 11B / 12B, SWSH1A / 1B, SWHH1A / 1B, SWSH2A / 2B to low level “L” and turns off these switches. To do.
- the capacitor CSC11 functions as the operation capacitor C1 MDAC (O) of the second MDAC (MDAC1 (O)).
- the capacitor CH1O is connected as the hold capacitor C1 H (O) of the second MDAC (MDAC1 (O)).
- the switch control unit SWC1 sets the control signals for the switches SWSC1A / 11B / 12B and SWSH1A / 1B to “H” to turn on these switches, and the switch SWHC1A / 11B Set the control signal for / 12B to "L” to turn off these switches.
- the control signals for the other switches SWVIN1E, SWVIN1O, SWHH1A / 1B, SWSH2A / 2B, SWHH2A / 2B are maintained at the same level as in the period (1).
- the capacitors CSC11 and CSC12 function as the sampling capacitor C1 S (E) of the first MDAC (MDAC1 (E)).
- the capacitor CH1O maintains the connection as the hold capacitor C1 H (O) of the second MDAC (MDAC1 (O)), and the capacitor CH1E is reset.
- the switch control unit SWC1 sets the control signals for the switches SWVIN1O, SWHC1A / 11B / 12B, SWHH1A / 1B to “H” and turns on these switches. Further, the switch control unit SWC1 sets the control signals for the switches SWVIN1E, SWSC1A / 11B / 12B, SWSH1A / 1B, SWSH2A / 2B to “L” and turns off these switches. Note that in the period (3), the control signal for the switch SWSH2A / 2B is maintained at the same level as in the period (2).
- the capacitor CSC11 functions as the operation capacitor C1 MDAC (E) of the first MDAC (MDAC1 (E)).
- the capacitor CH1E is connected as the hold capacitor C1 H (E) of the first MDAC (MDAC1 (E)).
- the switch control unit SWC1 sets the control signals for the switches SWSC1A / 11B / 12B and SWSH2A / 2B to “H” to turn on these switches, and the switch SWHC1A / 11B / The control signal for 12B is set to “L” to turn off these switches.
- the control signals for the other switches SWVIN1E, SWVIN1O, SWSH1A / 1B, SWHH1A / 1B, SWHH2A / 2B are maintained at the same level as in the period (3).
- the capacitors CSC11 and CSC12 function as the sampling capacitor C1 S (O) of the second MDAC (MDAC1 (O)).
- the capacitor CH1E maintains the connection as the hold capacitor C1 H (E) of the first MDAC (MDAC1 (E)), and the capacitor CH1O is reset.
- the operational amplifier OP1 (E) can be shared by MDAC1 (E) and MDAC1 (O) as described above.
- the MDAC of the fifth embodiment not only the operational amplifier but also the capacitors (CSC: CSC11, CSC12) can be shared by the two MDACs, and the switched capacitor circuit or the AD conversion circuit is occupied. The area can be further reduced.
- FIG. 29 is a diagram comparing the performances of the MDACs of the fourth and fifth embodiments and the MDAC shown in FIGS. 22A and 26A.
- the MDAC of the fourth embodiment reduces the capacity by about 33% in the case of no scaling and by about 22% in the case of scaling by sharing the capacity. That is, it can be seen that the area occupied by the capacitor (circuit) can be reduced.
- FIG. 30 is a block diagram schematically showing an example of a pipelined AD converter circuit to which the MDAC of each embodiment is applied
- FIG. 31 is a cyclic comparison AD converter circuit to which the MDAC of each embodiment is applied. It is a block diagram which shows an example of.
- the MDACs of the first to fifth embodiments described above are, for example, the cascade-connected MDAC circuits 202-1 to 202- (n ⁇ ) in the pipelined AD converter circuit 200 as shown in FIG. Applicable to 1).
- a pipelined AD converter circuit 200 includes a sample hold (S / H) circuit 201, an n-1 stage MDAC circuit (MDAC) 202-1 to 202- (n-1), and a final one.
- S / H sample hold
- MDAC n-1 stage MDAC circuit
- a flash ADC 203 and a logic operation circuit (digital correction circuit) 204 are provided.
- the sample hold circuit 201 receives and holds the input voltage VIN, and supplies the output signal to the MDAC circuits 202-1 to 202- (n-1).
- the logic operation circuit 204 receives the output signals DB (1) to DB (n-1) of the MDAC circuits 202-1 to 202- (n-1) and the output signal DB (n) of the flash ADC 203 at the final stage, An output code (ADC output) obtained by digitally converting the input voltage VIN with a resolution corresponding to the number of stages of the MDAC circuit is output.
- the MDACs of the first to fifth embodiments described above can be applied to, for example, the MDAC circuit 303 in the cyclic comparison type AD converter circuit 300 as shown in FIG.
- the cyclic comparison AD conversion circuit 300 includes a switch 301, a sample hold (S / H) circuit 302, an MDAC circuit (MDAC) 303, and a logic operation circuit 304. Note that the sample hold circuit 302 can be omitted without being provided.
- the output signal DB (i) that is circulated from the MDAC circuit 303 is supplied to the logic operation circuit 304, and the logic operation circuit 304 outputs the digitally converted output code with a resolution corresponding to the number of times of circulation through the MDAC circuit. (ADC output) is output.
- the MDAC switching capacitor circuit of the first to fifth embodiments has been described in detail above.
- the number and connection of switches and capacitors in each MDAC, or each switch controlled by the switch control unit The switching timing and the like can be changed variously.
- switched capacitor circuits of the first to fifth embodiments are widely applied not only to pipeline AD converter circuits and cyclic comparison AD converter circuits but also to various circuits such as DA converters and filters. Needless to say, you can.
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Abstract
Description
10, 10-1~10-(N-1) ステージ回路
11, 201, 302 サンプルホールド(S/H)回路
12, 203 フラッシュAD変換器(フラッシュADC)
13, 204, 304 デジタル補正回路(コード変換回路,ロジック演算回路)
100, 202-1~202-(n-1), 303 MDAC回路(MDAC)
101 サブDAC
102 アナログ演算部
110 サブAD変換器(ADC)
300 循環比較型AD変換回路
301 スイッチ
Claims (20)
- 2つ以上の内部容量,1つ以上の増幅器および2つ以上の内部スイッチを有するスイッチドキャパシタ回路と、
該スイッチドキャパシタ回路の次段に設けられたサンプリング容量および該サンプリング容量の接続をオン/オフ制御するサンプリングスイッチを有する負荷回路と、を有する回路において、
第1動作モードおよび第2動作モードを含む2種類以上の動作モードを有し、
前半の前記第1動作モードでは、前記次段のサンプリングスイッチをオフして、前記スイッチドキャパシタ回路の出力電圧と前記次段のサンプリング容量を切り離すと共に、前記スイッチドキャパシタ回路で演算を行い、
後半の前記第2動作モードでは、前記次段のサンプリングスイッチをオンして、前記スイッチドキャパシタ回路の出力電圧を前記次段のサンプリング容量にサンプリングし、そして、
前記スイッチドキャパシタ回路は、前記第1動作モードにおいて、1つ以上の前記内部容量を前記内部スイッチで切り離すことを特徴とするスイッチドキャパシタ回路。 - 請求項1に記載のスイッチドキャパシタ回路において、
前記増幅器は、演算増幅器であり、
前記第2動作モードでは、前記内部容量のうち,前記第1動作モードで前記演算増幅器の入力端子と出力端子間に接続した第1内部容量以外の全ての内部容量を、前記内部スイッチで切り離すことにより、前記演算増幅器が帰還量『1』の全帰還動作を行うことを特徴とするスイッチドキャパシタ回路。 - 請求項1または2に記載のスイッチドキャパシタ回路において、
前記第1動作モードの動作時間および前記第2動作モードの動作時間の比率を変化させることを特徴とするスイッチドキャパシタ回路。 - 請求項1または2に記載のスイッチドキャパシタ回路において、
前記第1動作モードおよび前記第2動作モードでの前記増幅器の電源電流を異なる値に設定することを特徴とするスイッチドキャパシタ回路。 - 請求項1~4のいずれか1項に記載のスイッチドキャパシタ回路と、
入力する信号をAD変換する1個以上の比較器を含むサブAD変換器と、を有するAD変換回路であって、
前記スイッチドキャパシタ回路は、前記入力する信号を増幅した第1信号および前記入力する信号をAD変換した第2信号に基づいた加減算係数を使用して、参照電圧を加減算した結果を出力することを特徴するAD変換回路。 - 請求項5に記載のAD変換回路おいて、
前記スイッチドキャパシタ回路の前記内部容量は、前記増幅器の入力端子と出力端子間に接続された第1内部容量と、前記増幅器の前記入力端子と前記参照電圧を供給する参照電源線に接続された第2内部容量と、を含み、
前記第1内部容量は、前記第1動作モードおよび前記第2動作モードで前記増幅器の前記入力端子と前記出力端子間に接続され、
前記第2内部容量は、前記第1動作モードでは前記増幅器の前記入力端子と前記参照電源線間に前記内部スイッチのうちの第1内部スイッチを介して接続され、前記第2動作モードでは前記第1内部スイッチにより前記増幅器の前記入力端子から切断されることを特徴するAD変換回路。 - 請求項5または6に記載のAD変換回路において、
前記比較器は、前記入力する信号の電圧を、前段のスイッチドキャパシタ回路の前記第2動作モードの出力結果を使用して比較判定することを特徴するAD変換回路。 - 請求項5または6に記載のAD変換回路において、
前記比較器は、前記入力する信号の電圧を、前段のスイッチドキャパシタ回路の前記第1動作モードの出力結果を使用して比較判定することを特徴するAD変換回路。 - 請求項5または6に記載のAD変換回路において、
前記比較器は、前記入力する信号の電圧を、前段のスイッチドキャパシタ回路の前記第1動作モードおよび前記第2動作モードの両方の出力結果を使用して比較判定し、
前記第2動作モードで前記比較器が前記入力する信号の電圧を比較する比較レベルを、前記第1動作モードで前記比較器が前記入力する信号の電圧を比較した比較結果に応じて切り換えることを特徴するAD変換回路。 - 請求項9に記載のAD変換回路において、
前記比較器の1個以上は、前記第1動作モードおよび前記第2動作モードの両方で使用されることを特徴するAD変換回路。 - 請求項1~4のいずれか1項に記載のスイッチドキャパシタ回路を、第1スイッチドキャパシタ回路および第2スイッチドキャパシタ回路として2つ有するスイッチドキャパシタ回路群であって、
前記第1および第2スイッチドキャパシタ回路は、前記第1動作モードおよび前記第2動作モードのアナログ演算を異なる期間に実行し、
前記第1および第2スイッチドキャパシタ回路における前記内部容量は、サンプリング動作時にそれぞれ入力する信号をサンプリングするサンプリング容量群、並びに、アナログ演算を行う第1および第2アナログ演算容量群を有し、
前記アナログ演算の前記第1動作モード時は、前記第1アナログ演算容量群および前記第2アナログ演算容量群が前記増幅器に接続され、前記アナログ演算の前記第2動作モード時は、前記第1アナログ演算容量群が前記増幅器から切り離されると共に、前記サンプリング容量群が前記第1アナログ演算容量群に全て含まれるか、または、同じ容量群であり、
前記第1スイッチドキャパシタ回路の前記サンプリング容量群、および、前記第2スイッチドキャパシタ回路の前記サンプリング容量群の少なくとも一部を共用化することを特徴とするスイッチドキャパシタ回路群。 - 請求項11に記載のスイッチドキャパシタ回路群において、
前記第1スイッチドキャパシタ回路における前記サンプリング容量群および前記第1アナログ演算容量群は、前記第2スイッチドキャパシタ回路における前記サンプリング容量群および前記第1アナログ演算容量群と同じ容量群であり、
前記第1スイッチドキャパシタ回路における前記第2アナログ演算容量群および前記第2スイッチドキャパシタ回路における前記第2アナログ演算容量群は、それぞれ前記第1および第2スイッチドキャパシタ回路の各サンプリング動作時に、その両端の電荷を一定値にリセットすることを特徴とスイッチドキャパシタ回路群。 - 請求項5~10のいずれか1項に記載のAD変換回路を、第1AD変換回路および第2AD変換回路として2つ有するAD変換回路群であって、
前記第1AD変換回路における第1スイッチドキャパシタ回路並びに前記第2AD変換回路における第2スイッチドキャパシタ回路は、前記第1動作モードおよび前記第2動作モードのアナログ演算を異なる期間に実行し、
前記第1および第2AD変換回路における前記内部容量は、サンプリング動作時にそれぞれ入力する信号をサンプリングするサンプリング容量群、並びに、アナログ演算を行う第1および第2アナログ演算容量群を有し、
前記アナログ演算の前記第1動作モード時は、前記第1アナログ演算容量群および前記第2アナログ演算容量群が前記増幅器に接続され、前記アナログ演算の前記第2動作モード時は、前記第1アナログ演算容量群が前記増幅器から切り離されると共に、前記サンプリング容量群が前記第1アナログ演算容量群に全て含まれるか、または、同じ容量群であり、
前記第1スイッチドキャパシタ回路の前記サンプリング容量群、および、前記第2スイッチドキャパシタ回路の前記サンプリング容量群の少なくとも一部を共用化することを特徴とするAD変換回路群。 - 請求項13に記載のAD変換回路群において、
前記第1スイッチドキャパシタ回路における前記サンプリング容量群および前記第1アナログ演算容量群は、前記第2スイッチドキャパシタ回路における前記サンプリング容量群および前記第1アナログ演算容量群と同じ容量群であり、
前記第1スイッチドキャパシタ回路における前記第2アナログ演算容量群および前記第2スイッチドキャパシタ回路における前記第2アナログ演算容量群は、それぞれ前記第1および第2スイッチドキャパシタ回路の各サンプリング動作時に、その両端の電荷を一定値にリセットすることを特徴とAD変換回路群。 - 請求項14に記載のAD変換回路群において、
前記第1および第2AD変換回路は、2個従属接続されていることを特徴とするAD変換回路群。 - 請求項14に記載のAD変換回路群において、
前記第1および第2AD変換回路は、2個並列接続されていることを特徴とするAD変換回路群。 - 請求項15または16に記載のAD変換回路群において、
前記第1および第2AD変換回路における前記増幅器を共用化することを特徴とするAD変換回路群。 - 請求項5~10のいずれか1項に記載のAD変換回路を2個以上有し、そのうちの2個のAD変換回路を従属接続するか、或いは、請求項15に記載のAD変換回路群を1個以上有することを特徴とするパイプライン型AD変換回路。
- 請求項16または17に記載のAD変換回路群を1個以上有して並列処理を行うことを特徴とする循環比較型AD変換回路。
- 請求項5~10のいずれか1項に記載のAD変換回路を1個以上有し、
1つのアナログ入力のAD変換動作において、少なくとも前記AD変換回路を2回以上使用することを特徴とするAD変換回路。
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CN200980159985XA CN102484479A (zh) | 2009-09-04 | 2009-09-04 | 开关电容电路以及ad转换电路 |
EP09848996.6A EP2475102A4 (en) | 2009-09-04 | 2009-09-04 | CAPACITOR SWITCHING CIRCUIT AND ANALOG / DIGITAL CONVERSION CIRCUIT |
KR1020127005809A KR101409657B1 (ko) | 2009-09-04 | 2009-09-04 | 스위치드 커패시터 회로, ad 변환 회로, 스위치드 커패시터 회로군, 및 ad 변환 회로군 |
JP2011529755A JP5252085B2 (ja) | 2009-09-04 | 2009-09-04 | スイッチドキャパシタ回路およびad変換回路 |
PCT/JP2009/065528 WO2011027465A1 (ja) | 2009-09-04 | 2009-09-04 | スイッチドキャパシタ回路およびad変換回路 |
US13/411,018 US8629797B2 (en) | 2009-09-04 | 2012-03-02 | Switched capacitor circuit and stage circuit for AD converter |
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US20120162000A1 (en) | 2012-06-28 |
CN102484479A (zh) | 2012-05-30 |
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EP2475102A4 (en) | 2013-06-05 |
KR101409657B1 (ko) | 2014-06-18 |
US8629797B2 (en) | 2014-01-14 |
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