WO2010111848A1 - 像素电极结构 - Google Patents

像素电极结构 Download PDF

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Publication number
WO2010111848A1
WO2010111848A1 PCT/CN2009/072496 CN2009072496W WO2010111848A1 WO 2010111848 A1 WO2010111848 A1 WO 2010111848A1 CN 2009072496 W CN2009072496 W CN 2009072496W WO 2010111848 A1 WO2010111848 A1 WO 2010111848A1
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Prior art keywords
line
pixel electrode
common electrode
thin film
disposed
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PCT/CN2009/072496
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English (en)
French (fr)
Inventor
柳智忠
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深超光电（深圳）有限公司
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Priority to US12/868,752 priority Critical patent/US8188479B2/en
Publication of WO2010111848A1 publication Critical patent/WO2010111848A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136263—Line defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136272—Auxiliary lines

Definitions

  • the present invention relates to an electrode structure, and more particularly to a pixel electrode structure of high display quality. ⁇ Background technique ⁇
  • each pixel of a single gate circuit structure has a thin film transistor (TFT) 10 whose gate is connected to a horizontal scanning line 12, a source Connected to the data line 14 in the vertical direction, the drain is connected to the pixel electrode, and the thin film transistors 10 in the adjacent row have the data lines 14 connected to each other.
  • TFT thin film transistor
  • the single-gate circuit architecture described above has a relatively high cost of being consumed on the source chip due to the excessive number of data lines 14, and in order to reduce the cost, the latter technology proposes a dual-gate circuit architecture. That is, as shown in FIG. 2, the adjacent two rows of thin film transistors 16 share the same data line 18, so that the number of data lines 18 used can be reduced, thereby reducing the manufacturing cost of the source chip.
  • a virtual line 20 is further disposed between the adjacent data lines 18, and a signal opposite to the polarity of the data line 18 is provided on the virtual line 20, such as This will make the panel look better.
  • the present invention has been made in view of the above drawbacks to provide a pixel electrode structure of high display quality for solving the problems existing in the prior art.
  • a main object of the present invention is to provide a pixel electrode structure in which a common electrode line is disposed between adjacent scan lines to reduce the number of common electrode lines, thereby increasing the pixel aperture ratio of the panel.
  • Another object of the present invention is to provide a pixel electrode structure in which a common electrode line and a dummy line are short-circuited to have better stability of a common signal, and when the data line is broken, a laser repair method can be utilized. Then connect with the virtual line to improve the pass rate.
  • the present invention provides a pixel electrode structure including a transparent substrate, wherein the substrate is provided with a data line, a common electrode line and first and second array pixels, and the first array of pixels forms a first thin film transistor, first a pixel electrode and a first scan line, wherein the common electrode line is disposed on a side of the first scan line, the second array of pixels forms a second thin film transistor, a second pixel electrode, and a second scan line, and the common electrode line is further disposed on a second scan line side, and a first and a second through hole are respectively disposed on the common electrode line, respectively contacting the extended ends of the first and second thin film transistors, and a dummy line is disposed on a side of the data line, and the third The through holes are located on the virtual line and the common electrode line.
  • 1 and 2 are circuit diagrams of a display panel of the prior art.
  • FIG. 3 is a schematic structural diagram of a circuit layout of a display panel of the prior art.
  • 4 is a schematic view showing the circuit layout structure of the first embodiment of the liquid crystal display panel of the present invention.
  • Fig. 5 is a partially enlarged schematic view showing the circuit layout structure of the first embodiment of the liquid crystal display panel of the present invention.
  • Figure 6 is a cross-sectional view showing the structure of the circuit layout structure of Figure 5 taken along line A-A.
  • Figure 7 is a cross-sectional view showing the structure of the circuit layout structure of Figure 5 taken along line B-B.
  • FIG. 8 is a schematic diagram showing the circuit layout structure of a second embodiment of the liquid crystal display panel of the present invention.
  • Fig. 9 is a partially enlarged schematic view showing the circuit layout structure of the second embodiment of the liquid crystal display panel of the present invention.
  • FIG. 10 is a circuit diagram of a liquid crystal display panel of the present invention.
  • FIG. 11 is a circuit diagram of a dual gate pixel unit of the present invention.
  • FIG. 12 is a schematic diagram of a circuit after laser repair of the liquid crystal display panel of the present invention.
  • the liquid crystal display panel provided by the present invention mainly utilizes a dummy line which has been provided in the prior art and a common electrode line connected to a common electrode of the thin film transistor terminal for short-circuit design.
  • FIG. 5 is an enlarged schematic view showing the structure of the pixel electrode in the dashed box of FIG. 4, in which all components in the dashed box include two electrode layers 50.
  • the formed pixel electrode, the two thin film transistors 26, 28 and the wiring therearound, the thin film transistors 26, 28 are N-type
  • FIG. 4 is a pixel electrode structure in the dashed box, using scan lines ( Gate line 30.
  • An array liquid crystal display panel in which a data line 32, a dummy line 34, and a common electrode line 36 are connected to each other.
  • the pixel electrode structures are arranged in a matrix on the display panel, the pixel electrode structures of the same row share the same data line 32 and the dummy line 34, and the pixel electrode structures of the same column share the same scan line 30 and are common.
  • Electrode line 36 The connection relationship and positional relationship of the components in each pixel electrode structure are the same. Now, taking a pixel electrode structure as an example, the following is stated.
  • FIG. 6 is the circuit of FIG. A cross-sectional view along the line AA and tangent in the layout structure, which can express the upper and lower stacking relationship of the components contained in Figure 5.
  • 5 is a pixel electrode structure, which mainly includes a transparent substrate 38, a first array of pixels and a second array of pixels, and the first and second array pixels respectively form first and second thin film transistors 26, 28, first and second pixel electrodes 33, 35, and first and second scan lines 60, 62.
  • the first and second array pixels are formed by the first metal layer 40, the insulating layer 42, the semiconductor layer 44, the second metal layer 46, the protective layer 48, and the electrode layer 50, and the liquid crystal layer is disposed on the electrode layer 50.
  • the protective layer 48 is an insulating material
  • the material of the insulating layer 42 is silicon nitride
  • the material of the electrode layer 50 is indium tin oxide (IT0)
  • the electrode layer 50 is formed with the first and second thin film transistors 26, 28
  • the first and second pixel electrodes 33, 35 are connected, respectively.
  • the first metal layer 40 is disposed on the transparent substrate 38 to form the gate 56 of the first thin film transistor 26, the gate 58 of the second thin film transistor 28, the first scan line 60, the second scan line 62, and the first scan.
  • the common electrode line 64 between the lower portion of the line 60 and the upper portion of the second scan line 62, but when the first metal layer 40 is formed, simultaneously the first and second scan lines 60, 62 and the first and second films, respectively.
  • the gates 56, 58 of the transistors 26, 28 are formed as connected lines.
  • an insulating layer 42 is formed thereon, and the insulating layer 42 is insulated as a gate on the first and second thin film transistors 26, 28. Floor.
  • the insulating layer 42 is provided with a semiconductor layer 44.
  • the semiconductor layer 44 is divided into upper and lower layers, and the lower layer is an amorphous silicon layer (a-Si) 52, which is directly disposed on the insulating layer 42, and the upper layer is n + doped non-
  • the second metal layer 46 is disposed on the ohmic contact layer 54 and the insulating layer 42 to form the sources 66, 68 of the first and second thin film transistors 26, 28.
  • the drain electrodes 70, 72, the dummy line 74 and the data line 78 on the side of the dummy line 74, the data line 78 is connected to the sources 66, 68 of the first and second thin film transistors 26, 28, and further, first, The second thin film transistors 26 and 28 are located on opposite sides of the data line 78.
  • the first and second thin film transistors 26 and 28 are respectively located on opposite sides of the first and second scan lines 60 and 62, first and second.
  • the sources 66, 68 and the drains 70, 72 of the thin film transistors 26, 28 are respectively located above the gates 56, 58 of the first and second thin film transistors 26, 28, and the amorphous silicon layer 52 and the ohmic contact layer 54 are located at the 1.
  • the source 66, 68 and the drains 70, 72 of the second thin film transistors 26, 28 are below, the virtual line 74 and the data line 78 are disposed in parallel with each other, and intersect perpendicularly with the common electrode line 64 and the first and second scanning lines 60, 62.
  • the first pixel electrode 33 is disposed under the first scan line 60 and overlaps the common electrode line 64 and the second scan line 62, wherein the overlap area of the first pixel electrode 33 and the second scan line 62 is smaller than
  • the first pixel electrode 33 overlaps the common electrode line 64.
  • the second pixel electrode 35 is disposed above the second scan line 62 and overlaps the common electrode line 64 and the first scan line 60.
  • the area of the second pixel electrode 35 overlaps with the first scan line 60 is smaller than that of the second pixel electrode 35.
  • the electrode lines 64 overlap the area.
  • Fig. 7 is a cross-sectional view along the line B-B' in the circuit layout structure of Fig. 5.
  • the ohmic contact layer 54 and the second metal layer 46 are covered with a protective layer 48 having first and second portions respectively above the drains 70, 72 and the semiconductor layer 44 of the first and second thin film transistors 26, 28.
  • the through holes 80, 81 are connected to the third through holes 82 at the boundary between the dummy lines 74 and the common electrode lines 64, and the protective layer 48 on the dummy lines 74 only partially covers the line width thereof, and the third through holes 82 are simultaneously penetrated.
  • the first and second via holes 80, 81 are etched by the protective layer 48, the first and second via holes 80 are not permeable to the semiconductor layer 44 and continue to etch the insulating layer 42.
  • the depth of 81 can only reach the semiconductor layer 44.
  • the first through hole 80 is a portion where the protective layer 48 in the cross-sectional view of Fig. 6 is not connected, and the third through hole 82 is a portion where the protective layer 48 and the insulating layer 42 are not connected in the cross-sectional view of Fig. 7.
  • An electrode layer 50 is disposed on the protective layer 48.
  • the electrode layer 50 can pass through the first and second via holes 80, 81 and the drains 70, 72 and the semiconductor layers of the corresponding first and second thin film transistors 26, 28.
  • the 44 contacts may also be in contact with the dummy line 74 and the common electrode line 64 through the third via 82.
  • the second metal layer 46 and the semiconductor layer 44, which are the drain electrodes 70 are exposed outside due to the via holes, so that they can be in contact with the electrode layer 50; as shown in FIG.
  • the second metal layer 46 as the dummy line 74 and the first metal layer 40 as the common electrode line 64 are also exposed, and thus can be in contact with the electrode layer 50, where the electrode layer 50 is an independent electrode layer block, which can be Virtual line 74
  • the common electrode line 64 is connected and turned on.
  • a portion of the drain electrode 70 of the first thin film transistor 26 extends toward the common electrode line 64, and a portion overlapping the common electrode line 64 and the electrode layer 50 is a storage capacitor of the first thin film transistor 26;
  • a drain of the second thin film transistor 28 A portion of the pole 72 extends toward the common electrode line 64, and a portion overlapping the common electrode line 64 and the electrode layer 50 is a storage capacitor of the second thin film transistor 28.
  • the electrode layer 50 of this embodiment does not overlap with the first and second scan lines 60, 62 on the drains 70, 72 side of the first and second thin film transistors 26, 28, so that each thin film transistor is connected.
  • a shading such as a black matrix (BM)
  • BM black matrix
  • the liquid crystal display panel manufactured by using the above circuit layout is as shown in FIG. 4, and can be compared with the prior art FIG. 3, and the two electrode layers 50 of the adjacent scan line 30 and the adjacent data line 32 are respectively two.
  • the pixel display area of the pixel under the design of the present invention, the common electrode line 36 does not encroach on the area of the light-transmitting area of the electrode layer 50, and in addition to the same number of transistors, the common electrode line 36 used in FIG. The number is smaller than that of FIG. 3. For example, eight transistors use only two common electrode lines in the present invention, but the prior art uses four. In other words, the design can increase the aperture ratio of the pixel.
  • the second embodiment shown in the circuit layout of FIG. 8 and FIG. 9, which differs from the first embodiment in the electrode layer 50 and the drains 70 of the first and second thin film transistors 26, 28,
  • the first and second scan lines 60, 62 on the side of the 72 are partially overlapped, so that it is not necessary to be in the color filter at the edge of the region where the electrode layer connecting each of the thin film transistors overlaps the first and second scan lines 60, 62.
  • this design can increase the distribution area of the storage capacitor at the same time, thereby reducing the panel flicker rate and increasing the aperture ratio.
  • the equivalent circuit of the liquid crystal display panel of the invention comprises a plurality of parallel scan lines 86 and a plurality of parallel data lines 84.
  • the scan lines 86 include a first scan line 862 and a second scan line 864, and the data line 84 is a scan line.
  • 86 is perpendicular to each other, and the data line 84 includes a first data line 842, the scan line 86 is parallel to the plurality of common electrode lines 88, and the common electrode line 88 includes a first common electrode line 882.
  • the liquid crystal display panel of the present invention further includes a plurality of double-gate pixel units 92 arranged in a matrix, and is formed by connecting data lines 84, scan lines 86 and common electrode lines 88 to each other, and each double-gate pixel unit 92 is connected.
  • the dual gate pixel units 92 of the same row share the same data line 84, and the dual gate pixel units 92 of the same column share the same scan line 86 and common electrode line 88.
  • the connection relationship and the positional relationship of the components in each of the dual-gate pixel units 92 are the same.
  • a dual-gate pixel unit 92 is taken as an example, and the first and second scan lines 862, 864 and the first data line 842 are used.
  • the connection and positional relationship between the first common electrode line 882 and the double gate pixel unit 92 are as follows.
  • each dual-gate pixel unit 92 includes a first thin film transistor 922 and a corresponding first liquid crystal capacitor 925, a first storage capacitor 926, and a second thin film transistor 924 and a corresponding second thereof.
  • a liquid crystal capacitor 927 and a second storage capacitor 928, and the opposite sides of the first scan line 862 and the second scan line 864 are respectively provided with a thin film transistor and a correspondingly connected liquid crystal capacitor and storage capacitor, and the phase of the first data line 842
  • the thin film transistors and their corresponding connected liquid crystal capacitors and storage capacitors are respectively disposed on the opposite sides, and the first scan line 862 and the second scan line 864 are disposed on opposite sides of the first common electrode line 882.
  • the first thin film transistor 922 has a gate connected to the first scan line 862, a source connected to the first data line 842, a drain connected to the first liquid crystal capacitor 925 and one end of the first storage capacitor 926, and the first liquid crystal capacitor 925 One end is connected to the common electrode of the color filter (CF) end to receive the first common electrode signal, and the other end of the first storage capacitor 926 is connected to the first common electrode line 882, and the first data line 842 and the first common electrode line 882 are respectively Transmitting the data signal and the second common electrode signal to the first thin film transistor 922, and the first scan line 862 controls the first thin film transistor 922 to receive the data signal, thereby controlling
  • the first liquid crystal capacitor 925 is charged and discharged, and the first storage capacitor 926 is used to maintain the potential difference between the first liquid crystal capacitor 925 to prevent the first liquid crystal capacitor 925 from leaking.
  • the gate of the second thin film transistor 924 is connected to the second scan line 864, the source thereof is connected to the first data line 842, and the drain thereof is connected to one end of the second liquid crystal capacitor 927 and the second storage capacitor 928, and the second liquid crystal capacitor
  • the other end of the 927 is connected to the common electrode of the color filter end to receive the first common electrode signal
  • the other end of the second storage capacitor 928 is connected to the first common electrode line 882.
  • the first data line 842 and the first common electrode line 882 are respectively Transmitting the data signal and the second common electrode signal to the second thin film transistor 924, and the second scan line 864 controls the second thin film transistor 924 to receive the data signal, thereby controlling charging and discharging of the second liquid crystal capacitor 927, and the second storage capacitor 928 is used to maintain the potential difference between the two liquid crystal capacitors 927 to prevent the second liquid crystal capacitor 927 from leaking.
  • the liquid crystal display panel further includes a plurality of imaginary lines 90, each of which is disposed between the adjacent two rows of double-gate pixel units 92, and is short-circuited to the common electrode line 88, because the second common electrode signals are common During the transmission of the electrode line 88, the signal at the center of the panel is unstable due to the length of the wiring being too long. Therefore, the common electrode line 88 is short-circuited with the plurality of dummy lines 90 to stabilize the second common electrode signal.
  • Figure 10 can be compared with Figure 2 of the prior art.
  • the number of common electrode lines used in Figure 8 is less than that of Figure 2 under the same number of transistors.
  • VA type vertical alignment type
  • TN type twisted nematic
  • IPS type planar conversion type
  • each common electrode line 88 and the data line 84 respectively transmit a second common electrode signal and a data signal to the connected storage capacitor 98 and the thin film transistor 94.
  • each of the liquid crystal capacitors 96 receives the first common electrode signal, and since each of the common electrode lines 88 is short-circuited to each other through the dummy line 90, the second common electrode signal in each of the common electrode lines 88 is relatively stable. .
  • the thin film transistor 94 that sequentially controls each row from top to bottom receives the data signal, thereby controlling the charge and discharge of the liquid crystal capacitor 96, and the storage capacitor 98 connected to the liquid crystal capacitor 96 is used to maintain the potential difference across the liquid crystal capacitor 96.
  • the circuit design of the liquid crystal display panel of the present invention has an advantage that when the first data line 842 is disconnected, the laser can be used to break the line at the position of the dotted line box, and the dotted line ⁇ At the position, the first data line 842 is connected to the common electrode line 88 by using a laser, and the first virtual line 902 can be used instead of the broken first data line 842 to complete the repair, and the product qualification rate is improved.
  • the invention not only can increase the pixel aperture ratio of the panel, but also short-circuit the common electrode line and the virtual line to have better stability of the common signal, which is a quite practical invention.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
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Description

像素电极结构
【技术领域】
本发明有关一种电极结构， 特别是关于一种高显示质量的像素电极结构。 【背景技术】
请参阅图 1 , 在传统主动矩阵式的液晶显示器（LCD ) 中， 其单栅极电路 架构的每个像素具有薄膜晶体管 （TFT ) 10, 其栅极连接至水平方向的扫描线 12, 源极连接至垂直方向的数据线 14, 漏极则连接至像素电极， 邻行的薄膜晶 体管 10有各自连接的数据线 14。
以下介绍此传统电路架构的基本操作方式，在水平方向上的同一条扫描线 12上， 所有薄膜晶体管 10的栅极都连接在一起， 所以施加电压是连动的， 若 在某一条扫描线 12上施加足够大的正电压， 则此条扫描在线所有的薄膜晶体 管 12都会被打开， 此时该条扫描线 12上的像素电极， 会与垂直方向的数据线 14连接， 而经由垂直数据线 14送入对应的视频信号， 以将像素电极充电至适 当的电压。接着施加足够大的负电压， 关闭薄膜晶体管 10, 直到下次再重新写 入信号， 其间使得电荷保存在液晶电容上； 此时再启动一条水平扫描线 12, 送 入其对应的视频信号。 如此依序将整个画面的视频数据写入， 再重新自第一条 重新写入信号。
上述的单栅极电路架构由于数据线 14的数量过多， 因此其消耗在源极芯 片上的成本相当高， 而为了减少此成本的消耗， 后来的技术提出了一种双栅极 电路架构， 也就是如图 2所示， 相邻两行的薄膜晶体管 16共用同一条数据线 18, 这样一来， 就可以减少数据线 18的使用数量， 进而降低源极芯片的制造 成本。 另外， 为了解决面板显示的串扰（crosstalk )现象， 在相邻的数据线 18 之间还设有虚拟线 20,并在虚拟线 20上提供与数据线 18极性相反的信号，如 此便能使面板呈现更好显示效果。
但是对于上述所提供的技术而言， 其从电路布局来观察， 如图 3所示， 因 为共通电极线 22占有面积过大， 使电极层 24扣掉形成共通电极线 22的金属 层的透光区域变少， 进而让整个面板的开口率有所损失。
因此， 本发明针对上述缺陷提出一种高显示质量的像素电极结构， 用以解 决现有所产生的问题。
【发明内容】
本发明的主要目的在于提供一种像素电极结构，将共通电极线设置在相邻 的扫描线之间， 用以减少共通电极线的数量， 如此可提升面板的像素开口率。
本发明的另一目的在于提供一种像素电极结构，将共通电极线与虚拟线做 短路连接， 以拥有较佳的共同信号的稳定性， 并在数据线断线时， 可利用激光 修补的方式再与虚拟线连接， 以此提升合格率。
为达上述目的， 本发明提供一种像素电极结构， 包含透明基板， 此基板上 设有数据线、 共通电极线与第一、 第二阵列像素， 第一阵列像素形成第一薄膜 晶体管、第一像素电极与第一扫描线，且使共通电极线设置于第一扫描线侧方， 第二阵列像素形成第二薄膜晶体管、 第二像素电极、 第二扫描线， 且还使共通 电极线设置于第二扫描线侧方， 另外， 在共通电极线设有第一、 第二通孔， 分 别与第一、 第二薄膜晶体管延伸端接触， 在数据线的侧边设有虚拟线， 而第三 通孔位于虚拟线与共通电极线。
【附图说明】
下面结合附图和实施例对发明进一步说明：
图 1和图 2为现有技术的显示面板的电路示意图。
图 3为现有技术的显示面板的电路布局 （layout )结构示意图。 图 4为本发明的液晶显示面板的第一实施例的电路布局结构示意图。
图 5为本发明的液晶显示面板的第一实施例的电路布局结构的局部放大示 意图。
图 6为图 5的电路布局结构中沿 A-A， 切线的结构剖视图。
图 7为图 5的电路布局结构中沿 B-B， 切线的结构剖视图。
图 8为本发明的液晶显示面板的第二实施例的电路布局结构示意图。
图 9为本发明的液晶显示面板的第二实施例的电路布局结构的局部放大示 意图。
图 10为本发明的液晶显示面板的电路示意图。
图 11为本发明的双栅极像素单元的电路示意图。
图 12为本发明的液晶显示面板进行激光修补后的电路示意图。
【具体实施方式】
本发明所提供的液晶显示面板主要利用现有技术已设有的虚拟线与和与 薄膜晶体管端的共通电极连接的共通电极线进行短路设计。请同时参阅图 4与 图 5的电路布局的第一实施例， 图 5为图 4中虚线方框中的像素电极结构的放 大示意图， 此虚线方框中所有的组件包含两个由电极层 50形成的像素电极、 两颗薄膜晶体管 26、 28及其周围的布线， 薄膜晶体管 26、 28为 N型， 而图 4 则是以此虚线方框中的像素电极结构为单元，彼此利用扫描线（ Gate line ) 30、 数据线（ Data line ) 32、 虚拟线 34以及共通电极线 36相互连接而构成的阵列 液晶显示面板。 然而， 由于像素电极结构在显示面板上是以矩阵方式排列， 因 此同一行的像素电极结构会共用同一条数据线 32、 虚拟线 34, 同一列的像素 电极结构会共用同一条扫描线 30与共通电极线 36。 每一个像素电极结构中的 组件之连接关系与位置关系都相同，现在以一个像素电极结构为例，陈述如下。
为了清楚说明实施方式， 以下请同时参阅图 5与图 6, 图 6为图 5的电路 布局 （layout ) 结构中沿 A-A， 切线的剖视图， 可表达出图 5中所包含的组件 的上下堆栈关系。 图 5为像素电极结构， 主要包含透明基板 38、 第一阵列像素 与第二阵列像素，第一、第二阵列像素分别形成第一、第二薄膜晶体管 26、 28、 第一、 第二像素电极 33、 35 , 以及第一、 第二扫描线 60、 62。 第一、 第二阵 列像素由第一金属层 40、绝缘层 42、半导体层 44、第二金属层 46、保护层 48、 电极层 50所形成， 而液晶层设在电极层 50上。 保护层 48为绝缘材料， 其与 绝缘层 42的材料皆为氮化硅， 电极层 50的材料为氧化铟锡（ IT0 ) , 且此电极 层 50形成与第一、第二薄膜晶体管 26、 28分别连接之第一、第二像素电极 33、 35。
第一金属层 40设于透明基板 38上，以形成第一薄膜晶体管 26的栅极 56、 第二薄膜晶体管 28的栅极 58、 第一扫描线 60、 第二扫描线 62与在第一扫描 线 60下方与第二扫描线 62上方的两者中间的共通电极线 64,然而在第一金属 层 40形成时， 同时分别将第一、 第二扫描线 60、 62与第一、 第二薄膜晶体管 26、 28的栅极 56、 58形成为相连的线路， 第一金属层 40形成后， 其上形成有 绝缘层 42, 绝缘层 42在第一、 二薄膜晶体管 26、 28上作为栅极绝缘层。 绝缘 层 42上设有半导体层 44,此半导体层 44分为上下二层结构，下层为非晶硅层 ( a-Si ) 52, 其直接设于绝缘层 42上， 上层为 n +掺杂非晶硅（ n + a-Si )的欧 姆接触层 54, 欧姆接触层 54与绝缘层 42上设有第二金属层 46, 以形成第一、 第二薄膜晶体管 26、 28的源极 66、 68与漏极 70、 72、 虚拟线 74与在该虚拟 线 74侧边的数据线 78, 数据线 78连接第一、 第二薄膜晶体管 26、 28的源极 66、 68, 再者， 第一、 第二薄膜晶体管 26、 28位于数据线 78的相异两侧， 第 一、 第二薄膜晶体管 26、 28分别位于第一、 第二扫描线 60、 62的相异两侧， 第一、 第二薄膜晶体管 26、 28之源 66、 68、 漏极 70、 72分别位于第一、 第二 薄膜晶体管 26、 28的栅极 56、 58上方， 且非晶硅层 52与欧姆接触层 54皆位 于第一、 第二薄膜晶体管 26、 28的源极 66、 68与漏极 70、 72下方， 虚拟线 74与数据线 78互相平行设置， 并与共通电极线 64及第一、 第二扫描线 60、 62垂直交会。
另外， 从图中可以发现， 第一像素电极 33设于第一扫描线 60下方且重叠 于共通电极线 64及第二扫描线 62， 其中第一像素电极 33与第二扫描线 62重 叠面积小于第一像素电极 33与共通电极线 64重叠面积。 而第二像素电极 35 设于第二扫描线 62上方且重叠于共通电极线 64及第一扫描线 60,其中第二像 素电极 35与第一扫描线 60重叠面积小于第二像素电极 35与共通电极线 64重 叠面积。
接下来请同时参阅图 5、 图 6以及图 7, 图 7为图 5的电路布局结构中沿 B-B' 切线的剖视图。 欧姆接触层 54与第二金属层 46上覆盖保护层 48, 此保 护层 48具有分别位于第一、 第二薄膜晶体管 26、 28的漏极 70、 72和半导体 层 44上方的第一、 第二通孔 80、 81 , 与位于虚拟线 74和共通电极线 64的交 界处的第三通孔 82,且虚拟线 74上的保护层 48仅有部分覆盖其线宽，第三通 孔 82同时贯穿下方的绝缘层 42, 另外， 在保护层 48蚀刻出第一、 第二通孔 80、 81时， 因无法透过半导体层 44并继续往绝缘层 42蚀刻， 所以第一、 第二 通孔 80、 81的深度仅能到达半导体层 44。第一通孔 80为图 6的剖视图中的保 护层 48没有连接的部分， 第三通孔 82为图 7的剖视图中的保护层 48与绝缘 层 42没有连接的部分。
在保护层 48上设有电极层 50, 此电极层 50不但可通过第一、 第二通孔 80、 81与对应的第一、 第二薄膜晶体管 26、 28的漏极 70、 72和半导体层 44 相接触， 还可通过第三通孔 82与虚拟线 74和共通电极线 64相接触。 如图 6 所示， 由于通孔的缘故， 作为漏极 70的第二金属层 46和半导体层 44暴露在 外， 因此可与电极层 50相接触； 如图 7所示， 由于通孔的缘故， 作为虚拟线 74的第二金属层 46和作为共通电极线 64的第一金属层 40也暴露在外， 因此 可与电极层 50相接触， 此处的电极层 50为独立电极层区块， 可将虚拟线 74 与共通电极线 64相连接并令其导通。
另外， 与薄膜晶体管的漏极相接触的电极层 50和第一金属层 40、 第二金 属层 46重叠的部分， 可形成该薄膜晶体管的储存电容。 如第一薄膜晶体管 26 的漏极 70有部分往共通电极线 64延伸，并与此共通电极线 64和电极层 50重 叠的部分为第一薄膜晶体管 26的储存电容； 第二薄膜晶体管 28的漏极 72有 一部分往共通电极线 64延伸， 并与此共通电极线 64和电极层 50重叠的部分 为第二薄膜晶体管 28的储存电容。
另外， 此实施例的电极层 50并没有与第一、 第二薄膜晶体管 26、 28的漏 极 70、 72侧的第一、 第二扫描线 60、 62重叠， 所以在连接每个薄膜晶体管的 电极层边缘处， 必需在彩色滤光片中对应设置遮光物， 如黑矩阵（BM )。 如此 一来， 当显示面板制作成液晶显示器时， 每一个像素边缘才不会出现漏光， 而 影响液晶分子排列， 且邻接像素才不会出现混色的现象。
利用上述电路布局所制造出来的液晶显示面板如图 4所示，可与现有技术 的图 3同时比较， 在相邻扫描线 30与相邻数据线 32的二个电极层 50为分别 二个像素的像素显示区， 在本发明的设计下， 共通电极线 36不会侵占到电极 层 50的透光区域的面积， 另外在相同的晶体管的数量下， 图 4所使用到的共 通电极线 36的数量比图 3少， 如八颗晶体管本发明仅用到二条共通电极线， 而现有技术却用到四条， 换句话说， 如此设计便能提升像素的开口率。
接下来， 请同时参阅图 8和图 9的电路布局所示的第二实施例， 其与第一 实施例的差异在于电极层 50与第一、 第二薄膜晶体管 26、 28的漏极 70、 72 侧的第一、 第二扫描线 60、 62部分重叠， 所以在连接每个薄膜晶体管的电极 层与第一、 第二扫描线 60、 62重叠区域的边缘处， 不必于彩色滤光片中对应 设置遮光物， 此种设计可同时增加了储存电容的分布面积， 进而减少面板闪烁 率， 且增加其开口率。
参阅完本发明的电路布局， 请继续参阅其等效电路图， 如图 10所示。 本 发明的液晶显示面板的等效电路包含多条平行之扫描线 86与多条平行之数据 线 84, 扫描线 86包含有第一扫描线 862与第二扫描线 864, 数据线 84是与扫 描线 86互相垂直，且数据线 84中包含第一数据线 842,扫描线 86是与多条共 通电极线 88互相平行， 且共通电极线 88包含第一共通电极线 882。
本发明的液晶显示面板还包含以矩阵方式排列的多个双栅极像素单元 92 , 并以数据线 84、扫描线 86与共通电极线 88彼此连接而成，每一个双栅极像素 单元 92连接条数据线 84、 二条扫描线 86与一条共通电极线 88。 同一行的双 栅极像素单元 92会共享同一条数据线 84,同一列的双栅极像素单元 92会共享 同一条扫描线 86与共通电极线 88。每一个双栅极像素单元 92中的组件之连接 关系与位置关系都相同， 现在以一个双栅极像素单元 92为例， 并将第一、 第 二扫描线 862、 864、 第一数据线 842、 第一共通电极线 882与一双栅极像素单 元 92彼此之间的连接与位置关系介绍如下。
请同时参阅图 12, 每一个双栅极像素单元 92包含第一薄膜晶体管 922及 其对应连接之第一液晶电容 925、 第一储存电容 926, 与第二薄膜晶体管 924 及其对应连接的第二液晶电容 927、 第二储存电容 928, 且第一扫描线 862与 第二扫描线 864的相异两侧分别设有薄膜晶体管及其对应连接的液晶电容、储 存电容，第一数据线 842的相异两侧也分别设有薄膜晶体管及其对应连接的液 晶电容、储存电容，第一扫描线 862及第二扫描线 864设于第一共通电极线 882 的相异两侧。
第一薄膜晶体管 922的栅极连接第一扫描线 862, 其源极连接第一数据线 842, 其漏极连接第一液晶电容 925与第一储存电容 926的一端， 第一液晶电 容 925的另一端连接彩色滤光片 （CF )端的共通电极， 以接收第一共通电极信 号， 第一储存电容 926的另一端连接第一共通电极线 882, 第一数据线 842与 第一共通电极线 882分别传输数据信号与第二共通电极信号至第一薄膜晶体管 922中， 且第一扫描线 862控制第一薄膜晶体管 922接收该数据信号， 进而控 制第一液晶电容 925的充放电，而第一储存电容 926用来维持第一液晶电容 925 两端的电位差， 以防第一液晶电容 925漏电的情况发生。
同样地， 第二薄膜晶体管 924的栅极连接第二扫描线 864, 其源极连接第 一数据线 842, 其漏极连接第二液晶电容 927与第二储存电容 928的一端， 第 二液晶电容 927的另一端连接彩色滤光片端的共通电极， 以接收第一共通电极 信号， 第二储存电容 928的另一端连接第一共通电极线 882, 第一数据线 842 与第一共通电极线 882分别传输数据信号与第二共通电极信号至第二薄膜晶体 管 924中， 且第二扫描线 864控制第二薄膜晶体管 924接收该数据信号， 进而 控制第二液晶电容 927的充放电， 而第二储存电容 928是用来维持第二液晶电 容 927两端的电位差， 以防第二液晶电容 927漏电的情况发生。
液晶显示面板还包含多条虚拟线 90, 每一条虚拟线 90分别设于相邻两行 的双栅极像素单元 92之间， 并短路连接共通电极线 88, 由于在第二共通电极 信号在共通电极线 88传输的过程中， 会因为布线的长度过长而造成面板中央 处的信号不稳定， 因此将共通电极线 88通过与该多条虚拟线 90短路， 以稳定 第二共通电极信号。
图 10可与现有技术的图 2同时比较， 如同电路布局比较的结果， 在相同 的晶体管的数量下， 图 8所使用到的共通电极线的数量比图 2少， 换句话说， 如此便能提升像素的开口率， 且此电路设计可应用于垂直配向式（VA type )、 扭转向列式（ TN type ), 平面转换式（ IPS type )的液晶或是有有机缘膜的像素 设计。
请继续参阅图 10,本发明的液晶显示面板的动作描述如下，首先每一条共 通电极线 88与数据线 84分别传输第二共通电极信号与数据信号至连接的储存 电容 98与薄膜晶体管 94中， 且每一个液晶电容 96接收第一共通电极信号， 同时由于每一条共通电极线 88彼此通过虚拟线 90短路连接的缘故， 因此在每 一条共通电极线 88中的第二共通电极信号是相当稳定的。 接着利用扫描线 86 由上而下依序控制每一行的薄膜晶体管 94接收该数据信号， 进而控制液晶电 容 96的充放电， 同时连接液晶电容 96的储存电容 98则用来维持液晶电容 96 两端的电位差。
最后请参阅图 12,本发明的液晶显示面板的电路设计还有一项优点， 即当 第一数据线 842断线时， 可在虚线方框所在位置处利用激光将其断线后， 在虚 线圏所在位置处， 再利用激光将第一数据线 842与共通电极线 88连接， 即可 利用第一虚拟线 902来代替以断线的第一数据线 842而修补完成， 同时提升产 品合格率。
综上所述， 本发明不但可提升面板的像素开口率， 又将共通电极线与虚拟 线做短路连接， 以拥有较佳的共同信号的稳定性， 是一种相当实用的发明。
在上述实施例中， 仅对本发明进行了示范性描述， 但是本领域技术人员在 阅读本专利申请后可以在不脱离本发明的精神和范围的情况下对本发明进行 各种修改。

Claims

权 利 要 求
1、 一种像素电极结构， 其特征在于： 包含，
透明基板；
数据线， 设于该透明基板上；
共通电极线， 设于该透明基板上；
第一阵列像素， 设于该透明基板上， 以形成第一薄膜晶体管、 第一像素电 极、 第一扫描线， 且该共通电极线设置于该第一扫描线侧方；
第一通孔， 位于该共通电极线并与该第一薄膜晶体管延伸端接触； 第二阵列像素， 设于该透明基板上， 以形成第二薄膜晶体管、 第二像素电 极、 第二扫描线， 且该共通电极线设置于该第二扫描线侧方；
第二通孔， 位于该共通电极线并与该第二薄膜晶体管延伸端接触； 虚拟线， 设于该数据线的侧边； 以及
第三通孔， 位于该虚拟线与该共通电极线。
2、 根据权利要求 1所述的像素电极结构， 其特征在于： 该共通电极线设 于该第一扫描线下方与该第二扫描线上方的两者中间。
3、 根据权利要求 1所述的像素电极结构， 其特征在于： 该第一像素电极 设于该第一扫描线下方且重叠于该共通电极线及该第二扫描线。
4、 根据权利要求 3所述的像素电极结构， 其特征在于： 该第一像素电极 与该第二扫描线重叠面积小于该第一像素电极与该共通电极线重叠面积。
5、 根据权利要求 1所述的像素电极结构， 其特征在于： 该第二像素电极 设于该第二扫描线上方且重叠于该共通电极线及该第一扫描线。
6、 根据权利要求 5所述的像素电极结构， 其特征在于： 该第二像素电极 与该第一扫描线重叠面积小于该第二像素电极与该共通电极线重叠面积。
7、 根据权利要求 1所述的像素电极结构， 其特征在于： 该第一、 第二薄 膜晶体管分别包含源极、 漏极以及栅极。
8、 根据权利要求 7所述的像素电极结构， 其特征在于： 该第一、 二通孔 与该第一、 第二薄膜晶体管接触的延伸端为该漏极。
9、 根据权利要求 1所述的像素电极结构， 其特征在于： 该第一、 第二阵 列像素结构包含第一金属层、 绝缘层、 半导体层、 第二金属层、 保护层以及电 极层。
10、 根据权利要求 9所述的像素电极结构， 其特征在于： 该电极层与该第 一、 第二晶体管的漏极侧的该第一、 第二扫描线部分重叠。
11、 根据权利要求 9所述的像素电极结构， 其特征在于： 该第一、 二通孔 形成于部分该第二金属层与部分该半导体层上，使该电极层与部分该第二金属 层以及部分该半导体层相连接。
12、 根据权利要求 1所述的像素电极结构， 其特征在于： 该第一、 第二薄 膜晶体管位于该数据线的相异两侧， 该第一、 第二薄膜晶体管位于该第一、 第 二扫描线的相异两侧。
13、 根据权利要求 1所述的像素电极结构， 其特征在于： 该第三通孔形成 于部分该虚拟线与部分该共通电极线，其再由独立部分的电极层将该虚拟线与 该共通电极线相连接。
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