WO2010098460A1 - 位相測定装置、および周波数測定装置 - Google Patents
位相測定装置、および周波数測定装置 Download PDFInfo
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- WO2010098460A1 WO2010098460A1 PCT/JP2010/053144 JP2010053144W WO2010098460A1 WO 2010098460 A1 WO2010098460 A1 WO 2010098460A1 JP 2010053144 W JP2010053144 W JP 2010053144W WO 2010098460 A1 WO2010098460 A1 WO 2010098460A1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R25/00—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
- G01R23/10—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage by converting frequency into a train of pulses, which are then counted, i.e. converting the signal into a square wave
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
- G01R23/12—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage by converting frequency into phase shift
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R25/00—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
- G01R25/04—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents involving adjustment of a phase shifter to produce a predetermined phase difference, e.g. zero difference
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
- G01R23/15—Indicating that frequency of pulses is either above or below a predetermined value or within or outside a predetermined range of values, by making use of non-linear or digital elements (indicating that pulse width is above or below a certain limit)
Definitions
- the present invention relates to a phase measurement device that measures the phase difference between two signals to be measured, and a frequency measurement device that measures the frequency of the signal to be measured.
- the time to be measured is calculated by detecting the number of clock signals for one period using a clock signal that is a reference for measurement.
- the wavelength of the clock signal may be shortened, but the wavelength of the clock signal that can be generated also has a practical limit. For this reason, how to measure the fractional part that is less than one cycle of the clock signal is very effective for high accuracy. For this reason, for example, in Non-Patent Document 1, measurement is performed by converting a fractional part into a voltage value by using a capacitor.
- an analog circuit such as a time-voltage conversion circuit or an ADC circuit (analog / digital conversion circuit) is an essential configuration. Therefore, errors such as noise, offset, and temperature fluctuation that are likely to occur due to the analog circuit are likely to be included in the measurement result. In addition, since various analog circuits are required, it is difficult to reduce the size and cost.
- an object of the present invention is to realize a phase measuring apparatus capable of measuring time, that is, a phase difference between two signals with high accuracy using a digital circuit.
- Another object of the present invention is to realize a frequency measuring device capable of measuring the frequency of a signal to be measured with high accuracy by a circuit configuration similar to that of the phase measuring device.
- an object of the present invention is to realize a reference signal generation device that can generate a highly accurate reference signal and an abnormality detection device that detects an abnormality of the reference signal generation device by using the above-described phase measurement device. .
- the phase measuring device of the present invention includes a buffer delay measuring circuit, a phase difference measuring circuit, and a phase difference calculating unit.
- the buffer delay measurement circuit has multiple buffers.
- a clock signal synchronized with a reference signal calculated by positioning calculation is input to each of the plurality of buffers at different timings with a certain delay time, and a sampling reference signal having a frequency lower than that of the clock signal is input simultaneously. Is done.
- Each buffer generates state data corresponding to the level of the clock signal at the transition timing of the sampling reference signal.
- the buffer delay amount measurement circuit outputs delay measurement data consisting of these state data groups.
- the phase difference measurement circuit includes a first partial phase difference measurement circuit and a second partial phase difference measurement circuit.
- the first partial phase difference measurement circuit includes a plurality of buffers as in the buffer delay amount measurement circuit. Each of the plurality of buffers receives a first signal to be measured out of a first signal to be measured and a second signal to be measured that cause a phase difference to be measured, and different timings depending on the delay amount. Clock signal is input. Each buffer generates state data corresponding to the level of the clock signal at the transition timing of the first signal under measurement.
- the first partial phase difference measurement circuit outputs first phase difference measurement data composed of a state data group from the plurality of buffers.
- the second partial phase difference measurement circuit includes a plurality of buffers as in the buffer delay amount measurement circuit. To each of the plurality of buffers, a second signal to be measured that causes a phase difference to be measured is input, and clock signals having different timings depending on the delay amount are input. Each buffer generates state data corresponding to the level of the clock signal at the transition timing of the second signal under measurement.
- the second partial phase difference measurement circuit outputs second phase difference measurement data composed of a state data group from the plurality of buffers.
- the phase calculation unit calculates a delay amount between the buffers based on the delay measurement data, and calculates a difference value and a delay amount with respect to the transition timing of the clock signal of the first phase difference measurement data and the second phase difference measurement data.
- the phase difference is calculated based on
- a phase difference is measured using a so-called TDC (Time-to-Digital Converter) having a plurality of buffers.
- TDC Time-to-Digital Converter
- the buffer delay amount measuring circuit includes one TDC including a plurality of buffers (flip-flops), and sequentially gives the same clock signal to each buffer of the TDC with a certain delay amount (time difference).
- the buffer delay amount measurement circuit simultaneously provides a sampling reference signal having a long period to each buffer.
- Each buffer includes a buffer in which the clock signal becomes Hi level and a buffer in which the clock signal becomes Low level at the timing of transition of the sampling reference signal. For example, “1” or “0” state data corresponding to the level is stored. Output.
- the number of state data existing between the transition timings of adjacent state data from “1” to “0” (see FIG. 2). ) Depends on the delay amount of the buffer and the frequency (period) of the clock signal.
- the phase difference measuring circuit includes one TDC in each of the first partial phase difference measuring circuit and the second partial phase difference measuring circuit, and the same clock signal as that of the buffer delay measuring circuit is given to each buffer of each TDC.
- the clock signal is synchronized with a high-accuracy reference signal such as GPS 1PPS, the amount of delay obtained from the clock signal is as high as the accuracy of the reference signal.
- the first signal to be measured is input to the first partial phase difference measurement circuit
- the second signal to be measured is input to the second partial phase difference measurement circuit.
- the state data of each buffer at the transition timing of the first signal to be measured is different according to the same principle as the above-described buffer delay measurement circuit, and the first partial data consisting of these state data groups. Data for phase difference measurement is output.
- the state data of each buffer at the transition timing of the second signal under measurement differs according to the same principle, and the second phase difference measurement data including these state data groups is output.
- the The number of state data until the specific transition timing of the first phase difference measurement data and the second phase difference measurement data (the timing at which the state data in FIG. 4 transitions from “1” to “0”) It depends on the time difference between the transition timing and the transition timing of the first measurement target signal or the second measurement target signal.
- phase difference calculation unit a delay amount between the buffers obtained from the delay measurement data is given to the number of state data until the specific transition timing of the first phase difference measurement data and the second phase difference measurement data (multiplication) By doing so, a time difference between the transition timing of the clock signal and the transition timing of the first measurement target signal or the second measurement target signal is obtained. By obtaining the time difference in this way, an accurate delay amount between the buffers can be obtained, and highly accurate phase difference measurement can be performed.
- the phase difference measuring circuit of the phase measuring apparatus provides the start timing and the end timing for measuring the number of clock signals per cycle by the first measurement target signal and the second measurement target signal.
- a third partial phase difference measuring circuit for calculating the number of clock signals included in the phase difference in one cycle unit.
- the phase difference calculation unit calculates the phase difference including the time length corresponding to the number of clock signals in one cycle unit.
- one period of the clock signal when the phase difference is equal to or longer than one period of the clock signal and the time length is such that one period can be counted, one period of the clock signal can be obtained without measuring all with only the delay amount of the buffer. A part of the phase difference can be calculated with the resolution as minutes. Then, the fractional part less than one period of the clock signal is calculated by the method using the delay amount between the TDC buffers. Thereby, when the phase difference is longer than one cycle of the clock signal as described above, the number of buffers of each TDC can be reduced.
- a frequency measurement device of the present invention includes the above-described buffer delay measurement circuit, frequency measurement circuit, and frequency calculation unit.
- the buffer delay measurement circuit has the same configuration as described above, and outputs delay measurement data.
- the frequency measurement circuit includes a plurality of buffers. The third signal to be measured is input to each buffer of the frequency measurement circuit at a different timing with a certain delay time, and a sampling reference signal having a frequency lower than that of the third signal to be measured is simultaneously input. .
- Each buffer generates state data corresponding to the level of the third signal under measurement at the transition timing of the sampling reference signal, and the frequency measurement circuit outputs frequency measurement data including these state data groups.
- the frequency calculation unit calculates the delay amount between the buffers based on the delay measurement data, and calculates the frequency or period of the third signal under measurement based on the frequency measurement data using the delay amount.
- the buffer delay measurement circuit is the same as the above-described phase difference measurement device, and outputs delay measurement data including a state data string depending on the buffer delay amount and the frequency (cycle) of the clock signal.
- the frequency measurement circuit is a circuit having the same TDC as the buffer delay circuit, and gives the delay amount to the signal to be measured instead of the clock signal and inputs it to each buffer. Thereby, the state data string of the frequency measurement data to be output depends on the frequency (cycle) of the signal under measurement.
- the frequency calculation unit detects one cycle of the signal under measurement by giving (multiplying) the delay amount obtained from the delay measurement data to the number of state data between the transition timings of the frequency measurement data.
- the frequency can be obtained by this one cycle.
- the delay amount shorter than the cycle of the clock signal becomes the resolution, the cycle and frequency can be measured with high accuracy.
- the frequency measuring device of the present invention includes a measuring circuit and a frequency calculating unit.
- the measurement circuit includes a plurality of buffers. Either one of the clock signal synchronized with the reference signal calculated by the positioning calculation or the third signal to be measured is input to each buffer at a different timing with a certain delay time. A sampling reference signal having a frequency lower than that of the measurement target signal is simultaneously input.
- the positioning circuit outputs delay measurement data including a state data group corresponding to the level of the clock signal at the transition timing of the sampling reference signal.
- the positioning circuit outputs frequency measurement data including a state data group corresponding to the level of the third signal to be measured at the transition timing of the sampling reference signal.
- the frequency calculation unit calculates a delay amount between the buffers based on the delay measurement data.
- the frequency calculation unit calculates the frequency or period of the third signal under measurement based on the frequency measurement data and the delay amount.
- a measurement circuit is provided that outputs delay measurement data when a signal is input, and outputs frequency measurement data when a signal to be measured is input. As a result, the required number of TDCs becomes one, and the circuit scale is further simplified.
- FIG. 2 is a block diagram showing a main configuration of a buffer delay measurement circuit 110 of the phase measuring apparatus 1 and a timing chart showing a measurement principle of the buffer delay measurement circuit 110.
- FIG. 3 is a block diagram showing a circuit configuration of a phase difference measurement circuit 120.
- FIG. It is a timing chart which shows a phase difference measurement principle.
- It is a block diagram which shows the main structures of the 2nd frequency measuring device and each apparatus which gives various signals to the said frequency measuring device, and the figure which shows the other structural example of a frequency measuring device.
- FIG. 1 is a block diagram showing the main configuration of the phase measuring device of this embodiment and the devices that give various signals to the phase measuring device.
- GPS Globalstar Satellite System
- FIG. 1 is a block diagram showing the main configuration of the phase measuring device of this embodiment and the devices that give various signals to the phase measuring device.
- GNSS Globalstar Satellite System
- a sampling reference signal or reference signal is sent from an external device to the phase measurement device 1 and the reference signal generator 3.
- the structure which gives may be sufficient.
- each device of the phase measurement system including the phase measurement device 1 of the present embodiment will be schematically described.
- the GPS receiver 2 includes an RF processing unit 21, a baseband processing unit 22, and a TCXO (crystal oscillator) 23.
- the TCXO 23 generates a demodulation GPS reference signal Ref (GPS), and supplies it to the RF processing unit 21 and the baseband processing unit 22 and to the frequency divider 40.
- the RF processing unit 21 is connected to the GPS antenna 20 and receives a GPS positioning signal.
- the RF processing unit 21 down-converts the received signal using the GPS reference signal Ref (GPS) and supplies the received signal to the baseband processing unit 22.
- the baseband processing unit 22 demodulates the baseband signal to perform positioning calculation, generates 1PPS (Re) corresponding to the reference signal of the present invention, and provides the reference signal generator 3 with it.
- the reference signal generator 3 includes a phase comparator 31, a loop filter 32, a VCO (voltage controlled oscillator) 33, a multiplier 34, and a frequency divider 35.
- the phase comparator 31 detects a phase difference between 1PPS (Re) from the GPS receiver 2 and 1PPS (Lo) corresponding to the synchronization signal of the present invention from the frequency divider 35, and based on the phase difference.
- a voltage level phase difference signal is generated and output.
- the loop filter 32 is constituted by a low-pass filter or the like, generates a drive voltage signal by averaging the voltage level of the phase difference signal on the time axis, and outputs the drive voltage signal to the VCO 33.
- the VCO 33 generates a reference signal Sout having a frequency (for example, 10 MHz) based on the drive voltage signal, and outputs the reference signal Sout to the multiplier 34.
- the multiplier 34 generates a clock signal CLK of about 100 MHz, for example, by multiplying the reference signal Sout.
- the frequency divider 35 divides the clock signal to generate 1 PPS (Lo), and supplies it to the phase comparator 31.
- the reference signal Sout and the clock signal CLK output from the reference signal generating device 3 become signals synchronized with 1 PPS (Re) from the GPS receiver 2 with high accuracy.
- the multiplier 34 can be omitted depending on the frequency of the reference signal Sout generated by the VCO 33.
- the phase measurement device 1 includes a digital measurement unit 11 and a phase difference calculation unit 12.
- the digital measurement unit 11 includes a buffer delay measurement circuit 110 and a phase difference measurement circuit 120.
- the buffer delay measurement circuit 110 receives a clock signal CLK from the reference signal generator 3 and a sampling reference signal SCL obtained by dividing the GPS reference signal Ref (GPS) of the GPS receiver 2 by the frequency divider 40. Is done.
- the sampling reference signal SCL is a signal having a sufficiently long period (low frequency) with respect to the clock signal.
- the buffer delay measurement circuit 110 includes a TDC and uses a clock signal CLK and a sampling reference signal SCL to measure a delay ⁇ B between clock signals to be provided to each buffer of the TDC.
- the measurement data Ds is generated and given to the phase difference calculator 12.
- the phase difference measuring circuit 120 receives the clock signal CLK and the first signal to be measured SS (A) and the second signal to be measured SS (B) that cause the phase difference to be measured. Although the details will be described later in the same manner as the buffer delay measurement circuit 110, the phase difference measurement circuit 120 generates a clock signal in the phase difference between the first signal to be measured SS (A) and the second signal to be measured SS (B). Coarse phase amount data Dt indicating the amount having the period as the resolution is generated.
- the phase difference measuring circuit 120 has a structure in which one TDC is assigned to each of the first signal to be measured SS (A) and the second signal to be measured SS (B), and the clock signal CLK And the first signal to be measured SS (A) or the second signal to be measured SS (B), for phase difference measurement that represents a fractional phase difference shorter than the period of the clock signal that cannot be represented by the coarse phase amount data Dt.
- Data Ds (A) and Ds (B) are generated and output to the phase difference calculation unit 12.
- the phase difference calculation unit 12 includes a processor, and calculates a delay amount ⁇ B between the buffers from the delay measurement data Ds.
- the phase difference calculation unit 12 calculates the coarse phase difference based on the cycle of the clock signal and the coarse phase amount data Dt, and calculates the calculated delay amount ⁇ B and the phase difference measurement data Ds (A) and Ds (B). Based on the above, the fractional phase difference is calculated.
- the phase difference calculating part 12 calculates the phase difference of 1st to-be-measured signal SS (A) and 2nd to-be-measured signal SS (B) from these rough phase differences Dt and fractional phase differences.
- phase measuring apparatus 1 Next, the configuration and principle of the phase measuring apparatus 1 will be described more specifically.
- FIG. 2A is a block diagram showing the main configuration of the buffer delay measurement circuit 110 of the phase measuring apparatus 1
- FIG. 2B is a timing chart showing the measurement principle of the buffer delay measurement circuit 110.
- the buffer delay measurement circuit 110 includes a plurality of buffer circuits 111 (1) to 111 (P) that are configured by TDC and have a predetermined number of stages.
- Each of the buffer circuits 111 (1) to 111 (P) includes a D input terminal, a CLK input terminal, and a Q output terminal.
- the Q output terminals of the buffer circuits 111 (1) to 111 (P) are connected to a data bus (Data Bus), and the data bus is connected to the phase difference calculation unit 12.
- the sampling reference signal SCL is input to the CLK input terminal of each of the buffer circuits 111 (1) to 111 (P).
- Clock signals CLK (0) to CLK (P-1) based on the clock signal CLK from the reference signal generator 3 are input to the D input terminals of the buffer circuits 111 (1) to 111 (P), respectively.
- the clock signal CLK (0) input to the buffer circuit 111 (1) is the clock signal CLK itself from the reference signal generator 3, and the clock signal CLK input to the buffer circuit 111 (2).
- (1) is a signal obtained by delaying the clock signal CLK by the delay amount 112 (1) by the delay amount ⁇ B.
- the clock signal CLK (2) input to the buffer circuit 111 (3) (not shown) is a signal obtained by further delaying the clock signal CLK (1) by the delay amount ⁇ B by the delay unit 112 (2).
- the clock signals CLK (0) to CLK (P ⁇ 1) having delay intervals of the delay amount ⁇ B are sequentially input to the buffer circuits 111 (1) to 111 (P).
- each of the buffer circuits 111 (1) to 111 (P) receives each clock signal CLK at the level transition timing (timing at which the sampling reference signal SCL in FIG. 2B transitions from “0” to “1”).
- the level of (0) to CLK (P ⁇ 1) is latched and “1” or “0” status data is output.
- the buffer circuit 111 (1) is “1” because the clock signal CLK (0) is at the “1” level at the level transition timing of the sampling reference signal SCL.
- the buffer circuits 111 (2) and 111 (3) also output the status data “1”.
- the buffer circuit 111 (4) outputs “0” state data at the level transition timing of the sampling reference signal SCL because the clock signal CLK (3) is at the “0” level.
- the state data group consisting of “1” or “0” output from the buffer circuits 111 (1) to 111 (P) has the MSB on the buffer circuit 111 (1) side and the buffer circuit 111 (P) side. Is output to the phase difference calculation unit 12 as delay measurement data Ds (see FIG. 2B).
- the number N B of state data included during the state transition timing in the specific direction of the delay measurement data Ds is the frequency f of the clock signal CLK.
- the delay amount ⁇ B given between the buffer circuits described above, and N B ⁇ ⁇ B 1 / f.
- phase difference calculation unit 12 the status data number N B from the delay measurement data Ds by obtaining multiple doses, (1) By averaging, as shown in the expression more accurate delay tau B Can be calculated.
- averaging process was performed in this description, a least square method or a digital filter may be used.
- FIG. 3 is a block diagram showing a circuit configuration of the phase difference measurement circuit 120
- FIG. 4 is a timing chart showing a phase difference measurement principle.
- the phase difference measurement circuit 120 includes a counter circuit 121, a counter latch circuit 122, a first partial phase difference measurement circuit 123, and a second partial phase difference measurement circuit 124.
- the combinational circuit including the counter circuit 121 and the counter latch circuit 122 corresponds to the third phase difference measurement circuit of the present invention.
- the counter circuit 121 receives the clock signal CLK, the first signal to be measured SS (A), and the second signal to be measured SS (B).
- the counter circuit 121 uses the transition timing of the first signal to be measured SS (A) as a start flag, uses the transition timing of the second signal to be measured SS (B) as a clear flag, and counts from the start flag to the clear flag. Dc is acquired and output to the counter latch circuit 122.
- the counter circuit 121 clears the count value after output to the counter latch circuit 122. For example, as in the example of FIG. 4, the transition timing of the first signal to be measured SS (A) occurs between the timing t (n0) and the timing t (n1) of the clock signal CLK (CLK (0)).
- the counter latch circuit 122 receives the count value Dc and the second signal to be measured SS (B).
- the counter latch circuit 122 latches the count value Dc input from the counter circuit 121 until the transition timing of the second signal to be measured SS (B) is detected, and the latched count is detected when the transition timing is detected.
- the value Dt is output to the phase difference calculator 12.
- the first partial phase difference measuring circuit 123 and the second partial phase difference measuring circuit 124 are constituted by TDC and are constituted by the same number of buffer circuits.
- the first partial phase difference measuring circuit 123 includes buffer circuits 1231 (1) to 1231 (P) having a plurality of stages.
- Each of the buffer circuits 1231 (1) to 1231 (P) includes a D input terminal, a CLK input terminal, and a Q output terminal.
- the Q output terminals of the buffer circuits 1231 (1) to 1231 (P) are connected to a data bus (Data Bus), and the data bus is connected to the phase difference calculation unit 12.
- the first signal under measurement SS (A) is input to the CLK input terminal of each of the buffer circuits 1231 (1) to 1231 (P).
- the D input terminals of the buffer circuits 1231 (1) to 1231 (P) are respectively clock signals CLK (0) to CLK (based on the clock signal CLK from the reference signal generating device 3. P-1) is input.
- the clock signal CLK (0) input to the buffer circuit 1231 (1) is the clock signal CLK itself from the reference signal generator 3, and the clock signal CLK input to the buffer circuit 1231 (2).
- (1) is a signal obtained by delaying the clock signal CLK by the delay amount ⁇ B by the delay unit 1232 (1).
- the clock signal CLK (2) input to the buffer circuit 1231 (3) (not shown) is a signal obtained by further delaying the clock signal CLK (1) by the delay amount ⁇ B by the delay unit 1232 (2).
- the clock signals CLK (0) to CLK (P ⁇ 1) each having a delay interval of the delay amount ⁇ B are input to the buffer circuits 1231 (1) to 1231 (P).
- the buffer circuits 1231 (1) to 1231 (P) With each of the clock signals CLK (0) to CLK (P-1) and the first signal under measurement SS (A) being input to the buffer circuits 1231 (1) to 1231 (P), the first When the level transition of the signal under measurement SS (A) occurs, the buffer circuits 1231 (1) to 1231 (P) have the level transition timing (the first signal under measurement SS (A) in FIG. 4 is “0”). The level of each clock signal CLK (0) to CLK (P-1) at the timing of transition from “1” to “1”) is latched and “1” or “0” state data is output. For example, in the example of FIG.
- the buffer circuit 1231 (1) has a level transition timing of the first signal under measurement SS (A) and the clock signal CLK (0) is at the “1” level. 1 "status data is output.
- the buffer circuits 1231 (2), 1231 (3), and 1231 (4) also output the state data “1”.
- the buffer circuit 1231 (5) outputs “0” state data at the level transition timing of the first signal under measurement SS (A) because the clock signal CLK (4) is at the “0” level.
- the state data group consisting of “1” or “0” output from the buffer circuits 1231 (1) to 1231 (P) has the MSB on the buffer circuit 1231 (1) side and the buffer circuit 1231 (P) side. Is output to the phase difference calculation unit 12 as first phase difference measurement data Ds (A) (see FIG. 4).
- the second partial phase difference measuring circuit 124 includes buffer circuits 1241 (1) to 1241 (P) having a plurality of stages.
- Each of the buffer circuits 1241 (1) to 1241 (P) includes a D input terminal, a CLK input terminal, and a Q output terminal.
- the Q output terminals of the buffer circuits 1241 (1) to 1241 (P) are connected to a data bus (Data Bus), and the data bus is connected to the phase difference calculation unit 12.
- the second signal under measurement SS (B) is input to the CLK input terminal of each of the buffer circuits 1241 (1) to 1241 (P).
- the D input terminals of the buffer circuits 1241 (1) to 1241 (P) have clock signals CLK (0) to CLK (based on the clock signal CLK from the reference signal generator 3, respectively. P-1) is input.
- the clock signal CLK (0) input to the buffer circuit 1241 (1) is the clock signal CLK itself from the reference signal generator 3, and the clock signal CLK input to the buffer circuit 1241 (2).
- (1) is a signal obtained by delaying the clock signal CLK by the delay device 1242 (1) by a predetermined delay amount ⁇ B.
- the clock signal CLK (2) input to the buffer circuit 1241 (3) (not shown) is a signal obtained by further delaying the clock signal CLK (1) by the delay amount ⁇ B by the delay device 1242 (2).
- the clock signals CLK (0) to CLK (P ⁇ 1) each having a delay interval of the delay amount ⁇ B are input to the buffer circuits 1241 (1) to 1241 (P).
- Each of the clock signals CLK (0) to CLK (P-1) and the second signal to be measured SS (B) are input to the buffer circuits 1241 (1) to 1241 (P), and the second When the level transition of the signal under test SS (B) occurs, each buffer circuit 1241 (1) to 1241 (P) has a level transition timing (the second signal under test SS (B) in FIG. 4 is “0”).
- the level of each clock signal CLK (0) to CLK (P-1) at the timing of transition from “1” to “1”) is latched and “1” or “0” state data is output. For example, in the example of FIG.
- the buffer circuit 1241 (1) is at the level transition timing of the second signal to be measured SS (B), and the clock signal CLK (0) is at the “0” level. "0" status data is output.
- the buffer circuits 1241 (2) and 1241 (3) also output “0” state data.
- the buffer circuit 1241 (4) outputs the state data “1” at the level transition timing of the second signal under measurement SS (B) because the clock signal CLK (3) is at the “1” level.
- the state data group consisting of “1” or “0” output from the buffer circuits 1241 (1) to 1241 (P) has the MSB on the buffer circuit 1241 (1) side and the buffer circuit 1241 (P) side. Is output to the phase difference calculation section 12 as second phase difference measurement data Ds (B) (see FIG. 4).
- the state data number N B (A) from the first state data in the first phase difference measurement data Ds (A) to the timing when the state data transitions from “1” to “0” is the first measured data.
- the elapsed time from the start timing of the clock signal CLK (CLK (0)) immediately before the transition timing of the target signal SS (A) to the transition timing of the first signal under measurement SS (A), and the delay amount ⁇ between the buffer circuits Determined by B. Therefore, the elapsed time ( ⁇ ts in FIG. 4) until the transition timing of the first signal to be measured SS (A) can be calculated as N B (A) ⁇ ⁇ B.
- the number of state data N B (B) from the first state data in the second phase difference measurement data Ds (B) to the state data at the transition timing from “1” to “0” is the second measured data.
- the elapsed time from the start timing of the clock signal CLK (CLK (0)) immediately before the transition timing of the target signal SS (B) to the transition timing of the second signal under measurement SS (B), and the delay amount ⁇ between the buffer circuits Determined by B. Therefore, the elapsed time ( ⁇ t3 in FIG. 4) until the transition timing of the second signal to be measured SS (B) can be calculated as N B (B) ⁇ ⁇ B.
- the phase difference calculation unit 12 calculates a rough phase difference ⁇ t1 having a resolution of one cycle ( ⁇ t clk ) of the clock signal CLK based on the number data string Dt.
- the phase difference calculation unit 12 acquires the number of state data N B (A) from the first phase difference measurement data Ds (A), the front side fraction phase difference which is a fraction on the front side with respect to the coarse phase difference ⁇ t1.
- ⁇ t2 is calculated.
- the front-end fraction phase difference ⁇ t2 is the start timing of the cycle of the clock signal CLK detected by the coarse phase difference ⁇ t1 from the transition timing of the first signal to be measured SS (A), that is, the end timing of the clock signal immediately before this. Is the length of time between. Therefore, the time length from the start timing of the clock signal CLK to the start timing of the first signal to be measured SS (A) may be subtracted from the time length of one cycle of the clock signal CLK (see FIG. 4).
- the phase difference calculation unit 12 multiplies the state data number N B (A) by the delay amount ⁇ B calculated as described above based on the output of the buffer delay measurement circuit 110.
- the phase difference calculation unit 12 acquires the number of state data N B (B) from the second phase difference measurement data Ds (B), the phase difference calculation unit 12 is a fraction that is rearward in time with respect to the rough phase difference ⁇ t1.
- the side fraction phase difference ⁇ t3 is calculated.
- the rear fractional phase difference ⁇ t3 is from the end timing of the cycle of the clock signal CLK detected by the coarse phase difference ⁇ t1, that is, from the start timing of the clock signal immediately after this to the transition timing of the second signal under measurement SS (A). It is a length of time. Therefore, the number of state data N B (B) may be multiplied by the delay amount ⁇ B (see FIG. 4).
- the phase difference calculation unit 12 adds the coarse phase difference ⁇ t1, the front side fraction phase difference ⁇ t2, and the rear side fraction phase difference ⁇ t3 calculated in this way, and thereby the first measured signal SS (A) and the second measured signal.
- the delay amount between the buffers can be set with high accuracy without using analog circuit elements.
- the delay amount between the buffers can be set with high accuracy without using analog circuit elements.
- the phase difference calculation unit 12 stores N B (B) a over multiple acquired and, above
- the phase difference ⁇ t may be calculated after calculating the average value as shown in the equation (1).
- the phase difference can be calculated with higher accuracy.
- the delay amount ⁇ B used at this time the phase difference can be calculated with higher accuracy by using the above-mentioned averaging process.
- circuit configurations of the buffer delay measurement circuit and the phase difference measurement circuit described above are examples.
- a configuration in which a delay device is installed on the CLK input side of each buffer circuit and the input signal is switched may be used.
- FIG. 5A is a block diagram illustrating a main configuration of a frequency measuring device and each device that provides various signals to the frequency measuring device.
- FIG. 5B is a diagram illustrating another configuration example of the frequency measurement device. Note that the GPS receiver 2 and the reference signal generator 1 shown in this embodiment are the same as those shown in the first embodiment, and a description thereof will be omitted.
- the frequency measurement device 6 includes a digital measurement unit 61 and a frequency calculation unit 62.
- the digital measurement unit 61 includes a buffer delay measurement circuit 610 and a frequency measurement circuit 620.
- the buffer delay measurement circuit 610 has the same configuration as the buffer delay measurement circuit 110 shown in the first embodiment, and supplies delay measurement data Ds related to the delay amount ⁇ B between the buffers to the frequency calculation unit 62.
- the frequency measurement circuit 620 also has the same internal circuit configuration as the buffer delay measurement circuits 110 and 610 except that the type of input signal is different.
- the frequency measurement circuit 620 includes the signal to be measured SS (C) and the sampling. A reference signal SCL is input. At this time, the signal to be measured SS (C) is input to the frequency measurement circuit 620 as a substitute for the clock signal CLK of the buffer delay measurement circuit 610.
- the frequency measurement circuit 620 provides the frequency calculation unit 62 with the frequency measurement data Ds (C) having the same data array of “1” and “0” as the delay measurement data Ds.
- the delay amount ⁇ B can be calculated with high accuracy as described above, the frequency f (C) of the signal to be measured SS (C) can also be calculated with high accuracy. As a result, it is possible to perform highly accurate frequency measurement using only a digital circuit without using an analog circuit.
- the buffer delay measurement circuit 610 and the frequency measurement circuit 620 formed by the same TDC are individually provided.
- a frequency measurement can also be performed by the circuit 630.
- an input signal circuit 631 for switching between the clock signal CLK and the signal to be measured SS (C) by digital processing may be provided before the measurement circuit 630.
- 1-phase measurement device 11 61-digital measurement unit 110,610-buffer delay measurement circuit 120-phase difference measurement circuit 12-phase difference calculation unit 2-GPS receiver 20-GPS antenna 21- RF processing unit, 22-baseband processing unit, 23-TCXO, 3-reference signal generator, 31-phase comparator, 32-loop filter, 33-VCO, 34-multiplier, 35, 40-frequency divider, 62-frequency calculation unit, 111, 1231, 1241-buffer circuit, 112, 1232, 1242-delay circuit, 121-counter circuit, 122-counter latch circuit, 620-frequency measurement unit
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Abstract
Description
図1は本実施形態の位相測定装置および当該位相測定装置に各種の信号を与える各装置の主要構成を示すブロック図である。なお、以下の説明では、GPSを用いた例を示すが、他のGNSSを用いてもよく、さらには、外部装置から位相測定装置1および基準信号発生装置3に対してサンプリング基準信号やリファレンス信号を与える構成であってもよい。
図2(A)は位相測定装置1のバッファ遅延測定回路110の主要構成を示すブロック図であり、図2(B)はバッファ遅延測定回路110の測定原理を示すタイミングチャートである。
図3は位相差測定回路120の回路構成を示すブロック図であり、図4は位相差測定原理を示すタイミングチャートである。
図5(A)は周波数測定装置および当該周波数測定装置に各種の信号を与える各装置の主要構成を示すブロック図である。図5(B)は、周波数測定装置の他の構成例を示す図である。なお、本実施形態に示すGPS受信機2および基準信号発生装置1は第1の実施形態に示したものと同じであり、説明は省略する。
Claims (4)
- 測位演算より算出されるリファレンス信号に同期したクロック信号が一定の遅延時間によりそれぞれ異なるタイミングで入力されるとともに、該クロック信号よりも低周波数のサンプリング基準信号が同時に入力され、該サンプリング基準信号の遷移タイミングでの前記クロック信号のレベルに応じた状態データをそれぞれに発生する複数のバッファを備え、該複数のバッファからの状態データ群からなる遅延測定用データを出力するバッファ遅延量測定回路と、
測定対象となる位相差を生じる第1被測定対象信号と第2被測定対象信号の内の前記第1被測定対象信号が入力されるとともに、前記遅延量による互いに異なるタイミングの前記クロック信号が入力され、前記第1被測定対象信号の遷移タイミングでの前記クロック信号のレベルに応じた状態データをそれぞれに発生する複数のバッファを備え、該複数のバッファからの状態データ群からなる第1位相差測定用データを出力する第1部分位相差測定回路と、前記第2被測定対象信号が入力されるとともに、前記遅延量による互いに異なるタイミングの前記クロック信号が入力され、前記第2被対象信号の遷移タイミングでの前記クロック信号のレベルに応じた状態データをそれぞれに発生する複数のバッファを備え、該複数のバッファからの状態データ群からなる第2位相差測定用データを出力する第2位相差測定用回路と、を備えた位相差測定回路と、
前記遅延測定用データに基づいて各バッファ間の前記遅延量を算出し、前記第1位相差測定用データおよび前記第2位相差測定用データの前記クロック信号の遷移タイミングに対する差分値と前記遅延量とに基づいて前記位相差を算出する位相差演算部と、
を備えた位相測定装置。 - 前記位相差測定回路は、前記クロック信号の1周期単位の個数を測定する開始タイミングと終了タイミングとを前記第1測定被対象信号と前記第2測定被対象信号によって与えることで、前記位相差に含まれる前記クロック信号の1周期単位の個数を算出する第3部分位相差測定回路を備え、
前記位相差演算部は、前記クロック信号の1周期単位の個数に応じた時間長をも含んで、前記位相差の算出を行う、請求項1に記載の位相測定装置。 - 測位演算より算出されるリファレンス信号に同期したクロック信号が一定の遅延時間によりそれぞれ異なるタイミングで入力されるとともに、該クロック信号よりも低周波数のサンプリング基準信号が同時に入力され、該サンプリング基準信号の遷移タイミングでの前記クロック信号のレベルに応じた状態データをそれぞれに発生する複数のバッファを備え、該複数のバッファからの状態データ群からなる遅延測定用データを出力するバッファ遅延量測定回路と、
第3被測定対象信号が一定の遅延時間によりそれぞれ異なるタイミングで入力されるとともに、該第3被測定対象信号よりも低周波数のサンプリング基準信号が同時に入力され、該サンプリング基準信号の遷移タイミングでの前記第3被測定対象信号のレベルに応じた状態データをそれぞれに発生する複数のバッファを備え、該複数のバッファからの状態データ群からなる周波数測定用データを出力する周波数測定回路と、
前記遅延測定用データに基づいて各バッファ間の前記遅延量を算出し、前記周波数測定用データと前記遅延量とに基づいて前記第3被測定対象信号の周波数または周期を算出する周波数演算部と、
を備えた周波数測定装置。 - 測位演算より算出されるリファレンス信号に同期したクロック信号もしくは第3被測定対象信号のいずれか一方が一定の遅延時間によりそれぞれ異なるタイミングで入力されるとともに、前記クロック信号および前記第3被測定対象信号よりも低周波数のサンプリング基準信号が同時に入力され、前記サンプリング基準信号の遷移タイミングでの前記クロック信号または前記第3被測定対象信号のレベルに応じた状態データをそれぞれに発生する複数のバッファを備え、前記クロック信号が入力された場合には複数のバッファからの状態データ群からなる遅延測定用データを出力し、前記第3被測定対象信号が入力された場合には前記複数のバッファからの状態データ群からなる周波数測定用データを出力する測定回路と、
前記遅延測定用データに基づいて各バッファ間の前記遅延量を算出し、前記周波数測定用データと前記遅延量とに基づいて前記第3被測定対象信号の周波数または周期を算出する周波数演算部と、
を備えた周波数測定装置。
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105589328A (zh) * | 2014-10-22 | 2016-05-18 | ***通信集团公司 | 时间同步测试方法、测试精度确定方法及装置 |
CN105842537A (zh) * | 2016-03-18 | 2016-08-10 | 山东交通学院 | 基于集成鉴相鉴频器的相位差测量方法及电路 |
CN106569033A (zh) * | 2016-10-31 | 2017-04-19 | 北京大学 | 一种高精度快速频率计 |
JP2020135350A (ja) * | 2019-02-19 | 2020-08-31 | ルネサスエレクトロニクス株式会社 | 半導体装置、信号処理システムおよび信号処理システムの制御方法 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
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JP7043959B2 (ja) * | 2018-04-27 | 2022-03-30 | セイコーエプソン株式会社 | カウント値生成回路、物理量センサーモジュール及び構造物監視装置 |
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TWI668453B (zh) * | 2018-12-26 | 2019-08-11 | 致茂電子股份有限公司 | 信號週期測量電路與方法 |
JP2021027496A (ja) * | 2019-08-07 | 2021-02-22 | セイコーエプソン株式会社 | 回路装置、物理量測定装置、電子機器及び移動体 |
WO2021254606A1 (en) * | 2020-06-17 | 2021-12-23 | Telefonaktiebolaget Lm Ericsson (Publ) | Devices and method for frequency determination |
CN112710897A (zh) * | 2020-12-07 | 2021-04-27 | 广东电网有限责任公司韶关供电局 | 一种频率测量电路 |
CN113092858B (zh) * | 2021-04-12 | 2022-04-12 | 湖南师范大学 | 一种基于时频信息测量的高精度频标比对***及比对方法 |
CN114814358B (zh) * | 2022-06-27 | 2022-11-01 | 成都凯天电子股份有限公司 | 一种频率测量***及方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07229979A (ja) * | 1994-02-18 | 1995-08-29 | Yokogawa Electric Corp | 多相クロック時間計測回路 |
JPH10111369A (ja) * | 1996-10-09 | 1998-04-28 | Matsushita Electric Ind Co Ltd | 時間計数回路及びpll回路 |
JP2000286698A (ja) * | 1999-01-26 | 2000-10-13 | Furuno Electric Co Ltd | 周波数信号および周期パルス信号発生装置 |
JP2002334434A (ja) * | 2001-05-01 | 2002-11-22 | Matsushita Electric Ind Co Ltd | 遅延制御回路 |
WO2007093221A1 (en) * | 2006-02-17 | 2007-08-23 | Verigy (Singapore) Pte. Ltd. | Time-to-digital conversion with calibration pulse injection |
WO2008108374A1 (ja) * | 2007-03-08 | 2008-09-12 | Advantest Corporation | 信号測定装置および試験装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3213801A1 (de) * | 1982-04-15 | 1983-10-27 | Alfred Teves Gmbh, 6000 Frankfurt | Verfahren und vorrichtung zur erzeugung von zahlenwerten, die der frequenz der messimpulse einer messimpulsfolge proportional sind |
JPS6128070U (ja) * | 1984-07-26 | 1986-02-19 | パイオニア株式会社 | デイジタル周波数位相比較器 |
DE4211701A1 (de) * | 1992-04-08 | 1993-10-14 | Thomson Brandt Gmbh | Verfahren und Vorrichtung zur Phasenmessung |
US5440592A (en) * | 1993-03-31 | 1995-08-08 | Intel Corporation | Method and apparatus for measuring frequency and high/low time of a digital signal |
JP3592376B2 (ja) * | 1994-08-10 | 2004-11-24 | 株式会社アドバンテスト | 時間間隔測定装置 |
US5796682A (en) * | 1995-10-30 | 1998-08-18 | Motorola, Inc. | Method for measuring time and structure therefor |
JP3175600B2 (ja) * | 1996-08-09 | 2001-06-11 | 株式会社デンソー | 時間測定装置 |
JP2001059863A (ja) * | 1999-08-25 | 2001-03-06 | Furuno Electric Co Ltd | 方位測定装置 |
JP2001074824A (ja) * | 1999-09-06 | 2001-03-23 | Furuno Electric Co Ltd | サイクルスリップ監視装置 |
JP2005134215A (ja) * | 2003-10-29 | 2005-05-26 | Furuno Electric Co Ltd | 信号到来時間差測定システム |
JP2005233975A (ja) * | 2005-03-28 | 2005-09-02 | Fujitsu Ltd | 遅延測定装置 |
JP2007017158A (ja) | 2005-07-05 | 2007-01-25 | Sharp Corp | テスト回路、遅延回路、クロック発生回路、及び、イメージセンサ |
JP2007248142A (ja) * | 2006-03-14 | 2007-09-27 | Toshiba Corp | 半導体装置 |
-
2010
- 2010-02-26 JP JP2011501675A patent/JP5559142B2/ja active Active
- 2010-02-26 US US13/201,648 patent/US8738312B2/en active Active
- 2010-02-26 CN CN2010800094757A patent/CN102334038B/zh active Active
- 2010-02-26 KR KR1020117020815A patent/KR101584394B1/ko active IP Right Grant
- 2010-02-26 EP EP17150720.5A patent/EP3196661B1/en active Active
- 2010-02-26 EP EP10746339.0A patent/EP2402772B1/en active Active
- 2010-02-26 WO PCT/JP2010/053144 patent/WO2010098460A1/ja active Application Filing
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07229979A (ja) * | 1994-02-18 | 1995-08-29 | Yokogawa Electric Corp | 多相クロック時間計測回路 |
JPH10111369A (ja) * | 1996-10-09 | 1998-04-28 | Matsushita Electric Ind Co Ltd | 時間計数回路及びpll回路 |
JP2000286698A (ja) * | 1999-01-26 | 2000-10-13 | Furuno Electric Co Ltd | 周波数信号および周期パルス信号発生装置 |
JP2002334434A (ja) * | 2001-05-01 | 2002-11-22 | Matsushita Electric Ind Co Ltd | 遅延制御回路 |
WO2007093221A1 (en) * | 2006-02-17 | 2007-08-23 | Verigy (Singapore) Pte. Ltd. | Time-to-digital conversion with calibration pulse injection |
WO2008108374A1 (ja) * | 2007-03-08 | 2008-09-12 | Advantest Corporation | 信号測定装置および試験装置 |
Non-Patent Citations (2)
Title |
---|
KAZUYA KATANO, YUJI YAMAGUCHI: "Time: Measuring Technique of Time and Frequency", MEASUREMENT AND CONTROL, vol. 44, no. 10, October 2005 (2005-10-01) |
See also references of EP2402772A4 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105589328A (zh) * | 2014-10-22 | 2016-05-18 | ***通信集团公司 | 时间同步测试方法、测试精度确定方法及装置 |
CN105842537A (zh) * | 2016-03-18 | 2016-08-10 | 山东交通学院 | 基于集成鉴相鉴频器的相位差测量方法及电路 |
CN105842537B (zh) * | 2016-03-18 | 2018-09-04 | 山东交通学院 | 基于集成鉴相鉴频器的相位差测量方法及电路 |
CN106569033A (zh) * | 2016-10-31 | 2017-04-19 | 北京大学 | 一种高精度快速频率计 |
CN106569033B (zh) * | 2016-10-31 | 2019-06-18 | 北京大学 | 一种高精度快速频率计 |
JP2020135350A (ja) * | 2019-02-19 | 2020-08-31 | ルネサスエレクトロニクス株式会社 | 半導体装置、信号処理システムおよび信号処理システムの制御方法 |
JP7273532B2 (ja) | 2019-02-19 | 2023-05-15 | ルネサスエレクトロニクス株式会社 | 半導体装置、信号処理システムおよび信号処理システムの制御方法 |
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Publication number | Publication date |
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JP5559142B2 (ja) | 2014-07-23 |
CN102334038B (zh) | 2013-11-06 |
JPWO2010098460A1 (ja) | 2012-09-06 |
EP2402772A4 (en) | 2012-08-22 |
CN102334038A (zh) | 2012-01-25 |
KR20110127676A (ko) | 2011-11-25 |
US8738312B2 (en) | 2014-05-27 |
EP2402772A1 (en) | 2012-01-04 |
US20110301895A1 (en) | 2011-12-08 |
EP3196661A1 (en) | 2017-07-26 |
EP3196661B1 (en) | 2021-04-21 |
EP2402772B1 (en) | 2017-06-14 |
KR101584394B1 (ko) | 2016-01-11 |
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