WO2010095378A1 - 出力装置および試験装置 - Google Patents
出力装置および試験装置 Download PDFInfo
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- WO2010095378A1 WO2010095378A1 PCT/JP2010/000637 JP2010000637W WO2010095378A1 WO 2010095378 A1 WO2010095378 A1 WO 2010095378A1 JP 2010000637 W JP2010000637 W JP 2010000637W WO 2010095378 A1 WO2010095378 A1 WO 2010095378A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/12—Shaping pulses by steepening leading or trailing edges
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
Definitions
- the present invention relates to an output device and a test device.
- a device such as a DDR that transmits a clock signal in parallel with a data signal is known. Such a device can transfer a plurality of bits of data in one cycle of the clock signal, so that the data transfer rate can be increased.
- the range of the slew rate of the data signal and the clock signal that can be obtained varies depending on the quality of the device. Therefore, such a device is tested by a test apparatus at the time of shipment to determine whether a signal with a predetermined slew rate can be acquired.
- an object of one aspect of the present invention is to provide an output device and a test device that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims.
- the dependent claims define further advantageous specific examples of the present invention.
- an output device that outputs an output signal corresponding to an input signal, each of which outputs an intermediate signal having a waveform corresponding to the input signal.
- the intermediate signal output from each of the plurality of drivers, an addition unit that outputs the intermediate signal as an output signal, and the input between the plurality of drivers according to a specified slew rate
- an output device including a control unit that sets a difference in delay amount from when a signal starts to change until the intermediate signal starts to change, and a test device including such an output device.
- an output device that outputs an output signal corresponding to an input signal, a driver that outputs an intermediate signal having a waveform corresponding to the input signal, and a waveform corresponding to the input signal.
- a correction driver that outputs a correction signal; a high-pass filter that passes a high-frequency component of the correction signal output from the correction driver; and the correction signal that has passed through the intermediate signal and the high-pass filter output from the driver.
- An output device comprising: an adding unit that adds and outputs the output signal; and a control unit that sets a voltage level of the correction signal output from the correction driver according to a specified slew rate; and A test apparatus including such an output device is provided.
- FIG. 1 shows a configuration of an output device 10 according to the present embodiment.
- FIG. 2 shows an example of an input signal, an intermediate signal, and an output signal when the difference in delay amount among the plurality of drivers 24 is zero.
- FIG. 3 shows a case where the delay amount difference between the first driver 24 and the second driver 24 is t1, and the delay amount difference between the second driver 24 and the third driver 24 is t2.
- An example of an input signal, an intermediate signal and an output signal is shown.
- FIG. 4 shows a first example of the rising waveform of the output signal.
- FIG. 5 shows a first example of the falling waveform of the output signal.
- FIG. 6 shows a second example of the rising waveform of the output signal.
- FIG. 7 shows a second example of the falling waveform of the output signal.
- FIG. 4 shows a first example of the rising waveform of the output signal.
- FIG. 5 shows a first example of the falling waveform of the output signal.
- FIG. 6 shows a second example of the rising
- FIG. 8 shows a configuration of the output device 10 according to a first modification of the present embodiment.
- FIG. 9 shows an example of the input signal, the intermediate signal, the correction signal before and after passing through the high-pass filter 72, and the output signal when the correction driver 70 outputs a correction signal having a non-inverted waveform with respect to the input signal.
- FIG. 10 shows an example of the input signal, the intermediate signal, the correction signal before and after passing through the high-pass filter 72, and the output signal when the correction driver 70 outputs a correction signal having an inverted waveform with respect to the input signal.
- FIG. 11 shows a first example of the rising waveform of the output signal when the voltage level of the correction signal output from the correction driver 70 is changed.
- FIG. 9 shows an example of the input signal, the intermediate signal, the correction signal before and after passing through the high-pass filter 72, and the output signal when the correction driver 70 outputs a correction signal having a non-inverted waveform with respect to the input signal.
- FIG. 10 shows an example of
- FIG. 12 shows a second example of the rising waveform of the output signal when the voltage level of the correction signal output from the correction driver 70 is changed.
- FIG. 13 shows a configuration of the output device 10 according to a second modification of the present embodiment.
- FIG. 14 shows a configuration of the test apparatus 100 according to the present embodiment.
- FIG. 1 shows a configuration of an output device 10 according to the present embodiment.
- the output device 10 outputs an output signal having a voltage waveform corresponding to the input signal.
- the output device 10 includes a plurality of variable delay units 22, a plurality of drivers 24, a plurality of power supply units 26, a plurality of output resistors 28, a plurality of transmission paths 30, an addition unit 32, a control unit 34, A calibration unit 36 and a storage unit 38 are provided.
- Each of the plurality of variable delay units 22 is associated with each of the plurality of drivers 24 on a one-to-one basis.
- the delay amount of each variable delay unit 22 is set by the control unit 34.
- Each variable delay unit 22 delays the input signal input by the output device 10 by a set delay amount and outputs the delayed signal.
- Each of the plurality of drivers 24 receives the input signal delayed by the corresponding variable delay unit 22 and outputs an intermediate signal having a waveform corresponding to the received input signal.
- each driver 24 is a buffer circuit that amplifies and outputs a given voltage signal.
- the plurality of drivers 24 are, for example, the same type of voltage buffer circuit having substantially the same characteristics.
- the plurality of power supply units 26 are associated with each of the plurality of drivers 24 on a one-to-one basis. Each power supply unit 26 applies a driving voltage to the corresponding driver 24 to control the voltage level of the intermediate signal output from the corresponding driver 24. As an example, the level of the driving voltage of each power supply unit 26 is set by the control unit 34.
- Each of the plurality of output resistors 28 is associated with each of the plurality of drivers 24 on a one-to-one basis.
- Each of the plurality of transmission lines 30 is associated with each of the plurality of drivers 24 on a one-to-one basis.
- each output resistor 28 is connected to the output terminal of the corresponding driver 24.
- Each transmission line 30 has one end connected to the other end of the corresponding output resistor 28 to which the driver 24 is not connected.
- Each transmission line 30 is connected to the adder 32 at the other end to which the output resistor 28 is not connected.
- the addition unit 32 receives the intermediate signal output from each of the plurality of drivers 24 via the output resistor 28 and the transmission path 30.
- the adder 32 adds the intermediate signals output from each of the plurality of drivers 24 and outputs the result as an output signal.
- the adding unit 32 includes a plurality of input-side resistors 56 and an output-side resistor 58.
- Each of the plurality of input-side resistors 56 is associated with each of the plurality of drivers 24 on a one-to-one basis.
- Each input-side resistor 56 is provided between the input node 52 for inputting the intermediate signal output from the corresponding driver 24 and the connection node 50.
- the output side resistor 58 is provided between the connection node 50 and the output node 54 that outputs an output signal to the outside.
- Such an adding unit 32 can add the voltage levels of the intermediate signals output from each of the plurality of drivers 24.
- the adding unit 32 has a resistance value when viewed from the output terminal 12 side of the output device 10 of the termination resistor 42 connected between the output terminal 12 of the output device 10 and the reference potential. Match the resistance value. For example, when the resistance value of each output resistor 28 is R ⁇ (for example, 50 ⁇ ) and the resistance value of the termination resistor 42 is R ⁇ (for example, 50 ⁇ ), each of the input side resistor 56 and the output side resistor 58 is R / 2 ⁇ (for example, 25 ⁇ ) may be used.
- each input-side resistor 56 is 0 ⁇ (that is, a state where each input node 52 and the connection node 50 are short-circuited), and the output-side resistor 58 is (R ⁇ 2 / 3) It may be ⁇ (for example, 33.3 ⁇ ).
- the control unit 34 is designated with a slew rate from the outside.
- the control unit 34 sets a difference in delay amount between the plurality of drivers 24 from when the input signal starts to change until the intermediate signal starts to change according to the designated slew rate. For example, the control unit 34 sets a delay amount corresponding to the designated slew rate for each of the plurality of variable delay units 22.
- control unit 34 may further set the voltage level of the intermediate signal output from each of the plurality of drivers 24 in accordance with the designated slew rate. As an example, the control unit 34 sets a driving voltage corresponding to the designated slew rate for each of the plurality of power supply units 26.
- the calibration unit 36 measures a difference in delay amount among the plurality of drivers 24 from which an output signal having a specified slew rate is obtained. As an example, the calibration unit 36 measures the delay amount of each of the plurality of variable delay units 22 from which an output signal having a specified slew rate is obtained.
- the calibration unit 36 gives an input signal to each of the plurality of variable delay units 22 in a state where the delay amount is set for each of the plurality of variable delay units 22, and is output from the addition unit 32. Measure the slew rate of the output signal. Then, the calibration unit 36 measures the slew rate in the same manner by changing the difference in delay amount given to each of the plurality of variable delay units 22 by a predetermined amount, for example. Thereby, the calibration unit 36 can detect the delay amount of each of the plurality of variable delay units 22 from which the output signal of the specified slew rate is obtained.
- the calibration unit 36 obtains an output signal with a specified slew rate, and provides a difference in delay amount between the plurality of drivers 24 and an intermediate signal output from each of the plurality of drivers 24.
- a combination of voltage levels may be measured.
- the calibration unit 36 changes the combination of the difference in delay amount given to each of the plurality of variable delay units 22 and the voltage level of the intermediate signal output from each of the plurality of drivers 24 by a predetermined amount, for example.
- the slew rate may be measured.
- the storage unit 38 stores the measurement result obtained by the calibration unit 36.
- the storage unit 38 stores a table representing a correspondence relationship between a slew rate designated for the control unit 34 and a delay amount set in each of the plurality of variable delay units 22. Then, the control unit 34 reads the delay amount of each of the plurality of variable delay units 22 corresponding to the designated slew rate, and sets the read delay amount in the corresponding variable delay unit 22. Thereby, the control unit 34 can set the difference in delay amount among the plurality of drivers 24 based on the measurement result by the calibration unit 36.
- the storage unit 38 further stores a table representing the correspondence relationship between the slew rate designated for the control unit 34 and the voltage levels of the intermediate signals output from each of the plurality of drivers 24. May be. Then, the control unit 34 reads the voltage level of the intermediate signal output from each of the plurality of drivers 24 corresponding to the designated slew rate, and supplies the drive voltage corresponding to the read voltage level to the corresponding power supply unit 26. Set. Accordingly, the control unit 34 can set the voltage level of the intermediate signal output from each of the plurality of drivers 24 based on the measurement result by the calibration unit 36.
- FIG. 2 and 3 show examples of input signals given to the output device 10, intermediate signals output from the first to third drivers 24, and output signals output from the output device 10, respectively.
- FIG. 2 shows signals when the difference in delay amount between the plurality of drivers 24 from when the input signal starts to change until the intermediate signal starts to change is zero.
- FIG. 3 shows a case where the delay amount difference between the first driver 24 and the second driver 24 is t1, and the delay amount difference between the second driver 24 and the third driver 24 is t2. Signals are shown.
- the amplitude of the output signal is the sum of the amplitudes of the intermediate signals output from each of the plurality of drivers 24. For example, when each of the voltage amplitudes of the intermediate signals output from the three drivers 24 is V volts, the voltage amplitude of the output signal is 3 ⁇ V volts.
- the period from when the output signal starts to change to when the change ends (sometimes referred to as a change period) is the change in the intermediate signal that has finished changing the latest from the change start timing of the intermediate signal that starts changing the earliest. This is the period until the end timing.
- the change period of the intermediate signal output from each of the first to third drivers 24 is T
- the delay amount difference between the first driver 24 and the second driver 24 is t1
- the change period of the output signal is T + t1 + t2.
- the timing at which the signal starts to change is the timing at which the level of the signal changes from the stable level by a first ratio (for example, 20%) of the amplitude.
- the timing at which the signal finishes changing is the second level of amplitude (the second rate is larger than the first rate, for example 80%) from the level when the signal is stable. ) The timing has changed.
- the signal slew rate is the slope of the signal (that is, the amount of time change of the signal). If the difference in delay amount among the plurality of drivers 24 is large, the change period of the output signal becomes large. Therefore, the slew rate of the output signal becomes smaller as the difference in delay amount among the plurality of drivers 24 becomes larger. Thus, the control unit 34 can change the slew rate of the output signal by changing the difference in delay amount among the plurality of drivers 24.
- control unit 34 can change the slew rate of the output signal by further changing the voltage level of the intermediate signal output from each of the plurality of drivers 24.
- the control unit 34 can maximize the slew rate of the output signal by setting the difference in delay amount among the plurality of drivers 24 to zero. Further, the control unit 34 can change the output signal with good linearity by equally shifting the difference in delay amount among the plurality of drivers 24. For example, the control unit 34 sets the delay amount difference t1 between the first driver and the second driver to be the same as the delay amount difference t2 between the second driver and the third driver. By doing so, the output signal can be changed with good linearity.
- control unit 34 may reduce the delay amount between the plurality of drivers 24 within a range in which the change period of the output signal is equal to or shorter than the total change time of the intermediate signals output from the plurality of drivers 24. Set the difference. For example, when the change period of each intermediate signal output from each of the first to third drivers 24 is T, the control unit 34 can change the output signal change period within a range of 3 ⁇ T or less. A difference in delay amount between the drivers 24 is set. Thereby, the control part 34 can change an output signal with sufficient linearity.
- FIG. 4 shows a first example of the rising waveform of the output signal when the delay amount difference among the plurality of drivers 24 is changed.
- FIG. 5 shows a first example of the falling waveform of the output signal when the delay amount difference between the plurality of drivers 24 is changed.
- the output device 10 can change the slew rate of the output signal stepwise by changing the difference in delay amount among the plurality of drivers 24.
- FIG. 6 shows a second example of the rising waveform of the output signal when the delay amount difference among the plurality of drivers 24 is changed.
- FIG. 7 shows a second example of the falling waveform of the output signal when the delay amount difference among the plurality of drivers 24 is changed.
- FIGS. 6 and 7 show waveforms in each case where the delay amount difference between the three-channel drivers 24 is changed from 0 ps to 300 ps at 50 ps / step, as in FIGS. 4 and 5.
- the control unit 34 sets the time between the drivers 24 so that the time from when the input signal starts to change until the output signal reaches a predetermined voltage level is the same.
- a difference in delay amount may be set.
- the control unit 34 may set the difference in delay amount among the plurality of drivers 24 so that the timing at which the amplitude of the output signal is 50% is the same regardless of the change in the slew rate.
- FIG. 8 shows a configuration of the output device 10 according to a first modification of the present embodiment. Since the output device 10 according to the present modification has substantially the same configuration and function as the output device 10 shown in FIG. 1, the output device 10 has substantially the same configuration and function as the members of the output device 10 shown in FIG. The same reference numerals are given to the members, and the description will be omitted except for the differences.
- the output device 10 includes one driver 24, a correction driver 70, two power supply units 26, two output resistors 28, two transmission lines 30, a high-pass filter 72, An adding unit 32, a control unit 34, a calibration unit 36, and a storage unit 38 are provided.
- the correction driver 70 receives the input signal and outputs a correction signal having a waveform corresponding to the received input signal.
- the correction driver 70 is a buffer circuit that amplifies and outputs a given voltage signal.
- the driver 24 and the correction driver 70 are the same type of voltage buffer circuit having substantially the same characteristics.
- One of the two power supply units 26 is associated with the driver 24, and the other is associated with the correction driver 70.
- the power supply unit 26 corresponding to the correction driver 70 gives a drive voltage to the correction driver 70 and sets the voltage level of the correction signal output from the correction driver 70.
- the power supply unit 26 associated with the correction driver 70 is set with a drive voltage from the control unit 34, and outputs an intermediate signal output from the correction driver 70 at a voltage of the set voltage level.
- the correction driver 70 also outputs a correction signal having a waveform obtained by inverting the input signal in accordance with the drive voltage supplied from the power supply unit 26.
- the correction driver 70 may be configured to have a circuit that switches inversion or non-inversion of the correction signal. For example, when a positive drive voltage is supplied from the power supply unit 26, the correction driver 70 outputs a correction signal having a non-inverted waveform with respect to the input signal, and is supplied with a negative drive voltage from the power supply unit 26. In this case, a configuration in which a correction signal having an inverted waveform with respect to the input signal may be output.
- One of the two output resistors 28 is associated with the driver 24, and the other is associated with the correction driver 70.
- One of the two transmission paths 30 is associated with the driver 24 and the other is associated with the correction driver 70.
- the output resistor 28 and the transmission line 30 associated with the correction driver 70 are connected in series, and the correction signal output from the correction driver 70 is propagated to the adding unit 32.
- the high pass filter 72 passes the high frequency component of the correction signal output from the correction driver 70 and propagates it to the adder 32.
- the high-pass filter 72 may be a capacitor inserted in series between the transmission line 30 corresponding to the correction driver 70 and the adder 32.
- the addition unit 32 according to the present modification receives the intermediate signal output from the driver 24 and the correction signal that has passed through the high-pass filter 72. Then, the adder 32 according to this modification adds the intermediate signal output from the driver 24 and the correction signal that has passed through the high-pass filter 72, and outputs the result as an output signal.
- the adder 32 includes a first signal line 74 that connects between the output terminal of the transmission line 30 that propagates the intermediate signal output from the driver 24 and the output terminal 12 of the output device 10, and a high-pass filter. And a second signal line 76 connecting the output terminal 72 and the first signal line 74.
- the adder 32 can add the voltage level of the correction signal output from the high-pass filter 72 to the voltage level of the intermediate signal output from the driver 24 and output the result from the output terminal 12.
- the control unit 34 sets the voltage level of the correction signal output from the correction driver 70 according to the specified slew rate. For example, the control unit 34 causes the power supply unit 26 corresponding to the correction driver 70 to output a drive voltage corresponding to the designated slew rate.
- the calibration unit 36 measures the voltage level of the correction signal from which an output signal with a specified slew rate is obtained.
- the calibration unit 36 supplies an input signal and measures the slew rate of the output signal in a state where a predetermined drive voltage is supplied to the correction driver 70. Then, the calibration unit 36 measures the slew rate in the same manner by changing the drive voltage supplied to the correction driver 70 by, for example, a predetermined amount. As a result, the calibration unit 36 can detect the voltage level of the correction signal from which the output signal of the specified slew rate is obtained.
- FIG. 9 and 10 show an input signal supplied to the output device 10 according to the first modification, an intermediate signal output from the driver 24, a correction signal before and after passing through the high-pass filter 72, and an output device 10.
- An example of an output signal is shown.
- FIG. 9 shows each signal when the correction driver 70 outputs a correction signal having a non-inverted waveform with respect to the input signal.
- FIG. 10 shows each signal when the correction driver 70 outputs a correction signal having an inverted waveform with respect to the input signal.
- the high-frequency component of the correction signal having a non-inverted waveform with respect to the input signal is a mountain-shaped waveform having a peak in the change direction of the input signal. Therefore, when the signal having such a waveform is added to the intermediate signal having a non-inverted waveform with respect to the input signal, the gradient of the change of the intermediate signal can be made steeper.
- the peak of the high frequency component of the correction signal having a non-inverted waveform with respect to the input signal increases as the amplitude of the correction signal increases. Therefore, when the high frequency component of the non-inverted waveform correction signal having a larger amplitude is added to the non-inverted waveform intermediate signal with respect to the input signal, the gradient of the change in the intermediate signal can be made steeper. .
- the high frequency component of the correction signal having an inverted waveform with respect to the input signal is a mountain-shaped waveform having a peak in the direction opposite to the change direction of the input signal. Therefore, when a signal having such a waveform is added to an intermediate signal having a non-inverted waveform with respect to the input signal, the slope of the change in the intermediate signal can be made more gradual.
- the peak of the high frequency component of the correction signal having an inverted waveform with respect to the input signal increases as the amplitude of the correction signal increases. Therefore, when the high-frequency component of the correction signal having an inverted waveform having a larger amplitude is added to the intermediate signal having a non-inverted waveform with respect to the input signal, the gradient of the change of the intermediate signal can be made gentler.
- control unit 34 can change the slew rate of the output signal by changing the voltage level of the correction signal output from the correction driver 70.
- FIG. 11 shows a first example of the rising waveform of the output signal when the voltage level of the correction signal output from the correction driver 70 is changed.
- FIG. 12 shows a second example of the rising waveform of the output signal when the voltage level of the correction signal output from the correction driver 70 is changed.
- correction signals R1, R2, R3 having non-inverted waveforms with amplitudes of 1, 2, and 3 volts, no correction signals (R4), and correcting inverted waveforms with amplitudes of 1, 2, and 3 volts. It represents the waveform of the signals (R5, R6, R7).
- the output device 10 can change the slew rate of the output signal stepwise by changing the amplitude and waveform pattern of the correction signal.
- control unit 34 adjusts the amplitude and waveform pattern of the correction signal so that the time from when the input signal starts to change until the output signal reaches a predetermined voltage level is the same. May be changed.
- control unit 34 may set the amplitude and waveform pattern of the correction signal so that the timing at which the amplitude of the output signal is 50% is the same regardless of the change in the slew rate.
- FIG. 13 shows a configuration of the output device 10 according to a second modification of the present embodiment. Since the output device 10 according to the present modification has substantially the same configuration and function as the output device 10 shown in FIG. 1, the output device 10 has substantially the same configuration and function as the members of the output device 10 shown in FIG. The same reference numerals are given to the members, and the description will be omitted except for the differences.
- the output device 10 according to this modification further includes a correction driver 70 and a high-pass filter 72.
- the output device 10 according to this modification further includes a power supply unit 26, an output resistor 28, and a transmission line 30, each corresponding to the correction driver 70.
- the correction driver 70 and the high-pass filter 72 have the same function and configuration as the members having the same reference numerals shown in FIG. Further, the power supply unit 26, the output resistor 28, and the transmission path 30 corresponding to the correction driver 70 have the same functions and functions as the power supply unit 26, the output resistance 28, and the transmission path 30 corresponding to the correction driver 70 shown in FIG. It has a configuration. Therefore, description of these components will be omitted except for differences.
- the adder 32 receives the intermediate signal output from each of the plurality of drivers 24 via the corresponding output resistor 28 and transmission line 30. Further, the adding unit 32 receives the correction signal that has passed through the high-pass filter 72. The adder 32 adds the intermediate signal output from the plurality of drivers 24 and the correction signal that has passed through the high-pass filter 72, and outputs the result as an output signal.
- the addition unit 32 includes a first addition circuit 82 and a second addition circuit 84 as an example.
- the first addition circuit 82 adds the voltage levels of the intermediate signals output from each of the plurality of drivers 24.
- the first addition circuit 82 has a configuration in which the resistance value when viewed from the output terminal 12 side of the output device 10 matches the resistance value of the termination resistor 42, as in the addition unit 32 illustrated in FIG. 1. It is.
- the second adder circuit 84 propagates the signal added by the first adder circuit 82 to the output terminal 12 of the output device 10, the output terminal of the high-pass filter 72, and the first signal line 74. And a second signal line 76 connecting between the two. Thereby, the adder 32 can add the voltage level of the correction signal output from the high-pass filter 72 to the signal after the voltage of the intermediate signal is added by the first adder circuit 82 and output the signal from the output terminal 12. .
- the control unit 34 sets the delay amount for each of the plurality of variable delay units 22 according to the specified slew rate, and sets the voltage level of the correction signal output from the correction driver 70. Set.
- the control unit 34 may further set the voltage level of the intermediate signal output from each of the plurality of drivers 24.
- the calibration unit 36 obtains an output signal having a specified slew rate, a delay amount difference between the plurality of drivers 24, and a voltage level and a waveform of the correction signal output from the correction driver 70. Measure the combination of patterns. Further, as an example, the calibration unit 36 may further measure a combination with the voltage level of the intermediate signal output from each of the plurality of drivers 24.
- the output device 10 according to this modification example can change the slew rate of the output signal in more detail.
- FIG. 14 shows a configuration of the test apparatus 100 according to the present embodiment.
- the test apparatus 100 includes a member included in the output apparatus 10 described with reference to FIGS.
- Members having substantially the same configuration and function as the members provided in the output device 10 are denoted by the same reference numerals in FIG. 14 and description thereof will be omitted except for differences.
- Test apparatus 100 tests DUT 200.
- the test apparatus 100 includes a main body unit 102 and a performance board 104.
- the main body 102 supplies a signal to the device under test (DUT) 200 and acquires the signal from the DUT 200.
- DUT device under test
- the performance board 104 is equipped with the DUT 200.
- the performance board 104 is connected to the main body 102 via a plurality of transmission paths 30.
- the main body 102 includes a pattern generator 110, a timing generator 112, a plurality of waveform generators 114, a comparator 118, an acquisition unit 120, a determination unit 122, a plurality of drivers 24, and a plurality of power supply units 26. And a plurality of output resistors 28.
- the pattern generator 110 generates a logic pattern that specifies the waveform and generation timing of a signal generated from the main body 102. Further, the pattern generator 110 generates an expected pattern that specifies an expected value of the signal input by the main body 102 and an acquisition timing for acquiring the signal. The pattern generator 110 supplies a logic pattern to the waveform generator 114. Further, the pattern generator 110 supplies the expected pattern to the determination unit 122.
- the timing generator 112 generates a timing signal for designating the timing at which the main body 102 outputs a signal.
- the timing generator 112 generates a strobe signal for designating the timing at which the main body 102 inputs a signal value.
- the timing generator 112 supplies a timing signal to the waveform generation unit 114 and supplies a strobe signal to the acquisition unit 120.
- Each waveform generation unit 114 delays the given timing signal by a delay amount corresponding to the generation timing designated by the pattern generator 110.
- the waveform generator 114 generates a logic signal having a waveform designated by the pattern generator 110 at the timing of the delayed timing signal.
- the waveform generator 114 supplies the generated logic signal to the corresponding driver 24.
- Each driver 24 supplies a signal of a voltage level corresponding to the logic signal given from the corresponding waveform generation unit 114 to the performance board 104 via the corresponding output resistor 28 and the transmission path 30.
- the comparator 118 receives a signal from a corresponding terminal of the DUT 200 and generates a logic signal representing a logic value corresponding to the voltage level of the input signal. Then, the comparator 118 gives the generated logic signal to the acquisition unit 120.
- the acquisition unit 120 delays the strobe signal supplied from the timing generator 112 by a delay amount corresponding to the acquisition timing specified by the pattern generator 110. Then, the acquisition unit 120 acquires the logical value of the logical signal output from the comparator 118 at the timing of the delayed strobe signal. The acquisition unit 120 supplies the acquired logical value to the determination unit 122.
- the determination unit 122 compares the logical value acquired by the acquisition unit 120 with the expected value specified by the pattern generator 110.
- the acquisition unit 120 supplies the comparison result to an external control device.
- the acquisition unit 120 may write the comparison result in a memory or the like.
- the performance board 104 includes the adding unit 32.
- the adder 32 adds the signals output from the plurality of drivers 24, and supplies the result to a predetermined terminal of the DUT 200 as an output signal.
- each waveform generation unit 114 functions as the variable delay unit 22 in the output device 10.
- the pattern generator 110 functions as the control unit 34 in the output device 10. That is, the pattern generator 110 sets the delay amounts of the plurality of waveform generators 114 according to the specified slew rate.
- the test apparatus 100 can supply a signal having a specified slew rate to the DUT 200.
- the pattern generator 110 may further set the voltage level of the intermediate signal output by each driver 24 in accordance with the designated slew rate.
- the performance board 104 may further include a high-pass filter 72.
- one driver 24 that supplies a signal to the high-pass filter 72 functions as the correction driver 70.
- the pattern generator 110 changes the voltage of the signal output from the driver 24 that functions as the correction driver 70. Even with such a configuration, the test apparatus 100 can supply a signal having a specified slew rate to the DUT 200.
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Abstract
Description
Claims (10)
- 入力信号に応じた出力信号を出力する出力装置であって、
それぞれが前記入力信号に応じた波形の中間信号を出力する複数のドライバと、
前記複数のドライバのそれぞれから出力された前記中間信号を加算して、前記出力信号として出力する加算部と、
指定されたスルーレートに応じて、前記複数のドライバ間における、前記入力信号が変化し始めてから前記中間信号が変化し始めるまでの遅延量の差を設定する制御部と、
を備える出力装置。 - 指定されるスルーレートの前記出力信号が得られる、前記複数のドライバ間における前記遅延量の差を測定するキャリブレーション部を更に備え、
前記制御部は、前記キャリブレーション部による測定結果に基づいて、前記複数のドライバ間における前記遅延量の差を設定する
請求項1に記載の出力装置。 - 前記制御部は、指定されたスルーレートに応じて、前記複数のドライバのそれぞれから出力される前記中間信号の電圧レベルを更に設定する
請求項1から2の何れかに記載の出力装置。 - 前記加算部は、当該出力装置の出力端側から見たときの抵抗値が、当該出力装置の出力端と基準電位との間に接続された終端抵抗の抵抗値に一致する
請求項1から3の何れかに記載の出力装置。 - 前記制御部は、前記入力信号が変化し始めてから前記出力信号が予め定められた電圧レベルとなるまでの時間が同一となるように、前記複数のドライバ間における前記遅延量の差を設定する
請求項1から4の何れかに記載の出力装置。 - 前記制御部は、前記出力信号の変化期間が、前記複数のドライバのそれぞれが出力する前記中間信号の変化時間を合計した時間以下となる範囲で、前記複数のドライバ間における前記遅延量の差を設定する
請求項1から5の何れかに記載の出力装置。 - 前記入力信号に応じた波形の補正信号を出力する補正ドライバと、
前記補正ドライバから出力された前記補正信号の高周波数成分を通過させるハイパスフィルタと、
を更に備え、
前記加算部は、前記複数のドライバから出力された前記中間信号および前記ハイパスフィルタを通過した前記補正信号を加算して、前記出力信号として出力し、
前記制御部は、指定されたスルーレートに応じて、前記補正ドライバから出力される前記補正信号の電圧レベルを更に設定する
請求項1から6の何れかに記載の出力装置。 - 入力信号に応じた出力信号を出力する出力装置であって、
前記入力信号に応じた波形の中間信号を出力するドライバと、
前記入力信号に応じた波形の補正信号を出力する補正ドライバと、
前記補正ドライバから出力された前記補正信号の高周波数成分を通過させるハイパスフィルタと、
前記ドライバから出力された前記中間信号および前記ハイパスフィルタを通過した前記補正信号を加算して、前記出力信号として出力する加算部と、
指定されたスルーレートに応じて、前記補正ドライバから出力される前記補正信号の電圧レベルを設定する制御部と、
を備える出力装置。 - 被試験デバイスを試験する試験装置であって、
試験信号を前記被試験デバイスに供給する出力装置を備え、
前記出力装置は、
それぞれが入力信号に応じた波形の中間信号を出力する複数のドライバと、
前記複数のドライバのそれぞれから出力された前記中間信号を加算して、前記試験信号として出力する加算部と、
指定されたスルーレートに応じて、前記複数のドライバ間における、前記入力信号が変化し始めてから前記中間信号が変化し始めるまでの遅延量の差を設定する制御部と、
を有する試験装置。 - 被試験デバイスを試験する試験装置であって、
試験信号を前記被試験デバイスに供給する出力装置を備え、
前記出力装置は、
入力信号に応じた波形の中間信号を出力するドライバと、
前記入力信号に応じた波形の補正信号を出力する補正ドライバと、
前記補正ドライバから出力された前記補正信号の高周波数成分を通過させるハイパスフィルタと、
前記ドライバから出力された前記中間信号および前記ハイパスフィルタを通過した前記補正信号を加算して、前記試験信号として出力する加算部と、
指定されたスルーレートに応じて、前記補正ドライバから出力される前記補正信号の電圧レベルを設定する制御部と、
を有する試験装置。
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KR1020117014756A KR101250498B1 (ko) | 2009-02-18 | 2010-02-03 | 출력 장치 및 시험 장치 |
JP2011500486A JPWO2010095378A1 (ja) | 2009-02-18 | 2010-02-03 | 出力装置および試験装置 |
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JP2016521852A (ja) * | 2013-06-07 | 2016-07-25 | テラダイン、 インコーポレイテッド | 較正装置 |
JP2018066739A (ja) * | 2016-10-21 | 2018-04-26 | 新特系統股▲フン▼有限公司Sync−Tech System Corporation | プローブカードモジュール |
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DE102011100742B4 (de) * | 2011-05-06 | 2018-07-12 | Austriamicrosystems Ag | Signalverarbeitungsanordnung und Signalverarbeitungsverfahren, insbesondere für elektronische Schaltkreise |
US8941430B2 (en) * | 2012-09-12 | 2015-01-27 | Nvidia Corporation | Timing calibration for on-chip interconnect |
KR102021336B1 (ko) * | 2012-12-20 | 2019-09-16 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 동작방법 |
JP2015162753A (ja) * | 2014-02-26 | 2015-09-07 | ソニー株式会社 | 回路、送受信機および通信システム |
US9748933B2 (en) * | 2015-12-28 | 2017-08-29 | Taiwan Semiconductor Manufacturing Company Limited | Multi-step slew rate control circuits |
JP6332397B2 (ja) * | 2016-10-14 | 2018-05-30 | 日本電気株式会社 | スルーレート調整回路、及びスルーレート調整方法 |
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KR101250498B1 (ko) | 2013-04-05 |
TW201034385A (en) | 2010-09-16 |
TWI454055B (zh) | 2014-09-21 |
JPWO2010095378A1 (ja) | 2012-08-23 |
KR20110099276A (ko) | 2011-09-07 |
US20110298522A1 (en) | 2011-12-08 |
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