WO2010021226A1 - 直接形変換装置及びその制御方法並びに制御信号生成装置 - Google Patents
直接形変換装置及びその制御方法並びに制御信号生成装置 Download PDFInfo
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- WO2010021226A1 WO2010021226A1 PCT/JP2009/063351 JP2009063351W WO2010021226A1 WO 2010021226 A1 WO2010021226 A1 WO 2010021226A1 JP 2009063351 W JP2009063351 W JP 2009063351W WO 2010021226 A1 WO2010021226 A1 WO 2010021226A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M5/00—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases
- H02M5/40—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc
- H02M5/42—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters
- H02M5/44—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac
- H02M5/453—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac using devices of a triode or transistor type requiring continuous application of a control signal
- H02M5/458—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M5/4585—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only having a rectifier with controlled elements
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M5/00—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases
- H02M5/02—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc
- H02M5/04—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters
- H02M5/22—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M5/275—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M5/297—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal for conversion of frequency
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/493—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode the static converters being arranged for operation in parallel
Definitions
- the present invention relates to a direct conversion device, and more particularly to a direct conversion device including a converter and a plurality of inverters.
- the direct AC power converter does not require a large capacitor or reactor.
- the conversion device can be expected to be miniaturized, and has recently been attracting attention as a next-generation power conversion device.
- one inverter is connected to one converter, the inverter is operated based on a zero vector, and the converter is commutated when a so-called zero current state is obtained (hereinafter referred to as a “zero current” state). Is simply expressed as "converter commutation at zero current”).
- zero current so-called zero current state
- Non-Patent Document 1 a technique of operating a plurality of inverters connected to one converter has been proposed.
- Such a technique is disclosed, for example, in Non-Patent Document 1 described later.
- the DC / DC converter and the voltage source inverter are connected in parallel.
- the current source rectifier can be grasped as a converter, and the DC / DC converter can be grasped as an inverter.
- a plurality of inverters are controlled by pulse width modulation with one carrier synchronized with the carrier on which the operation of the current source rectifier is based. It is shown.
- Patent Document 3 introduces a technique for controlling switching for generating a current-type pulse width control pattern by using a comparison result between a command value and a carrier for a phase voltage and a dual phase current.
- Patent Document 4 discloses a technique in which the slope is different between a carrier used for pulse width modulation of a converter and a carrier used for pulse width modulation of an inverter.
- the frequency of the carrier used for controlling the plurality of inverters can be set arbitrarily.
- a plurality of inverters are modulated by the carrier having the same frequency as the carrier used for controlling the converter.
- the frequency at which electromagnetic noise peaks for the same carrier frequency is different. Therefore, even if the carrier frequency is selected so that the electromagnetic noise in one inverter and load combination is reduced (or the peak of the electromagnetic noise is out of the audible range), the electromagnetic noise in the other inverter and load combination is selected. May not be reduced (or the peak of electromagnetic noise cannot be removed from the audible range).
- the present invention provides a direct conversion device including a converter and a plurality of inverters, while performing an operation synchronized with the converter, while making the substantial carrier frequency in the plurality of inverters different from each other, thereby improving the load characteristics of the inverter.
- the purpose is to improve the degree of freedom in selecting the corresponding carrier.
- a control method for a direct conversion apparatus includes a converter (3) that rectifies a multiphase AC voltage (Vr, Vs, Vt) by pulse width modulation and outputs the rectified voltage to a pair of DC power supply lines (L1, L2).
- a direct type comprising a first inverter (4) and a second inverter (5) connected in parallel with each other between the pair of DC power supply lines and operating by pulse width modulation according to instantaneous space vector control.
- the converter commutates when the converter carrier (C0) takes the value of the converter command value (drt), and the commutation is performed for one period (T) of the converter carrier.
- the timing is divided internally by the first value (dst) and the second value (drt) and is divided into a first period (dst ⁇ T) and a second period (drt ⁇ T).
- the instantaneous space vector (V01, V41, V61) employed in the instantaneous space vector control of the first inverter is the zero vector (V01) in the first commutation zero vector period (T01) that is the period including the timing. adopt.
- An instantaneous space vector (V02, V42, V62; V02, V42, V62, V72) used for the instantaneous space vector control of the second inverter is a second commutation zero vector period (T02) that is a period including the timing.
- the zero vector (V02; V02, V72) is adopted in T02, T72).
- the instantaneous space vector array pattern (V41, V61, V41) employed by the first inverter other than the zero vector (V01) employed in the first commutation zero vector period. Appears M times (M is an integer of 1 or more).
- V42 appears N times (N is an integer greater than or equal to 2 and different from M).
- a second aspect of the control method of the direct conversion apparatus is the first aspect thereof, wherein the first period of the second inverter is the second commutation zero vector period (T02; (N ⁇ 1) non-commutation zero vectors that are discrete periods of T02, T72) and are the periods in which the zero vectors (V02; V02, V72) employed in the second commutation zero vector period are employed. It has a period (Ts01; Ts1).
- a third aspect of the control method of the direct conversion device according to the present invention is the second aspect, and is a first carrier (C1) employed in the instantaneous space vector control of the first inverter (4). ) And the second carrier (C2) employed in the instantaneous space vector control of the second inverter (5) are synchronized with the converter carrier (C0).
- the same waveform appears M times in the first period (dst ⁇ T), and in the second carrier, the same waveform appears N times in the first period.
- a fourth aspect of the control method of the direct conversion apparatus is the second aspect thereof, wherein the first carrier (C1) employed in the instantaneous space vector control of the first inverter is the above-mentioned
- the period of the second carrier (C2) that is synchronized with the converter carrier (C0) and is used for the instantaneous space vector control of the second inverter is equal to the period of the converter carrier (C0).
- the signal wave (dst (1 ⁇ V * ), drt + dst ⁇ V * ) set based on the arrangement pattern in the second inverter with respect to the second carrier .
- Drt (1 ⁇ V * ), drt ⁇ V * ; drt + (2/3) dst + dst ⁇ V * , drt + (2/3) dst ⁇ dst ⁇ V * , drt + dst ⁇ V * ; drt (1 ⁇ V * ) , Drt (1/3 + V * ), drt (1 ⁇ 3 ⁇ V * )) are set for each phase of the second inverter.
- a fifth aspect of the control method of the direct conversion device is the fourth aspect thereof, wherein the second inverter is not based on the arrangement pattern with respect to the second carrier, and Further, (N ⁇ 1) signal waves (drt + dst / 2, drt / 2) based on one value and the second value (drt, dst) are set in the first period (dst ⁇ T).
- any one of the first to fifth aspects of the control method of the direct conversion apparatus is executed, and the converter (3) and the first inverter (4 ) And the second inverter (5).
- the control signal generator includes a converter (3) that rectifies a multiphase AC voltage (Vr, Vs, Vt) and outputs the rectified voltage to a pair of DC power supply lines (L1, L2), and the pair of DC power supply lines. It is an apparatus which controls the direct form conversion apparatus provided with the 1st inverter (4) and 2nd inverter (5) which are mutually connected in parallel.
- the first mode is to output a first control signal (Sup1 * , Sun1 * ; Svp1 * , Svn1 * ; Swp1 * , Swn1 * ) for operating the first inverter by pulse width modulation according to instantaneous space vector control.
- a first control signal (Sup1 * , Sun1 * ; Svp1 * , Svn1 * ; Swp1 * , Swn1 * ) for operating the first inverter by pulse width modulation according to instantaneous space vector control.
- a second control signal for operating a pulse width modulation of the second inverter according to the instantaneous space vector control (Sup2 *, Sun2 *; Svp2 *, Svn2 *; Swp2 *, Swn2 * )
- a second inverter control unit (62) that outputs a third control signal (Srp * , Ssp * , Stp * , Srn * , Ssn * , Stn * ) that causes the converter to perform commutation .
- the converter control unit includes a carrier generation unit (604) that generates a converter carrier (C0) and a converter command generation unit (601) that generates converter command values (Vr * , Vs * , Vt * ). And a third control signal generator (603, 609) for generating the third control signal for controlling the pulse width of the converter using a comparison result between the converter carrier and the converter command value, and the converter command
- An intermediate phase detection unit (602) that outputs a flow ratio (dst) of the intermediate phase (Vs * ) of the values (Vr * , Vs * , Vt * ).
- the first inverter control unit includes a first output command generation unit (611) that generates a first output command value (Vu1 * , Vv1 * , Vw1 * ) that is a command value of an output of the first inverter; Based on the flow ratio and the first output command value, the first inverter signal wave (drt + dst ⁇ V * , drt (1 ⁇ V) is compared with the first carrier (C1) synchronized with the converter carrier. * ), And a first control signal generator (614, 615, 619) that generates the first control signal based on the comparison result.
- a first output command generation unit (611) that generates a first output command value (Vu1 * , Vv1 * , Vw1 * ) that is a command value of an output of the first inverter; Based on the flow ratio and the first output command value, the first inverter signal wave (drt + dst ⁇ V * , drt (1 ⁇ V) is
- the second inverter control unit includes a second output command generation unit (621) that generates a second output command value (Vu2 * , Vv2 * , Vw2 * ) that is a command value of the output of the second inverter; Based on the flow ratio and the second output command value, the second inverter signal wave (drt + dst ⁇ V * , drt (1 ⁇ V) is compared with the second carrier (C2) synchronized with the converter carrier.
- a second output command generation unit (621) that generates a second output command value (Vu2 * , Vv2 * , Vw2 * ) that is a command value of the output of the second inverter
- the instantaneous space vector (V01, V41, V61) employed in the instantaneous space vector control of the first inverter is a first commutation that is a period including the timing when the converter carrier takes the intermediate phase value.
- the zero vector (V01) is employed.
- An instantaneous space vector (V02, V42, V62; V02, V42, V62, V72) used for the instantaneous space vector control of the second inverter is a second commutation zero vector period (T02) that is a period including the timing.
- the zero vector (V02; V02, V72) is adopted in T02, T72).
- the first inverter is other than the zero vector (V01) adopted in the first commutation zero vector period.
- the adopted arrangement pattern (V41, V61, V41) of the instantaneous space vector appears M times (M is an integer of 1 or more).
- V42 appears N times (N is an integer greater than or equal to 2 and different from M).
- a second aspect of the control signal generation device is the first aspect, and in the second inverter, the first period is the second commutation zero vector period (T02; T02, T72). ) And (N ⁇ 1) non-commutation zero vector periods (Ts01) that are periods in which the zero vector (V02; V02, V72) employed in the second commutation zero vector period is employed. ; Ts1).
- a third aspect of the control signal generation device is the second aspect, wherein the same waveform appears M times in the first carrier (dst ⁇ T) in the first carrier, In two carriers, the same waveform appears N times in the first period.
- a fourth aspect of the control signal generation device is the second aspect thereof, wherein the period of the second carrier (C2) employed in the instantaneous space vector control of the second inverter is It is equal to the period of the converter carrier (C0).
- the second inverter signal wave has a value (dst (1 ⁇ V * ), drt + dst ⁇ V * , drt (1 ⁇ V * ), drt ⁇ V * ; drt + (2/3) dst + dst ⁇ V * , drt + (2/3) dst ⁇ dst ⁇ V * , drt + dst ⁇ V * , drt (1 ⁇ V * ), drt (1/3 + V * ), drt (1 / 3 ⁇ V * )) is set to N for each phase.
- a fifth aspect of the control signal generation device is the fourth aspect thereof, wherein the second inverter signal wave is not based on the arrangement pattern but based on the current ratio (drt + dst). / 2, drt / 2) are further set in the first period (dst ⁇ T).
- any one of the first to fifth aspects of the control signal generator, the converter (3), the first inverter (4), and the second And an inverter (5) is provided.
- the direct conversion device substantially operates in the plurality of inverters while performing the operation synchronized with the converter. Since different carrier frequencies are different from each other, the degree of freedom of carrier selection according to the load characteristics of the inverter is improved.
- the same pattern of the instantaneous space vector adopted by the second inverter is twice or more in the first period. Since it appears, it contributes to the first aspect of the control method and the first aspect of the control signal generation device.
- the third aspect of the control method of the direct conversion device and the third aspect of the control signal generation device according to the present invention by adopting the first carrier and the second carrier individually, The second aspect and the second aspect of the control signal generation device can be realized.
- the control is achieved while realizing the second carrier without multiplying the converter carrier.
- the second aspect of the method and the second aspect of the control signal generation device can be realized.
- the fourth aspect of the control method and the control signal generation device can be realized.
- the effects of the first to fifth aspects of the control method can be obtained.
- the effects of the first to fifth aspects of the control signal generation device can be obtained.
- FIG. 1 is a circuit diagram showing the configuration of a direct conversion device to which the present invention is applicable.
- the conversion device includes a converter 3, inverters 4 and 5, and a pair of DC power supply lines L1 and L2 that connect the two.
- Converter 3 rectifies three-phase (here, R-phase, S-phase, and T-phase) AC voltages Vr, Vs, and Vt obtained from AC power supply 1 and outputs them to a pair of DC power supply lines L1 and L2.
- An input capacitor group 2 may be provided between the AC power supply 1 and the converter 3.
- the input capacitor group 2 includes, for example, three Y-connected capacitors that receive the multiphase AC voltages Vr, Vs, and Vt. Here, a case where the neutral point of the Y connection is virtually grounded is illustrated.
- Converter 3 is, for example, a current source rectifier and operates by pulse width modulation.
- Converter 3 has a plurality of current paths connected in parallel to each other between DC power supply lines L1 and L2.
- the current path of converter 3 corresponding to the R phase includes a pair of switching elements Srp and Srn connected in series between DC power supply lines L1 and L2.
- a voltage Vr is applied to a connection point between the switching elements Srp and Srn.
- the current path of converter 3 corresponding to the S phase includes a pair of switching elements Ssp and Ssn connected in series between DC power supply lines L1 and L2.
- a voltage Vs is applied to a connection point between the switching elements Ssp and Ssn.
- the current path of converter 3 corresponding to the T phase includes a pair of switching elements Stp and Stn connected in series between DC power supply lines L1 and L2.
- a voltage Vt is applied to a connection point between the switching elements Stp and Stn.
- the switching elements Srp, Ssp, Stp are connected to the DC power supply line L1
- the switching elements Srn, Ssn, Stn are connected to the DC power supply line L2, respectively.
- the configurations of these switching elements themselves are known and exemplified in Non-Patent Document 1, for example.
- the inverters 4 and 5 are, for example, voltage type inverters, and all operate by pulse width modulation according to instantaneous space vector control (hereinafter simply referred to as “vector control”).
- the inverters 4 and 5 are connected in parallel with each other between the DC power supply lines L1 and L2, and individually output three-phase (here, U-phase, V-phase, and W-phase) AC voltages.
- the inverters 4 and 5 each have a plurality of current paths connected in parallel between the DC power supply lines L1 and L2.
- the current path of the inverter 4 corresponding to the U phase includes a pair of switching elements Sup1 and Sun1 connected in series between the DC power supply lines L1 and L2. An output voltage Vu1 is obtained from a connection point between the switching elements Sup1 and Sun1.
- the current path of inverter 4 corresponding to the V phase includes a pair of switching elements Svp1 and Svn1 connected in series between DC power supply lines L1 and L2.
- An output voltage Vv1 is obtained from a connection point between the switching elements Svp1 and Svn1.
- the current path of inverter 4 corresponding to the W phase includes a pair of switching elements Swp1 and Swn1 connected in series between DC power supply lines L1 and L2.
- An output voltage Vw1 is obtained from a connection point between the switching elements Swp1 and Swn1.
- the current path of the inverter 5 corresponding to the U phase includes a pair of switching elements Sup2, Sun2 connected in series between the DC power supply lines L1, L2.
- An output voltage Vu2 is obtained from a connection point between the switching elements Sup2 and Sun2.
- the current path of inverter 5 corresponding to the V phase includes a pair of switching elements Svp2 and Svn2 connected in series between DC power supply lines L1 and L2.
- An output voltage Vv2 is obtained from a connection point between the switching elements Svp2 and Svn2.
- the current path of inverter 5 corresponding to the W phase includes a pair of switching elements Swp2 and Swn2 connected in series between DC power supply lines L1 and L2.
- An output voltage Vw2 is obtained from a connection point between the switching elements Swp2 and Swn2.
- Switching elements Sup1, Svp1, Swp1, Sup2, Svp2, and Swp2 are connected to the DC power supply line L1 side. Hereinafter, these switching elements are grasped as switching elements on the upper arm side. Switching elements Sun1, Svn1, Swn1, Sun2, Svn2, and Swn2 are connected to the DC power supply line L2. Hereinafter, these switching elements will be grasped as switching elements on the lower arm side.
- the configurations of these switching elements themselves are known and exemplified in Non-Patent Document 1, for example.
- Inverters 4 and 5 operate under vector control.
- the switching elements Sup1, Svp1, Swp1, Sun1, Svn1, Swn1 are controlled by gate signals Sup1 * , Svp1 * , Swp1 * , Sun1 * , Svn1 * , Swn1 * as control signals.
- a description will be given assuming that the switching elements corresponding to the gate signals having logical values “1” / “0” are turned on / off.
- the gate signals Sup1 *, Svp1 *, Swp1 *, the gate signals Sun1 *, Svn1 * take complementary values and Swn1 *. That is, if the subscript q is used to represent the subscripts u, v, and w, the exclusive OR of the signals Sqp1 * and Sqn1 * is “1”.
- the switching elements Sup1, Svp1, Swp1 on the upper arm side are all non-conductive, all the switching elements Sun1, Svn1, Swn1 on the lower arm side are conductive.
- x 0, and the inverter 4 is in one state of a zero vector called the vector V0.
- the voltage vector is marked for the inverter 5 as well.
- the voltage vector of the inverter 4 is expressed as a vector Vx1
- the voltage vector of the inverter 5 is expressed as a vector Vx2.
- Loads M1 and M2 are inductive loads and are connected to inverters 4 and 5, respectively.
- the load M1 is a motor having a three-phase coil that is Y-connected and to which voltages Vu1, Vv1, and Vw1 are applied.
- the load M2 is a motor having a three-phase coil that is Y-connected and to which voltages Vu2, Vv2, and Vw2 are applied.
- each resistance component of the three-phase coil is described as a resistor connected in series to the coil.
- the parasitic capacitance in each of the loads M1 and M2 is described as three Y-connected capacitors. Here, a case where the neutral point of the Y connection is virtually grounded is illustrated.
- the carrier used for pulse width modulation in the inverter 4 (hereinafter also referred to as “first carrier”) has the same frequency as the carrier used for pulse width modulation in the converter 3 (hereinafter also referred to as “converter carrier”).
- first carrier the carrier used for pulse width modulation in the converter 3
- converter carrier the carrier used for pulse width modulation in the converter 3
- second carrier a carrier used for pulse width modulation in the inverter 5
- the substantial frequency of the first carrier may be higher than the frequency of the converter carrier.
- FIG. 2 is a block diagram showing a configuration of the gate signal generation device 6.
- the gate signal generation device 6 includes a converter control unit 60, a first inverter control unit 61, and a second inverter control unit 62.
- the converter control unit 60 receives a power supply synchronization signal (hereinafter, also simply referred to as “angle”) ⁇ r indicating the phase angle of the voltage Vr as a power supply synchronization signal, and gate signals Srp * , Ssp * , Stp * , Srn * , Ssn * and Stn * are output. These gate signals are control signals for controlling the operations of the switching elements Srp, Ssp, Stp, Srn, Ssn, Stn of the converter 3, respectively.
- the first inverter control unit 61 inputs the angle ⁇ r, the command value f1 * of the operation frequency of the inverter 4, the voltage command value v1 * , and the phase command value ⁇ 1 * (collectively referred to as “first command value”). Then, the gate signals Sup1 * , Svp1 * , Swp1 * , Sun1 * , Svn1 * , and Swn1 * are output.
- Second inverter control unit 62 inputs angle ⁇ r, command value f2 * of inverter 5 operating frequency, voltage command value v2 * , and phase command value ⁇ 2 * (collectively referred to as “second command value”). and, gate signal Sup2 *, Svp2 *, Swp2 * , Sun2 *, Svn2 *, and outputs the Swn2 *. These gate signals control the operations of the switching elements Sup2, Svp2, Swp2, Sun2, Svn2, and Swn2 of the inverter 5, respectively.
- control unit 3 For the configuration of the converter control unit 60 and the first inverter control unit 61, or the configuration of the converter control unit 60 and the second inverter control unit 62, the configuration shown as “control unit 3” in Patent Document 2 may be adopted. It can. The following explanation will be given although it is simple because there is a slight difference in expression from the technique shown in Patent Document 2.
- the converter control unit 60 includes a trapezoidal voltage command generation unit 601, an intermediate phase detection unit 602, a comparator 603, a carrier generation unit 604, and a current source gate logic conversion unit 609. These are “trapezoidal voltage command signal generation unit 11”, “intermediate phase detection unit 14”, “comparison unit 12”, “carrier signal generation unit 15”, and “current source gate logic conversion unit 13” described in Patent Document 2, respectively. Fulfills the same function.
- the trapezoidal voltage command generation unit 601 generates voltage commands Vr * , Vs * , and Vt * for the converter 3 based on the angle ⁇ r and using the voltage Vr as a reference.
- Each of these voltage commands has a trapezoidal waveform with a period of 360 degrees and is shifted by 120 degrees from each other.
- the trapezoidal waveform exhibits a trapezoidal wave having a pair of flat sections continuous at 120 degrees and a pair of inclined areas of 60 degrees connecting the pair of flat sections.
- the slope region takes the center as the phase reference, and the minimum value and maximum value of the waveform (which appear in the flat section) are 0 and 1, respectively, (1- ⁇ 3 tan ⁇ ) / 2 or (1 + ⁇ 3 tan ⁇ ) / 2.
- the intermediate phase detection unit 602 selects the voltage command Vr * , Vs * , Vt * that is not the maximum phase that takes the maximum value and that is not the minimum phase that takes the minimum value, in other words, that exhibits an inclined region.
- the voltage commands Vr * and Vt * take a flat section in which the maximum value and the minimum value are taken, and the voltage command Vs * takes a slope region.
- the direct form conversion device and the gate signal generation device 6 operate in such a situation unless otherwise specified. Since the voltage commands Vr * , Vs * , and Vt * exhibit the same waveform except for the phase shift, the generality is not lost even if such an assumption is made.
- the intermediate phase detection unit 602 selects the voltage command Vs * .
- the intermediate phase detector 602 outputs the values drt and dst.
- the carrier generation unit 604 outputs the converter carrier C0 that takes the minimum and maximum values (0 and 1 in the above example) of the voltage commands Vr * , Vs * , and Vt * , respectively.
- the converter carrier C0 is a triangular wave.
- the comparator 603 compares the voltage commands Vr * , Vs * , Vt * with the converter carrier C0. Based on the comparison result, the current-type signal logic conversion unit 609 uses the converter 3 gate signal (hereinafter also referred to as “converter gate signal”) Srp * , Ssp * , Stp * , Srn * , Ssn * , Stn *. Is output. Therefore, the comparator 603 current-type signal logic conversion unit 609 collectively generates a converter gate signal for controlling the pulse width of the converter 3 using the comparison result between the converter carrier C0 and the voltage commands Vr * , Vs * , Vt *. It can be grasped as a signal generation unit.
- converter gate signal hereinafter also referred to as “converter gate signal”
- converter 3 is a current source rectifier, in principle, the upper arm side switching element corresponding to the maximum phase and the upper arm side switching element corresponding to the intermediate phase are alternately conducted, and the lower arm side corresponding to the minimum phase The switching element conducts and operates.
- rectification may be performed by the function of the diode element by making all the switching elements conductive, but this is not an operation of pulse width modulation. The rectification operation is excluded and considered here.
- the first inverter control unit 61 includes an output voltage generation unit 611, calculation units 612 and 613, comparators 614 and 615, and a logical sum calculation unit 619. These perform the same functions as “output voltage command signal generation unit 21”, “calculation units 22 and 23”, “comparison unit 24”, and “OR operation unit 25” described in Patent Document 2, respectively.
- the output voltage generator 611 outputs the phase voltage commands Vu1 * , Vv1 * , Vw1 * based on the first command value and the angle ⁇ r. These are command values of the output voltages Vu1, Vv1, Vw1 (see FIG. 1) of the inverter 4.
- the arithmetic units 612 and 613 generate a signal wave (signal wave) to be compared with the first carrier C1 based on the phase voltage commands Vu1 * , Vv1 * , Vw1 * and the values drt, dst.
- the first carrier C1 is synchronized with the converter carrier C0 and takes the value drt when the converter carrier C0 takes the value drt.
- a converter carrier C0 is employed as the first carrier C1.
- the values drt and dst are input to the calculation unit 613 only by arrows that enter the calculation unit 613 from above.
- Patent Document 2 the calculation based on the values drt, dst and the phase voltage commands Vu1 * , Vv1 * , Vw1 * is representatively indicated by drt + dst (1-V * ), drt (1-V * ). . This is because the symbol V * representatively represents a voltage vector.
- the calculation in the present application is also shown following Patent Document 2.
- the comparator 614 compares the result of the calculation unit 612 with the first carrier C1, and the comparator 615 compares the result of the calculation unit 613 with the first carrier C1. Based on these comparison results, the OR operation unit 619 outputs gate signals Sup1 * , Svp1 * , Swp1 * , Sun1 * , Svn1 * , and Swn1 * . Therefore, the comparators 614 and 615 and the logical sum operation unit 619 are combined, and based on the result of comparing the first carrier C1 with the signal waves drt + dst (1 ⁇ V * ) and drt (1 ⁇ V * ), the first inverter It can be grasped as a signal generation unit that generates a gate signal for operation.
- the trapezoidal wave voltage commands Vr * , Vs * , Vt * are compared with the converter carrier C0 when obtaining the gate signal for controlling the converter 3 and the gate signal for controlling the inverter 4 is generated.
- the commutation of the converter 3 is performed during the zero vector period of the inverter 4.
- Patent Document 2 discloses that direct conversion is performed while performing. Details of the operation are introduced in Japanese Patent Application Laid-Open No. H10-228707, and details thereof are omitted.
- generation part 604 can also be included in the 1st inverter control part 61, and can also be grasped
- the second inverter control unit 62 includes an output voltage generation unit 621, calculation units 622 and 623, comparators 624 and 625, and a logical sum calculation unit 629. These perform the same functions as the output voltage generation unit 611, the calculation units 612 and 613, the comparators 614 and 615, and the OR operation unit 619 of the first inverter control unit 61, respectively.
- the phase voltage commands Vu2 * , Vv2 * , Vw2 * output from the output voltage generation unit 621 are command values of the output voltages Vu2, Vv2, Vw2 (see FIG. 1) of the inverter 5.
- the second inverter control unit 62 includes a carrier generation unit 605, and generates a second carrier C2. If the carrier generation unit 604 is included in the first inverter control unit 61 and grasped, the gate signal generation device 6 shown in FIG. 2 is the “inverter control unit” of the “control unit 3” shown in Patent Document 2. It is also possible to grasp that the configuration is simply increased by one.
- the second carrier C2 will be described in detail later. First, the operation of the first inverter control unit 61 will be described.
- FIG. 3 shows converter carrier C0, converter gate signals Srp * , Ssp * , Stn * , first carrier C1, gate signal Sup1 * , Svp1 * , Swp1 * for inverter 4 (hereinafter referred to as “first inverter gate signal”). It is also a graph showing the waveform of
- One period T of the converter carrier C0 is internally divided by values dst and drt indicating the commutation ratio, and is divided into a period dst ⁇ T and a period drt ⁇ T, and the commutation of the converter 3 is performed at the divided timing. Is called.
- the converter gate signal Ssp * is activated corresponding to the S phase that is an intermediate phase
- the converter gate signal Srp * is activated corresponding to the R phase that is the maximum phase.
- the signal wave and the first carrier C1 are compared so that the inverter 4 takes the zero vector V01 in the vicinity of the timing at which the converter 3 is commutated.
- the W phase is the minimum phase and adopting a triangular wave as the first carrier C1
- the periods d01, d41, d61 are determined by the phase voltage commands Vu1 * , Vv1 * , Vw1 * (see FIG. 2).
- the vector V0 In order to realize commutation of the converter 3 at zero current, the vector V0 must be adopted in the inverter 4 when the converter carrier C0 takes the value drt.
- the first carrier C1 fluctuates in the region of the width drt of the value 0 to drt below the value drt, and fluctuates in the region of the width dst of the value drt to 1 above the value drt.
- V * d01, d01 + d41, d01 + d41 + d61
- the logical sum operation unit 619 calculates the logical sum of the comparison results of the comparators 614 and 615 for each of the U phase, V phase, and W phase, and outputs first inverter gate signals Sup1 * , Svp1 * , and Swp1 * .
- the first carrier C1 takes one of a value equal to or higher than the signal wave drt + dst ⁇ d01 and a value equal to or lower than the signal wave drt (1 ⁇ d0)
- the first inverter gate signal Sup1 * is activated.
- the timing at which the vectors V01, V41, V61 are switched is determined by comparing the signal wave drt + dst ⁇ V * , drt (1 ⁇ V * ) with the first carrier C1. Since the period T01 in which the zero vector V0 is employed includes the commutation timing of the converter 3, commutation of the converter 3 at a so-called zero current can be realized.
- a period including the timing at which the converter 3 commutates and the zero vector is employed (for example, the above-described period T01) will be referred to as a “commutation zero vector period”.
- FIG. 4 shows converter carrier C0, converter gate signals Srp * , Ssp * , Stn * , second carrier C2, gate signals Sup2 * , Svp2 * , Swp2 * for inverter 5 (hereinafter “second inverter gate signal”). It is also a graph showing the waveform of
- a comparison between the signal wave and the second carrier C2 is performed so that the inverter 5 takes the zero vector V02 in the vicinity of the timing at which the converter 3 is commutated.
- the second carrier C2 is synchronized with the converter carrier C0 and takes the value drt when the converter carrier C0 takes the value drt. Referring also to FIG. 3, the same waveform appears only once in each of the periods dst ⁇ T and drt ⁇ T in the first carrier C1, whereas the same waveform appears in the second carrier C2 in the period dst ⁇ T. Appears twice.
- the first carrier C1 exhibits a triangular wave that reciprocates between values drt ⁇ 1 in the period dst ⁇ T, while the second carrier C2 has a value between two values drt ⁇ 1 in the period dst ⁇ T.
- a triangular wave that changes back and forth.
- the first carrier C1 exhibits a triangular wave that changes once during the period drt ⁇ T between the values drt to 0, while the second carrier C2 performs two reciprocations between the values drt ⁇ 0 during the period drt ⁇ T.
- the periods d02, d42, d62 are determined by the phase voltage commands Vu2 * , Vv2 * , Vw2 * .
- These signal waves are compared with the second carrier C ⁇ b> 2 by the comparator 624, and the comparison result is given to the OR operation unit 629.
- V * d02, d02 + d42, d02 + d42 + d62
- the logical sum operation unit 629 takes the logical sum of the comparison results of the comparators 624 and 625 for each of the U phase, the V phase, and the W phase, and outputs the second inverter gate signals Sup2 * , Svp2 * , and Swp2 * .
- the second carrier C2 takes the value drt when the converter carrier C0 takes the value drt. Therefore, the vector V02 is employed in the commutation zero vector period T02 including the timing at which the converter 3 commutates.
- the second inverter gate signal Sup2 * is the number of times the gate signal Sup1 * for the first inverter to activate, Svp1 *, Swp1 * becomes twice the number of times of activation.
- the vector arrangement pattern (V42 ⁇ V62 ⁇ V42) adopted by the inverter 5 other than the zero vector V02 repeatedly appears twice in each of the periods dst ⁇ T and drt ⁇ T.
- the degree of freedom for selecting a carrier is improved according to the characteristics of loads M1 and M2 of inverters 4 and 5, respectively.
- non-commutation zero vector period there is a period in which the zero vector V02 is employed because the second carrier C2 takes the value drt even at other timings.
- a period in which the zero vector employed in the commutation zero vector period is employed without including the timing at which the converter 3 commutates is referred to as a “non-commutation zero vector period”.
- the zero vector used in the noncommutation zero vector period and the commutation zero vector period are common. Therefore, if the non-commutation zero vector period and the commutation zero vector period are continuous, they cannot be distinguished from each other and include the timing at which the converter 3 commutates as a whole. Is different. Therefore, the noncommutation zero vector period must be discrete from the commutation zero vector period.
- the noncommutation zero vector period Ts01 is discrete from the commutation zero vector period T02 in the period dst ⁇ T
- the noncommutation zero vector period Ts02 is discrete from the commutation zero vector period T02 in the period drt ⁇ T. .
- the second carrier C2 is a triangular wave, and due to its symmetry, the vector order employed in the period Tk sandwiched between the commutation zero vector period T02 and the noncommutation zero vector period Ts01 (V42 ⁇ V62 ⁇ V42). Are equal to each other (period dst ⁇ T). As described above, since the order of the vectors employed in the period Tk is equal, the arrangement pattern of vectors other than the zero vector V02 employed in the commutation zero vector period T02 can be repeated.
- the signal wave drt + dst ⁇ V * is smaller than 1, and the signal wave drt (1 ⁇ V * ) is larger than 0.
- the period in which the first carrier C1 takes the zero vector V71 exists in the vicinity of the position where the first carrier C1 is maximized or minimized, and the period in which the second carrier C2 takes the zero vector V72 is maximized. Or, it exists in the vicinity of a minimum position.
- the arrangement pattern of vectors other than the zero vector V02 employed in the commutation zero vector period T02 is V42 ⁇ V62 ⁇ V72 ⁇ V62 ⁇ V42.
- the vector order (V42 ⁇ V62 ⁇ V72 ⁇ V62 ⁇ V42) employed in the period Tk is equal to each other.
- At least the second carrier C2 is generated by multiplying the converter carrier C0. Good.
- FIG. 5 is a graph conceptually showing the operation of the carrier generation units 604 and 605, and the first carrier C1 and the original second carrier C20 are indicated by a broken line and a solid line, respectively.
- the second carrier C2 can be obtained by normalizing the original second carrier C20 around the value drt.
- each of the carrier generation units 604 and 605 has an up-count function that increases the value with the passage of time and a down-count function that decreases the value with the passage of time.
- the carrier generation unit 604 continues to count up from the value 0, and counts down when the upper limit value (drt + dst) (here, value 1) is counted.
- the upper limit value (drt + dst) (here, value 1) is counted.
- the lower limit value 0 is obtained by continuing the down-counting, the up-counting is performed.
- the first carrier C1 can be generated.
- such generation may be applied to generation of the converter carrier C0, and the converter carrier C0 may be diverted as the first carrier C1.
- the carrier generation unit 605 continues to count up from the value drt, and counts down when the upper limit value (drt + dst / 2) is counted.
- the up-counting is performed.
- the upper limit value (drt + dst / 2) is counted for the second time
- the down-counting is continued until the lower limit value drt / 2 is obtained.
- up-counting is performed.
- the down-counting is performed.
- the up-counting continues until the upper limit value (drt + dst / 2) is obtained.
- the original second carrier C20 is obtained by performing such up-counting and down-counting.
- the waveform of the original second carrier C20 is doubled around the value drt.
- the same waveform (here, a triangular wave) appears twice in the period dst ⁇ T.
- the carrier generation unit 604 Since the maximum value and the minimum value (here, 1 and 0 respectively) are fixed values, the carrier generation unit 604 does not need to input the values drt and dst. On the other hand, the carrier generation unit 605 needs to generate and normalize the original second carrier C20, and values drt and dst are input in the same manner as the calculation units 622 and 623.
- the original second carrier C20 is directly adopted as the second carrier C2, and values drt + (dst / 2) ⁇ V * and drt ⁇ (drt / 2) ⁇ V * are generated as signal waves generated by the calculation units 622 and 623, respectively . Even if is adopted, the second inverter gate signals Sup2 * , Svp2 * , Swp2 * shown in FIG. 4 can be obtained.
- the total length of the periods d02, d42, and d62 of the second carrier C2 generated in this manner is, due to its symmetry, even when compared to the case where the converter carrier C0 is used as the second carrier. Maintained. Each of these periods is half the length, but the number of appearances is doubled.
- FIG. 6 is a graph conceptually showing the operation of the carrier generation units 604 and 605 when a sawtooth wave is adopted as these carriers.
- the carrier generation units 604 and 605 do not need either the up-count function or the down-count function.
- a sawtooth wave having a pattern that does not require a down-count function will be described as an example.
- the carrier generation unit 604 continues to count up from the value 0, and when the upper limit value (drt + dst) (here, the value 1) is counted, the counted value is forcibly set to the lower limit value 0. Thereby, the first carrier C1 is obtained.
- the carrier generation unit 605 continues to count up from the lower limit value drt / 2, and when the value drt is counted, the counted value is forcibly set to the lower limit value drt / 2.
- the up-count is continued until the upper limit value drt + dst / 2 is obtained.
- the counted value is forcibly set to the value drt.
- the up-count is performed again and the upper limit value drt + dst / 2 is obtained for the second time, the counted value is forcibly set to the lower limit value drt / 2.
- the first carrier C1 may also multiply the converter carrier C0 in the same manner as the second carrier C2.
- the same vector pattern adopted by the inverter 4 appears M times (M is an integer of 1 or more), and the same vector pattern adopted by the inverter 5 appears.
- N times N is an integer greater than or equal to 2 and different from M
- the degree of freedom for selecting a carrier is improved according to the characteristics of the loads M1 and M2 of the inverters 4 and 5, respectively.
- the first carrier C1 and the second carrier C2 can be generated in the same manner as the processes shown in FIGS. 5 and 6, although the number of repetitions is different.
- the operation of the inverter 5 in the case where the carrier used for the pulse width modulation of the inverters 4 and 5 is shared with each other using the signal wave devised as described above will be described.
- the carrier used for the pulse width modulation of the inverters 4 and 5 is simply referred to as carrier C0.
- the carrier shared by the inverters 4 and 5 is synchronized with the converter carrier C0, and if the value drt is taken at the timing when the converter 3 is commutated, the frequency of the shared carrier is an integer of the frequency of the converter carrier C0. It may be doubled.
- the inverter 4 may use the first carrier C1 obtained by multiplying the converter carrier C0 as shown in the previous section B using the second carrier C2.
- FIG. 7 is a graph showing the carrier C0 and the second inverter gate signal Sup2 * .
- the second inverter gate signals Svp2 * and Swp2 * are omitted.
- (1-d02-d04-d06) and drt (d02 + d04 + d06) are set (these signal waves are not shown).
- the logical value J1 becomes “H” (activated) only when the carrier C0 takes the signal wave dst (1 ⁇ d02) or higher, and the logical value J2 becomes “H” only when the carrier C0 takes the signal wave drt + dst ⁇ d02 or higher.
- the logic value J3 becomes “H” only when the carrier C0 takes the signal wave drt (1 ⁇ d02) or less, and the logic value J4 becomes “H” only when the carrier C0 takes the signal wave drt ⁇ d02 or less.
- the logical sum of the logical values J1 and J3 corresponds to the first inverter gate signal Sup1 * .
- the period “L” of the logical sum of the logical values J1 and J3 corresponds to the commutation zero vector period T01.
- the logical values J2 and J4 correspond to the non-commutation zero vector periods Ts01 and Ts02, respectively.
- the gate signal Sup2 * for the second inverter in the period dst ⁇ T is a logical product of the logical value J1 and the inversion of the logical value J2 (in the figure, the logical inversion is indicated by the upper line: the same applies hereinafter) ( ⁇ in the figure surrounded by ⁇ ) Is expressed by a logical value K1 which is the same as the following).
- the second inverter gate signal Sup2 * in the period drt ⁇ T is obtained as a logical value K2 which is a logical product of the logical value J3 and the logical value J4.
- the second inverter gate signal Sup2 * is obtained as a logical sum of the logical value K1 and the logical value K2 (indicated by + surrounded by ⁇ in the figure: the same applies hereinafter).
- the other second inverter gate signals Svp2 * and Swp2 * are obtained in the same manner.
- FIG. 8 is a block diagram showing the configuration of the second inverter control unit 62 when 2N signal waves per phase are used as described above.
- an output voltage command generation unit 621 is provided, from which phase voltage commands Vu2 * , Vv2 * , Vw2 * are obtained.
- the arithmetic units 622A and 623A generate signal waves drt + dst ⁇ V * and drt (1 ⁇ V * ) in the same manner as the arithmetic units 622 and 623 (see FIG. 2), respectively.
- the comparators 624A and 625A also output the result of comparing the signal wave and the carrier C0 in the same manner as the comparators 624 and 625 (see FIG. 2).
- the outputs of the comparators 624A and 625A correspond to the above-described logical values J1 and J3, respectively.
- calculation units 622B and 623B and comparators 624B and 625B are further provided.
- Operation units 622B and 623B generate signal waves dst (1-V * ) and drt ⁇ V * , respectively.
- the comparators 624B and 625B also output the result of comparing the signal wave and the carrier C0 in the same manner as the comparators 624 and 625 (see FIG. 2).
- the outputs of the comparators 624B and 625B correspond to the above-described logical values J2 and J4, respectively.
- the second inverter control unit 62 shown in FIG. 8 includes a logic synthesis unit 628 instead of the logical sum 629. This is because the logical operation of the above-described logical values J1 to J4 is not a simple logical sum but also requires inversion and logical product processing.
- FIG. 9 and FIG. 10 are graphs showing the carrier C0 and the logical values that are part of the second inverter gate signal Sup2 * .
- the discussion on the second inverter gate signals Svp2 * and Swp2 * is omitted.
- 9 and 10 show waveforms in the periods dst ⁇ T and drt ⁇ T, respectively.
- logical value J5 becomes “H” only when carrier C0 takes signal wave drt + dst ⁇ d02 or more, and only when carrier C0 takes signal wave drt + (2/3) dst ⁇ dst ⁇ d02 or more.
- the logical value J6 becomes “H” only when the logical value J6 becomes “H” and the carrier C0 takes the signal wave drt + (2/3) dst + dst ⁇ d02 or more.
- logical value J8 is “H” only when carrier C0 takes signal wave drt (1 ⁇ d02) or less, and logical value only when carrier C0 takes signal wave drt (1/3 + d02) or less.
- the logical value J10 becomes “H” only when J9 becomes “H” and the carrier C0 takes the signal wave drt (1 / 3 ⁇ d02) or less.
- the logical sum of the logical values J5 and J8 corresponds to the first inverter gate signal Sup1 * .
- the “L” period of the logical sum of the logical values J5 and J8 corresponds to the commutation zero vector period T01.
- the second inverter gate signal Sup2 * in the period dst ⁇ T is obtained as a logical sum of the logical values K3 and K4.
- the logical value K3 is the logical sum of the logical product of the logical value J5 and the logical value J6 and the logical value J7
- the logical value K4 is the logical product of the logical value J8 and the logical value J9.
- the other second inverter gate signals Svp2 * and Swp2 * are obtained in the same manner.
- a period in which the carrier C0 takes between the minimum value drt (in the period dst ⁇ T) and the signal wave drt + dst ⁇ d02 is a commutation zero vector period T02 (in the period dst ⁇ T).
- the width of the signal wave corresponding to the non-commutation zero vector period Ts01 is 2 ⁇ dst ⁇ d02
- the width of the signal wave corresponding to the commutation zero vector period T02 appearing in the period dst ⁇ T is dst ⁇ d02
- the commutation zero vector period T02 appears twice. Therefore, the length of the commutation zero vector period T02 that appears in the period dst ⁇ T is equal to the length of each of the noncommutation zero vector periods Ts01.
- the carrier C0 takes the signal wave drt + (2/3) dst ⁇ dst ⁇ d02, drt + dst ⁇ d02. It is a period. The difference between these signal waves is (2/3) dst ⁇ dst ⁇ d02.
- the difference between the signal wave and the maximum value is (1/3) dst ⁇ dst ⁇ d02. Therefore, the lengths of the periods Tk1 and Tk2 are equal to each other.
- the periods in which the zero vector V02 is employed in the period dst ⁇ T are equal to each other, and the periods in which other vectors (specifically, the vectors V42 and V62) are employed are also equal to each other. Therefore, it is possible to obtain an array pattern with good symmetry. The same applies to the period drt ⁇ T.
- FIG. 11 is a block diagram showing the configuration of the second inverter control unit 62 when 3N signal waves per phase are used as described above. 8, arithmetic units 622C1 and 623C1 and comparators 624C and 625C are added, the logic synthesis unit 628 is replaced with a logic synthesis unit 627, and the arithmetic units 622B and 623B are respectively calculated as arithmetic units 622B1, The configuration replaced with 623B1 is adopted.
- the arithmetic units 622A and 623A generate signal waves drt + dst ⁇ V * and drt (1 ⁇ V * ), respectively, as described in (c ⁇ 1).
- Comparators 624A and 625A output the result of comparing the signal wave and carrier C0.
- the outputs of the comparators 624A and 625A correspond to the above-described logical values J5 and J8, respectively.
- the arithmetic units 622B1 and 623B1 generate signal waves drt + dst (2 / 3 ⁇ V * ) and drt (1/3 + V * ), respectively.
- Comparators 624B and 625B output the result of comparing the signal wave and carrier C0.
- the outputs of the comparators 624B and 625B correspond to the above-described logical values J6 and J9, respectively.
- the arithmetic units 622C1 and 623C1 generate signal waves drt + dst (2/3 + V * ) and drt (1 / 3 ⁇ V * ), respectively.
- Comparators 624C and 625C output the result of comparing the signal wave and carrier C0.
- the outputs of the comparators 624C and 625C correspond to the above-described logical values J7 and J10, respectively.
- the logic synthesis unit 627 obtains logic values K3 and K4 based on the logic values J5 to J10, calculates the logical sum of the logic values K3 and K4, and outputs the second inverter gate signal Sup2 * . .
- the other second inverter gate signals Svp2 * and Swp2 * are output in the same manner.
- 3N signal waves set on the basis of the vector arrangement pattern are required for each phase in each of the periods dst ⁇ T and drt ⁇ T. , Is grasped.
- FIG. 12 is a graph showing the carrier C0 exhibiting a sawtooth wave and the second inverter gate signals Sup2 * , Svp2 * , Swp2 * .
- the signal wave is 2 (N) compared to the case where the carrier C0 exhibiting a triangular wave is employed. -1) It is necessary to add them.
- the timing at which the sawtooth wave shown in FIG. 6 takes the abrupt change described above is fixed at the time when the periods dst ⁇ T and drt ⁇ T are equally divided into N, and is based on the vector pattern employed. Rather, it is based on the values drt and dst as the flow ratio.
- d02, drt + dst / 2, and drt + dst (1/2 + d02) are set.
- the logical value J11 becomes “H” only when the carrier C0 takes the signal wave drt + dst ⁇ d02 or more, and the logical value J12 becomes “H” only when the carrier C0 takes the signal wave drt + dst / 2 or more, and the carrier C0 has the signal wave drt + dst.
- the logical value J13 becomes “H” only when (1/2 + d02) or more is taken, and the logical value J14 becomes “H” only when the carrier C0 takes the signal wave drt (1 ⁇ d02) or less, and the carrier C0 becomes the signal wave drt.
- the logical value J15 becomes “H” only when the frequency is equal to or lower than / 2
- the logical value J16 becomes “H” only when the carrier C0 takes the signal wave drt (1 / 2 ⁇ d02) or lower.
- the gate signal Sup2 * for the second inverter in the period dst ⁇ T is obtained as a logical value K5 that is a logical sum of the logical product of the logical value J11 and the logical value J12 and the logical value J13. Further, the second inverter gate signal Sup2 * in the period drt ⁇ T is obtained by a logical value K6 that is a logical sum of the logical product of the logical value J14 and the logical value J15 and the logical value J16. Therefore, the second inverter gate signal Sup2 * is obtained as a logical sum of the logical value K5 and the logical value K6.
- the other second inverter gate signals Svp2 * and Swp2 * are obtained in the same manner.
- the carrier When the carrier is a sawtooth wave, the carrier fluctuates sharply between the minimum value (for example, 0) and the maximum value (for example, 1), as introduced in Patent Document 2 (for example, paragraph 0073 and FIG. 9). Then, the commutation of the converter at zero current is also performed using the zero vector V72. That is, the zero vector V72 is employed in the commutation zero vector period T72 including the timing at which the converter commutates. In order to employ the zero vector V72, d01 + d41 + d61 ⁇ 1 is set in the inverter 5.
- the inverter 5 adopts V42 and V62 in addition to the zero vector. Therefore, the second inverter gate signal Swp2 has the shortest activation period in the second inverter gate signal. * Moreover, when the second inverter gate signal Swp2 * is activated, the second inverter gate signals Sup2 * and Svp2 * are always activated. Therefore, the commutation zero vector period T72 coincides with the period in which the second inverter gate signal Swp2 * is activated.
- the zero vector V02 is employed as in the case where the triangular wave is used for the carrier C0.
- the sawtooth wave adopted here includes a portion that increases with time and increases from a value of 0 to a value of 1, and a portion that decreases sharply from a value of 1 to a value of 0.
- the signal waves drt / 2 and drt + dst / 2 when the carrier C0 takes these values, it can be grasped that the sawtooth wave virtually falls sharply. Therefore, similar to the boundary between the end of the period dst ⁇ T and the start of the period drt ⁇ T (the timing of the broken line at the right end in the figure), the vector V72 is adopted immediately after the timing at which the carrier C0 takes the signal wave drt / 2. Period Ts72 is generated.
- a period Ts02 in which the vector V02 is employed corresponding to the signal wave dst (1 / 2 ⁇ d02) occurs.
- the periods Ts02 and Ts72 are continuous at the timing when the carrier C0 takes the signal wave drt / 2 and include both the zero vectors V02 and V72 employed in the commutation zero vector periods T02 and T72, respectively. It can be grasped as a flow zero vector period Ts2.
- a period Ts71 in which the vector V72 is employed occurs immediately before the timing at which the carrier C0 takes the signal wave drt + dst / 2.
- a period Ts01 in which the vector V02 is employed corresponding to the signal wave drt + dst (1/2 + d02) occurs.
- the periods Ts01 and Ts71 are continuous at the timing when the carrier C0 takes the signal wave drt + dst / 2 and include both of the zero vectors V02 and V72.
- the carrier C0 is a sawtooth wave having a minimum value 0 and a maximum value drt in the period drt ⁇ T.
- the second inverter gate signal Sup2 * is “H” twice, and these periods correspond to the value drt ⁇ d02. Therefore, in the period drt ⁇ T, the length of the period in which the second inverter gate signal Sup2 * is activated is equal to each other.
- the period Tk sandwiched between the period T72 and the period Ts02 and the period Tk sandwiched between the period Ts72 and the period T02 have the same length.
- the period Tk sandwiched between the commutation zero vector period T72 and the noncommutation zero vector period Ts2 and the period Tk sandwiched between the commutation zero vector period T02 and the noncommutation zero vector period Ts2 are:
- vectors other than the zero vectors V02 and V72 employed in the commutation zero vector periods T02 and T72 are employed in the period Tk.
- FIG. 13 is a block diagram showing the configuration of the second inverter control unit 62 when 3N signal waves per phase are used as described above.
- arithmetic units 622B1, 623B1, 622C1, 623C1, and comparators 624C, 625C are replaced with arithmetic units 622B2, 623B2, 622C2, 623C2, and comparators 624D, 625D, respectively. ing.
- the arithmetic units 622A and 623A generate signal waves drt + dst ⁇ V * and drt (1 ⁇ V * ), respectively, as described in (c-1).
- Comparators 624A and 625A output the result of comparing the signal wave and carrier C0.
- the outputs of the comparators 624A and 625A correspond to the above-described logical values J11 and J14, respectively.
- the calculation units 622B2 and 623B2 generate signal waves drt + dst (1/2 + V * ) and drt (1 / 2 ⁇ V * ), respectively.
- Comparators 624B and 625B output the result of comparing the signal wave and carrier C0.
- the outputs of the comparators 624B and 625B correspond to the above-described logical values J13 and J16, respectively.
- the calculation units 622C2 and 623C2 generate signal waves drt + dst / 2 and drt / 2, respectively.
- the comparators 624D and 625D output the result of comparing the signal wave and the carrier C0.
- the outputs of the comparators 624D and 625D correspond to the logical values J12 and J15, respectively. Therefore, unlike the other comparators 624A, 624B, 625A, and 625B, it is not necessary to provide a comparison element for each phase.
- the logic synthesis unit 627 obtains logic values K5 and K6 based on the logic values J11 to J13, takes the logical sum of the logic values K5 and K6, and outputs the second inverter gate signal Sup2 * . .
- the other second inverter gate signals Svp2 * and Swp2 * are output in the same manner. Since the logical operations based on these logical values J11 to J13 are the same as the logical operations based on the logical values J5 to J10 described in (c-2), the logical synthesis unit 627 has the configuration shown in FIG. It is common.
- the signal wave device described in the preceding section C may be applied to only one of the periods drt ⁇ T and dst ⁇ T.
- FIG. 14 is a graph showing the carrier C0 and the second inverter gate signal Sup2 * .
- the two signal waves drt + dst ⁇ d02, dst (1 ⁇ d02) described in (c-1) are shown.
- the period drt ⁇ T one signal wave drt (1-d02) is used.
- the pulse width modulation can be performed by multiplying the frequency of the converter carrier C0 by 3/2.
- FIG. 15 is a graph showing the carrier C0 and the logical value K2 that is a part of the second inverter gate signal Sup2 *.
- the two signal waves described in (c-1) are shown.
- drt (1-d02) drt ⁇ d02 is adopted.
- the signal waves drt + dst ⁇ d02, drt + (2/3) dst ⁇ dst ⁇ d02, drt + (2/3) dst + dst ⁇ d02 shown in FIG. 9 may be employed.
- the pulse width modulation can be performed by multiplying the frequency of the converter carrier C0 by 5/2.
- Such virtual multiplication of fractions is easier to control than when actual multiplication is performed. This is because the carrier actually multiplied by a fractional multiple does not take the value drt at the timing at which the converter carrier C0 commutates (the timing at which the value drt is taken), and therefore it is difficult to commutate the converter 3 at zero current.
- Converter controller 61 First inverter controller 62 Second inverter controller 601 Trapezoidal voltage command generator 602 Intermediate phase detector 603, 614, 615, 624, 625, 624A , 625A, 624B, 625B, 624C, 625C Comparator 604,605 Carrier generation unit 612,613,622,623,622A, 622B, 622B1,622B2,622C1,622C2,623A, 623B, 623B1,623B2,623C1,623C2 part 609 current-source gate logic converting unit 619,629 logical sum operation unit 627 and 628 logic synthesis section C0 converter carrier C1 first carrier C2 second carrier drt, dst through flow ratio dst (1-V *), dr + Dst ⁇ V *, drt ⁇ V *, drt + (2/3) dst + dst ⁇ V *, d
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Abstract
Description
図1は、本発明が適用可能な直接形変換装置の構成を示す回路図である。当該変換装置は、コンバータ3とインバータ4,5と、両者を接続する一対の直流電源線L1,L2とを有している。
図2はゲート信号生成装置6の構成を示すブロック図である。ゲート信号生成装置6はコンバータ制御部60、第1インバータ制御部61及び第2インバータ制御部62を備えている。
前節Bで示されたように、第1キャリアC1及び第2キャリアC2と比較される信号波を特許文献2と同様に生成すると、第1キャリアC1と第2キャリアC2とはその周波数が異ならなければならない。そして例えば両者の少なくともいずれか一方はコンバータ用キャリアC0と異なる周波数を採用することになる。しかし、信号波の生成方法を工夫することにより、第2キャリアC2をコンバータ用キャリアC0で兼用することができる。これはキャリア生成部605を省略できる利点を招来する。
上述のように、インバータ5が零ベクトルV02以外で採用するベクトルは、期間dst・T,dst・Tのそれぞれにおいて同じパターンをN回繰り返す。以下ではまず、N=2の場合について説明する。
次にN=3の場合について説明する。図9及び図10はキャリアC0と、第2インバータ用ゲート信号Sup2*の一部となる論理値とを示すグラフである。以下でも繁雑を避けるため、第2インバータ用ゲート信号Svp2*,Swp2*についての考察は省略する。図9及び図10はそれぞれ期間dst・T,drt・Tにおける波形を示している。
図12は鋸歯波を呈するキャリアC0と第2インバータ用ゲート信号Sup2*,Svp2*,Swp2*を示すグラフである。キャリアC0に鋸歯波が採用される場合であっても、期間dst・T,drt・Tの各々において各相毎に非転流零ベクトル期間を(N-1)個得ることが必要であり、採用されるベクトルの配列パターンに基づいて設定される信号波が相毎に2N個必要となる。そしてキャリアとして鋸歯波が採用された場合には、信号波が期間dst・T,drt・Tの各々において更に(N-1)個必要となる。その理由は以下の通りである。
前節Cで説明した信号波の工夫は、期間drt・T,dst・Tのいずれか一方のみに適用してもよい。
4,5 インバータ
6 ゲート信号生成装置
60 コンバータ制御部
61 第1インバータ制御部
62 第2インバータ制御部
601 台形状電圧指令生成部
602 中間相検出部
603,614,615,624,625,624A,625A,624B,625B,624C,625C 比較器
604,605 キャリア生成部
612,613,622,623,622A,622B,622B1,622B2,622C1,622C2,623A,623B,623B1,623B2,623C1,623C2 演算部
609 電流形ゲート論理変換部
619,629 論理和演算部
627,628 論理合成部
C0 コンバータ用キャリア
C1 第1キャリア
C2 第2キャリア
drt,dst 通流比
dst(1-V*),drt+dst・V*,drt・V*,drt+(2/3)dst+dst・V*,drt+(2/3)dst-dst・V*,drt(1-V*),drt(1/3+V*),drt(1/3-V*),drt+dst/2,drt/2 信号波
L1,L2 直流電源線
Srp*,Ssp*,Stp*,Srn*,Ssn*,Stn* コンバータ用ゲート信号
Sup1,Sun1,Svp1,Svn1,Swp1,Swn1,Sup2,Sun2,Svp2,Svn2,Swp2,Swn2 スイッチング素子
Sup1*,Sun1*,Svp1*,Svn1*,Swp1*,Swn1*,Sup2*,Sun2*,Svp2*,Svn2*,Swp2*,Swn2* インバータ用ゲート信号
T 一周期
T01,T02 転流零ベクトル期間
Ts01,Ts02,Ts1,Ts2 非転流零ベクトル期間
V01,V41,V61,V02,V42,V62,V72 瞬時空間ベクトル
V01,V02,V72 零ベクトル
Vu1*,Vv1*,Vw1*,Vu2*,Vv2*,Vw2* 相電圧指令
Vr,Vs,Vt 交流電圧
Claims (12)
- 多相交流電圧(Vr,Vs,Vt)をパルス幅変調によって整流して一対の直流電源線(L1,L2)に出力するコンバータ(3)と、
前記一対の直流電源線の間で相互に並列に接続され、いずれも瞬時空間ベクトル制御に従ったパルス幅変調で動作する第1インバータ(4)及び第2インバータ(5)と
を備える直接形変換装置を制御する方法であって、
前記コンバータはコンバータ用キャリア(C0)がコンバータ用指令値(drt)の値を採るときに転流し、
前記コンバータ用キャリアの一周期(T)は、前記転流が行われるタイミングで第1値(dst)及び第2値(drt)で内分されて第1期間(dst・T)と第2期間(drt・T)とに区分され、
前記第1インバータの前記瞬時空間ベクトル制御で採用する瞬時空間ベクトル(V01,V41,V61)は、前記タイミングを含む期間である第1の転流零ベクトル期間(T01)において零ベクトル(V01)を採用し、
前記第2インバータの前記瞬時空間ベクトル制御に用いられる瞬時空間ベクトル(V02,V42,V62;V02,V42,V62,V72)は、前記タイミングを含む期間である第2の転流零ベクトル期間(T02;T02,T72)において零ベクトル(V02;V02,V72)を採用し、
前記第1期間において、前記第1インバータが前記第1の転流零ベクトル期間で採用された前記零ベクトル(V01)以外で採用する前記瞬時空間ベクトルの配列パターン(V41,V61,V41)はM回(Mは1以上の整数)出現し、
前記第1期間において、前記第2インバータが前記第2の転流零ベクトル期間で採用された前記零ベクトル(V02;V02,V72)以外で採用する前記瞬時空間ベクトルの配列パターン(V42,V62,V42)はN回(Nは2以上で前記Mと異なる整数)出現する、直接形変換装置の制御方法。 - 前記第2インバータにおいて前記第1期間は、前記第2の転流零ベクトル期間(T02;T02,T72)と離散し、前記第2の転流零ベクトル期間で採用された前記零ベクトル(V02;V02,V72)が採用される期間である(N-1)個の非転流零ベクトル期間(Ts01;Ts1)を有し、
前記第2の転流零ベクトル期間と前記非転流零ベクトル期間とで挟まれた期間(Tk)の各々において前記第2インバータの前記瞬時空間ベクトル制御に用いられるベクトルの順序(V42,V62,V42;V62,V42)は相互に等しい、請求項1記載の直接形変換装置の制御方法。 - 前記第1インバータ(4)の前記瞬時空間ベクトル制御に採用される第1のキャリア(C1)と、前記第2インバータ(5)の前記瞬時空間ベクトル制御に採用される第2のキャリア(C2)とは、前記コンバータ用キャリア(C0)と同期し、
前記第1キャリアでは前記第1期間(dst・T)において同じ波形が前記M回出現し、
前記第2キャリアでは前記第1期間において同じ波形が前記N回出現する、請求項2記載の直接形変換装置の制御方法。 - 前記第1インバータの前記瞬時空間ベクトル制御に採用される第1のキャリア(C1)は前記コンバータ用キャリア(C0)と同期し、
前記第2インバータの前記瞬時空間ベクトル制御に採用される第2のキャリア(C2)の周期は、前記コンバータ用キャリア(C0)の周期と等しく、
前記第1期間(dst・T)において前記第2のキャリアに対して、前記第2インバータにおいて前記配列パターンに基づいて設定される信号波(dst(1-V*),drt+dst・V*;drt(1-V*),drt・V*;drt+(2/3)dst+dst・V*,drt+(2/3)dst-dst・V*,drt+dst・V*;drt(1-V*),drt(1/3+V*),drt(1/3-V*))が第2インバータの相毎にN個設定される、請求項2記載の直接形変換装置の制御方法。 - 前記第2のキャリアに対して、前記第2インバータにおいて前記配列パターンに基づかず、前記第1値及び前記第2値(drt,dst)に基づいた信号波(drt+dst/2,drt/2)が前記第1期間(dst・T)において更に(N-1)個設定される、請求項4記載の直接形変換装置の制御方法。
- 請求項1乃至請求項5の何れか一つに記載の直接形変換装置の制御方法が実行され、前記コンバータ(3)と、前記第1インバータ(4)と、前記第2インバータ(5)とを備える直接形変換装置。
- 多相交流電圧(Vr,Vs,Vt)を整流して一対の直流電源線(L1,L2)に出力するコンバータ(3)と、
前記一対の直流電源線の間で相互に並列に接続される第1インバータ(4)及び第2インバータ(5)と
を備える直接形変換装置を制御する装置であって、
前記第1インバータを瞬時空間ベクトル制御に従ったパルス幅変調で動作させる第1制御信号(Sup1*,Sun1*;Svp1*,Svn1*;Swp1*,Swn1*)を出力する第1インバータ制御部(61)と、
前記第2インバータを瞬時空間ベクトル制御に従ったパルス幅変調で動作させる第2制御信号(Sup2*,Sun2*;Svp2*,Svn2*;Swp2*,Swn2*)を出力する第2インバータ制御部(62)と、
前記コンバータに転流を行わせる第3制御信号(Srp*,Ssp*,Stp*,Srn*,Ssn*,Stn*)を出力するコンバータ制御部(60)と
を備え、
前記コンバータ制御部は、
コンバータ用キャリア(C0)を生成するキャリア生成部(604)と、
コンバータ用指令値(Vr*,Vs*、Vt*)を生成するコンバータ用指令生成部(601)と、
前記コンバータ用キャリアとコンバータ用指令値との比較結果を用い、前記コンバータをパルス幅制御する前記第3制御信号を生成する第3制御信号生成部(603,609)と、
前記コンバータ用指令値(Vr*,Vs*、Vt*)の中間相(Vs*)の通流比(dst)を出力する中間相検出部(602)とを有し、
前記第1インバータ制御部は、
前記第1インバータの出力の指令値である第1出力指令値(Vu1*,Vv1*、Vw1*)を生成する第1出力指令生成部(611)と、
前記通流比と前記第1出力指令値とに基づいて、前記コンバータ用キャリアと同期した第1キャリア(C1)との比較がなされる第1インバータ用信号波(drt+dst・V*,drt(1-V*)を生成する第1演算部(612,613)と、
前記比較の結果に基づいて前記第1制御信号を生成する第1制御信号生成部(614,615,619)と
を有し、
前記第2インバータ制御部は、
前記第2インバータの出力の指令値である第2出力指令値(Vu2*,Vv2*、Vw2*)を生成する第2出力指令生成部(621)と、
前記通流比と前記第2出力指令値とに基づいて、前記コンバータ用キャリアと同期した第2キャリア(C2)との比較がなされる第2インバータ用信号波(drt+dst・V*,drt(1-V*);drt(1-V*)、drt・V*;drt+dst・V*、drt+dst(2/3-V*),drt+dst(2/3+V*),drt(1-V*),drt(1/3+V*,drt(1/3-V*);drt+dst・V*,drt+dst(1/2+V*),drt+dst/2,drt(1-V*),drt(1/2-V*),drt/2))を生成する第2演算部(622,623;622A,622B,623A,623B;622A,622B1,622C1,623A,623B1,623C1;622A,622B2,622C2,623A,623B2,623C2)と、
前記比較の結果に基づいて前記第2制御信号を生成する第2制御信号生成部(624,625,629;624A,624B,625A,625B,628;624A,624B,624C,625A,625B,625C,627;624A,624B,624C,625A,625B,625C,627)と
を有し、
前記第1インバータの前記瞬時空間ベクトル制御で採用する瞬時空間ベクトル(V01,V41,V61)は、前記コンバータ用キャリアが前記中間相の値を採るタイミングを含む期間である第1の転流零ベクトル期間(T01)において、零ベクトル(V01)を採用し、
前記第2インバータの前記瞬時空間ベクトル制御に用いられる瞬時空間ベクトル(V02,V42,V62;V02,V42,V62,V72)は、前記タイミングを含む期間である第2の転流零ベクトル期間(T02;T02,T72)において零ベクトル(V02;V02,V72)を採用し、
前記コンバータ用キャリアの一周期(T)のうち、前記タイミングによって区分される第1期間において、前記第1インバータが前記第1の転流零ベクトル期間で採用された前記零ベクトル(V01)以外で採用する前記瞬時空間ベクトルの配列パターン(V41,V61,V41)はM回(Mは1以上の整数)出現し、
前記第1期間において、前記第2インバータが前記第2の転流零ベクトル期間で採用された前記零ベクトル(V02;V02,V72)以外で採用する前記瞬時空間ベクトルの配列パターン(V42,V62,V42)はN回(Nは2以上で前記Mと異なる整数)出現する、制御信号生成装置(6)。 - 前記第2インバータにおいて前記第1期間は、前記第2の転流零ベクトル期間(T02;T02,T72)と離散し、前記第2の転流零ベクトル期間で採用された前記零ベクトル(V02;V02,V72)が採用される期間である(N-1)個の非転流零ベクトル期間(Ts01;Ts1)を有し、
前記第2の転流零ベクトル期間と前記非転流零ベクトル期間とで挟まれた期間(Tk)の各々において前記第2インバータの前記瞬時空間ベクトル制御に用いられるベクトルの順序(V42,V62,V42;V62,V42)は相互に等しい、請求項7に記載の制御信号生成装置。 - 前記第1キャリアでは前記第1期間(dst・T)において同じ波形が前記M回出現し、
前記第2キャリアでは前記第1期間において同じ波形が前記N回出現する、請求項8に記載の制御信号生成装置。 - 前記第2インバータの前記瞬時空間ベクトル制御に採用される第2のキャリア(C2)の周期は、前記コンバータ用キャリア(C0)の周期と等しく、
前記第1期間(dst・T)において前記第2インバータ用信号波は、前記配列パターンに基づいた値(dst(1-V*),drt+dst・V*,drt(1-V*),drt・V*;drt+(2/3)dst+dst・V*,drt+(2/3)dst-dst・V*,drt+dst・V*,drt(1-V*),drt(1/3+V*),drt(1/3-V*))が相毎にN個設定される、請求項8記載の制御信号生成装置。 - 前記第2インバータ用信号波は、前記配列パターンに基づかず、前記通流比に基づいた値(drt+dst/2,drt/2)が前記第1期間(dst・T)において更に(N-1)個設定される、請求項10記載の制御信号生成装置。
- 請求項7乃至請求項11の何れか一つに記載の制御信号生成装置(6)と、
前記コンバータ(3)と、前記第1インバータ(4)と、前記第2インバータ(5)とを備える直接形変換装置。
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KR (1) | KR101181137B1 (ja) |
CN (1) | CN102124642B (ja) |
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US9543887B2 (en) | 2010-10-15 | 2017-01-10 | Mitsubishi Electric Corporation | Heat pump device, heat pump system, and method for controlling three-phase inverter |
US9618249B2 (en) | 2010-12-21 | 2017-04-11 | Mitsubishi Electric Corporation | Heat pump device, heat pump system, and method for controlling three-phase inverter |
US9829226B2 (en) | 2011-04-28 | 2017-11-28 | Mitsubishi Electric Corporation | Heat pump device, heat pump system, and method for controlling inverter |
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JP4911241B1 (ja) * | 2010-11-16 | 2012-04-04 | ダイキン工業株式会社 | 電力変換装置 |
AU2011358803B2 (en) * | 2011-02-07 | 2015-08-06 | Mitsubishi Electric Corporation | Heat pump device, heat pump system, and control method for three-phase inverter |
FR2975843B1 (fr) * | 2011-05-23 | 2013-05-17 | Renault Sa | Procede de commande des interrupteurs d'un redresseur de courant connecte a un chargeur embarque. |
CN103595268B (zh) * | 2013-11-26 | 2017-01-25 | 中国人民解放军重庆通信学院 | 变频器 |
JP6337732B2 (ja) * | 2014-10-09 | 2018-06-06 | 富士通株式会社 | 電源回路 |
US10158299B1 (en) * | 2018-04-18 | 2018-12-18 | Rockwell Automation Technologies, Inc. | Common voltage reduction for active front end drives |
JP7299477B2 (ja) * | 2019-03-27 | 2023-06-28 | ダイキン工業株式会社 | 電動機システム |
US11211879B2 (en) | 2019-09-23 | 2021-12-28 | Rockwell Automation Technologies, Inc. | Capacitor size reduction and lifetime extension for cascaded H-bridge drives |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US9543887B2 (en) | 2010-10-15 | 2017-01-10 | Mitsubishi Electric Corporation | Heat pump device, heat pump system, and method for controlling three-phase inverter |
US9618249B2 (en) | 2010-12-21 | 2017-04-11 | Mitsubishi Electric Corporation | Heat pump device, heat pump system, and method for controlling three-phase inverter |
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Publication number | Publication date |
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EP2317638A1 (en) | 2011-05-04 |
US8711589B2 (en) | 2014-04-29 |
KR101181137B1 (ko) | 2012-09-14 |
KR20110019441A (ko) | 2011-02-25 |
CN102124642A (zh) | 2011-07-13 |
JP2010051090A (ja) | 2010-03-04 |
JP4471027B2 (ja) | 2010-06-02 |
AU2009283588A1 (en) | 2010-02-25 |
US20110141777A1 (en) | 2011-06-16 |
CN102124642B (zh) | 2013-12-04 |
EP2317638A4 (en) | 2013-07-17 |
EP2317638B1 (en) | 2019-05-01 |
AU2009283588B2 (en) | 2013-05-16 |
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