WO2007145307A1 - Dispositif à circuit intégré semi-conducteur - Google Patents

Dispositif à circuit intégré semi-conducteur Download PDF

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Publication number
WO2007145307A1
WO2007145307A1 PCT/JP2007/062079 JP2007062079W WO2007145307A1 WO 2007145307 A1 WO2007145307 A1 WO 2007145307A1 JP 2007062079 W JP2007062079 W JP 2007062079W WO 2007145307 A1 WO2007145307 A1 WO 2007145307A1
Authority
WO
WIPO (PCT)
Prior art keywords
power supply
semiconductor integrated
integrated circuit
power
cell
Prior art date
Application number
PCT/JP2007/062079
Other languages
English (en)
Japanese (ja)
Inventor
Shunsuke Toyoshima
Hiroyasu Ishizuka
Kazuo Tanaka
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to JP2008521263A priority Critical patent/JP4873504B2/ja
Publication of WO2007145307A1 publication Critical patent/WO2007145307A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/0285—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits

Definitions

  • the present invention relates to a semiconductor integrated circuit device, and relates to a technology that is effective when applied to an ESD (Electro-Static Discharge) protection circuit.
  • ESD Electro-Static Discharge
  • WO2004Z015776 discloses a device in which a shunt device is provided in an input / output cell and is controlled by a trigger circuit provided in one or a plurality of power supply cells.
  • a shunt device is also provided in the power cell, a boost bus is connected to the trigger circuit, and the trigger circuit drives the control electrode of the shunt device to a large voltage level during an ESD event. This is intended to reduce the on-resistance.
  • the number of external terminals is increased to several hundreds due to the high functionality of semiconductor integrated circuit devices having a microcomputer function.
  • Power supply terminals must be supplied with the same power supply voltage through multiple power supply terminals in order to reduce power supply impedance.
  • the power supply terminal occupies about 10% of the total number of terminals.
  • the size of the input / output cell for signal processing is larger than that of the input / output cell because the ESD protection element for escaping ESD surge is arranged in the power cell, compared to the recent trend toward downsizing of the signal input / output cell. Become.
  • FIG. 9 shows a schematic layout diagram of a semiconductor integrated circuit device studied by the inventors of the present application prior to the present invention.
  • the power cell GCNMOS has a time constant circuit CR that detects the surge voltage and a large size to discharge the powerful surge voltage at high speed. This is a larger size than the input / output cell IO. Since the power supply impedance needs to be evenly reduced, the power supply cell GCNMOS needs to be distributed and arranged for each of the plurality of input / output cells IO. Therefore, the input / output cell IO and the power cell GCNMOS of different sizes are mixedly arranged as shown in FIG.
  • the pitch of the pad (PAD) on both sides of the power cell GCNMOS is set to the size of the power cell GCNMOS.
  • the present inventor if the input / output cell IO and the power supply cell GCNMOS are made different sizes as described above, a large space dl is generated on both sides of the power supply cell GCNMOS which is enlarged when viewed from the PAD side.
  • the number of PADs that can be placed is limited. In other words, the present inventor has realized that if cells of almost the same size are used, the interval between the PADs becomes smaller as the interval d2 between the input / output cells IO, and the number of PADs can be increased accordingly.
  • An object of the present invention is to provide a semiconductor integrated circuit device that can efficiently arrange the number of external terminals while providing an ESD protection circuit.
  • First and second power supply cells and input / output cells are provided corresponding to the first and second power supply pads and signal pads for supplying the first and second power supply voltages, respectively.
  • the first power supply voltage supplied from the first power supply pad is supplied to the first power supply line
  • the second power supply voltage supplied from the second power supply pad is supplied to the second power supply line.
  • a first MOSFET is provided in the input / output cell to allow surge current flow between the first and second power lines.
  • the first and second power cells include a time constant circuit that temporarily turns on the first MOSFET provided in the input / output cell in response to positive static electricity at the first power pad, and the first and second power cells. Consists of unidirectional elements that allow current to flow to the power pads.
  • FIG. 1 shows a circuit diagram of an input / output circuit portion of an embodiment of a semiconductor integrated circuit device according to the present invention.
  • FIG. 1 exemplarily shows two input / output cells (IO cells) and one power cell.
  • Each I / O cell has a P-channel output MOSFET Q1 and an N-channel output MOSFET Q2 that transmit output signals to the input / output terminal DQO, an input circuit IB that receives the input signal input from the input / output terminal DQO, and an ESD protection circuit. It includes diodes Dl and D2 and resistors Rl and R2.
  • Diode D1 causes a direct surge current to flow from input / output terminal DQO to power supply line VCCQ, and diode D2 causes the circuit's ground potential line VSSQ force to also flow a direct surge current to external terminal DQO.
  • Resistors R1 and R2 serve as protection elements for the MOSFETs that make up MOSFETs Ql and Q2 and input circuit IB.
  • the IO cell is provided with a MOSFET Q3 for discharging a surge voltage due to the power supply terminal VCCQ or the like.
  • This MOSFET Q3 is formed with a small size. As a result, the occupied area of the IO cell is not substantially increased.
  • the other IO cells including the IO cells corresponding to the input / output terminal DQn have the same configuration as described above.
  • the diodes Dl, D2 and the like that discharge the surge voltage at the corresponding input / output terminals DQO to DQn (n is a positive integer) are connected.
  • MOSFET power that discharges surge voltage due to power supply terminals VCCQ, etc. is divided like MOSFETQ3 and distributed to each IO cell.
  • the power cell corresponding to the power supply terminal VCCQ is provided with a time constant circuit GC for detecting a positive surge voltage of the power supply terminal VCCQ.
  • a diode D3 is provided to discharge negative surge voltage at the power supply terminal VCCQ. This diode D3 carries a surge current so that the ground line VS SQ force is also directed to the power supply terminal VCCQ.
  • the power supply cell corresponding to the circuit ground terminal VSSQ has the same configuration.
  • the time constant circuit GC output lines GTDV and WLD V corresponding to the power supply terminal VCCQ and the ground terminal VSSQ and the time constant circuit GC output lines GTDV and WLDV are connected in common to the IO cell.
  • FIG. 2 shows a circuit diagram of an embodiment of the power cell.
  • the time constant circuit GC is also composed of an integration circuit force consisting of a resistor R3 and a capacitor C1.
  • the charge voltage of the capacitor C1 is supplied to the input terminals of the inverter circuits INV1 and INV2.
  • the output terminals of these inverter circuits INV1 and INV2 are connected to output lines GTDV and WLDV.
  • These inverter circuits INV1 and INV2 operate by receiving operating voltage from VCCQ.
  • FIG. 3 shows a specific circuit diagram of an embodiment of the power cell.
  • a P-channel MOSFET Q10 formed in series is provided as the resistor R3 in FIG. 2 between the power supply terminal VCCQ and the ground terminal VSSQ.
  • Capacitor C1 in FIG. 2 is configured by the gate capacitance of MOSFET Q11. That is, the source, drain, and tool of the MOS FET Q11 are connected to the circuit ground terminal VSSQ, and the gate is connected to the drain of the MOSFET Q10 corresponding to one end of the resistor element R3.
  • the inverter circuit INV1 in FIG. 2 includes a P-channel MOSFET Q12 and an N-channel MOSFET Q13.
  • the inverter circuit INV2 in FIG. 2 is composed of a P-channel MOSFETQ 14 and an N-channel MOSFETQ15.
  • the gates of the MOSFETs Q12 to Q15 are connected in common and connected to the gate of the MOSFET Q11 as the capacitor C1.
  • the output terminal of the CMOS inverter circuit composed of MOSFETs Q12 and Q13 is connected to the output line GT DV.
  • the output terminal of the CMOS inverter circuit consisting of MOSFETs Q14 and Q15 is connected to the output line WLDV.
  • pull-down resistors RIO, R11 are provided between the output terminals of the two inverter circuits and the ground terminal VSSQ.
  • MOSFETs Q10 to Q15 have a high withstand voltage structure because the gate insulating film is formed thick.
  • MOSFETQ3, etc., whose gate is connected to the output line GTDV, has the same high voltage structure.
  • FIGS. 4B are explanatory diagrams of the operation of the MOSFET provided in the IO cell.
  • Figure 4A shows the circuit symbol for the MOSFET
  • Figure 4B shows the MOSFET element structure and parasitic elements.
  • the output lines GTDV and WLDV are connected to the gate G and the well WELL, and both are made high by the surge voltage. Therefore, in addition to flowing current as a MOSFET, a parasitic transistor is constructed with n + type drain D as collector C, p type well as base B, and n + type source S as emitter E. Current is allowed to flow.
  • the parasitic transistor can be operated by controlling the well potential WELL, so that a larger current can flow than when the surge current is flowed only as a MOSFET with the well potential equal to the source.
  • FIG. 5 shows a circuit diagram of another embodiment of the power cell.
  • This embodiment is directed to a power supply cell that supplies a low voltage VDD for an internal circuit of a semiconductor integrated circuit device.
  • This power cell has a MOSFET Q4 of the same size as the MOSFET Q3 provided in the IO cell, for example, within a range that does not become larger than the size of the 0 cell. Thereby, it is possible to cause a surge current to flow even in the power cell itself.
  • This configuration can be similarly applied to the power cell of the power supply terminal VCCQ for the input / output circuit as in the embodiment of FIG.
  • FIG. 6 shows a layout diagram of an embodiment of a semiconductor integrated circuit device according to the present invention.
  • input / output circuits are arranged around the chip, and an internal circuit is provided in the center of the chip.
  • the internal circuit is divided into two circuits such as internal circuit 1 and internal circuit 2.
  • a plurality of input / output circuit cells corresponding to a plurality of external terminals are arranged in the periphery of the chip.
  • a plurality of power supply cells are arranged for a plurality of input / output circuit cells in order to reduce the power supply impedance and stabilize the power supply impedance.
  • the power cells are shown with diagonal lines to distinguish them from the input / output circuits. This power cell has operating voltages VCCQ and VSSQ for input / output circuits and operating voltages VDD and VSS for internal circuits.
  • the input / output circuit cell in FIG. 6 is provided with an input / output circuit IO and an N-channel MOSFET as shown in FIG. Therefore, the input / output circuit cell is represented as IO + NMOS.
  • the power cell is composed of a time constant circuit GC.
  • power cell and input / output circuit cell support
  • the pitch between the input / output terminal DQ and the power supply terminals VCCQ and VSSQ and the power supply terminals VDD and VSS for the internal circuits can be made to be a substantially constant narrow pitch d2, as shown in FIG. Since the useless space as in the above configuration does not occur, the chip size of the semiconductor integrated circuit device ((LSI chip) circuit) can be reduced. On the other hand, if it is! /, The number of external terminals can be increased.
  • drive signals (GTDV, WLDV) output from time constant circuit GC to power supply lines VDD and VSS arranged so as to surround internal circuits 1 and 2 ) Is provided.
  • this MOSFET is shown in black, like NMOS.
  • an inverter circuit as a buffer amplifier BA is provided corresponding to the NMOS. This buffer amplifier amplifies the drive signals from the output lines GTDV and WLDV to speed up the switching operation of the MNOS.
  • the NMOS corresponding to the internal circuit uses a MOSFET having a gate breakdown voltage equivalent to that of the MOSFET constituting the internal circuit, unlike the NMOS provided in the IO cell.
  • FIG. 7 shows a layout diagram of another embodiment of the semiconductor integrated circuit device according to the present invention.
  • an N-channel MOSFET for discharging a surge voltage is provided there.
  • an M NOS cell as shown by the dotted line in FIG. 7 and place the MNOS cell appropriately in the part where the spacing between the bonding pads PAD at the corners of the chip becomes rough, such as d3. That's it. Roughening the pitch of the bonding pad PAD is also the force required to maintain the spacing between adjacent wires arranged diagonally at the chip corner.
  • an NMOS cell is prepared as described above, it can be used to reduce the size of the N-channel MOSFET provided in the IO cell.
  • FIG. 8 shows a layout diagram of another embodiment of the semiconductor integrated circuit device according to the present invention.
  • the semiconductor integrated circuit device (LSI chip) of this embodiment pays attention to the fact that the corner around the chip is a dead space where no IO cell or power cell is provided, and an N-channel MOSFET that discharges a surge voltage there.
  • the dotted line in Figure 8 An NMOS cell as shown in Fig. 2 is prepared, and the NMOS cell is arranged at the corner of the chip.
  • an NMOS cell is prepared as described above, it can be used to reduce the size of the N-channel MOSFET provided in the IO cell. Further, the NMOS cell of FIG. 7 may be combined.
  • the MOSFET Q3 well may be connected to the source and the inverter circuit INV2 of the time constant circuit GC may be omitted. If there are two types of circuit ground potential pins, VS SQ and VSS, a surge protection circuit is provided with a diode that sends a surge current to VSS, and a diode that sends a surge current to VSS vs VSSQ. It is done. These diodes may be appropriately provided on the semiconductor chip.
  • a buffer amplifier that amplifies a drive signal such as MOS FET Q3 may be provided in a portion where the pad pitch is wide as indicated by d3 in FIG.
  • the present invention can be similarly applied to a power supply that supplies an external terminal power of 3 or more.
  • the present invention can be widely used as an ESD protection circuit for semiconductor integrated circuit devices.
  • FIG. 1 is a circuit diagram of an input / output circuit portion showing an embodiment of a semiconductor integrated circuit device according to the present invention.
  • FIG. 2 is a circuit diagram showing an embodiment of the power cell of FIG.
  • FIG. 3 is a specific circuit diagram showing an embodiment of the power cell of FIG. 1.
  • FIG. 4A is an operation explanatory diagram of a MOSFET provided in the IO cell of FIG. 1.
  • FIG. 4B is an operation explanatory diagram of the MOSFET provided in the IO cell of FIG. 1.
  • FIG. 5 is a circuit diagram showing another embodiment of the power cell used in the present invention.
  • FIG. 6 is a layout diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention.
  • FIG. 7 is a layout diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention.
  • FIG. 8 is a layout diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention.
  • FIG. 9 is a schematic outside layer view of a semiconductor integrated circuit device studied prior to the present invention.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne un dispositif à circuit intégré semi-conducteur dans lequel un circuit de protection ESD est disposé et dont le nombre de bornes externes est arrangé efficacement. Des première et seconde cellules d'alimentation et une cellule d'entrée/sortie sont disposées, correspondant à des première et seconde pastilles d'alimentation servant à appliquer des première et seconde tensions d'alimentation et correspondant à une pastille de signal. Une première ligne d'alimentation est alimentée par la première tension d'alimentation provenant de la première pastille d'alimentation, et une seconde ligne d'alimentation est alimentée par la seconde tension d'alimentation provenant de la seconde pastille d'alimentation. Le dispositif comporte un premier MOSFET permettant qu'un courant de surcharge de la première ligne d'alimentation et de la seconde ligne d'alimentation circule dans la cellule d'entrée/sortie. Les première et seconde cellules d'alimentation sont composées d'un circuit constant dans le temps grâce à la présence du premier MOSFET sur la cellule d'entrée/sortie temporairement sous tension, correspondant à l'électricité statique positive à la première pastille d'alimentation ; et d'un élément unidirectionnel permettant aux courants de circuler respectivement vers les première et seconde pastilles d'alimentation.
PCT/JP2007/062079 2006-06-15 2007-06-15 Dispositif à circuit intégré semi-conducteur WO2007145307A1 (fr)

Priority Applications (1)

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JP2008521263A JP4873504B2 (ja) 2006-06-15 2007-06-15 半導体集積回路装置

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JP2006165473 2006-06-15
JP2006-165473 2006-06-15

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013051175A1 (fr) * 2011-10-06 2013-04-11 パナソニック株式会社 Dispositif de circuit intégré à semi-conducteur
CN104347613A (zh) * 2013-08-09 2015-02-11 联华电子股份有限公司 具静电放电保护功能的芯片
US10256228B2 (en) 2017-01-25 2019-04-09 Renesas Electronics Corporation Semiconductor device
CN110999024A (zh) * 2017-08-14 2020-04-10 三星Sdi株式会社 电池保护电路和包括该电路的电池组

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10214936A (ja) * 1996-12-31 1998-08-11 Sgs Thomson Microelectron Inc 過剰電圧保護を改良した集積回路
JP2000208718A (ja) * 1999-01-19 2000-07-28 Matsushita Electric Ind Co Ltd 半導体装置
JP2005536046A (ja) * 2002-08-09 2005-11-24 フリースケール セミコンダクター インコーポレイテッド 静電気放電保護回路及び動作方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3883697B2 (ja) * 1998-05-15 2007-02-21 旭化成マイクロシステム株式会社 過電圧の保護回路
JP2004327538A (ja) * 2003-04-22 2004-11-18 Kawasaki Microelectronics Kk 半導体チップ
US8035188B2 (en) * 2004-07-28 2011-10-11 Panasonic Corporation Semiconductor device
JP2006128422A (ja) * 2004-10-29 2006-05-18 Renesas Technology Corp 半導体集積回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10214936A (ja) * 1996-12-31 1998-08-11 Sgs Thomson Microelectron Inc 過剰電圧保護を改良した集積回路
JP2000208718A (ja) * 1999-01-19 2000-07-28 Matsushita Electric Ind Co Ltd 半導体装置
JP2005536046A (ja) * 2002-08-09 2005-11-24 フリースケール セミコンダクター インコーポレイテッド 静電気放電保護回路及び動作方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KER M.-D.: "Whole-Chip ESD Protection Design with Efficient VDD-to-VSS ESD Clamp Circuits for Submicron CMOS VLSI", vol. 46, no. 1, 1999, pages 173 - 183, XP000792085 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013051175A1 (fr) * 2011-10-06 2013-04-11 パナソニック株式会社 Dispositif de circuit intégré à semi-conducteur
US9401602B2 (en) 2011-10-06 2016-07-26 Socionext Inc. Semiconductor integrated circuit device
CN104347613A (zh) * 2013-08-09 2015-02-11 联华电子股份有限公司 具静电放电保护功能的芯片
CN104347613B (zh) * 2013-08-09 2017-07-14 联华电子股份有限公司 具静电放电保护功能的芯片
US10256228B2 (en) 2017-01-25 2019-04-09 Renesas Electronics Corporation Semiconductor device
CN110999024A (zh) * 2017-08-14 2020-04-10 三星Sdi株式会社 电池保护电路和包括该电路的电池组
CN110999024B (zh) * 2017-08-14 2023-08-29 三星Sdi株式会社 电池保护电路和包括该电路的电池组
US11799303B2 (en) 2017-08-14 2023-10-24 Samsung Sdi Co., Ltd. Battery protection circuit and battery pack comprising same

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Publication number Publication date
JPWO2007145307A1 (ja) 2009-11-12
JP2011254100A (ja) 2011-12-15
JP4873504B2 (ja) 2012-02-08

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