JP6251387B2 - 複合型半導体装置 - Google Patents
複合型半導体装置 Download PDFInfo
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- JP6251387B2 JP6251387B2 JP2016519128A JP2016519128A JP6251387B2 JP 6251387 B2 JP6251387 B2 JP 6251387B2 JP 2016519128 A JP2016519128 A JP 2016519128A JP 2016519128 A JP2016519128 A JP 2016519128A JP 6251387 B2 JP6251387 B2 JP 6251387B2
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Description
本発明の第1実施形態を説明する。図1に、第1実施形態に係る複合型半導体装置(複合型スイッチング素子)1の回路図を示す。複合型半導体装置1は、互いに直列に接続された電界効果トランジスタ(以下、FETという)11及び12と、抵抗素子13と、コンデンサ14と、抵抗素子15と、FET(放電用FET)16と、ドレイン端子17と、ゲート端子18と、ソース端子19と、を備える。FET11、12及び16の夫々はNチャネル型のFETである。
Cx・Rx・(dV/dt)ESD > VTH16 …(1)
Cx・Rx・(dV/dt)SWITCH <VTH16 …(2)
本発明の第2実施形態を説明する。第2実施形態並びに後述の第3及び第4実施形態は第1実施形態を基礎とする実施形態であり、第2〜第4実施形態において特に述べない事項に関しては、矛盾の無い限り、第1実施形態の記載が第2〜第4実施形態にも適用される。矛盾の無い限り、第1〜第4実施形態の内、任意の複数の実施形態を組み合わせても良い。
本発明の第3実施形態を説明する。図6は、第3実施形態に係る複合型半導体装置1bの回路図である。図1の複合型半導体装置1を基準として、ツェナーダイオード21を追加することで複合型半導体装置1bが形成される。当該追加を除き、装置1及び1bは互いに同じものである。
本発明の第4実施形態を説明する。第4実施形態の技術を第1〜第3実施形態の何れに対しても適用できるが、以下では説明の具体化のため、第1実施形態に係る複合型半導体装置1(図1)を参照して第4実施形態の技術を説明する。
本発明の実施形態は、特許請求の範囲に示された技術的思想の範囲内において、適宜、種々の変更が可能である。以上の実施形態は、あくまでも、本発明の実施形態の例であって、本発明ないし各構成要件の用語の意義は、以上の実施形態に記載されたものに制限されるものではない。上述の説明文中に示した具体的な数値は、単なる例示であって、当然の如く、それらを様々な数値に変更することができる。
本発明について考察する。
11 GaNFET
12、16 MOSFET
13、15 抵抗素子
14 コンデンサ
17 ドレイン端子
18 ゲート端子
19 ソース端子
20 ダイオード
21 ツェナーダイオード
41 GaNFETチップ
42 MOSFETチップ
Claims (5)
- 第1及び第2端子間に互いに直列接続されたノーマリオン型の第1FET及びノーマリオフ型の第2FETを備えた複合型半導体装置において、
前記第2FETに並列接続された放電用スイッチング素子と、前記第1及び前記第2端子間に配置され、前記第1端子にサージが加わったときに前記放電用スイッチング素子をオンさせるためのトリガ回路と、を有する保護回路を設けた
ことを特徴とする複合型半導体装置。 - 前記トリガ回路は、前記第1端子と前記放電用スイッチング素子の制御電極との間に介在する容量成分と、前記放電用スイッチング素子の制御電極と前記第2端子との間に配置された抵抗素子と、を有する
ことを特徴とする請求項1に記載の複合型半導体装置。 - 前記保護回路は、前記第1端子にサージが加わったときに、前記抵抗素子の発生電圧に基づき前記放電用スイッチング素子をオンさせて、前記第1端子からのサージ電流を前記第1FET及び前記放電用スイッチング素子を通じて前記第2端子に放電させる
ことを特徴とする請求項2に記載の複合型半導体装置。 - 前記第2FETを形成するためのノーマリオフ型の複数の単位FETの一部を転用して、前記放電用スイッチング素子としての放電用FETを形成した
ことを特徴とする請求項1〜3の何れかに記載の複合型半導体装置。 - 前記放電用スイッチング素子としての放電用FETの閾電圧を、前記第2FETの閾電圧よりも高くした
ことを特徴とする請求項1〜4の何れかに記載の複合型半導体装置。
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