WO2006131968A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- WO2006131968A1 WO2006131968A1 PCT/JP2005/010554 JP2005010554W WO2006131968A1 WO 2006131968 A1 WO2006131968 A1 WO 2006131968A1 JP 2005010554 W JP2005010554 W JP 2005010554W WO 2006131968 A1 WO2006131968 A1 WO 2006131968A1
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- film
- interlayer insulating
- lower electrode
- insulating film
- ferroelectric
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/57—Capacitors with a dielectric comprising a perovskite structure material comprising a barrier layer to prevent diffusion of hydrogen or oxygen
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
Definitions
- the present invention relates to a semiconductor device having a ferroelectric capacitor structure in which a dielectric film having ferroelectric characteristics is sandwiched between a lower electrode and an upper electrode, and a method for manufacturing the same.
- Flash memory and ferroelectric memory have been known as nonvolatile memories in which stored information is not lost even when the power is turned off.
- a flash memory has a floating gate embedded in a gate insulating film of an insulated gate field effect transistor (IGFET), and stores information by accumulating charges representing stored information in the floating gate. .
- IGFET insulated gate field effect transistor
- FeRAM stores information using the hysteresis characteristics (ferroelectric characteristics) of ferroelectrics.
- a ferroelectric capacitor structure having a ferroelectric film as a dielectric between a pair of electrodes generates polarization according to the applied voltage between the electrodes, and has spontaneous polarization even when the applied voltage is removed. If the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed. Information can be read by detecting this spontaneous polarization.
- FeRAM has the advantage that it operates at a lower voltage than flash memory and can be written at high speed with low power consumption. It is being studied for applications such as a logic-on-chip (SC: System On Chip) IC chip that incorporates FeRAM into conventional logic technology.
- SC System On Chip
- the FeRAM ferroelectric capacitor employs a structure in which the electrical connection between the capacitor lower electrode and the impurity diffusion region of the transistor is performed by a lead electrode provided on the lower electrode.
- Application of the so-called planar capacitor structure has been put into practical use.
- the lower electrode is a conductive contact that becomes the Balta contact directly below it. It is considered urgent to apply the V, so-called stacked capacitor structure, which uses a structure that connects to the impurity diffusion region via an electric plug.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2002-33459
- Patent Document 2 Japanese Patent Laid-Open No. 10-50956
- a barrier conductive layer formed directly above the conductive plug (or as an anti-oxidation film of the conductive plug) is used to connect the conductive plug and the lower electrode of the ferroelectric capacitor.
- a lower electrode is laminated (through the membrane).
- the laminate after the lower electrode (or barrier conductive film: the same applies hereinafter) inherits the orientation of the conductive plug and the effect of the step.
- the ferroelectric film formed on the lower electrode is strongly affected by the orientation and the level difference, and inevitably deteriorates the ferroelectric film due to the influence of the conductive plug.
- tungsten is often used as the material of the conductive plug used for the Balta contact.
- the W plug has a groove-like depression called a seam on its surface, and degassing occurs due to impurities accumulated in the seam, which promotes the deterioration of the ferroelectric film.
- CMP chemical mechanical polishing
- the stacked capacitor structure can reduce the area occupied by the capacitor while securing a relatively large capacity.
- the ferroelectric capacitor By applying this to the ferroelectric capacitor, it is possible to meet the recent demand. Contributes to miniaturization and high integration of certain elements.
- a serious problem is that the orientation of the ferroelectric film is inevitably deteriorated due to the provision of a conductive plug as a Balta contact directly under the lower electrode, which inevitably deteriorates the ferroelectric properties. Is still unresolved.
- the present invention has been made in view of the above problems, and adopts a stack type capacitor structure for a ferroelectric capacitor to reduce the occupied area of the capacitor while securing a relatively large capacity. Realizes ferroelectric film orientation that is equal to or better than when a planar capacitor structure is used, and achieves excellent ferroelectric properties. It is an object of the present invention to provide a conductor device and a manufacturing method thereof.
- the semiconductor device of the present invention is formed in a semiconductor substrate, a conductive plug formed above the semiconductor substrate, and a portion aligned above the conductive plug, and includes a lower electrode and an upper electrode.
- the conductive plug and the lower electrode are electrically connected to each other in a region other than the region corresponding to the gap between the conductive plug and the lower electrode in the insulating film.
- a method for manufacturing a semiconductor device of the present invention includes a step of forming a conductive plug above a semiconductor substrate, a step of forming a conductive film so as to cover an upper surface of the conductive plug, and the conductive film.
- forming the connection portion in a region including a peripheral region of the lower electrode other than a region corresponding to the space between the conductive plug and the lower electrode in the interlayer insulating film. .
- FIG. 1A is a schematic cross-sectional view showing an element in the vicinity of a conventional FeRAM stack type ferroelectric capacitor.
- FIG. 1B is a schematic plan view schematically showing the orientation of a ferroelectric film of a conventional ferroelectric capacitor.
- FIG. 2A is a schematic cross-sectional view showing a state in the vicinity of a FeRAM stack type ferroelectric capacitor according to the present invention.
- FIG. 2B is a schematic plan view schematically showing the orientation of the ferroelectric film of the ferroelectric capacitor in the present invention.
- FIG. 3A is a schematic cross-sectional view showing the FeRAM manufacturing method according to the first embodiment in the order of steps.
- FIG. 3B is a schematic cross-sectional view showing the FeRAM manufacturing method according to the first embodiment in the order of steps.
- FIG. 3C is a schematic cross-sectional view showing the FeRAM manufacturing method according to the first embodiment in the order of steps.
- FIG. 3D is a schematic cross-sectional view showing the FeRAM manufacturing method according to the first embodiment in the order of steps.
- FIG. 3E is a schematic cross-sectional view showing the FeRAM manufacturing method according to the first embodiment in the order of steps.
- FIG. 3F is a schematic cross-sectional view showing the FeRAM manufacturing method according to the first embodiment in the order of steps.
- FIG. 3G is a schematic cross-sectional view showing the FeRAM manufacturing method according to the first embodiment in the order of steps.
- FIG. 4A is a schematic cross-sectional view showing the FeRAM manufacturing method according to the first embodiment in the order of steps.
- FIG. 4B is a schematic sectional view showing the FeRAM manufacturing method according to the first embodiment in the order of steps.
- FIG. 4C is a schematic cross-sectional view showing the FeRAM manufacturing method according to the first embodiment in the order of steps.
- FIG. 4D is a schematic cross-sectional view showing the FeRAM manufacturing method according to the first embodiment in the order of steps.
- FIG. 5A is a schematic cross-sectional view showing the FeRAM manufacturing method according to the first embodiment in the order of steps.
- FIG. 5B is a schematic cross-sectional view showing the method of manufacturing the FeRAM according to the first embodiment in the order of steps.
- FIG. 5C is a schematic cross-sectional view showing the FeRAM manufacturing method according to the first embodiment in the order of steps.
- FIG. 5D is a schematic cross-sectional view showing the FeRAM manufacturing method according to the first embodiment in the order of steps.
- FIG. 6A is a schematic sectional view showing the FeRAM manufacturing method according to the first embodiment in the order of steps.
- FIG. 6B is a schematic cross-sectional view showing the method of manufacturing the FeRAM according to the first embodiment in the order of steps.
- FIG. 7A is a schematic cross-sectional view showing the FeRAM manufacturing method according to the first embodiment in the order of steps.
- FIG. 7B is a schematic cross-sectional view showing the FeRAM manufacturing method according to the first embodiment in the order of steps.
- FIG. 8A is a schematic plan view showing grooves formed in the interlayer insulating film.
- FIG. 8B is a schematic plan view showing a connection portion formed in a groove formed in the interlayer insulating film.
- FIG. 9A is a schematic cross-sectional view showing a state in which the steps of FIG. 5A and FIG. 5B are performed using a hard mask method.
- FIG. 9B is a schematic cross-sectional view showing a state in which the steps of FIGS. 5A and 5B are performed using a hard mask method.
- FIG. 10A is a schematic cross-sectional view showing a state in which the processes of FIGS. 5A and 5B are performed using a hard mask method.
- FIG. 10B is a schematic cross-sectional view showing a state in which the steps of FIG. 5A and FIG. 5B are performed using a hard mask method.
- FIG. 10C is a schematic cross-sectional view showing a state in which the steps of FIG. 5A and FIG. 5B are performed using a hard mask method.
- FIG. 11A is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 1.
- FIG. 11B is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 1.
- FIG. 11C is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 1.
- Fig. 11D is a schematic diagram showing the main steps in the FeRAM manufacturing method according to Modification 1. It is sectional drawing.
- FIG. 12A is a schematic plan view showing an opening formed in an interlayer insulating film.
- FIG. 12B is a schematic plan view showing the connection portion formed in the opening formed in the interlayer insulating film.
- FIG. 13A is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 2.
- FIG. 13B is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 2.
- FIG. 14A is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 3.
- FIG. 14B is a schematic cross-sectional view showing the main processes in the FeRAM manufacturing method according to Modification 3.
- FIG. 15A is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 4.
- FIG. 15B is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 4.
- FIG. 15C is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 4.
- FIG. 15D is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 4.
- FIG. 15E is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 4.
- FIG. 15F is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 4.
- FIG. 16A is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 4.
- FIG. 16B is a schematic cross-sectional view showing main steps in the FeRAM manufacturing method according to Modification 4.
- FIG. 16C is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 4.
- FIG. 16D is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 4.
- FIG. 17A is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 4.
- FIG. 17B is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 4.
- FIG. 18A is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 4.
- FIG. 18B is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 4.
- Fig. 19 is a schematic cross-sectional view showing how each hydrogen protective film is formed on the entire surface of FeRAM.
- FIG. 20A is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 5.
- FIG. 20B is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 5.
- FIG. 20C is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 5.
- FIG. 20D is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 5.
- FIG. 20E is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 5.
- FIG. 21A is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 5.
- FIG. 21B is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 5.
- FIG. 21C is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 5.
- FIG. 21D is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to Modification 5.
- FIG. 22A is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to the second embodiment.
- FIG. 22B is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to the second embodiment.
- FIG. 22C is a schematic cross-sectional view showing the main steps in the method for manufacturing FeRAM according to the second embodiment.
- FIG. 22D is a schematic cross-sectional view showing the main steps in the FeRAM manufacturing method according to the second embodiment.
- FIG. 23A is a schematic plan view showing an opening formed in an interlayer insulating film.
- FIG. 23B is a schematic plan view showing the connection portion formed in the opening formed in the interlayer insulating film.
- FIG. 24A is a schematic plan view showing an ideal connection state between the lower electrode and each connection portion.
- FIG. 24B is a schematic plan view showing a case where a slight shift occurs in the direction of arrow A at the position where the lower electrode is formed.
- FIG. 25 is a schematic plan view showing a state in which each connection portion is formed at two opposing corner positions in the peripheral region of the conductive film.
- the lower electrode (or barrier conductive film) and the conductive film should be removed to eliminate the effect of the orientation step on the surface of the conductive plug relative to the ferroelectric film.
- An interlayer insulating film is formed between the plugs. Unlike the conductive film such as the lower electrode and the barrier conductive film, the inter-layer insulating film can be formed so as not to inherit the lower alignment step, unlike the conductive film such as the lower electrode and the barrier conductive film.
- the lower electrode corresponds to the space between the conductive plug and the lower electrode in the interlayer insulating film in a plan view that ensures good orientation in the central region of the ferroelectric film.
- the conductive plug and the lower electrode are electrically connected at a region other than the central region.
- a conductive film is formed so as to cover the upper surface of the conductive plug, and the conductive plug and the lower electrode are interposed between the conductive film and the portion including the peripheral region of the lower electrode in the interlayer insulating film covering the conductive film. To form a connection portion for electrically connecting the two.
- an annealing process is required to restore the characteristics of the ferroelectric film S, and this annealing process causes a ferroelectric film (for example, PZT) to be recovered.
- Pb and oxygen are released from the peripheral region in the case of the above, and the Pb concentration and oxygen concentration in the peripheral region decrease. This Pb detachment and oxygen detachment inevitably deteriorates the ferroelectric properties in the peripheral region of the ferroelectric film.
- connection portion for connecting the conductive plug and the lower electrode is essential, and the ferroelectric characteristics of the ferroelectric film are unavoidable at the formation position of the connection portion of the lower electrode. to degrade.
- the peripheral region in which deterioration of the ferroelectric properties in the ferroelectric film is unavoidable is actively used, and the connection portion is provided at a portion corresponding to the peripheral portion of the lower electrode.
- the connection portion is formed in the peripheral region which is inherently inevitable to be deteriorated, and a structure which causes deterioration of the orientation of the ferroelectric film is not provided in the central region of the lower electrode.
- the influence of the conductive plug is blocked by the interlayer insulating film, and the orientation of the laminate formed on the interlayer insulating film is reduced. It can be formed with good control of properties. Accordingly, it is possible to form the ferroelectric film so as to have as much orientation as possible and high ferroelectric properties.
- Patent Document 1 discloses an example in which a frame-shaped recess is formed in a barrier conductive film on a lower electrode.
- the barrier conductive film is formed immediately above the conductive plug, it is inevitable that the subsequent laminate will take over the effects of the orientation of the conductive plug and the steps.
- Patent Document 2 discloses an example in which a lower electrode is interposed and formed in a laminated film of a silicon oxide film and a silicon nitride film via a barrier conductive film. Similar to Patent Document 1, as long as the barrier conductive film is formed immediately above the conductive plug, the subsequent laminates are conductive. Inheriting the influence of the orientation of the electric plug and the level difference is inevitable.
- FIG. 1A and 2A are schematic cross-sectional views showing the vicinity of a FeRAM stack type ferroelectric capacitor.
- FIG. 1A is a conventional example
- FIG. 2A is an example of the present invention.
- a ferroelectric capacitor 111 in which a W plug 101 serving as a Balta contact is formed to be supported in an interlayer insulating film 102, and a ferroelectric film 105 is sandwiched between a lower electrode 103 and an upper electrode 104. Is formed on the interlayer insulating film 106.
- FIG. 1A shows a state of the ferroelectric film 105 in plan view at this time.
- the central portion 105c and the peripheral region 105b in the central region 105a of the ferroelectric film 105 are low in orientation and higher in orientation than these.
- the central region 105a only the gap portion 105d excluding the central portion 105c is used.
- a conductive film 112 is formed so as to cover the W plug 101, and an interlayer is formed so as to cover this conductive film 112.
- An insulating film 113 is formed. The surface of the interlayer insulating film 113 is flattened.
- a lower electrode 103 is formed on the W plug 101 via an interlayer insulating film 113, and a ferroelectric film 105 and an upper electrode 104 are sequentially stacked on the lower electrode 103.
- the W plug 101 and the lower electrode 103 are formed by connecting the conductive film 112 and the lower electrode 103 at a connection portion 114 formed in a portion corresponding to the peripheral region 105b of the ferroelectric film 105 in the interlayer insulating film 113. It is electrically connected by connecting.
- FIG. 2B shows the state of the ferroelectric film 105 in plan view at this time. As described above, in the structure of the present invention, it is most effective to ensure the ferroelectric characteristics with low orientation only in the peripheral region 105b (the region indicated by the broken line in FIG. 2A) that inevitably deteriorates the orientation. High alignment and orientation are realized over the entire central region 105a of the ferroelectric film 105, which is the region.
- connection portion may be formed in a frame shape along the peripheral region of the lower electrode.
- connection portion is formed in a plug shape at two or four corners in the peripheral region of the lower electrode.
- connection portion It is desirable to form the connection portion in a specific position in the peripheral region of the lower electrode.
- annealing is required to recover the characteristics of the ferroelectric film after forming the ferroelectric capacitor.
- the connecting part is W or the like due to annealing, the surface is oxidized and the conductivity is remarkably deteriorated. Therefore, by forming the connection portion at a position in the peripheral region of the lower electrode as described above, oxidation of the connection portion can be prevented and sufficient connection is ensured.
- connection portion When the connection portion is formed at a position in the peripheral region of the lower electrode, W or copper (Cu), which is commonly used as a material for the connection portion, can be used.
- Cu copper
- grooves or openings to be connected are filled with Cu by the so-called Met method, and the surface is flattened by the CMP method.
- the METSUKI method does not generate seams. For this reason, it is possible to fill the groove or the opening where there is no concern about degassing due to impurities accumulated in the seam with good filling ability. Since the Cu is relatively soft and close to the polishing speed of the interlayer insulation film, there is little difference in level between the interlayer insulation film. Therefore, by using Cu, it is possible to sufficiently fill even fine grooves or openings.
- connection portion a position extending inside and outside the lower electrode including the peripheral region of the lower electrode can be considered.
- the connection portion is formed at a position in the peripheral region of the lower electrode as described above, and in particular, the frame-shaped connection portion is formed in the peripheral region. It is difficult to form at the position. Therefore, as described above, the connection portion is formed at a position extending inside and outside of the lower electrode including the peripheral region of the lower electrode, so that miniaturization can be dealt with.
- connection part As a measure against the oxidation of the connection part, it is conceivable to set the annealing temperature for characteristic recovery low and to select the material of the connection part. Specific examples of the latter include iridium (Ir) and TiAlN. Ir is also oxidized and becomes IrO (conductive oxide).
- connection part is a metal that does not lose its electrical properties.
- TiAlN is a conductive nitride with excellent oxidation resistance.
- an FeRAM structure employing a stacked capacitor structure and a method for manufacturing the same are disclosed.
- this embodiment only the vicinity of the memory cell portion of FeRAM is shown, and description and illustration of the logic portion and the like are omitted.
- the structure of FeRAM is described together with its manufacturing method.
- 3A to 7B are schematic cross-sectional views illustrating the FeRAM manufacturing method according to the first embodiment in the order of steps.
- a MOS transistor 20 that functions as a selection transistor is formed on a silicon semiconductor substrate 10.
- the element isolation structure 11 is formed on the surface layer of the silicon semiconductor substrate 10 by, for example, the STI (Shallow Trench Isolation) method to determine the element active region.
- STI Shallow Trench Isolation
- an impurity here B, for example, is ion-implanted into the element active region under the conditions of a dose amount of 3.0 ⁇ 10 13 Zcm 2 and an acceleration energy of 300 keV to form the wall 12.
- a silicon nitride film having a thickness of about 29 nm is deposited, and the silicon nitride film, the polycrystalline silicon film, and the gate insulating film 13 are processed into an electrode shape by lithography and subsequent dry etching, whereby the gate insulating film 13 is formed.
- Pattern the gate electrode 14 The At the same time, a cap film 15 made of a silicon nitride film is patterned on the gate electrode 14.
- an impurity for example, As in this case, is ion-implanted into the element active region under the conditions of a dose of 5.
- a silicon oxide film is deposited on the entire surface by a CVD method, and this silicon oxide film is so-called etched back, thereby leaving the silicon oxide film only on the side surfaces of the gate electrode 14 and the cap film 15 to form sidewalls.
- An insulating film 17 is formed.
- an impurity in the element active region here P is a condition that the impurity concentration is higher than that of the LDD region 16, for example, a dose of 5.0 X 10 Ions are implanted under the conditions of 14 Zcm 2 and acceleration energy of 13 keV to form the source / drain regions 18 that overlap the LDD regions 16, thereby completing the MOS transistor 20.
- a protective film 19 is formed so as to cover the MOS transistor 20.
- silicon oxynitride (SiON) is deposited to a thickness of about 200 nm.
- an interlayer insulating film 21 covering the MOS transistor 20 and a W plug 22 serving as a Balter contact are formed.
- an interlayer insulating film 21 is formed so as to cover the MOS transistor 20.
- a silicon oxide film is deposited to a thickness of about 600 nm by, for example, a CVD method using TEOS.
- the surface of the interlayer insulating film 21 is planarized by, eg, CMP.
- the interlayer insulating film 21 and the protective film 19 are processed by lithography and subsequent dry etching until a part of the surface of the source Z drain region 18 is exposed.
- a contact hole 21a having a 0.25 z m diameter is formed.
- a Ti film (thickness of about 30 nm) and a TiN film (thickness of about 20 nm) are sequentially deposited on the interlayer insulating film 2 by a sputtering method so as to cover the wall surface of the contact hole 21a.
- a base film (glu film) 23 is formed.
- a tungsten (W) film is formed by the CVD method so as to fill the contact hole 21a through the glue film 23.
- the W film and the glue film 23 are polished by CMP using the interlayer insulating film 21 as a stopper to form a W plug 22 that fills the contact hole 21a with W via the glue film 23.
- a conductive film 24 is formed.
- a TiN film (film thickness of about 150 nm), an Al_Cu film (film thickness of about 30 Onm), and a TiN film (film thickness of about 150 nm) are sequentially deposited by sputtering to form a conductive film 24 having a laminated structure.
- the TiN film has better heat resistance than the Al-Cu film, it is good to form a thick TiN film without forming the Al_Cu film.
- a TiN film is deposited to a thickness of about 300 nm to 500 nm to form a single layer structure conductive film 24.
- a resist pattern 26 for processing the conductive film 24 is formed.
- an antireflection film 25 (which can be omitted) is formed on the conductive film 24 and then a resist is formed on the antireflection film 25 by coating. Then, the resist is processed by lithography to form a resist pattern 26.
- the conductive film 24 is processed using the resist pattern 26.
- the conductive film 24 is dry etched using the resist pattern 26 as a mask.
- the antireflection film 25 is also etched.
- the conductive film 24 is patterned by this dry etching so as to cover the W plug 22 on the interlayer insulating film 21 following the resist pattern 26. Thereafter, the resist pattern 26 and the antireflection film 25 thereunder are removed.
- an interlayer insulating film 27 is formed.
- an interlayer insulating film 27 is formed on the interlayer insulating film 21 so as to carry the conductive film 24.
- the interlayer insulating film 27 a silicon oxide film is deposited with a film thickness of about 1300 nm to about 1500 nm by, for example, a CVD method using TEOS.
- the surface layer of the interlayer insulating film 27 is formed so that the interlayer insulating film 27 remains about 3 OO nm to 400 nm in thickness. For example, it is removed by the CMP method. As a result, the surface of the interlayer insulating film 27 is planarized.
- the interlayer insulating film 27 blocks the influence of the orientation of the W plug 22 without taking over the effect of the step, ie, The interlayer insulating film 27 is formed on the surface so as to have excellent orientation.
- a resist pattern 29 for forming a groove in the interlayer insulating film 27 is formed.
- an antireflection film 28 (which can be omitted) is formed on the interlayer insulating film 27 and then a resist is applied on the antireflection film 28. Then, the resist is processed by lithography to form a resist pattern 29 having a frame-like groove 29 a aligned with the position of the peripheral region of the conductive film 24. Applicable shapes other than the frame-shaped groove 29a will be described in a later-described modification.
- the interlayer insulating film 27 is processed using the resist pattern 29.
- the interlayer insulating film 27 is dry etched using the resist pattern 29 as a mask.
- the antireflection film 28 is also etched.
- a groove 27 a that exposes the end portion in a frame shape is formed along the end portion of the conductive film 24, following the groove 29 a of the resist pattern 29 by this dry etching.
- FIG. 8A shows a plan view of the groove 27a formed in the interlayer insulating film 27.
- FIG. Since the frame-like groove 27a is very small in size, it may not be generally easy to form it.
- the fine frame-shaped groove 27a can be easily formed. can do. After this dry etching, the resist pattern 29 and the underlying antireflection film 28 are removed.
- EB electron beam
- a conductive material 32 is deposited so as to fill the groove 27a.
- a TiN film for example, is deposited to a thickness of about 20 nm on the interlayer insulating film 27 so as to cover the wall surface of the groove 27a, thereby forming a base film (Gnore film) 31.
- a conductive material 32 is deposited so as to enclose the groove 27a via the glue film 31 by the CVD method.
- a tungsten (W) film is formed to a thickness of about 400 nm.
- connection portion 33 is formed.
- the conductive material 32 and the glue film 31 are polished by CMP using the interlayer insulating film 27 as a stopper, and the groove-shaped connection portion 33 is held in the groove 27a by the conductive material 32 via the glue film 31.
- FIG. 8B shows a plan view of the connecting portion 33 formed in the groove 27a. After that, it is cured by relatively low-temperature N-nealing.
- a lower electrode layer 34, a ferroelectric film 35, and an upper electrode layer 36 are sequentially formed.
- a Ti film having a thickness of, for example, about 20 nm and a Pt film having a thickness of about 150 nm are sequentially deposited on the interlayer insulating film 27 including the connection portion 33 by a sputtering method.
- a lower electrode layer 34 is formed as a laminated structure of films.
- the lower electrode layer 34 may be formed through the conductive barrier film.
- PZT PbZr Ti O 0 x x 1
- the ferroelectric film 35 is subjected to RTA treatment to crystallize the ferroelectric film 35.
- IrO which is a conductive oxide, is used as a material on the ferroelectric film 35 by reactive sputtering.
- the upper electrode layer 36 is deposited to a thickness of about 200 nm.
- the material of the lower electrode layer 34 instead of the laminated structure of Ti and Pt, the laminated structure of Ir and Pt, the laminated structure of IrO and Pt, and the laminated structure of Ir, IrO and Pt in order of the lower layer force. Lamination of layers
- uO SrRuO or other conductive oxides or a laminated structure thereof may be used.
- the surface of the interlayer insulating film 27 is flattened, the influence of the orientation of the W plug 22 'step' is blocked, and the surface has excellent orientation. .
- the surface of the connecting portion 33 inevitably has a slight step between the surface of the interlayer insulating film 27 whose orientation is low. Therefore, except for the part directly above the connecting part 33, the interlayer insulating film
- Each of the lower electrode layer 34, the ferroelectric film 35, and the upper electrode layer 36 deposited on the layer 27 has excellent orientation without taking over the orientation of the W plug 22 and the effect of the step.
- the ferroelectric film 35 can be formed so as to have excellent orientation and high ferroelectric properties except for the portion directly above the connection portion 33.
- a resist pattern 38 for processing the lower electrode layer 34, the ferroelectric film 35, and the upper electrode layer 36 is formed.
- an antireflection film 37 (which can be omitted) is formed on the upper electrode layer 36, and then a resist is formed on the antireflection film 37. Then, the resist is processed by lithography and a resist pattern 38 is formed.
- the upper electrode layer 36, the ferroelectric film 35, and the lower electrode layer 34 are processed using the resist pattern 38 to form a ferroelectric capacitor structure 30.
- the upper electrode layer 36, the ferroelectric film 35, and the lower electrode layer 34 are dry-etched using the resist pattern 38 as a mask.
- the antireflection film 37 is also etched.
- the lower electrode layer 34, the ferroelectric film 35, and the upper electrode layer 36 are obtained by patterning the ferroelectric film 40 obtained by patterning the ferroelectric film 35 in accordance with the resist pattern 38 by this dry etching.
- a ferroelectric capacitor structure 30 having a structure sandwiched between 41 and 41 is formed. Thereafter, the resist pattern 38 and the antireflection film 37 thereunder are removed.
- the resist pattern 38 In order to perform the single layer resist process, the resist pattern 38 needs to be formed relatively thick.
- the single-layer resist process is difficult, the upper electrode layer 36 and the ferroelectric film 35 are etched together with the first resist pattern, and then the lower electrode layer 34 is etched with the second resist pattern. It is also possible to execute a process or a three-layer resist process in which the upper electrode layer 36, the ferroelectric film 35, and the lower electrode layer 34 are sequentially etched with the first to third resist patterns.
- FIGS. 9A to 10C show how the processes of FIGS. 5A and 5B are performed using the hard mask method.
- a TiN film 91 and a silicon oxide film 92 are sequentially stacked on the upper electrode layer 36.
- the TiN film 91 is formed with a film thickness of 200 nm by sputtering, for example.
- the silicon oxide film 92 is formed as a high-density plasma (HDP) film by a CVD method using TEOS or a plasma CVD method with a film thickness of about 800 nm to about 1000 ⁇ m.
- the silicon oxide film 92 is formed using TEOS.
- FIGS. 9B to 10C only the lower electrode layer 34 and its upper layer portion are shown for convenience of illustration.
- a capacitor-shaped resist pattern 93 is formed. More specifically, after a resist is applied to the silicon oxide film 92, the resist is processed into a capacitor shape by lithography to form a resist pattern 93.
- the silicon oxide film 92 is dry-etched using the resist pattern 93 as a mask. By this dry etching, the silicon oxide film 92 is patterned into a capacitor shape following the resist pattern 93. When the silicon oxide film 92 is patterned, the resist pattern 93 is thinned by the etching.
- the TiN film 91 is dry-etched using the remaining resist pattern 93 and silicon oxide film 92 as a mask. By this dry etching, the TiN film 91 is patterned into a capacitor shape following the silicon oxide film 92.
- the resist pattern 93 is almost (or completely) lost by the etching, and the silicon oxide film 92 is thinned by the etching.
- the lower electrode layer 34, the ferroelectric film 35, and the upper electrode layer 36 are dry-etched using the remaining silicon oxide film 92 and TiN film 91 as a mask.
- the lower electrode layer 34, the ferroelectric film 35, and the upper electrode layer 36 are patterned into a capacitor shape following the TiN film 91, and the ferroelectric film 40 is formed between the lower electrode 39 and the upper electrode 41.
- a ferroelectric capacitor structure 30 having a sandwiched structure is formed.
- the silicon oxide film 92 is almost (or completely) lost by the etching.
- the lower electrode 39 is connected to the connection portion 33 and a portion including the peripheral region of the lower electrode 39, in this embodiment, the peripheral region.
- the peripheral area of the lower electrode 39 is an area in the vicinity of the peripheral edge on the inner side of the lower electrode 39. In other words, a portion corresponding to the lower surface of the lower electrode 39 and above the W plug 22 of the lower electrode 39. This is an area excluding the central area including.
- FIG. 5B shows a peripheral region 39a and a central region 39b of the lower electrode 39 as an example.
- the inside of the frame-shaped connection portion 33 is a portion having a surface with a highly flat surface and excellent orientation.
- the surface of the connecting portion 33 inevitably has a slight step between the surface of the interlayer insulating film 27 whose orientation is low. Therefore, in the lower electrode 39, the central region 39 b has excellent orientation without being affected by the surface of the W plug 22, except for the peripheral region 39 a that is the connection portion of the connection portion 33.
- the ferroelectric film 40 is excellent in the central region of the ferroelectric film 40 aligned with the central region 39b except for the peripheral region of the ferroelectric film 40 aligned with the peripheral region 39a. It has high orientation and high ferroelectricity. The ratio of the central region of the ferroelectric film 40 is large.
- the ferroelectric film 40 has a sufficiently excellent orientation and high ferroelectric characteristics as a whole.
- a hydrogen protective film 42 for preventing deterioration of characteristics due to hydrogen of the ferroelectric capacitor structure 30 is formed.
- a hydrogen protective film 42 is formed so as to cover the ferroelectric capacitor structure 30.
- the hydrogen protective film 42 is for suppressing the intrusion of hydrogen generated in the process after the formation of the ferroelectric capacitor structure 30 into the ferroelectric capacitor structure 30 and its lower layer structure.
- AlO AlO
- a film thickness of 50 nm to about 100 nm is formed by sputtering.
- FIG. 5C shows the state when the removal step is executed.
- an interlayer insulating film 43 is formed. Specifically, the interlayer insulating film 43 is formed so as to completely cover the ferroelectric capacitor structure 30 with the hydrogen protective film 42 interposed therebetween. As the interlayer insulating film 43, if the thickness of the ferroelectric capacitor structure 30 is about 800 nm, for example, a silicon oxide film is formed by CVD using TEOS so as to completely cover the ferroelectric capacitor structure 30. Deposits at about 1500nm.
- the surface layer of the interlayer insulating film 43 is formed so that the interlayer insulating film 43 remains about 300 nm to 400 nm in thickness. For example, it is removed by the CMP method. Thereby, the surface of the interlayer insulating film 43 is flattened.
- a resist pattern 45 for forming a via hole is formed in the interlayer insulating film 43.
- an antireflection film 44 (which can be omitted) is formed on the interlayer insulating film 43, and then a resist is formed on the antireflection film 44. Then, the resist is processed by lithography to form a resist pattern 45 having an opening 45a aligned with a predetermined position on the surface of the upper electrode 41.
- the interlayer insulating film 43 is processed using the resist pattern 45.
- the interlayer insulating film 43 and part of the hydrogen protective film 42 are dry-etched using the resist pattern 45 as a mask.
- the antireflection film 44 is also etched. Via holes 46 that expose a part of the surface of the upper electrode 41 are formed in the interlayer insulating film 43 and the hydrogen protective film 42 by following the openings 45a of the resist pattern 45 by this dry etching. Thereafter, the resist pattern 45 and the antireflection film 44 thereunder are removed.
- annealing treatment is performed to recover the damage received by the ferroelectric film 40 during various steps during and after the formation of the ferroelectric capacitor structure 30.
- annealing is performed for 60 minutes in an oxygen atmosphere of a treatment temperature of 500 ° C. and 20 liters of oxygen.
- this annealing treatment also causes the peripheral region force of the ferroelectric film 40 to be released from Pb and oxygen, and the Pb concentration and oxygen concentration in the peripheral region are reduced. . Due to this Pb detachment and oxygen detachment, in the peripheral region of the ferroelectric film 40, the ferroelectric characteristics inevitably deteriorate. [0069]
- the peripheral region in which deterioration of the ferroelectric characteristics in the ferroelectric film 40 is unavoidable is actively used, and the ferroelectric material is applied to the peripheral portion 39a of the lower electrode 39 as described above. A connecting portion 33 that inevitably deteriorates the ferroelectric properties of the film 40 is provided. With this configuration, it is possible to form the ferroelectric film 40 so as to have as excellent orientation and high ferroelectric characteristics as possible.
- a W plug 48 connected to the upper electrode 41 is formed.
- a Ti film (thickness of about 30 nm) and a TiN film (thickness of about 20 nm) are sequentially deposited on the interlayer insulating film 43 by a sputtering method so as to cover the wall surface of the via hole 46 to form a base film.
- (Glue film) 47 is formed.
- a tungsten (W) film is formed by the CVD method so as to fill the via hole 46 through the gnoley film 47.
- the W film and the glue film 47 are polished by CMP using the interlayer insulating film 43 as a stopper, and a W plug 48 is formed in which the inside of the via hole 46 is carried by W via the glue film 47.
- the W plug 22 and the W plug 48 are formed on a substantially straight line vertically with the conductive film 24, the interlayer insulating film 27, and the ferroelectric capacitor structure 30 interposed therebetween. Yes. With this configuration, the area occupied by the memory cell portion including the ferroelectric capacitor structure 30 can be suppressed as small as possible.
- a multilayer wiring structure 50 is formed.
- the first wiring 51 connected to the W plug 48 is formed.
- TiN is deposited to a thickness of about 150 nm on the interlayer insulating film 43 including the W plug 48 by sputtering to form the barrier layer 51a.
- an Al-Cu alloy for example, is deposited on the silicon layer 51a to a thickness of about 550 nm by a sputtering method to form a wiring layer of 5 lb.
- TiN is deposited to a thickness of about 150 nm on the wiring layer 51b by sputtering to form a barrier layer 51c.
- the barrier layer 51c, the wiring layer 51b, and the barrier layer 51a are patterned into a desired wiring shape by lithography and subsequent dry etching, whereby the wiring layer 51b is sandwiched between the barrier layers 51a and 51c. 1 Wiring 51 is formed.
- an interlayer insulating film 52 that covers the first wiring 51 is formed.
- the interlayer insulation film As 52 for example, a silicon oxide film is deposited to a thickness of about 2500 nm by a CVD method using TEOS. Thereafter, the surface of the interlayer insulating film 52 is flattened by, eg, CMP.
- the interlayer insulating film 52 is processed by lithography and subsequent dry etching until a part of the surface of the nore layer 51c is exposed, thereby forming a via hole 52a. Then, for example, a Ti film (film thickness of about 30 nm) and a TiN film (film thickness of about 20 nm) are sequentially deposited on the interlayer insulating film 52 by a sputtering method so as to cover the wall surface of the via hole 52a. Membrane) 53 is formed.
- a tundane (W) film is formed by the CVD method so as to carry the via hole 52a through the glue film 53.
- the W film and the glue film 53 are polished by CMP using the interlayer insulating film 52 as a stopper to form a W plug 54 that fills the via hole 52 with W via the glue film 53.
- TiN is deposited to a thickness of about 150 nm on the interlayer insulating film 52 including the W plug 54 by sputtering to form the barrier layer 55a.
- an Al-Cu alloy for example, is deposited on the silicon layer 55a by a sputtering method to a film thickness of about 550 nm, thereby forming the wiring layer 55b.
- TiN is deposited to a thickness of about 150 nm on the wiring layer 55b by sputtering to form the barrier layer 55c.
- the barrier layer 55c, the wiring layer 55b, and the barrier layer 55a are patterned into a desired wiring shape by lithography and subsequent dry etching, whereby the wiring layer 55b is sandwiched between the barrier layers 55a and 55c.
- Wiring 55 is formed
- the W plug and the wiring are further repeatedly formed, for example, the 20th wiring is sequentially formed, and the multilayer wiring structure 50 is formed.
- the second wiring 55 is shown for convenience of illustration.
- A1 is exemplified as a material of each wiring layer in the multilayer wiring structure 50.
- Cu may be used by a so-called damascene method instead of sputtering A1.
- the first wiring 51 is taken as an example, the interlayer insulating film 52 is first formed, and its surface is displayed. After the surface is flattened, a groove having a desired wiring shape is formed in the interlayer insulating film 52 so that the surface of the W plug 48 is exposed on the bottom surface.
- Ta for example, is deposited on the groove wall by MOCVD, for example, to form a noor film, and then a seed film is formed on the barrier film, and then Cu is deposited so as to fill the groove by the metch method. . Thereafter, using the interlayer insulating film 52 as a stopper, the Cu surface layer (and the plating seed film) is removed by CMP to form a first wiring 51 that fills the trench with Cu.
- the FeR AM of this embodiment is completed through a process of forming a protective film, a pad electrode, and the like (not shown).
- the ferroelectric capacitor structure 30 employs a stack type capacitor structure to reduce the occupied area of the capacitor while ensuring a relatively large capacitance.
- FeRAM is realized with high reliability that can achieve high orientation of the ferroelectric film 40 equivalent to or better than that of the planar capacitor structure and obtain excellent ferroelectric characteristics.
- connection portion formed on the conductive film 24 is formed in a plug shape.
- FIGS 11A to 11D are schematic cross-sectional views showing the main steps in the FeRAM manufacturing method according to Modification 1.
- the interlayer insulating film is formed on the interlayer insulating film 21 so as to embed the conductive film 24 above the silicon semiconductor substrate 10 through the steps of FIGS. 3A to 3F. Form 2-7.
- a resist pattern 61 for forming an opening in the interlayer insulating film 27 is formed.
- the antireflection film 28 (optional) is formed on the interlayer insulating film 27 and then reflected.
- a resist is applied and formed on the prevention film 28.
- the resist is processed by lithography to form a resist pattern 61 having four openings 61 a aligned with the positions of the four corners of the peripheral region of the conductive film 24.
- the interlayer insulating film 27 is processed using the resist pattern 61.
- the interlayer insulating film 27 is dry etched using the resist pattern 61 as a mask.
- the antireflection film 28 is also etched.
- each opening 27 b that exposes a part of the end portion of the conductive film 24 is formed following this opening 61 a of the resist pattern 61 by this dry etching.
- FIG. 12A shows a plan view of each opening 27b formed in the interlayer insulating film 27.
- the opening 27b has a relatively simple shape, it is easy to form the hole 27b.
- the resist pattern 61 and the antireflection film 28 underneath are removed.
- a conductive material 32 is deposited so as to enclose each of the openings 27b.
- TiN is deposited to a thickness of about 20 nm on the interlayer insulating film 27 by a sputtering method so as to cover the wall surface of each opening 27b, thereby forming a base film (Gnore film) 31.
- a conductive material 32 is deposited so as to embed the groove 27a via the gnoley film 31 by the CVD method.
- tungsten (W) is formed to a thickness of about 400 nm as the conductive material 32.
- connection portion 63 is formed.
- each of the plug-shaped connecting portions is polished by CMP using the interlayer insulating film 27 as a stopper to polish the conductive material 32 and the glue film 31 and filling each opening 27b with the conductive material 32 via the glue film 31. 62 is formed.
- FIG. 12B shows a state in plan view of each connecting portion 62 formed in each opening 27b.
- the interlayer insulating film 27 is dehydrated by performing a curing process by annealing at a relatively low temperature.
- annealing at a high temperature oxidizes the surface of W, which is conductive material 32. From the viewpoint of preventing this, annealing is performed at a relatively low temperature, for example, N gas at 350 ° C for 2 minutes. .
- each connection portion 62 may be formed at two opposing corner positions in the peripheral region of the conductive film 24. Subsequently, similarly to the first embodiment, the ferroelectric capacitor structure 30 is formed through the processes of FIGS. 4D, 5A, and 5B.
- the lower electrode 39 is connected to a portion including the connecting portion 62 and the peripheral region 39 a of the lower electrode 39, in this embodiment, the peripheral region 39 a.
- the central region 39 b has excellent orientation without being affected by the surface of the W plug 22.
- the ferroelectric film 40 is excellent in the central region of the ferroelectric film 40 aligned with the central region 39b except for the peripheral region of the ferroelectric film 40 aligned with the peripheral region 39a. It has excellent orientation and high ferroelectric properties.
- the ratio of the central region of the ferroelectric film 40 is large, and the ferroelectric film 40 has a sufficiently excellent orientation and high ferroelectric characteristics as a whole.
- the FeRAM of this example is completed through the steps of FIGS. 5C, 5D, 6A, 6B, 7A, and 7B.
- the ferroelectric capacitor structure 30 employs a stacked capacitor structure to reduce the occupied area of the capacitor while securing a relatively large capacitance.
- a highly reliable FeRAM that achieves the high orientation of the ferroelectric film 40 equivalent to or higher than that in the case of adopting the planar type capacitor structure and can obtain excellent ferroelectric characteristics is realized.
- 13A and 13B are schematic cross-sectional views showing main steps in the FeRAM manufacturing method according to Modification 2.
- a frame-like groove 27a is formed in the interlayer insulating film 27 above the silicon semiconductor substrate 10 through the steps of FIGS. 3A to 3G and FIG. 4A. .
- a conductive material 32 is deposited so as to receive the groove 27a.
- TiN for example, is deposited to a thickness of about 20 nm on the interlayer insulating film 27 so as to cover the wall surface of the groove 27a, thereby forming a base film (Gnore film) 31.
- a conductive material 32 is deposited so as to fill the groove 27a through the glue film 31 by MOCVD.
- the conductive material 32 the noble metal iridium (Ir) is formed to a thickness of about 300 nm, or TiAIN, which is a conductive nitride film, is formed to a thickness of about 300 nm. Further, there is room for applying platinum (Pt) as the conductive material 32.
- connection part 63 is formed.
- the conductive material 32 and the glue film 31 are polished by CMP using the interlayer insulating film 27 as a stopper, and the groove-shaped connection part 63 is held in the groove 27a by the conductive material 32 via the glue film 31.
- the interlayer insulating film 27 is dehydrated by being cured by annealing.
- the annealing process can be performed at a high temperature. That is, when Ir is used for the conductive material 32, IrO remains conductive even if the surface layer of the connection 63 is oxidized to produce IrO.
- the connecting portion 63 maintains good conductivity. Further, when TiAIN is used for the conductive material 32, TiAIN is a conductive nitride excellent in oxidation resistance, so that the connection part 63 maintains good conductivity.
- the annealing process is performed at a temperature of 400 ° C. for 2 minutes using, for example, N gas having a relatively high temperature.
- the FeRAM of this example is completed through the respective steps of FIGS. 4D, 5C, 5D, 6A, 6B, 7A, and 7B.
- the ferroelectric capacitor structure 30 employs a stack type capacitor structure to reduce the occupied area of the capacitor while securing a relatively large capacity.
- a highly reliable FeRAM that achieves the high orientation of the ferroelectric film 40 equivalent to or higher than that in the case of adopting the planar type capacitor structure and can obtain excellent ferroelectric characteristics is realized.
- 14A and 14B are schematic cross-sectional views showing the main steps in the FeRAM manufacturing method according to Modification 3.
- a frame-like groove 27a is formed in the interlayer insulating film 27 above the silicon semiconductor substrate 10 through the steps of FIGS. 3A to 3G and FIG. 4A. .
- a conductive material 32 is deposited so as to receive the groove 27a.
- a Ta film film thickness of about 15 nm
- a plating seed film (not shown) on the gnoley film 64
- Cu65 is deposited to a thickness of about 600 nm so as to be embedded in the groove 27a by the plating method.
- connection portion 66 is formed.
- the conductive material 32 and the glue film 64 are polished by CMP using the interlayer insulating film 27 as a stopper, and a frame-shaped connection portion 66 is held in the groove 27a by the conductive material 32 via the glue film 64.
- the interlayer insulating film 27 is dehydrated by being cured by a relatively low temperature annealing process.
- annealing at a high temperature oxidizes the surface of Cu, which is the conductive material 32. From the viewpoint of preventing this, the temperature is relatively low.
- N gas is used for 60 seconds at 350 ° C, or NH gas is used. At 350 ° C for 60 seconds
- the ferroelectric capacitor structure 30 is formed through the steps of FIGS. 4D, 5A, and 5B.
- the lower electrode 39 is connected to a portion including the connecting portion 66 and the peripheral region 39a of the lower electrode 39, in this embodiment, the peripheral region 39a.
- the MEKI method can fill the groove 27a with good filling properties without generating a seam or the like, and Cu is relatively soft and close to the polishing speed of the interlayer insulating film 27. Therefore, a step is hardly generated between the interlayer insulating film 27. Therefore, by using Cu, even when the groove 27a is fine, it can be sufficiently filled.
- the central region 39 b has excellent orientation without being affected by the surface of the W plug 22.
- the ferroelectric film 40 is excellent in the central region of the ferroelectric film 40 aligned with the central region 39b except for the peripheral region of the ferroelectric film 40 aligned with the peripheral region 39a. It has excellent orientation and high ferroelectric properties.
- the ratio of the central region of the ferroelectric film 40 is large, and the ferroelectric film 40 has a sufficiently excellent orientation and high ferroelectric characteristics as a whole.
- the ferroelectric capacitor structure 30 adopts the stack type capacitor structure to reduce the occupied area of the capacitor while securing a relatively large capacity.
- a highly reliable FeRAM that achieves the same or better orientation of the ferroelectric film 40 as that of a planar capacitor structure and that can achieve excellent ferroelectric properties is realized.
- FIGS. 15A to 19 are schematic cross-sectional views showing main steps in the FeRAM manufacturing method according to the fourth modification.
- the MOS transistor 20 functioning as a selection transistor is formed on the silicon semiconductor substrate 10 through the process of FIG. 3A.
- an interlayer insulating film 21 covering the MOS transistor 20 is formed.
- a silicon oxide film is deposited to a thickness of about 600 nm so as to cover the MOS transistor 20 by, for example, a CVD method using TEOS, and an interlayer insulating film 21 is formed. Thereafter, the surface of the interlayer insulating film 21 is planarized by, eg, CMP, and then the planarized surface of the interlayer insulating film 21 is annealed in an N atmosphere to nitride the surface.
- a hydrogen protective film 71 for preventing characteristic deterioration due to hydrogen of the ferroelectric capacitor structure 30 formed in the subsequent steps is formed.
- a hydrogen protective film 71 is formed on the interlayer insulating film 21.
- the hydrogen protective film 71 is, for example, for suppressing the intrusion of hydrogen generated from the interlayer insulating film 21 and the like into the ferroelectric capacitor structure 30 in the subsequent processes.
- alumina (AIO) or SiO For example, sputtering is performed using N, SiN, or the like as a material.
- the film thickness is about 20 nm to 50 nm.
- SiON the film thickness is about lOOnm.
- an interlayer insulating film 72 is formed on the hydrogen protective film 71.
- a silicon oxide film is deposited on the hydrogen protective film 71 to a thickness of about 50 nm by a CVD method using TEOS, and an interlayer insulating film 72 is formed. Then, interlayer insulation film 72 The surface of is annealed in an N atmosphere to nitride the surface.
- a resist pattern 74 for processing the contact hole is formed.
- an antireflection film 73 (which can be omitted) is formed on the interlayer insulating film 72, and then a resist is formed on the antireflection film 73 by coating. Then, the resist is processed by lithography to form a resist pattern 74 having an opening 74a.
- the interlayer insulating film 72, the hydrogen protective film 71 and the interlayer insulating film 21 are processed using the resist pattern 74.
- the interlayer insulating film 72, the hydrogen protective film 71, and the interlayer insulating film 21 are dry etched.
- the interlayer insulating film 72 patterned by the resist pattern 74 functions as a hard mask when the hydrogen protective film 71 and the interlayer insulating film 21 are etched.
- the antireflection film 73 is also etched.
- a contact hole that exposes part of the surface of the source / drain region 18 is imitated by the dry etching to follow the opening 74a of the resist pattern 74. 70 is formed. Thereafter, the resist pattern 74 and the antireflection film 73 thereunder are removed.
- a W plug 22 serving as a Balta contact is formed.
- a Ti film (film thickness of about 30 nm) and a TiN film (film thickness of about 20 nm) are sequentially deposited on the interlayer insulating film 2 by a sputtering method so as to cover the wall surface of the contact hole 70.
- a base film (glue film) 23 is formed.
- a tungsten (W) film is formed by the CVD method so that the contact hole 70 is carried through the glue film 23. Then, the W film and the glue film 23 are polished by, for example, CMP using the interlayer insulating film 21 as a stopper, and a W plug 22 is formed in which the inside of the contact hole 70 is trapped by W via the glue film 23.
- FIGS. 3C to 3G, FIG. 4A, and FIG. 4B are performed to fill the groove 27a of the interlayer insulating film 27 as shown in FIG. 16A.
- a connection portion 33 connected to the conductive film 24 is formed.
- connection portion 33 is exposed from the surface of the interlayer insulating film 27. Make it.
- the entire surface of the interlayer insulating film 27 is anisotropically etched (etched back) by utilizing the difference in etching rate between the interlayer insulating film 27 and the connection portion 33.
- the surface layer of the interlayer insulating film 27 is etched so that the upper part of the connection part 33 is exposed by about 30 nm to 50 nm.
- a hydrogen protective film 75 for preventing characteristic deterioration due to hydrogen of the ferroelectric capacitor structure 30 formed in the subsequent steps is formed.
- a hydrogen protective film 75 is formed on the interlayer insulating film 27 so as to cover the exposed upper portion of the connection portion 33.
- the hydrogen protective film 75 is, for example, for preventing hydrogen generated from the interlayer insulating film 21 and the like in the subsequent processes together with the hydrogen protective film 71 from entering the ferroelectric capacitor structure 30, for example, AlO.TiO. Is formed to a thickness of about lOOnm.
- the surface layer of the hydrogen protective film 75 is polished to expose the surface of the connection portion 33.
- the surface layer of the hydrogen protective film 75 is polished by the CMP method using the connection portion 33 as a stopper. As a result, the surface of the hydrogen protective film 75 is exposed so that the surface of the connecting portion 33 is exposed.
- an interlayer insulating film 43 is formed so as to completely cover the ferroelectric capacitor structure 30 with the hydrogen protective film 42 interposed therebetween. Thereafter, the surface of the interlayer insulating film 43 is flattened by, for example, CMP, and then the surface of the flattened interlayer insulating film 43 is annealed in an N atmosphere to nitride the surface.
- a hydrogen protective film 76 for preventing characteristic deterioration due to hydrogen of the ferroelectric capacitor structure 30 is formed.
- a hydrogen protective film 76 is formed on the interlayer insulating film 43.
- the hydrogen protective film 76 is for suppressing the intrusion of hydrogen generated in the process after the formation of the ferroelectric capacitor structure 30 into the ferroelectric capacitor structure 30 and its underlying structure.
- AlO) or SiON, SiN, etc. are used as materials, for example, by sputtering.
- the film thickness is about 20 nm to 50 nm, and in the case of SiON, the film thickness is about lOOnm.
- an interlayer insulating film 77 is formed on the hydrogen protective film 76.
- a W plug 48 that fills the via hole 78 with W through the glue film 47 is formed.
- the ferroelectric capacitor structure 30 is caused by hydrogen.
- a hydrogen protective film 79 is formed to prevent the deterioration of characteristics.
- a hydrogen protective film 79 is formed on the interlayer insulating film 52.
- the hydrogen protective film 79 is for suppressing the intrusion of hydrogen generated by the process after the formation of the ferroelectric capacitor structure 30 into the ferroelectric capacitor structure 30 and its lower layer structure.
- AlO) or SiON, SiN or the like is used as a material, for example, by sputtering.
- the film thickness is about 20 nm to 50 nm, and in the case of SiON, the film thickness is about lOOnm.
- an interlayer insulating film 81 is formed on the hydrogen protective film 79.
- the formation of the W plug and the wiring is repeated repeatedly until the 20th wiring, for example. Then, the multilayer wiring structure 50 is formed.
- the force S has been shown only in the vicinity of the memory cell portion of FeRAM, and in this modification, hydrogen protective films 42, 71, 75, 76, 78 are formed on the entire surface of FeRAM. Is preferred.
- the basic protection module 42, 71, 75, 76, and 78 are provided with a logic section and a lead electrode constituting a peripheral circuit path such as a memory sensor and a C MOS transistor.
- a pad portion and a scribe portion for cutting out individual semiconductor chips from the silicon semiconductor substrate 10 are formed on the entire surface of the FeRAM.
- This configuration can prevent hydrogen from entering the ferroelectric capacitor structure to the maximum extent.
- only the respective regions of the mouthpiece portion, the pad portion, and the scribe portion are shown, and illustration of the transistors in the logic portion, the lead electrodes in the pad portion, and the like is omitted.
- the FeRAM of this embodiment is completed through a process of forming a protective film, a pad electrode, and the like (not shown).
- the ferroelectric capacitor structure 30 has the stack type key. Although the capacitor structure is used to reduce the area occupied by the capacitor while securing a relatively large capacitance, it is possible to obtain a high orientation of the ferroelectric film 40 equivalent to or higher than that of the planar capacitor structure. it can. By reducing the penetration of hydrogen into the ferroelectric film 40 as much as possible, a highly reliable FeRAM that makes it possible to obtain excellent ferroelectric properties is realized.
- 20A to 21D are schematic cross-sectional views showing main steps in the FeRAM manufacturing method according to Modification 5.
- the MOS transistor 20 is formed on the silicon semiconductor substrate 10 through the process of FIG. 3A.
- an interlayer insulating film 21 and a stopper film 94 covering the MOS transistor 20 are sequentially formed.
- an interlayer insulating film 21 is formed so as to cover the MOS transistor 20.
- a silicon oxide film is deposited to a thickness of about 600 nm by, for example, a CVD method using TEOS.
- the surface of the interlayer insulating film 21 is planarized by, eg, CMP.
- a stopper film 94 is formed on the interlayer insulating film 21 whose surface is planarized.
- SiON is deposited to a thickness of about 50 nm.
- a W plug 22 serving as a Balta contact is formed.
- the stopper film 94, the interlayer insulating film 21 and the protective film 19 are processed by lithography and subsequent dry etching until a part of the surface of the source / drain region 18 is exposed, for example, about 0.
- a contact hole 21a having a diameter of 25 zm is formed.
- a Ti film (film thickness of about 30 nm) and a TiN film (film thickness of about 20 nm) are sequentially deposited on the interlayer insulating film 2 by a sputtering method so as to cover the wall surface of the contact hole 21a.
- a base film (glu film) 23 is formed.
- a tungsten (W) film is formed by the CVD method so as to fill the contact hole 21a via the glue film 23.
- the stopper film 94 is polished by, for example, CMP.
- the W film and the glue film 23 are polished as one, and a W plug 22 is formed that fills the contact hole 21a with W through the glue film 23.
- an interlayer insulating film 95 is formed on the stopper film 94 so as to cover the W plug 22.
- the interlayer insulating film 95 for example, a silicon oxide film is deposited to a thickness of about 100 nm to 200 nm by the CVD method.
- a resist pattern 26 for processing the interlayer insulating film 95 is formed.
- an antireflection film (not shown: can be omitted) is formed on the interlayer insulating film 95, and then a resist is formed on the antireflection film. Then, a resist is added by lithography to form a resist pattern 96 having an opening 96a.
- the interlayer insulating film 95 is processed using the resist pattern 96 to form an opening 95a.
- the interlayer insulating film 95 is dry-etched using the resist pattern 96 as a mask and the stopper film 94 as an etching stopper.
- the antireflection film is also etched.
- a rectangular opening 95a exposing a part of the surface of the stopper film 94 and the surface of the W plug 22 along the opening 96a of the resist pattern 96 is formed in the interlayer insulating film 95. Thereafter, the resist pattern 96 and the underlying antireflection film are removed.
- a conductive film 97 is formed.
- a conductive film 97 is formed by laminating a W film on the interlayer insulating film 95 via a base film (a single film) so as to cover the inner wall surface of the opening 95a.
- TiN is formed to a thickness of about 20 nm.
- W film is formed to a thickness of about 80 nm.
- an interlayer insulating film 98 is formed on the conductive film 97 so as to embed the opening 95a through the conductive film 97.
- the interlayer insulating film 98 for example, a silicon oxide film is deposited to a thickness of about 1 OOOnm by a CVD method.
- connection portion 99 is formed.
- the interlayer insulating film 98 and the conductive film 97 are polished by CMP using the interlayer insulating film 95 as a stopper. At this time, the conductive material remaining only in the portion covering the inner wall surface of the opening 95a.
- the connection part 99 is constituted by the membrane 97.
- the interlayer insulating film 98 remains so as to hold the connection portion 99 in the opening 95a. After that, it is cured by relatively low-temperature N-nealing.
- the lower electrode 39 is connected to a portion including the connecting portion 99 and the peripheral region 39a of the lower electrode 39, in this embodiment, the peripheral region 39a.
- the central region 39b has excellent orientation without being affected by the surface of the W plug 22.
- the ferroelectric film 40 is excellent in the central region of the ferroelectric film 40 aligned with the central region 39b except for the peripheral region of the ferroelectric film 40 aligned with the peripheral region 39a. It has excellent orientation and high ferroelectric properties.
- the ratio of the central region of the ferroelectric film 40 is large, and the ferroelectric film 40 has a sufficiently excellent orientation, high level, and ferroelectric characteristics as a whole.
- the size of the groove 27a is very small. It may not be easy in general.
- the size of the connection part with the lower electrode 39 of the connection part 99 without forming a groove in the interlayer insulating film can be defined by the film thickness of the conductive film 97 (in this example, 20 nm + 80 nm Therefore, it is possible to easily and reliably form the connection portion 99 having a connection portion of a very small size.
- the ferroelectric capacitor structure 30 employs a stack type capacitor structure to reduce the occupied area of the capacitor while securing a relatively large capacity.
- a highly reliable FeRAM that achieves the high orientation of the ferroelectric film 40 equivalent to or higher than that in the case of adopting the planar type capacitor structure and can obtain excellent ferroelectric characteristics is realized.
- the structure of FeRAM and the method for manufacturing the same are disclosed, but differ in the aspect of the connection portion. Note that the same components as those disclosed in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
- 22A to 22D are schematic cross-sectional views showing main steps in the FeRAM manufacturing method according to the second embodiment.
- the interlayer insulating film is formed on the interlayer insulating film 21 so as to embed the conductive film 24 above the silicon semiconductor substrate 10 through the steps of FIGS. 3A to 3F. Form 2-7.
- a resist pattern 82 for forming an opening in the interlayer insulating film 27 is formed.
- an antireflection film 28 (which can be omitted) is formed on the interlayer insulating film 27 and then a resist is formed on the antireflection film 28. Then, the resist is processed by lithography to form a resist pattern 82 having four openings 82 a aligned with the positions of the four corners of the peripheral region of the conductive film 24.
- each opening 82a of the resist pattern 82 corresponding to the difficulty in forming the connection portion in the peripheral region of the lower electrode due to further miniaturization of the ferroelectric capacitor structure
- the resist pattern 61 in the first modification of the first embodiment is formed in a size larger than each opening 61a.
- the interlayer insulating film 27 is processed using the resist pattern 82.
- the interlayer insulating film 27 is dry etched using the resist pattern 82 as a mask.
- the antireflection film 28 is also etched.
- each opening 27 c that exposes a part of the end of the conductive film 24 is formed following this opening 82 a of the resist pattern 82 by this dry etching.
- a plan view of each opening 27c formed in the interlayer insulating film 27 is shown in FIG. 23A. Since each opening 27c is larger in size than the opening 27b in Modification 1 of the first embodiment, each opening 27c is relatively easy even for a further miniaturized ferroelectric capacitor structure. 27c can be formed. Of this dry etching Thereafter, the resist pattern 82 and the antireflection film 28 under the resist pattern 82 are removed.
- a conductive material 32 is deposited so as to fill each opening 27c.
- TiN is deposited to a thickness of about 20 nm on the interlayer insulating film 27 by a sputtering method so as to cover the wall surface of each opening 27c to form a base film (Gnore film) 31.
- a conductive material 32 is deposited so as to fill each opening 27c through the glue film 31 by MOCVD.
- the conductive material 32 the noble metal iridium (Ir) is formed to a film thickness of about 400 nm to 6 OO nm, or TiAIN which is a conductive nitride film is formed to a film thickness of about 400 nm to 600 nm.
- platinum (Pt) as the conductive material 32 (since the hole diameter is large, it is formed a little more).
- connection portion 83 is formed.
- FIG. 23B shows a plan view of the connecting portion 83 formed in each opening 27c.
- the interlayer insulating film 27 is dehydrated by performing a curing process by annealing.
- the annealing process can be performed at a high temperature. That is, when Ir is used for the conductive material 32, IrO remains conductive even if the surface layer of the connection portion 83 is oxidized to produce IrO.
- the connecting portion 83 maintains good conductivity. Further, when TiAIN is used for the conductive material 32, TiAIN is a conductive nitride excellent in oxidation resistance, so that the connection part 83 maintains good conductivity.
- the annealing process is performed at a temperature of 400 ° C. for 2 minutes using, for example, N gas having a relatively high temperature.
- the ferroelectric capacitor structure 30 is formed through the steps of FIGS. 4D, 5A, and 5B.
- the lower electrode 39 is a portion including the connecting portion 83 and the peripheral region 39a of the lower electrode 39, and in this embodiment, the surface of the connecting portion 83 is relatively wide.
- the connection is made so as to extend inside and outside the lower electrode 39 including a part of 39a (that is, a part of the connecting part 83 protrudes from the lower electrode 39).
- the connection The central region 39b has excellent orientation without being affected by the surface of the W plug 22, except for the peripheral region 39a, which is the connecting portion of 83.
- the ferroelectric film 40 is excellent in the central region of the ferroelectric film 40 aligned with the central region 39b except for the peripheral region of the ferroelectric film 40 aligned with the peripheral region 39a. It has excellent orientation and high ferroelectric properties. The ratio of the central region of the ferroelectric film 40 is large. The ferroelectric film 40 as a whole has a sufficiently excellent orientation and high ferroelectric characteristics.
- the connecting portion 83 is formed so as to extend inside and outside the lower electrode 39 including a part of the peripheral region 39a where the size of the connecting portion 83 is relatively large, A large positioning margin can be obtained. That is, when patterning the ferroelectric capacitor structure 30 including the lower electrode 39, it is ideal that the lower electrode 39 and each connection portion 83 are connected as shown in FIG. 24A. In this case, an equal connection state is realized for the four connection portions 83 so as to extend inside and outside the lower electrode 39 including a part of the peripheral region 39a.
- FIG. 24B even if a slight shift occurs in the formation position of the lower electrode 39, for example, in the direction of arrow A, the lower electrode 39 is stably connected to the connection portion 83 without causing a connection failure. Is done.
- the via hole 46 is formed in the interlayer insulating film 43 and the hydrogen protective film 42 through the respective steps of FIG. 5C, FIG. 6A, and FIG. Annealing is performed to recover the damage received by the ferroelectric film 40 during the formation of the capacitor structure 30 and after the formation.
- connection portion 83 is formed so that a part thereof protrudes from the lower electrode 39, there is a problem if the conductive material 32 of the connection portion 83 loses conductivity due to oxidation.
- IrO is a conductive oxide and TiAIN is excellent in oxidation resistance.
- connection portion 83 Since the conductive nitride is formed, deterioration of the electrical connection of the connection portion 83 is suppressed. Therefore, it is possible to execute the annealing process without worrying about deterioration of the electrical connection of the connecting portion 83.
- each connection portion 83 is formed at two opposing corner positions in the peripheral region of the conductive film 24. Also good. In this case, each connection part 83 can be formed in a slightly larger size than each connection part 83 in FIG. 22A, and the connectivity with the lower electrode 39 of the connection part 83 can be improved.
- the frame-shaped connection portion is formed so as to extend inside and outside the lower electrode 39 including a part of the peripheral region 39a. It is also possible to make it.
- the ferroelectric capacitor structure 30 employs a stack type capacitor structure, and the area occupied by the capacitor can be reduced while securing a relatively large capacitance.
- Ferroelectrics equivalent to or better than those using a planar capacitor structure High reliability of FeRAM that enables easy acquisition of high orientation of film 40 and excellent ferroelectric properties is realized. To do.
- the planar capacitor structure is employed. This realizes a highly reliable FeRAM that realizes the orientation of the ferroelectric film 40 that is equal to or better than the above, and that can obtain excellent ferroelectric properties.
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Abstract
Description
Claims
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CN2005800500764A CN101199053B (zh) | 2005-06-09 | 2005-06-09 | 半导体器件及其制造方法 |
JP2007519995A JP4935672B2 (ja) | 2005-06-09 | 2005-06-09 | 半導体装置及びその製造方法 |
KR1020077027697A KR100949108B1 (ko) | 2005-06-09 | 2005-06-09 | 반도체 장치 및 그 제조 방법 |
PCT/JP2005/010554 WO2006131968A1 (ja) | 2005-06-09 | 2005-06-09 | 半導体装置及びその製造方法 |
US11/952,387 US7629636B2 (en) | 2005-06-09 | 2007-12-07 | Semiconductor device and manufacturing method thereof |
US12/608,439 US7820456B2 (en) | 2005-06-09 | 2009-10-29 | Semiconductor device and manufacturing method thereof |
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JP2007201042A (ja) * | 2006-01-25 | 2007-08-09 | Seiko Epson Corp | 半導体装置 |
JP2009054814A (ja) * | 2007-08-28 | 2009-03-12 | National Institute For Materials Science | 電子素子 |
US8445913B2 (en) * | 2007-10-30 | 2013-05-21 | Spansion Llc | Metal-insulator-metal (MIM) device and method of formation thereof |
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US7857948B2 (en) | 2006-07-19 | 2010-12-28 | Oerlikon Trading Ag, Trubbach | Method for manufacturing poorly conductive layers |
JP4845937B2 (ja) * | 2008-07-24 | 2011-12-28 | 株式会社東芝 | スピンmosfetおよびこのスピンmosfetを用いたリコンフィギュラブル論理回路 |
JP2012039004A (ja) * | 2010-08-10 | 2012-02-23 | Sony Corp | 光電変換素子およびその製造方法 |
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JP2003068990A (ja) * | 2001-08-23 | 2003-03-07 | Sony Corp | 強誘電体型不揮発性半導体メモリ及びその製造方法 |
JP2004193175A (ja) * | 2002-12-06 | 2004-07-08 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2005072474A (ja) * | 2003-08-27 | 2005-03-17 | Seiko Epson Corp | キャパシタとその製造方法、及び半導体装置 |
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JP3929513B2 (ja) | 1995-07-07 | 2007-06-13 | ローム株式会社 | 誘電体キャパシタおよびその製造方法 |
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JP2002033459A (ja) | 2000-07-14 | 2002-01-31 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP4825373B2 (ja) * | 2001-08-14 | 2011-11-30 | ローム株式会社 | 強誘電体薄膜の製造方法およびこれを用いた強誘電体メモリの製造方法 |
US6773929B2 (en) * | 2001-09-14 | 2004-08-10 | Hynix Semiconductor Inc. | Ferroelectric memory device and method for manufacturing the same |
US6815223B2 (en) * | 2002-11-22 | 2004-11-09 | Symetrix Corporation | Low thermal budget fabrication of ferroelectric memory using RTP |
US6855565B2 (en) * | 2002-06-25 | 2005-02-15 | Kabushiki Kaisha Toshiba | Semiconductor device having ferroelectric film and manufacturing method thereof |
TWI229935B (en) * | 2002-11-13 | 2005-03-21 | Matsushita Electric Ind Co Ltd | Semiconductor device and method for fabricating the same |
KR100578212B1 (ko) * | 2003-06-30 | 2006-05-11 | 주식회사 하이닉스반도체 | 엠티피 구조의 강유전체 캐패시터 및 그 제조 방법 |
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JP2003068990A (ja) * | 2001-08-23 | 2003-03-07 | Sony Corp | 強誘電体型不揮発性半導体メモリ及びその製造方法 |
JP2004193175A (ja) * | 2002-12-06 | 2004-07-08 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2005072474A (ja) * | 2003-08-27 | 2005-03-17 | Seiko Epson Corp | キャパシタとその製造方法、及び半導体装置 |
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JP2007201042A (ja) * | 2006-01-25 | 2007-08-09 | Seiko Epson Corp | 半導体装置 |
JP2009054814A (ja) * | 2007-08-28 | 2009-03-12 | National Institute For Materials Science | 電子素子 |
US8445913B2 (en) * | 2007-10-30 | 2013-05-21 | Spansion Llc | Metal-insulator-metal (MIM) device and method of formation thereof |
US20130237030A1 (en) * | 2007-10-30 | 2013-09-12 | Spansion Llc | Metal-insulator-metal (mim) device and method of formation thereof |
US8828837B2 (en) * | 2007-10-30 | 2014-09-09 | Spansion Llc | Metal-insulator-metal (MIM) device and method of formation thereof |
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US7629636B2 (en) | 2009-12-08 |
JP4935672B2 (ja) | 2012-05-23 |
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CN101199053B (zh) | 2011-11-02 |
US20080128858A1 (en) | 2008-06-05 |
JPWO2006131968A1 (ja) | 2009-01-08 |
US20100047931A1 (en) | 2010-02-25 |
KR100949108B1 (ko) | 2010-03-22 |
US7820456B2 (en) | 2010-10-26 |
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