WO2006129341A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- WO2006129341A1 WO2006129341A1 PCT/JP2005/009878 JP2005009878W WO2006129341A1 WO 2006129341 A1 WO2006129341 A1 WO 2006129341A1 JP 2005009878 W JP2005009878 W JP 2005009878W WO 2006129341 A1 WO2006129341 A1 WO 2006129341A1
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- Prior art keywords
- layer
- conductive layer
- bit line
- semiconductor device
- film
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 78
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 58
- 238000000034 method Methods 0.000 title claims abstract description 54
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 230000001681 protective effect Effects 0.000 claims description 58
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 229910021332 silicide Inorganic materials 0.000 claims description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 11
- 239000002253 acid Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 3
- 230000006866 deterioration Effects 0.000 abstract description 8
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 243
- 230000015654 memory Effects 0.000 description 66
- 239000011229 interlayer Substances 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 239000011241 protective layer Substances 0.000 description 9
- 238000002513 implantation Methods 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000007687 exposure technique Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- -1 Metal Oxide Nitride Chemical class 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a bit line formed in a semiconductor substrate and a manufacturing method thereof.
- nonvolatile memories which are semiconductor devices capable of rewriting data
- MONOS Metal Oxide Nitride Oxide Silicon
- SONOS Silicon Oxide Nitride Oxide Silicon
- flash memories that accumulate charges in an ONO (Oxide / Nitride / Oxide) film.
- Patent Document 1 discloses a transistor having two charge storage regions between a gate electrode and a semiconductor substrate. This transistor operates symmetrically by switching the source and drain. Thus, the source region and the drain region are not distinguished. In addition, it also serves as a bit line force source region and a drain region, resulting in a structure embedded in the semiconductor substrate. Thereby, miniaturization of the memory cell is achieved.
- an ONO film 18 is formed on a P-type semiconductor substrate 10 as a tunnel oxide film 12 (acid silicon film), a trap layer 14 (silicon nitride film), and a top oxide film 16 ( An oxide silicon film) is formed.
- a photoresist 50 is applied and an opening is formed using a normal exposure technique.
- FIG. 1 (c) for example, arsenic is ion-implanted using the photoresist 50 as a mask to form the bit line 20.
- Pocket implantation is performed using the same photoresist 50 as a mask to form a pocket implantation region 22.
- Pocket implantation means that, for example, boron is implanted obliquely with respect to the vertical direction of the semiconductor substrate 10 so that the P-type semiconductor substrate 10 is further exposed on both sides of the bit line 22. This is a method for forming a high concentration P-type region. As a result, the junction profile in the vicinity of the bit line 20 can be made steep, and the write characteristics can be improved.
- FIG. 1 (d) the photoresist 50 is removed.
- FIG. 1 (e) the word line 24 is formed on the ONO film 18. Thereafter, a flash memory is completed by forming an interlayer insulating film, a wiring layer, and a protective film.
- the semiconductor substrate 10 between the bit line 20 functions as a channel
- the trap layer 14 of the ONO film 18 between the channel and the word line 24 gate electrode It accumulates charges and functions as a nonvolatile memory.
- Two charge storage regions can be formed between the bit lines 20 under the word line 24.
- Accumulation of electric charge in the ONO film 18 is performed by applying a high electric field between the source region and the drain region (that is, between the bit lines 20) and causing the electrons that have become high energy to be trapped in the trap layer 14 in the ONO film 18. This is done by inserting. Data is erased by injecting holes that have become high-tech energy into the trap layer 14. Therefore, in order to improve the write / erase characteristics, it is required to make the bit line 20 region shallow and form a steep junction.
- bit line 20 is formed of a diffusion region, the resistance is higher than that of metal.
- the bit line 20 is connected to the wiring layer through a contact hole formed in the interlayer insulating film every time a plurality of word lines 24 are exceeded.
- Patent Document 1 Special Table 2000-514946
- the memory cell can be miniaturized by reducing the bit line 20 resistance. This is because the bit line width can be reduced if the resistance of the bit line 20 is lowered, and the number of contact holes connecting the bit line 20 and the wiring layer can be reduced.
- the low resistance of the bit line 20 can be achieved by increasing the ion implantation energy dose when forming the bit line 20.
- the junction leakage current increases between the bit line 20 and the semiconductor substrate 10. In this way, the resistance of the bit line is reduced. That is, if the memory cell is miniaturized, the junction leakage current increases and the transistor characteristics deteriorate.
- bit line 20 In order to improve the write / erase characteristics, it is required to make the source region and the drain region (that is, the bit line 20) shallow and form a steep junction. However, when the source region and the drain region (bit line 20) are formed shallowly, the resistance of the bit line 20 becomes high. This is contrary to the miniaturization of memory cells as described above.
- an object of the present invention is to provide a semiconductor device capable of suppressing deterioration of transistor characteristics and further reducing a bit line resistance and a manufacturing method thereof.
- the present invention provides an ONO film formed on a semiconductor substrate, a grid line formed on the ONO film, a bit line formed in the semiconductor substrate, and in contact with the bit line, And a conductive layer extending in the longitudinal direction of the bit line and including a polycrystalline silicon layer or a metal layer.
- bit line resistance since the resistance of the two layers of the bit line and the conductive layer (referred to as bit line resistance in this specification) can be lowered by the conductive layer having low resistance, the implantation energy and the dose amount of the bit line can be reduced. Can be lowered. This can improve the write / erase characteristics and suppress the junction leakage current. Therefore, it is possible to provide a semiconductor device capable of suppressing deterioration of transistor characteristics such as write / erase characteristics and junction leakage and further reducing the bit line resistance.
- the present invention can be a semiconductor device in which the conductive layer is thicker than the ONO film. According to the present invention, the resistance of the conductive layer can be further reduced, and the bit line resistance can be further reduced.
- the present invention can be a semiconductor device in which the word line and the conductive layer are insulated by at least part of the top oxide film in the ONO film. According to the present invention, the word line and the conductive layer are insulated by the top oxide film having good film quality. Therefore, the leakage current between them can be suppressed.
- the present invention may be a semiconductor device having a silicon metal layer on the conductive layer. According to the present invention, it is possible to provide a semiconductor device capable of further reducing the bit line resistance.
- a semiconductor device in which the conductive layer is embedded in the ONO film and the surface of the ONO film is planarized can be obtained.
- the word line 24 can be formed on a flat surface. For this reason, the memory cell can be miniaturized.
- the present invention may be a semiconductor device in which the conductive layer extends continuously in the direction in which current flows. According to the present invention, the bit line resistance can be lowered.
- the present invention provides a wiring layer that intersects the word line and extends in the longitudinal direction of the bit line, and a plurality of the word lines that extend in the longitudinal direction of the word line.
- a bit line contact region provided between one drain line region, and in the bit line contact region, every other wiring layer is connected to the conductive layer, and in the bit line contact region, the wiring
- the conductive layer connected to a layer may be a semiconductor device having a contact pad having a width wider than the width of the conductive layer in the word line region in the bit line contact region.
- the present invention includes a step of forming a tunnel oxide film and a trap layer on a semiconductor substrate, a step of forming a bit line in the semiconductor substrate, and the bit line in the tunnel oxide film and the trap layer.
- a step of forming an opening in contact with the bit line, and a step of forming a conductive layer in contact with the bit line and extending in the longitudinal direction of the bit line and including a polycrystalline silicon or metal layer It is a manufacturing method.
- the bit line resistance can be lowered by the conductive layer having a low resistance, the implantation energy and the dose amount of the bit line can be lowered. Thereby, the junction leakage current can be suppressed if the write / erase characteristics are improved. Therefore, it is possible to provide a method for manufacturing a semiconductor device capable of suppressing deterioration of transistor characteristics such as write / erase characteristics and junction leakage and further reducing bit line resistance.
- the present invention includes a step of forming a protective film on the trap layer, and forms the opening.
- the forming step can be a method for manufacturing a semiconductor device including a step of forming the opening in the protective film. According to the present invention, it is possible to prevent the trap layer from being damaged in the subsequent manufacturing process.
- the step of forming the conductive layer includes a step of forming a polycrystalline silicon layer or a metal layer on the trap layer and the opening, and the polycrystalline silicon layer other than the opening.
- a method of manufacturing a semiconductor device including a step of etching a metal layer can be provided.
- the conductive layer can be made thicker than the ONO film.
- the present invention can be a method for manufacturing a semiconductor device in which the width of the conductive layer is wider than the width of the opening. According to the present invention, it is possible to prevent the contact hole from coming off the conductive layer and damaging the bit line.
- the present invention can be a method for manufacturing a semiconductor device comprising a step of forming a metal silicide layer on the polycrystalline silicon layer or the metal layer. According to the present invention, it is possible to provide a method for manufacturing a semiconductor device capable of further reducing the bit line resistance.
- the step of forming the conductive layer includes a step of forming a polycrystalline silicon layer or a metal layer over the protective film and the opening, and polishing the polycrystalline silicon layer or the metal layer and the protective film. And a process for manufacturing the semiconductor device.
- the word line can be formed on a flat surface. For this reason, the memory cell can be miniaturized.
- the present invention can be a method for manufacturing a semiconductor device comprising a step of forming a metal silicide layer on the conductive layer. According to the present invention, it is possible to provide a method for manufacturing a semiconductor device capable of further reducing the bit line resistance.
- the present invention can be a method for manufacturing a semiconductor device, wherein the step of forming the metal silicide includes a step of forming a metal layer to be silicided on the conductive layer and the silicon nitride film. According to the present invention, it is possible to prevent the silicon oxide film surface from being silly.
- the present invention can be a method for manufacturing a semiconductor device comprising: a step of removing the protective film; and a step of forming a top oxide film on the trap layer and the conductive layer.
- the word line and the conductive layer are insulated by the top oxide film. Therefore, ⁇ Leakage current between the drain line and the conductive layer can be suppressed.
- the present invention may be a method for manufacturing a semiconductor device in which the protective film has a thickness greater than that of the top layer.
- the conductive layer can be made thicker than the ONO film.
- the present invention includes a step of forming a part of a top oxide film on the protective film and the conductive layer, the top oxide film being formed of the protective film and the top oxide film.
- a method of manufacturing a semiconductor device that is partially configured can be obtained.
- the word line and the conductive layer are insulated by a part of the top oxide film. Furthermore, the manufacturing process can be reduced because the protective film is not removed.
- the present invention can be a method for manufacturing a semiconductor device comprising a step of forming a word line on the top oxide film.
- the word line and the conductive layer are insulated by the top oxide film. Therefore, leakage current between the word line and the conductive layer can be suppressed.
- the trap layer and the tunnel oxide layer are formed using a mask layer formed on the trap layer and a side wall formed on a side surface of the mask layer as a mask.
- a method for manufacturing a semiconductor device which is a step of etching a film, can be employed.
- an opening having a width narrower than the exposure dimension can be formed.
- the memory cell can be further miniaturized.
- the present invention it is possible to provide a semiconductor device capable of suppressing deterioration of transistor characteristics and further reducing a bit line resistance and a manufacturing method thereof.
- FIG. 1 is a cross-sectional view showing a method for manufacturing a memory cell of a flash memory according to the prior art.
- FIG. 2 is a top view of the memory cell of the flash memory according to the first embodiment.
- FIG. 3 is a cross-sectional view of the memory cell of the flash memory according to the first embodiment, and shows a cross section taken along the line AA of FIG.
- FIG. 4 is a cross-sectional view showing a method for manufacturing a memory cell of a flash memory according to the first embodiment. 1).
- FIG. 5 is a sectional view (No. 2) showing the method for manufacturing the memory cell of the flash memory according to the first embodiment.
- FIG. 6 is a cross-sectional view of the vicinity of a conductive layer of a flash memory according to a modification of Example 1.
- FIG. 7 is a cross-sectional view showing the method for manufacturing the memory cell of the flash memory according to the second embodiment.
- FIG. 8 is a cross-sectional view showing the method of manufacturing the memory cell of the flash memory according to the third embodiment.
- FIG. 9 is a sectional view (No. 1) showing the method for manufacturing the memory cell of the flash memory according to the fourth embodiment.
- FIG. 10 is a sectional view (No. 2) showing the method for manufacturing the memory cell of the flash memory according to the fourth embodiment.
- FIG. 11 is a cross-sectional view showing the method of manufacturing the memory cell of the flash memory according to the fifth embodiment.
- FIG. 12 is a cross-sectional view showing the method for manufacturing the memory cell of the flash memory according to the sixth embodiment.
- FIG. 13 is a top view of the memory cell of the flash memory according to the seventh embodiment.
- FIG. 2 is a top view of the memory cell of the flash memory according to the first embodiment (the protective layer 44, the wiring layer 42, the interlayer insulating film 40, and the ONO film 18 are not shown).
- Fig. 3 is a cross-sectional view taken along line AA in Fig. 2.
- a bit line 20 serving as a source region and a drain region is formed in a P-type silicon semiconductor substrate 10 (or a P-type region in the semiconductor substrate).
- a pocket injection region 22 is formed in the upper portion.
- the bit line 20 extends in the vertical direction in FIG. 2, and a conductive layer 32 is formed on the bit line 20 so as to be in contact with the bit line 20 and continuously extending in the longitudinal direction of the bit line 20.
- the An ONO film 18 including a tunnel oxide film 12, a trap layer 14, and a top oxide film 16 is formed on the semiconductor substrate 10.
- a word line 24 is formed on the ONO film 18.
- the word line 24 and the conductive layer 32 are insulated by the top oxide film 16 in the ONO film 18.
- An interlayer insulating film 40 is formed on the word line 24, and a wiring layer 42 connected to the bit line 20 and the conductive layer 32 through the contact hole 46 is formed on the interlayer insulating film 40.
- a protective layer 44 is formed on the interlayer insulating film 40 and the wiring layer 42.
- bit line 20 and the conductive layer 32 are connected to the wiring layer 42 via the contact hole 46 every plurality of word lines 24 (16 in FIG. 2, for example, 16 are drawn).
- a region where the contact hole 46 is arranged is a bit line contact region 28, and a region where the word line is arranged is a word line region 29.
- FIGS. 4 and 5 are diagrams corresponding to the AA cross section of FIG.
- a tunnel oxide film 12 (acid silicon film) is applied to a P-type silicon semiconductor substrate 10 (or a P-type region in the semiconductor substrate) by a thermal acid method.
- the trap layer 14 silicon nitride film
- the protective film 26 oxide silicon film
- the film thicknesses of the tunnel oxide film 12, the trap layer 14, and the protective film 26 are, for example, 7.5 nm, 12 nm, and lOnm, respectively.
- arsenic ions are implanted into the semiconductor substrate 10 to form the bit lines 20 in the semiconductor substrate 10. Further, a pocket implantation region 22 is formed. Then heat treatment. Formation of the bit line 20 is performed, for example an implantation energy 40 keV, a dose of 1. 5 X 10 15 cm_ 2.
- a photoresist 52 having a predetermined opening is formed using a normal exposure technique.
- the protective film 26, the trap layer 14 and the tunnel oxide film 12 are etched using the photoresist 52 as a mask.
- an opening 54 in contact with the bit line 20 is formed in the protective film 26, the trap layer 14, and the tunnel oxide film 12.
- a P-type doped polycrystalline silicon layer 30 is formed on the opening 54 and the protective film 26.
- a photoresist 56 having a predetermined opening is formed using a normal exposure technique.
- the polycrystalline silicon layer 30 is etched using the photoresist 56 as a mask to form a conductive layer 32 in contact with the bit line 20 and extending in the longitudinal direction of the bit line 20.
- the conductive layer 32 includes a polycrystalline silicon layer 30.
- the film thickness of the conductive layer 32 is, for example, 50 nm. Thereafter, the protective film 26 is removed.
- the top oxide film 16 is formed by the CVD method so as to cover the trap layer 14 and the conductive layer 32.
- the film thickness of the top oxide film 16 is, for example,
- a polycrystalline silicon word line 24 is formed on the top oxide film 16 by a normal exposure technique and etching method.
- a silicon oxide film such as BPSG (Boro-Phospho Silicated Glass) is formed as the interlayer insulating film 40.
- a contact hole 46 is formed in the interlayer insulating film 40, and a metal such as TiZWN or TiZTiN and W is embedded in the contact hole 46.
- Aluminum is formed as the wiring layer 42, and the protective layer 44 is formed. This completes the flash memory shown in FIG.
- the conductive layer 32 is formed in contact with the bit line 20.
- the conductive layer 32 is formed of a P-type doped polycrystalline silicon layer, and can have a lower resistance than the bit line 20 formed of a diffusion layer.
- bit line resistance the resistance of the two layers of the bit line 20 and the conductive layer 32
- the implantation energy and the dose amount of the bit line 20 can be reduced. Can be small.
- the number of bit lines 20 and conductive layers 32 that exceed the word lines 24 for connection to the wiring layer 42 can be increased. That is, the word line region 29 can be expanded and the area occupied by the bit line contact region 28 in the memory cell can be reduced.
- the width of the bit line 20 and the conductive layer 32 can be reduced. As a result, the memory cell can be miniaturized.
- the first embodiment it is possible to suppress deterioration of transistor characteristics such as write / erase characteristics and junction leakage, and to further reduce the bit line resistance.
- the conductive layer 32 is made thicker than the ONO film 18, so that the conductive layer 32 32 resistance can be made lower. Therefore, the bit line resistance can be lowered.
- the word line 24 and the conductive layer 32 are insulated by the entire top oxide film 14 in the ONO film 18. As a result, the word line 24 and the conductive layer 32 are insulated by the top oxide film 16 having a good film quality that has not undergone various processes. Therefore, it is possible to suppress the leakage current between them.
- the conductive layer 32 extends continuously in the direction of current flow. As a result, the bit line resistance can be lowered.
- FIG. 4 (a) a protective film 26 is formed on the trap layer 14, and in FIG. 4 (c), when the opening 54 is formed in the tunnel oxide film 12 and the trap layer 14, the protective film 26 is formed. An opening 54 is formed in the membrane 26. This prevents the trap layer 14 from being damaged in the subsequent manufacturing process.
- FIG. 5B the protective film 26 is removed, and a top oxide film is formed on the trap layer 14 and the conductive layer 32 so as to cover them. Further, in FIG. 5D, a drain line is formed on the top oxide film 16. As a result, the word line 24 and the conductive layer 32 are insulated by the top oxide film 14 in the ONO film 18. Therefore, the leakage current between the word line 24 and the conductive layer 32 can be suppressed.
- a polycrystalline silicon layer 30 is formed on the trap layer 14 and the opening 54, and a polycrystal other than the opening 54 is formed.
- the crystalline silicon layer 30 is etched.
- the protective film 26 is not removed, and in FIG. 5 (c), the top oxide film 16 and the conductive layer 32 are covered so as to cover them. It is also possible to form a part of 16 (acid silicon film), and to form the top acid film 16 as a partial force of the protective film 26 and the top acid film. In this case, the process of removing the protective film 26 can be reduced. Further, the word line 24 and the conductive layer 32 are insulated by a part of the top oxide film 14 in the ONO film 18. Thereby, since the word line 24 and the conductive layer 32 are insulated by a part of the top oxide film 16 having a good film quality that has not undergone various processes, the leakage current between them can be suppressed.
- FIG. 6A is a cross-sectional view of the vicinity of the conductive layer 32a at this time. Except for the conductive layer 32a, the process is the same as in FIG.
- Example 1 when the overlay of the photoresist 56 and the opening 54 in FIG. 5 (a) is shifted, the cross section corresponding to the conductive layer 32 in FIG. 5 (b) is shown in FIG. 6 (b). Will be deformed. This modification prevents this and prevents the contact hole 46 from coming off the conductive layer 32.
- the polycrystalline silicon layer 30 is etched, a part of the polycrystalline silicon layer 30 is etched up to the bit line 20 to prevent the bit line 20 from being damaged.
- FIG. 7 is a cross-sectional view illustrating the method for manufacturing the flash memory according to the second embodiment.
- the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
- cobalt or titanium for example, is formed on the polycrystalline silicon layer 30 by sputtering and heat-treated.
- the surface of the polycrystalline silicon layer 30 is siliconized, and a silicon metal layer 34 is formed on the polycrystalline silicon layer 30.
- FIG. 7B predetermined regions of the silicon metal layer 34 and the polycrystalline silicon layer 30 are etched. As a result, a metal silicide layer 34 is formed on the conductive layer 32.
- FIG. 7C the protective film 26 is removed, the top oxide film 16 is formed, and the word line 24 is formed as in the first embodiment. Thereafter, the interlayer insulating film 40, the wiring layer 42, and the protective layer 44 are formed, and the flash memory according to Example 2 is completed.
- the bit line resistance can be made lower than that of the first embodiment by forming a silicide metal having a lower resistance than the conductive layer 32 on the conductive layer 32.
- a silicide metal having a lower resistance than the conductive layer 32 on the conductive layer 32.
- FIG. 8 is a cross-sectional view illustrating the method for manufacturing the flash memory according to the third embodiment.
- the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
- up to Fig. 4 (c) Perform the manufacturing process.
- a polycrystalline silicon layer 30 is formed on the protective film 26 and the opening 54.
- the polycrystalline silicon layer 30 and the protective film 26 are polished halfway through the protective film 26 using the CMP method. Thereby, the conductive layer 32b is formed.
- top oxide film 16 (acid silicon film) is formed on the protective film 26 and the conductive layer 32b, and the top oxide film 16 is formed on the protective film 26. And a part of the top oxide film.
- the word line 24 is formed on the top oxide film 16 as in the first embodiment. Thereafter, the interlayer insulating film 40, the wiring layer 42, and the protective layer 44 are formed, and the flash memory according to the third embodiment is completed.
- Example 3 by polishing the polycrystalline silicon layer 30 and the protective film 26 to the middle of the protective film 26 using the CMP method, the conductive layer 32b is embedded in the ONO film 18, and the ONO film 18 is formed.
- the word line 24 can be formed on a flat surface. For this reason, the memory cell can be miniaturized.
- the ONO film 18 cannot be flattened because the thickness of the conductive layer 32 can be increased and its resistance can be reduced.
- the ONO film 18 can be flattened, but the thickness of the conductive layer 32b cannot be increased, and its resistance increases.
- Example 1 can be applied to lower the resistance of the conductive layer 32, and Example 3 can be applied to make the ONO film 18 flatter.
- a part of the top oxide film 16 is formed on the protective film 26 and the conductive layer 32b, and the top oxide film 16 is also configured with a partial force of the protective film 26 and the top oxide film.
- a word line 24 is formed on the top oxide film 16.
- the word line 24 and the conductive layer 32 b are insulated by a part of the top oxide film 14 in the ONO film 18.
- FIG. 9 and FIG. 10 are cross-sectional views showing a method for manufacturing a flash memory according to the fourth embodiment.
- the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
- FIG. 9A is a view similar to FIG. 9A of Example 1 except that the protective film 26a is formed thicker than the protective film 26 of Example 1.
- FIG. The film thickness of the protective film 26a is, for example, 50 nm.
- a polycrystalline silicon layer 30 is formed on the protective film 26 a and the opening 54.
- FIG. 9 (c) the polycrystalline silicon layer 30 and the protective film 26a are polished halfway through the protective film 26a using the CMP method. Thereby, the conductive layer 32c is formed.
- the film thickness of the conductive layer 32c is, for example, 50 nm.
- the protective film 26a is removed with, for example, a hydrofluoric acid aqueous solution.
- the film thickness is on the trap layer 14 and the conductive layer 32c.
- the word line 24 is formed on the top oxide film 16 as in the first embodiment. Thereafter, the interlayer insulating film 40, the wiring layer 42, and the protective layer 44 are formed, and the flash memory according to Example 4 is completed.
- the protective film 26 is made thicker than the top oxide film 16, and the polycrystalline silicon layer 30 and the protective film 26 are polished halfway through the protective film 26. The protective film is removed, and a top oxide film 16 is formed on the trap layer 14.
- the conductive layer 32c can be made thicker than the ONO film 18. Therefore, similarly to Example 1, the resistance of the conductive layer 32c can be lowered.
- the thickness of the conductive layer 32c is increased, the flatness of the ONO film 18 is deteriorated, and it is difficult to miniaturize the memory cell. Therefore, it is preferable to determine the thickness of the conductive layer 32c in consideration of the resistance of the conductive layer 32c and the flatness of the ONO film 18.
- FIG. 11 is a sectional view showing the method for manufacturing the flash memory according to the fifth embodiment.
- the same components as those in the fourth embodiment are denoted by the same reference numerals, and description thereof is omitted.
- a metal to be silicided such as cobalt or titanium is formed on the trap layer 14 (silicon nitride film) and the conductive layer 32c using, for example, a sputtering method. To do. Next, heat treatment is performed. As a result, the surface of the conductive layer 32c is silicided. Thereby, the metal silicide layer 34 is formed on the conductive layer 32c.
- the top oxide film 16 and the word line 24 are formed in the same manner as in Example 4. Thereafter, the interlayer insulating film 40, the wiring layer 42, and the protective layer 44 are formed, and the flash memory according to Example 5 is completed.
- Example 5 a silicon metal having a lower resistance than that of the conductive layer 32c is formed on the conductive layer 32c. As a result, the bit line resistance can be reduced as compared with the fourth embodiment. As a result, in addition to the effects of the fourth embodiment, it is possible to further suppress deterioration of transistor characteristics such as write / erase characteristics and junction leakage, and to further reduce the bit line resistance.
- the metal silicide layer 34 is formed by forming a metal to be silicided on the trap layer 14 (silicon nitride film) and the conductive layer 32c, and silicidizing the conductive layer 32c by heat treatment.
- a metal to be silicified is formed on a silicon oxide film and heat-treated, the silicon oxide film surface may be silicified. Therefore, in order to prevent this, it is preferable to form a metal to be silicided on the silicon nitride film and heat-treat it.
- the protective film 26 is not removed before the formation of the silicon metal layer 34.
- a metal silicide layer 34 is formed.
- the silicon nitride film may be removed to form a part of the top oxide film 16.
- FIG. 12 is a cross-sectional view illustrating the method for manufacturing the flash memory according to the sixth embodiment.
- the same components as those in the third embodiment are denoted by the same reference numerals, and description thereof is omitted.
- FIG. 12 (a) is a diagram similar to FIG. 1 (a) of the first embodiment.
- a silicon nitride film for example, is formed as a mask layer 58 on the protective film 26 (on the trap layer 14) by the CVD method.
- a normal exposure method and etching method are used for the mask layer 58, and an opening is formed in a predetermined region.
- a silicon nitride film is formed as a film for the sidewall 60 by the CVD method.
- side walls 60 are formed on the side surfaces of the mask layer 58 by an etch back method.
- the protective film 26, the trap layer 14 and the tunnel oxide film 12 are etched using the mask layer 58 and the side wall 60 formed on the side surface of the mask layer 58 as a mask.
- Mask layer 58 and sidewall 60 are removed.
- the mask layer 58 and the side wall 60 can be selectively removed with respect to the protective film 26 that is an oxide silicon film. As a result, an opening 54 a is formed in the protective film 26, the trap layer 14, and the tunnel oxide film 12.
- the conductive layer 32b, the top oxide film 16, and the word line 24 are formed in the same manner as in FIGS. 8A to 8D of the third embodiment. Then, interlayer insulating film 40, wiring layer 42, protective layer 44 is formed, and the flash memory according to Example 5 is completed.
- the opening 54a by forming the opening 54a with the mask layer 58 and the side wall 60, the opening 54a having a width narrower than the exposure dimension can be formed.
- the memory cell can be further miniaturized. For example, by setting the exposure dimension to 115 nm and the sidewall width to lOnm, the width of the opening 54a can be set to 95 nm.
- the force applied to the sixth embodiment is an example applied to the third embodiment, and the memory cell can be miniaturized by applying to the other embodiments.
- FIG. 13 is a top view of the memory cell of the flash memory according to the seventh embodiment.
- the protective layer 44, the wiring layer 42, the interlayer insulating film 40, and the ONO film 18 are not shown.
- the manufacturing process is the same as in Example 1!
- every other wiring layer 42 has a contact hole 46 connected to the conductive layer 32d.
- the conductive layer 32d connected to the wiring layer 42 through the contact hole 46 has a contact pad 33 wider in the bit line contact region 28 than the width of the conductive layer 32d in the word line region 29. Further, adjacent contact pads 33 are electrically separated by the semiconductor substrate 10.
- the conductive layer 32d can have the contact pad 33 for the following reason.
- every other wiring layer 42 has a contact hole 46 formed therein. Therefore, the conductive layer 32d connected to the wiring layer 42 can be expanded under the wiring layer 42 where the contact hole 46 is not formed. Therefore, in the bit line contact region 28, the conductive layer 32 d connected to the wiring layer 42 through the contact hole 46 can have a wide contact pad 33.
- the reason why the contact pad 33 can be provided in the bit line contact region 28 is as follows.
- the wiring layer 42 separated from the conductive layer 32d in the bit line contact region 28a is connected to the conductive layer 32d in the adjacent bit line contact region 28b with the word line region 29 interposed therebetween.
- the conductive layer 32d is connected to one wiring layer 42 only in one bit line contact region 28, and extends to the word line regions 26 on both sides of the bit line contact region 28. Accordingly, the conductive layer 32d does not need to extend to the bit line contact region 28 that is not connected to the wiring layer 42. That is, the conductive layer 32d adjacent in the longitudinal direction of the conductive layer 32d is electrically isolated in the bit line contact region 28.
- the length of the conductive layer 32d can be shortened.
- the conductive layer 32 d connected to the wiring layer 42 can extend the contact pad 33 to the bottom of the wiring layer 42 in the region 28.
- the current flowing through the transistor 48 is supplied from the bit line contact region 28a and reaches the bit line contact region 28b as shown by the arrow in FIG. That is, the two conductive layers 32d connected to the transistor 48 provided in the side line region 26 are respectively connected to the bit line contact region 28 formed on opposite sides of the word line region 26. Connected to the wiring layer 42.
- the conductive layer 32d does not need to extend to the bit line contact region 28 that is not connected to the wiring layer 42. Therefore, in the bit line contact region 28, the conductive layer 32d connected to the wiring layer 42 can extend the contact pad 33 in the region 28 to below the wiring layer 42.
- the bit line resistance can be lowered.
- the number of word lines in the word line region 29 can be increased (indicated by two in FIG. 13), so that the bit line contact region 28 can be reduced. In this way, the memory cell can be miniaturized.
- the contact hole 46 prevents the force of the conductive layer 32d (contact pad 33) from being released.
- the distance between the conductive layers 32d can be made smaller than those in the first to sixth embodiments. For example, considering only the interval between the conductive layers 32d, the interval between the bit lines 20d can be about 1Z2 as compared with the first to sixth embodiments. Therefore, the memory cell can be further miniaturized.
- a polycrystalline silicon layer is used as the conductive layer 32.
- a metal layer such as TiNZW can be used. According to this, the same effects as those of the first to seventh embodiments can be obtained.
- the power described above in detail for the preferred embodiments of the present invention The present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims. Deformation 'can be changed.
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Abstract
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JP2007518815A JP5053084B2 (ja) | 2005-05-30 | 2005-05-30 | 半導体装置およびその製造方法 |
PCT/JP2005/009878 WO2006129341A1 (ja) | 2005-05-30 | 2005-05-30 | 半導体装置およびその製造方法 |
US11/444,216 US7943982B2 (en) | 2005-05-30 | 2006-05-30 | Semiconductor device having laminated electronic conductor on bit line |
US13/081,777 US8278171B2 (en) | 2005-05-30 | 2011-04-07 | Fabrication method for semiconductor device having laminated electronic conductor on bit line |
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US11/444,216 Continuation US7943982B2 (en) | 2005-05-30 | 2006-05-30 | Semiconductor device having laminated electronic conductor on bit line |
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JP2007158297A (ja) * | 2005-12-05 | 2007-06-21 | Taiwan Semiconductor Manufacturing Co Ltd | メモリデバイス |
JP2009049133A (ja) * | 2007-08-17 | 2009-03-05 | Spansion Llc | 半導体装置およびその製造方法 |
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US8188536B2 (en) * | 2006-06-26 | 2012-05-29 | Macronix International Co., Ltd. | Memory device and manufacturing method and operating method thereof |
JP5379366B2 (ja) * | 2007-09-20 | 2013-12-25 | スパンション エルエルシー | 半導体装置およびその製造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0766372A (ja) * | 1993-08-27 | 1995-03-10 | Sony Corp | 拡散抵抗層の形成方法 |
JPH07106443A (ja) * | 1993-09-30 | 1995-04-21 | Nkk Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2002026149A (ja) * | 2000-05-02 | 2002-01-25 | Sony Corp | 不揮発性半導体記憶装置およびその動作方法 |
JP2005057127A (ja) * | 2003-08-06 | 2005-03-03 | Renesas Technology Corp | 半導体記憶装置およびその製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5631179A (en) * | 1995-08-03 | 1997-05-20 | Taiwan Semiconductor Manufacturing Company | Method of manufacturing metallic source line, self-aligned contact for flash memory devices |
US5768192A (en) | 1996-07-23 | 1998-06-16 | Saifun Semiconductors, Ltd. | Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping |
US6133096A (en) * | 1998-12-10 | 2000-10-17 | Su; Hung-Der | Process for simultaneously fabricating a stack gate flash memory cell and salicided periphereral devices |
EP1300888B1 (en) * | 2001-10-08 | 2013-03-13 | STMicroelectronics Srl | Process for manufacturing a dual charge storage location memory cell |
-
2005
- 2005-05-30 WO PCT/JP2005/009878 patent/WO2006129341A1/ja active Application Filing
- 2005-05-30 JP JP2007518815A patent/JP5053084B2/ja active Active
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0766372A (ja) * | 1993-08-27 | 1995-03-10 | Sony Corp | 拡散抵抗層の形成方法 |
JPH07106443A (ja) * | 1993-09-30 | 1995-04-21 | Nkk Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2002026149A (ja) * | 2000-05-02 | 2002-01-25 | Sony Corp | 不揮発性半導体記憶装置およびその動作方法 |
JP2005057127A (ja) * | 2003-08-06 | 2005-03-03 | Renesas Technology Corp | 半導体記憶装置およびその製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007158297A (ja) * | 2005-12-05 | 2007-06-21 | Taiwan Semiconductor Manufacturing Co Ltd | メモリデバイス |
JP2011103488A (ja) * | 2005-12-05 | 2011-05-26 | Taiwan Semiconductor Manufacturing Co Ltd | メモリデバイス |
JP2009049133A (ja) * | 2007-08-17 | 2009-03-05 | Spansion Llc | 半導体装置およびその製造方法 |
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US7943982B2 (en) | 2011-05-17 |
US8278171B2 (en) | 2012-10-02 |
JPWO2006129341A1 (ja) | 2008-12-25 |
US20060278936A1 (en) | 2006-12-14 |
US20110183510A1 (en) | 2011-07-28 |
JP5053084B2 (ja) | 2012-10-17 |
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