WO2006109383A1 - 配線基板を有する電子デバイス、その製造方法、および前記電子デバイスに用いられる配線基板 - Google Patents
配線基板を有する電子デバイス、その製造方法、および前記電子デバイスに用いられる配線基板 Download PDFInfo
- Publication number
- WO2006109383A1 WO2006109383A1 PCT/JP2006/304974 JP2006304974W WO2006109383A1 WO 2006109383 A1 WO2006109383 A1 WO 2006109383A1 JP 2006304974 W JP2006304974 W JP 2006304974W WO 2006109383 A1 WO2006109383 A1 WO 2006109383A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- resin layer
- wiring
- resin
- electronic device
- wiring board
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 66
- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 229920005989 resin Polymers 0.000 claims abstract description 527
- 239000011347 resin Substances 0.000 claims abstract description 527
- 239000004065 semiconductor Substances 0.000 claims abstract description 318
- 238000002844 melting Methods 0.000 claims abstract description 50
- 230000008018 melting Effects 0.000 claims abstract description 50
- 229920005992 thermoplastic resin Polymers 0.000 claims abstract description 37
- 239000010410 layer Substances 0.000 claims description 539
- 229920006038 crystalline resin Polymers 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 12
- 229920006127 amorphous resin Polymers 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 11
- 239000002131 composite material Substances 0.000 claims description 7
- 238000003825 pressing Methods 0.000 claims description 5
- 239000000945 filler Substances 0.000 claims description 4
- 238000009832 plasma treatment Methods 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 4
- 239000011247 coating layer Substances 0.000 claims 1
- 239000000463 material Substances 0.000 description 37
- 229910000679 solder Inorganic materials 0.000 description 23
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 12
- 239000012792 core layer Substances 0.000 description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 12
- 229920001187 thermosetting polymer Polymers 0.000 description 12
- 229920000106 Liquid crystal polymer Polymers 0.000 description 11
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 11
- 230000000694 effects Effects 0.000 description 11
- 239000010931 gold Substances 0.000 description 9
- 238000007747 plating Methods 0.000 description 9
- 230000035882 stress Effects 0.000 description 9
- 239000002344 surface layer Substances 0.000 description 9
- 239000011889 copper foil Substances 0.000 description 8
- 230000007423 decrease Effects 0.000 description 8
- 230000006870 function Effects 0.000 description 8
- 229910052737 gold Inorganic materials 0.000 description 8
- 239000004697 Polyetherimide Substances 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 229920001601 polyetherimide Polymers 0.000 description 7
- 239000000654 additive Substances 0.000 description 6
- 238000004080 punching Methods 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 239000004696 Poly ether ether ketone Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 5
- 230000008859 change Effects 0.000 description 5
- 238000001816 cooling Methods 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 229920002530 polyetherether ketone Polymers 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 239000000047 product Substances 0.000 description 5
- PPBRXRYQALVLMV-UHFFFAOYSA-N Styrene Chemical compound C=CC1=CC=CC=C1 PPBRXRYQALVLMV-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 230000009477 glass transition Effects 0.000 description 4
- 229910010272 inorganic material Inorganic materials 0.000 description 4
- 239000011147 inorganic material Substances 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- -1 polybutylene terephthalate Polymers 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 230000000996 additive effect Effects 0.000 description 3
- 238000007373 indentation Methods 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 239000000155 melt Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000000704 physical effect Effects 0.000 description 3
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- UFWIBTONFRDIAS-UHFFFAOYSA-N Naphthalene Chemical compound C1=CC=CC2=CC=CC=C21 UFWIBTONFRDIAS-UHFFFAOYSA-N 0.000 description 2
- 239000004962 Polyamide-imide Substances 0.000 description 2
- 239000004693 Polybenzimidazole Substances 0.000 description 2
- 239000004695 Polyether sulfone Substances 0.000 description 2
- 239000004698 Polyethylene Substances 0.000 description 2
- 239000004721 Polyphenylene oxide Substances 0.000 description 2
- 239000004734 Polyphenylene sulfide Substances 0.000 description 2
- 239000004954 Polyphthalamide Substances 0.000 description 2
- 239000004743 Polypropylene Substances 0.000 description 2
- 239000004793 Polystyrene Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000004840 adhesive resin Substances 0.000 description 2
- 229920006223 adhesive resin Polymers 0.000 description 2
- IISBACLAFKSPIT-UHFFFAOYSA-N bisphenol A Chemical compound C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 IISBACLAFKSPIT-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- ZUOUZKKEUPVFJK-UHFFFAOYSA-N diphenyl Chemical compound C1=CC=CC=C1C1=CC=CC=C1 ZUOUZKKEUPVFJK-UHFFFAOYSA-N 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229920003986 novolac Polymers 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229920002492 poly(sulfone) Polymers 0.000 description 2
- 229920002312 polyamide-imide Polymers 0.000 description 2
- 229920001230 polyarylate Polymers 0.000 description 2
- 229920002480 polybenzimidazole Polymers 0.000 description 2
- 229920001707 polybutylene terephthalate Polymers 0.000 description 2
- 239000004417 polycarbonate Substances 0.000 description 2
- 229920001123 polycyclohexylenedimethylene terephthalate Polymers 0.000 description 2
- 229920006393 polyether sulfone Polymers 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229920006380 polyphenylene oxide Polymers 0.000 description 2
- 229920000069 polyphenylene sulfide Polymers 0.000 description 2
- 229920006375 polyphtalamide Polymers 0.000 description 2
- 239000004800 polyvinyl chloride Substances 0.000 description 2
- 229920000915 polyvinyl chloride Polymers 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229920001169 thermoplastic Polymers 0.000 description 2
- 239000004416 thermosoftening plastic Substances 0.000 description 2
- QTWJRLJHJPIABL-UHFFFAOYSA-N 2-methylphenol;3-methylphenol;4-methylphenol Chemical compound CC1=CC=C(O)C=C1.CC1=CC=CC(O)=C1.CC1=CC=CC=C1O QTWJRLJHJPIABL-UHFFFAOYSA-N 0.000 description 1
- 229920001342 Bakelite® Polymers 0.000 description 1
- 229930182556 Polyacetal Natural products 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 235000013405 beer Nutrition 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 235000010290 biphenyl Nutrition 0.000 description 1
- 239000004305 biphenyl Substances 0.000 description 1
- 239000001273 butane Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 239000000805 composite resin Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229930003836 cresol Natural products 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 150000002343 gold Chemical class 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000113 methacrylic resin Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- IJDNQMDRQITEOD-UHFFFAOYSA-N n-butane Chemical compound CCCC IJDNQMDRQITEOD-UHFFFAOYSA-N 0.000 description 1
- OFBQJSOFQDEBGM-UHFFFAOYSA-N n-pentane Natural products CCCCC OFBQJSOFQDEBGM-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007500 overflow downdraw method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 229920001470 polyketone Polymers 0.000 description 1
- 239000004926 polymethyl methacrylate Substances 0.000 description 1
- 229920006324 polyoxymethylene Polymers 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229920003987 resole Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
- H01L24/742—Apparatus for manufacturing bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/90—Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75251—Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83194—Lateral distribution of the layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0104—Properties and characteristics in general
- H05K2201/0129—Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0104—Properties and characteristics in general
- H05K2201/0133—Elastomeric or compliant polymer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10515—Stacked components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
- H05K3/305—Affixing by adhesive
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
Definitions
- the present invention relates to an electronic device, a manufacturing method thereof, and a wiring board used for the electronic device, and more particularly to an electronic device having a wiring board and a semiconductor chip mounted on the wiring board by a flip chip method.
- connection structure of a semiconductor chip and a wiring board using a flip chip method an improvement in the reliability of a connection portion between the semiconductor chip and the wiring board is one of important issues.
- a method of fixing the semiconductor chip and the wiring board with a resin is known.
- Patent Document 1 An example of a fixing method using a resin is a method disclosed in Japanese Patent Laid-Open No. Hei 41-82241 (Patent Document 1).
- Patent Document 1 an ultraviolet curable or thermosetting adhesive resin is applied to a wiring board provided with wiring, and a semiconductor chip provided with a protruding electrode is applied thereon. The wiring and the protruding electrode are brought into contact with each other. Then, while maintaining this state, the adhesive resin is cured to fix the semiconductor chip to the wiring board.
- Such a method is generally called a pressure welding method.
- an air-type dispenser device is used to supply resin.
- the upper surface of the semiconductor chip is attracted and held by the mounting tool, aligned with the wiring board, and then pressed onto the wiring board.
- the pressure welding method the wiring and the protruding electrode are brought into contact with each other while the resin is in a liquid state, and the resin is cured while maintaining the contact state between the two. Therefore, the residual stress generated at the junction between the wiring board and the semiconductor chip is small, and the connection reliability is high.
- the area of the contact surface of the mounting tool with the semiconductor chip is made sufficiently smaller than the area of the semiconductor chip, and only the central region of the semiconductor chip is mounted.
- the tool should be held. However, in this case, if the thickness of the semiconductor chip is small, when the semiconductor chip is pressed, a local stress is applied to the central portion of the semiconductor chip, and the semiconductor chip breaks.
- the resin is likely to reach the upper surface of the semiconductor chip. Therefore, it is necessary to suppress the variation in the amount of the supplied resin to the limit. In general, it is known that when the thickness of a semiconductor chip is 0.15 mm or less, it is difficult to control the amount of resin with a liquid resin.
- film-like resin material In order to avoid the various problems caused by using a liquid resin as described above, a film-like resin material has been proposed.
- film-like resin materials for underfill applications are unique to film forms, such as film stickability on the wiring board, generation of bubbles between the wiring board and the film, and connection reliability after curing. I have a problem.
- the conventional dispenser device cannot be used, and there is a problem that a new film applicator must be installed. Has a problem.
- Patent Document 2 As another method for fixing the gap between the semiconductor chip and the wiring board with a resin, there is a method disclosed in Japanese Patent Laid-Open No. 2001-156110 (Patent Document 2).
- Patent Document 2 first, a thermoplastic resin film is formed on a film-like substrate on which wiring is formed, covering the wiring. Next, in a state where the thermoplastic resin film is heated and melted, the semiconductor chip is pressed from above the thermoplastic resin film while applying ultrasonic waves so that the wiring and the protruding electrode of the semiconductor chip are brought into contact with each other.
- the ultrasonic bonding method disclosed in Patent Document 2 stably bonds all electrodes to a semiconductor chip having a side length exceeding 10 mm. This is known to be difficult to do and limits the applicable chip size.
- Cu wiring is generally adopted for electronic devices from the viewpoint of connection reliability and electrical characteristics. For more accurate connection, electrolytic nickel plating or electrolytic gold plating is used for the wiring. Etc. are required.
- An object of the present invention is to improve the reliability of connection between a wiring board and a chip component even when a chip component having a large size and a large number of electrodes is mounted on the wiring board, and An electronic device suitable for miniaturization and thinning, a manufacturing method thereof, and the like are provided.
- an electronic device of the present invention includes a wiring board and at least one chip component mounted on the wiring board.
- the wiring board has a first resin layer and a second resin layer stacked on each other via the wiring.
- the chip component has a protruding electrode formed on one side, and is connected to the wiring by entering the first resin layer and contacting the wiring on the wiring board.
- the first resin layer contains at least one kind of thermoplastic resin and has a modulus of elasticity SlGPa or more of the second resin layer at the melting point of the first resin layer.
- An electronic device manufacturing method of the present invention is an electronic device manufacturing method in which a chip component is mounted on a wiring board, and the chip component having a protruding electrode formed on one side and the chip component stacked on each other via a wiring.
- a step of pressing the chip component into the first resin layer with the surface on which the protruding electrode is formed facing the first resin layer in the region where the first resin layer is heated, and the protrusion of the chip component A step of bringing the electrode into contact with the wiring through the first resin layer, and a step of maintaining the contact state between the protruding electrode and the wiring until the first resin layer is cured.
- the first resin layer contains at least one thermoplastic resin, and the elastic modulus of the second resin layer at the melting point of the first resin layer is lGPa or more.
- the present invention provides a wiring board on which at least one chip component having a protruding electrode formed on one side is mounted, and the first resin layer and the first resin layer via the wiring.
- a wiring board having a laminated second resin layer.
- the first resin layer contains at least one thermoplastic resin, and the elastic modulus of the second resin layer at the melting point of the first resin layer is 1 GPa or more. Then, when the chip component enters the first resin layer, the protruding electrode is connected to the wiring.
- the first resin layer is heated above its melting point in the region where the chip component is mounted, and in this state, the chip component is allowed to enter the first resin layer. Then, the protruding electrode is brought into contact with the wiring. At this time, since the elastic modulus of the second resin layer is equal to or greater than lGPa, the wiring is suppressed from sinking into the second resin layer while the chip component is entering the first resin layer.
- the second resin layer functions as a chip component connection auxiliary layer that makes it easy for the chip component to enter the first resin layer while suppressing the sinking of the wiring.
- the first resin layer is cured in a state where the contact between the protruding electrode and the wiring is maintained. Retained.
- the chip component and the second resin layer are in contact with the first resin layer due to temperature changes up to the temperature at which the first resin layer is cured. And a dimensional change arises in the 2nd resin layer.
- the chip component and the second resin layer have different linear expansion coefficients, and this causes a difference in the amount of dimensional change between them.
- the first resin layer that is melted or softened exists between the chip component and the second resin layer, it is caused by a difference in dimensional change between the chip component and the second resin layer. The stress is relaxed by the first resin layer.
- the first resin layer functions as a chip component holding layer that holds the chip component in a state of being advanced, and a stress relaxation layer that relieves stress generated between the chip component and the wiring board.
- the contact state between the protruding electrode of the chip component and the wiring is maintained, and as a result, the reliability of the connection between the chip component and the wiring board is improved.
- the force by which the first resin layer swells around the chip component is based on the amount of the chip component entering, in other words, the first resin layer.
- a film type resin material is generally used as the material of the resin layer, and the thickness is controlled in real time by the film manufacturing apparatus, so the thickness accuracy of the film material applied to the resin layer is very high. high. Therefore, the thickness of the first resin layer can be managed with high accuracy. Therefore, even when the thickness of the chip component is small, the thickness and size of the chip component and the first component are set so that the first resin layer does not reach the surface of the chip component that has entered the first resin layer.
- the thickness of the first resin layer It is easy to manage the thickness of the first resin layer by selecting the optimum film thickness according to the amount of resin extruded by the entry of the chip part into the resin layer.
- the resin constituting the first resin layer can be easily prevented from adhering to the mounting tool by an extremely simple method of controlling the thickness of the first resin layer.
- the mounting tool it is possible to use a mounting tool that is larger than a chip component that does not need to be smaller than the chip component in order to prevent resin adhesion.
- the mounting tool does not apply local stress to the chip component, and there is no possibility of damaging the chip component when the chip component enters the first resin layer.
- the connection between the chip component and the wiring board can be reduced. Reliability can be improved.
- the chip components are directly connected to the wiring in the wiring board, which simplifies wiring compared to conventional devices, thereby reducing the size and thickness of electronic devices and various devices that use them. Can be achieved.
- FIG. 1 is a cross-sectional view of an electronic device according to an embodiment of the present invention.
- FIG. 2 is a cross-sectional view of a wiring board used in the electronic device shown in FIG.
- FIG. 3 is a cross-sectional view of a semiconductor chip used in the electronic device shown in FIG.
- FIG. 4 is a diagram illustrating an example of a method for forming bumps on a semiconductor chip.
- FIG. 5 is a diagram for explaining another example of a method of forming bumps on a semiconductor chip.
- FIG. 6 is a graph showing the relationship between temperature and elastic modulus of a crystalline resin and an amorphous resin.
- FIG. 7 is a cross-sectional view showing another example of an electronic device to which the present invention is applied.
- FIG. 8 is a cross-sectional view showing an example of a semiconductor package to which the present invention is applied.
- FIG. 9 is a cross-sectional view showing another example of an electronic device to which the present invention is applied.
- FIG. 10 is a cross-sectional view showing another example of an electronic device to which the present invention is applied.
- FIG. 11 is a cross-sectional view showing another example of an electronic device to which the present invention is applied.
- FIG. 12 is a cross-sectional view showing another example of an electronic device to which the present invention is applied.
- FIG. 13 is a cross-sectional view showing another example of an electronic device to which the present invention is applied.
- FIG. 14 is a cross-sectional view showing another example of an electronic device to which the present invention is applied.
- FIG. 15 is a cross-sectional view showing another example of an electronic device to which the present invention is applied.
- FIG. 16 is a cross-sectional view showing another example of an electronic device to which the present invention is applied.
- FIG. 17 is a cross-sectional view showing another example of an electronic device to which the present invention is applied.
- FIG. 18 is a cross-sectional view showing another example of an electronic device to which the present invention is applied.
- FIG. 19A is a plan view of a wiring board used in another example of an electronic device to which the present invention is applied.
- FIG. 19B is a cross-sectional view of an electronic device in which two semiconductor chips are mounted in parallel on the wiring board shown in FIG. 19A.
- FIG. 20 is a cross-sectional view showing another example of an electronic device to which the present invention is applied.
- FIG. 21A is a plan view of a wiring board used in another example of the present invention.
- FIG. 21B is a cross-sectional view of the semiconductor package in which two semiconductor chips are mounted on the wiring board shown in FIG. 21A.
- FIG. 22 is a schematic cross-sectional view of a functional module to which the present invention is applied.
- FIG. 23 is a schematic cross-sectional view of a functional module to which a conventional configuration is applied.
- FIG. 24 is a cross-sectional view illustrating a malfunction when the second resin layer does not satisfy the conditions specified in the present invention.
- an electronic device 1 having a wiring substrate 2 and a semiconductor chip 5 according to an embodiment of the present invention is shown.
- the wiring board 2 includes a first resin layer 3a and a second resin layer 3b.
- Wirings 4 are formed in a predetermined pattern on the second resin layer 3b.
- the first resin layer 3a is laminated on the surface of the second resin layer 3b where the wiring 4 is formed.
- the wiring 4 can be formed by a subtractive method generally used for forming a wiring on a substrate. Of course, other methods such as an additive method and a semi-additive method can be used.
- a typical example of the material of the wiring 4 is copper.
- a material that is difficult to oxidize such as Au may be used for the wiring 4 for the purpose of improving the reliability.
- FIG. 3 shows a semiconductor chip 5 used in the electronic device 1 shown in FIG.
- One side of the semiconductor chip 5 is a circuit surface.
- An electrode pad (not shown in FIG. 3) connected to the internal circuit of the semiconductor chip 5 is formed on the circuit surface, and a bump 6 with a sharp tip is formed as an external terminal on the electrode pad.
- the bump 6 can be formed by wire bonding or punching.
- the gold ball 18 is formed at the tip of the gold wire 17 held by the fly 16. This gold ball 18 is pressed against the electrode pad 5 a formed on the circuit surface of the semiconductor chip 5 by the cavities 16. As a result, the gold ball 18 is joined to the electrode pad 5a, and then the gold wire 17 is torn off to form the bump 6 having a sharp tip.
- the gold ball 18 has the gold wire 17 protruding from the tip of the pillar 16 and sparks by applying a high voltage between the torch and the gold wire 17 so that the portion of the gold wire 17 protruding from the tip of the pillar 16 is removed. When melted and solidified, it is formed into a spherical shape by surface tension.
- the bump 6 is formed by the punching method by punching the ribbon material 21 with a punch 19 having a conical recess 19a and a die 20, and using the punched portion as a semiconductor chip 5 Bonded to the pad 5a formed on the circuit surface. As a result, a bump 6 with a sharp tip is formed.
- the bump 6 penetrates the first resin layer 3a and is in contact with the wiring 4 by pushing the semiconductor chip 5 into the first resin layer 3a.
- the first resin layer 3a has a sufficiently small elastic modulus, so that the tip does not necessarily have to be sharp.
- it is preferable to sharpen the tip of the bump 6 because it is easy to penetrate the first resin layer 3a and it is easy to ensure connection reliability.
- Various bumps such as high-temperature solder bumps, copper bumps, and gold bumps can be used as the bumps 6. There are no particular restrictions.
- the semiconductor chip 5 has the side on which the bump 6 is provided enters the first resin layer 3a, and the bump 6 penetrates the first resin layer 3a and is connected to the wiring 4 Has been. Further, the semiconductor chip 5 is held by the first resin layer 3a.
- the following resin layers 3a and 3b of the wiring board 2 are used.
- the first resin layer 3a contains at least one thermoplastic resin.
- the second resin layer 3b has an elastic modulus equal to or higher than lGPa.
- the thickness of the first resin layer 3a is the height of the semiconductor chip 5 after mounting on the wiring board 2 (the end of the bump 6 is crushed after mounting and is lower than the height before mounting).
- the surface of the thinner semiconductor chip 5 protrudes from the surface of the first resin layer 3a.
- the surface of the first resin layer 3a Prior to mounting the semiconductor chip 5 on the wiring board 2, the surface of the first resin layer 3a is increased in order to improve the adhesion of the first resin layer 3a of the wiring board 2 to the semiconductor chip 5. It is desirable to activate by plasma treatment or ultraviolet irradiation.
- the wiring board 2 and the semiconductor chip 5 are aligned.
- This alignment can be performed using an alignment technique by image processing between the semiconductor chip 5 attracted and held by the mounting tool of the mounting apparatus and the alignment mark provided on the wiring board 2. It is desirable to provide the alignment mark on the wiring 4 to which the bump 6 is connected.
- the alignment mark is formed at the same time as the wiring 4 is formed.
- the first resin layer 3a is not transparent, the alignment mark can be recognized from the surface side of the wiring board 2, so that the first resin layer 3a corresponding to the alignment mark is formed on the portion of the first resin layer 3a.
- the opening is formed by laser power, photo / etching, or the like.
- the wiring board 2 is configured by bonding the first resin layer 3a and the second resin layer 3b, before bonding the resin layers 3a and 3b, the first resin layer 3 is formed by punching or the like.
- a through hole may be provided in a portion corresponding to the alignment mark 3a.
- the semiconductor chip 5 attracted and held by the mounting tool is caused to enter the first resin layer 3 a of the wiring board 2.
- the mounting tool should be structured so that it can be heated and pressurized, and suction While holding the held semiconductor chip 5 to a temperature equal to or higher than the melting point of the first resin layer 3a, the semiconductor chip 5 is pressurized so as to be pressed against the first resin layer 3a of the aligned wiring board 2.
- the semiconductor chip 5 is heated and pressed against the first resin layer 3a, the heat of the semiconductor chip 5 is transferred to the first resin layer 3a, and the first resin layer 3a is in contact with the semiconductor chip 5. And its surroundings melt. As a result, the semiconductor chip 5 easily enters the first resin layer 3a while melting the first resin layer 3a around it.
- the semiconductor chip 5 enters the first resin layer 3a, and finally, the bump 6 penetrates the first resin layer 3a, and the bump 6 and the wiring 4 are connected. Connected.
- the second resin layer 3b has a sufficiently high elastic modulus, and the semiconductor chip 5 is attached to the first resin layer 3a.
- the second resin layer 3b is hardly deformed by being pressed against the layer 3a. Therefore, it is possible to obtain a good adhesion state between the wiring 4 and the bump 6 in which the sinking of the wiring 4 into the second resin layer 3b is significantly suppressed.
- the wiring substrate 2 and the semiconductor chip 5 are cooled until the first resin layer 3a is cured while maintaining the close contact state.
- the cooling may be natural cooling or forced cooling.
- the cooling temperature may be about room temperature because the first resin layer 3a only needs to be cured.
- the wiring board 2 is held in the step of causing the semiconductor chip 5 to enter the first resin layer 3a. It is preferable that the heated stage is also heated. However, when the second resin layer 3b is also a thermoplastic resin, if the second resin layer 3b is too soft, a sufficient contact pressure between the bump 6 and the wiring 4 may not be ensured. Therefore, it is desirable that the temperature of the stage that holds the wiring board 2 is lower than the temperature of the mounting tool that holds the semiconductor chip 5. For example, the temperature of the force stage that selects 200 to 350 ° C as the temperature range of the mounting tool should be set lower than the temperature of the mounting tool in the range of 50 ° C to 200 ° C.
- the bump 6 By setting the tip of the bump 6 in a sharp shape, the bump 6 enters while separating the first resin layer 3a, and the tip is pressed against the wiring 4 to be deformed. This is more advantageous in terms of connection reliability.
- the semiconductor chip 5 is loaded in the first resin layer 3a to a desired depth. In rare cases, when the bonding between the bump 6 and the wiring 4 is completed, the heating of the mounting tool is terminated. Whether or not the bump 6 is bonded to the wiring 4 can be determined by measuring the load from the semiconductor chip 5 applied to the mounting tool when the semiconductor chip 5 is pushed in.
- the amount of collapse of the bump 6, that is, the bonding state between the bump 6 and the wiring 4 can be found from the load applied to the mounting tool. After that, the first resin layer 3a is sufficiently cured by the temperature drop of the semiconductor chip 5, and the pressure applied by the mounting tool is maintained until the elastic modulus that can maintain the contact between the bump 6 and the wiring 4 is reached. Raise the tool.
- connection surface of the wiring 4 to which the bump 6 is connected is already covered with the first resin layer 3a, so that oxidation and contamination in the manufacturing process are prevented.
- the connection between the bump 6 and the wiring 4 can be applied to either metal diffusion bonding or a method of maintaining a connection by an insulating resin only by contact.
- the first resin layer 3a a resin containing a thermoplastic resin is used as the first resin layer 3a, and the elastic modulus force S at the melting point of the first resin layer 3a is used as the second resin layer 3b. Since a resin of 1 GPa or more is used, with the first resin layer 3a heated and melted, the semiconductor chip 5 enters the first resin layer 3a and the bumps 6 of the semiconductor chip 5 are brought into close contact with the wiring 4. Thus, the connection between the wiring board 4 and the semiconductor chip 5 can be easily obtained.
- the semiconductor chip 5 since the semiconductor chip 5 is held in the state where it is embedded in the wiring board 4 by the subsequent curing of the first resin layer 3a, the connection state between the wiring board 4 and the semiconductor chip 5 is excellent. Maintained.
- the second resin layer 3b while the semiconductor chip 5 enters the first resin layer 3a, the second resin layer 3b has a sufficient elastic modulus, so that the wiring 4 is connected to the second resin layer by pushing the semiconductor chip 5. Sinking into 3b is suppressed, and adhesion between the wiring 4 and the bump 6 is improved.
- an inorganic material such as glass or ceramic may be used as a material constituting the insulating layer of the wiring board.
- these inorganic materials may be used. It is also possible to suppress the sinking of the wiring 4.
- this kind of inorganic material is brittle and brittle, so it is not easy to handle in the manufacturing process.
- the main material of the insulating layer is resin, handling properties are not deteriorated. Also book As one of the usage forms of the electronic device of the embodiment, it is conceivable that the electronic device is configured as a BGA device and mounted on a substrate such as another mother board.
- the second resin layer 3b is made of an inorganic material, the linear expansion coefficient differs greatly from other substrates, and it is difficult to ensure connection reliability.
- the insulating layer is mainly made of resin, and the linear expansion coefficient is almost equal to that of other substrates, so that it is easy to ensure connection reliability.
- the above-described configuration and method can be applied to any one whose length is about several millimeters to more than 10mm. Even when such a semiconductor chip 5 is mounted on the wiring board 2, it can be widely applied.
- the first resin layer 3a contains a thermoplastic resin so that it can be melted when the semiconductor chip 5 is mounted on the wiring board 2, and the semiconductor chip 5 can be pushed in this state. There is a need.
- the first resin layer 3a may contain a thermosetting resin and other additives as long as it can exhibit such an action.
- the second resin layer 3b needs to have a modulus of elasticity of 1 GPa or more at the melting point of the first resin layer 3a. If this condition is satisfied, the thermoplastic resin Both thermosetting resins and thermosetting resins are applicable. Furthermore, thermoplastic resin and thermosetting resin Composite hybrid materials can also be used. As described above, the second resin layer 3b can be made of not only the thermoplastic resin but also the thermosetting resin itself, so that the range of material selection can be expanded.
- Thermoplastic resins can be broadly classified into crystalline resins in which polymer chains are regularly arranged in the temperature range below the melting point, and amorphous resins in which the polymer chains are not regularly arranged in the temperature range below the melting point.
- FIG. 6 is a graph showing the relationship between temperature (T) and elastic modulus (EM) between a crystalline resin and an amorphous resin.
- T temperature
- EM elastic modulus
- the elastic modulus curve of the crystalline resin is indicated by reference numeral 100
- the elastic modulus curve of the amorphous resin is indicated by reference numeral 200.
- Tgl and Tml in the curve 100 indicate the glass transition point and melting point of the crystalline resin, respectively.
- Tg2 and Tm2 in the curve 200 indicate the glass transition point and melting point of the amorphous resin, respectively. Since the purpose of Fig. 6 is to explain the tendency of the elastic modulus to change with temperature, the specific value of the elastic modulus is omitted.
- the crystalline resin has the property that the elastic modulus gradually decreases as the temperature increases.
- non-crystalline resins maintain a substantially constant elastic modulus up to the glass transition temperature (Tg), and have a characteristic that the elastic modulus rapidly decreases at higher temperatures.
- the non-crystalline resin has a lower melting point than the crystalline resin, so that the mounting temperature at the time of bump penetration can be lowered.
- An advantageous resin is advantageous.
- the resin constituting the first resin layer 3a has a melting point of 240 to 300 ° C for products that require reflow heat resistance, and a reflow temperature range of 190 to 220 ° C.
- a material having rigidity capable of maintaining the connection between the bump 6 and the wiring 4 is suitable.
- materials with a melting point of 100 ° C to 250 ° C are suitable.
- Crystalline resins include PK (polyketone), PEEK (polyetheretherketone), LCP
- PPA polyphthalamide
- PPS polyphenylene sulfide
- PCT polycyclohexylenedimethylene terephthalate
- PBT polybutylene terephthalate
- PET polyethylene terephthalate
- P ⁇ M polyacetal
- PA polyamide
- PE polyethylene
- PP polypropylene
- Non-crystalline resins include PBI (polybenzimidazole), PAI (polyamideimide), PI (polyimide), PES (polyethersulfone), PEI (polyetherimide), PAR (polyarylate), PSF (polysulfone) , PC (Polycarbonate), Modified PPE (Polyphenine ether), PPO (Polyphenylene oxide), ABS (Atarilotoryl'butane styrene), PMMA (Methacrylic resin), PVC (Polyvinyl chloride), PS (Polystyrene) AS (Atarirotoril 'styrene) and the like.
- PBI polybenzimidazole
- PAI polyamideimide
- PI polyimide
- PES polyethersulfone
- PEI polyetherimide
- PAR polyarylate
- PSF polysulfone
- PC Polycarbonate
- Modified PPE Polyphenine ether
- PPO Polyphenylene oxide
- one of the important factors for selecting the material of the first resin layer 3a and the second resin layer 3b is a linear expansion coefficient. It is done. For the reliability after mounting the semiconductor chip 5, especially the environmental load such as temperature cycle, if the coefficient of linear expansion in the Z direction (thickness direction) is large, it adversely affects the contact between the bump 6 and the wiring 4. . Therefore, as a means for adjusting the linear expansion coefficient, there is a method in which a filler (fine particles) having a low linear expansion coefficient is mixed in the resin.
- the first resin layer 3a has a linear expansion coefficient that is equal to the linear expansion coefficient of the semiconductor chip 5 and the second expansion coefficient for the purpose of ensuring the reliability of the connection portion with the semiconductor chip 5 and the bump 6 against temperature changes. It is preferably in the range between the linear expansion coefficient of the resin layer 3b. More preferably, the linear expansion coefficient of the first resin layer 3a is greater than the intermediate value between the linear expansion coefficient of the semiconductor chip 5 and the linear expansion coefficient of the second resin layer 3b. Soon. Therefore, it is desirable to reduce the linear expansion coefficient to about 5 ppmZ ° C to 60 ppmZ ° C by including a material with a low linear expansion coefficient such as silica filler.
- the pressure applied when the semiconductor chip 5 enters the first resin layer 3a compresses and holds the connecting portion between the bump 6 and the wiring 4, and reduces the height of the bump 6.
- the distance between the semiconductor chip 5 and the wiring 4 is suppressed to about 50 ⁇ m or less, and the temperature between the semiconductor chip 5 and the wiring 4 depends on the temperature of the first resin layer 3a in the Z direction.
- the influence of the linear expansion coefficient in the Z direction can be reduced. Therefore, in the present invention, it is not necessarily limited that the linear expansion coefficient of the first resin layer 3a is smaller than the linear expansion coefficient of the second resin layer 3b.
- the second resin layer 3b has a high rigidity and low strength like a general glass epoxy material in which a glass cloth is impregnated with a resin. Even in the method of applying the expansion material to suppress the expansion of the first resin layer 3a, it is possible to suppress the decrease in the connection reliability due to the difference in the linear expansion coefficient.
- the linear expansion coefficient of the first resin layer 3a varies depending on the chip size, bump pitch, number of bumps, and thickness of the wiring board 2 of the semiconductor chip 5 to be mounted, but 10mm XI Omm
- a chip size of about 6 Oppm / ° C or less in the XY direction and 80 ppm / ° C or less in the Z direction is a guide.
- thermosetting resin added to the first resin layer 3a and the thermosetting resin constituting at least part of the second resin layer 3b include bisphenol A type, dicyclopentagen type, An epoxy resin such as a cresol novolac type, a biphenyl type, or a naphthalene type, a phenol resin such as a resol type or a novolak type, or the like may be applied, and a mixed resin material of these may be used.
- PEI which is a non-crystalline thermoplastic resin having a melting point of 250 ° C
- crystallinity having a melting point of about 350 ° C is used as the second resin layer 3b.
- a semiconductor chip 5 was mounted on a wiring board 2 using LCP, which is a thermo-plastic resin, according to the procedure described above.
- LCP which is a thermo-plastic resin
- two types were used, one having an elastic modulus of 0.7 GPa at 250 ° C, which is a temperature near the melting point of PEI, and one having 1. OGPa.
- the main dimensions of the wiring board 2 and the semiconductor chip 5 used here are as follows.
- the first resin layer 3a and the second resin layer 3b are made of a film having a thickness of 50 xm, and the layer structure of the resin layer is the second resin layer. Three layers 3b were formed, and one layer of the first resin layer 3a was provided thereon to form a seven-layer structure.
- Wiring 4 is a copper pattern with 3-5 xm thick Ni plating and 0.5-: 1.0 ⁇ m thick gold plating. Wiring 4 has a total thickness of about 20 zm It is.
- the wiring 4 is provided as an entire wiring board between the resin layers 3a and 3b and on both surfaces of the wiring board.
- the total finished thickness of the wiring board 2 in which the resin layers 3a and 3b and the wiring 4 were combined was 400 ⁇ . Since the wiring board 2 has a part of the resin layers 3a and 3b between the wirings 4 during press molding, the finished thickness varies depending on the wiring density.
- the planar dimensions were 10 mm X 10 mm, the thickness was 0.3 mm, the number of bumps 6 was 480, and the height of the bumps 6 was about 57 / im.
- the temperature of the mounting tool when the semiconductor chip 5 is mounted on the wiring board 2 is set to 300 ° C while the semiconductor chip 5 is pushed into the wiring board 2, and the bump 6 of the semiconductor chip 5 is After contacting the wiring 4, heating of the mounting tool was stopped, and when the temperature reached 200 ° C, the mounting tool was raised from the semiconductor chip 5.
- the second resin layer 3b had an elastic modulus at 250 ° C of 0.
- the contact pressure is high or low can be determined by measuring the conduction resistance between the bump 6 and the wiring 4. The higher the contact pressure, the lower the conduction resistance, and the higher the contact pressure, the higher the conduction resistance.
- the PEI used in Combination Example 1 is used as the first resin layer 3a
- “IBUKI” which is a PEEK thermoplastic copper-clad film manufactured by Mitsubishi Plastics, Inc.
- IBUKI is a composite material with a non-crystalline resin that is based on a crystalline PEEK material. The linear expansion coefficient is kept low by containing.
- the base PEEK-based material has high heat resistance with a melting point exceeding 300 ° C.
- PEI used for the first resin layer 3a has a melting point about 50 ° C. lower than that of “IBUKI”. And at the melting point of PEI, the elastic modulus of “IBUKI” is higher than lGPa.
- the temperature conditions of the mounting tool were also the same as in Combination Example 1.
- the sinking of the wiring 4 is small, so that the connection between the wiring and the bump 6 is good, and the conduction failure between the bump 6 and the wiring 4 due to the sinking of the wiring 4 occurs. I didn't.
- the first resin layer 3a “IBF-3021” manufactured by Sumitomo Bakelite Co., Ltd., which is a resin material containing a thermoplastic resin as a main component and a small amount of a thermosetting resin, is used.
- LCP was used as the second resin layer 3b. 200 which is the mounting temperature range of "IBF-3021”. "IBF-3021” melts at C to 250 ° C, and in this temperature range, the elastic modulus of LCP is higher than 1 GPa.
- the temperature of the mounting tool was 250 ° C while the semiconductor chip 5 was being pushed into the wiring board 2. After the bump 6 of the semiconductor chip 5 and the wiring 4 were in contact, heating of the mounting tool was stopped, When the temperature reaches 150 ° C, raise the mounting tool from the semiconductor chip 5. It was.
- the sinking of the wiring 4 is small, so that the connection between the wiring and the bump 6 is good, and the conduction failure between the bump 6 and the wiring 4 due to the sinking of the wiring 4 occurs. I didn't.
- the same “IBF-3021” as used in Combination Example 3 is used as the first resin layer 3a, and polyimide, which is widely used as a flexible wiring board, is used as the second resin layer 3b. It was.
- Polyimide is an amorphous thermoplastic resin.
- "IBF-3021” melts in the mounting temperature range of "IBF-3021” from 200 ° C to 250 ° C, and in this temperature range, the elastic modulus of polyimide is higher than lGPa.
- the main dimensions of the wiring board 2 and the semiconductor chip 5 are as follows.
- the thickness of the first resin layer 3a was 50 ⁇ m
- the thickness of the second resin layer 3b was 25 ⁇ m
- the total thickness of the wiring board 2 was 75 / im.
- Wiring 4 shall have a 3-5 ⁇ m thick Ni plating and a 0.5-5 mm thick gold plating on the copper pattern, and the total thickness of wiring 4 should be about 20 ⁇ It is.
- the semiconductor chip 5 a semiconductor chip having a planar dimension of 6 mm ⁇ 8 mm, a thickness of 0.1 mm, and 64 knobs 6 was used.
- the temperature of the mounting tool when the semiconductor chip 5 is mounted on the wiring board 2 is 250 ° C while the semiconductor chip 5 is being pushed into the wiring board 2, and the bump 6 of the semiconductor chip 5 is After contact with wiring 4, heating of the mounting tool was stopped, and when the temperature reached 150, the mounting tool was raised from semiconductor chip 5.
- the sinking of the wiring 4 is small, so that the connection between the wiring and the bump 6 is good, and the conduction failure between the bump 6 and the wiring 4 due to the sinking of the wiring 4 occurs. I didn't.
- the second resin layer 3b preferably has an elastic modulus as high as possible in the temperature range when the semiconductor chip 5 is mounted, that is, in the vicinity of the melting point of the first resin layer 3a. For this reason, when a thermoplastic resin is applied to the second resin layer 3b, it is preferable to use an amorphous resin having a property of having a relatively high elastic modulus up to the vicinity of the melting point. For example, crystalline resins that can secure an elastic modulus of 1 GPa or higher at very high temperatures such as 250 ° C are limited. On the other hand, non-crystalline resin Has the advantage that more types of materials such as polyimide used in this example can be selected.
- the first resin layer 3a melts or softens at least the portion in contact with the semiconductor chip 5 and its surroundings by heating, and then the temperature decreases. To cure. During this temperature decrease, the semiconductor chip 5 and the second resin layer 3b contract, but generally the semiconductor chip 5 and the second resin layer have a linear expansion coefficient smaller than that of the resin. There is a difference in shrinkage from 3b. However, since the first resin layer 3a existing between the semiconductor chip 5 and the second resin layer 3b is melted or softened during the temperature drop, the semiconductor chip 5 and the second resin The stress generated by the difference in shrinkage from the layer 3b is relaxed by the first resin layer 3a.
- the first resin layer 3a removed by the semiconductor chip 5 rises around the semiconductor chip 5.
- the rising height of the first resin layer 3a is increased, a part of the first resin layer 3a reaches the surface of the semiconductor chip 5, and in some cases, the resin constituting the first resin layer 3a is mounted. It can stick to the tool and make the mounting tool unusable.
- the rise of the first resin layer 3a is more likely to occur as the amount of the semiconductor chip 5 entering the first resin layer 3a increases.
- the first resin layer 3a also serves to hold the semiconductor chip 5 that only forms part of the wiring board 2 to the wiring board 2, so that the thickness of the first resin layer 3a is insufficient. If so, the semiconductor chip 5 is not securely fixed.
- the first resin layer 3a having a thickness of about several tens of xm a material formed as a film is generally used. Since the thickness of the finolem can be controlled in real time by the film manufacturing apparatus, the thickness accuracy of the first resin layer 3a formed as a film is very high. Therefore, since the thickness of the first resin layer 3a can be managed with high accuracy, even if the semiconductor chip 5 is thin, the semiconductor that has entered the first resin layer 3a.
- the thickness of the semiconductor chip 5 is sized so that the first resin layer 3a does not reach the surface of the chip 5, and further the resin extruded by the semiconductor chip 5 entering the first resin layer 3a. It is easy to manage the thickness of the first resin layer 3a by selecting the optimum film thickness according to the amount.
- the present embodiment it is possible to easily prevent the resin holding the semiconductor chip 5 from adhering to the mounting tool by an extremely simple method of managing the thickness of the first resin layer 3a. it can.
- a mounting tool of a size larger than that of the semiconductor chip 5 without having to reduce the size of the mounting tool than that of the semiconductor chip 5 in order to prevent adhesion of resin, local stress to the semiconductor chip 5 is not applied by also mounting tool, the semiconductor chip 5 second
- the elastic modulus of the second resin layer 3b at the melting point of the first resin layer 3a is It has been described as being over lGPa.
- the wiring substrate is used to ensure that the region of the first resin layer 3a on which the semiconductor chip 5 is mounted is in a molten state. 2
- the temperature of the first resin layer 3a may be set higher than the melting point of the first resin layer 3a.
- the temperature T ° C of the first resin layer 3a is set so that the second resin layer 3b is not softened by the heat of the first resin layer 3a.
- T ° C T ° C ⁇ T ⁇ T + 10 ° C
- the relationship between the first resin layer 3a and the second resin layer 3b is the same as that of the second resin layer 3b in the temperature range of T ° C ⁇ T ⁇ T + 10 ° C.
- the modulus is 1 GPa or more than the elastic modulus of the first resin layer 3a. Thereby, the sinking of the wiring 4 due to the mounting of the semiconductor chip 5 can be suppressed more effectively.
- the semiconductor chip 5 has entered the first resin layer 3a in a state where the first resin layer 3a is heated and melted.
- the first resin layer 3a If a material that is soft enough to allow the bump 6 to penetrate even at a temperature below the melting point is selected, the semiconductor chip 5 can be allowed to enter at a temperature below the melting point. Also at this time, the semiconductor chip While pressing the plug 5 against the wiring board 2, the first resin layer 3a needs to have a modulus of elasticity SlGPa or more.
- the wiring itself is made highly rigid, and the wiring 4 is connected to the first wiring.
- Specific means for increasing the rigidity of the wiring itself include adding a highly rigid metal such as Ni to the material of the wiring 4 and increasing the thickness of the wiring 4. The effect of improving the contact pressure between the bump 6 and the wiring 4 can be expected by increasing the rigidity of the wiring itself.
- As a specific means for reducing the indentation load it is important to reduce the indentation load without reducing the contact pressure between the bump 6 and the wiring 4. If so, use a material with low rigidity for the bump 6 so that the bump 6 can be easily deformed by reducing the diameter of the bump 6 so that a higher contact pressure can be obtained, or by pushing the semiconductor chip 5. And so on.
- a semiconductor chip or a package such as a wafer level CSP, which is secondarily wired on the circuit surface, is provided, as long as it has a protruding electrode on one side of only a general semiconductor chip 5. It can also be applied to mounted electronic parts and even passive electronic parts.
- FIG. 7 is configured by laminating the first resin layer 3a formed with the second wiring 4a as the conductive pattern on the second resin layer 3b formed with the wiring 4.
- An electronic device using wiring board 2 is shown.
- the semiconductor chip 5 enters the first resin layer 3a, and is bonded by the bumps 6 penetrating the first resin layer 3a and contacting the wirings 4.
- a manufacturing method of the wiring board 2 after wiring the wiring 4 on the second resin layer 2b, a copper-clad insulating resin layer having a copper foil formed on one side is laminated, and the copper foil is patterned.
- a subtractive method, an additive method, a semi-additive method or the like generally used for manufacturing a wiring board can be used.
- the build-up method is used in which the layers are stacked one after the other, but general manufacturing methods such as a method of laminating the layers 4a and 4a individually on the resin layers 3a and 3b and then laminating them can be applied. It is.
- the conductive pattern on the first resin layer 3a is formed as a ground pattern 7, and this ground pattern 7 is connected to the ground 7a on the inner layer of the wiring board via the via hole 8.
- a type semiconductor package is shown.
- Solder resist 9 is formed on both sides of the wiring board.
- the lower surface of the second resin layer 3b (the surface opposite to the first resin layer 3a), there are a plurality of pads connected to the wiring 4 and ground 7a on the second resin layer 3b via via holes 8a. Is formed. Solder balls 31 are provided on these pads. In this way, the noise shielding effect can be expected by using the ground pattern 7 as the outermost conductive pattern.
- FIG. 9 is a cross-sectional view showing an example in which the wiring board 2 shown in FIG. 7 is applied to a board having a multilayer wiring layer.
- the wiring 4 and the insulating layer are alternately stacked on both surfaces of the core layer 23 to constitute a multilayer wiring board.
- Each insulating layer is configured as a first resin layer 3a whose outermost layer is made of a thermoplastic resin, and the other insulating layer is configured as a second resin layer 3b.
- the thickness of the first resin layer 3a is about 30 to about 100 ⁇ m.
- a glass epoxy substrate can be used for the core layer 23, and a buildup insulating resin can be used for the second resin layer 3b.
- a thermosetting resin can be used for both the core layer 23 and the second resin layer 3b.
- the first resin layer 3a is made of a thermoplastic resin, and the other layers are made of a thermosetting resin.
- the elastic modulus force SlGPa of the second resin layer 3b at the melting point of the first resin layer 3a As shown, when the materials of the first resin layer 3a and the second resin layer 3b are selected, the first resin layer 3a is sufficiently heated by the heat generated when the semiconductor chip 5 enters the first resin layer 3a.
- thermosetting resin is applied to layers other than the first resin layer 3a through which the bumps of the semiconductor chip 5 penetrate, but as described above, all the insulating layers are made of thermoplastic resin. It is also possible to configure.
- the melting point of the second resin layer 3b is higher than the melting point of the second resin layer 3b so that the second resin layer 3b has an elastic modulus equal to or higher than lGPa at the melting point of the first resin layer 3a. Also use a low material. Then, when the semiconductor chip 5 is introduced into the first resin layer 3a, the second resin layer 3b has a melting point higher than that of the first resin layer 3a within a range where the elastic modulus can be maintained at or above lGPa. If the wiring board is heated, the semiconductor chip 5 can enter the first resin layer 3a in a state where only the first resin layer 3a is melted. Further, when all the insulating layers are made of thermoplastic resin, the wiring board can be constituted as a batch laminated board which is advantageous in terms of cost.
- FIG. 10 shows a cross-sectional view of an electronic device using a wiring board having the first resin layer 3a made of thermoplastic resin as a core layer.
- the wiring board was manufactured using a copper-clad board in which copper foil was formed on both surfaces of the first resin layer 3a, and was formed by patterning the copper foil by a subtractive method or the like. It is manufactured by a general manufacturing method having wirings 4 and 4a and solder resist 9 coated on the outermost layer on both sides.
- the semiconductor chip 5 allows the semiconductor chip 5 to enter the first resin layer 3a with the first resin layer 3a softened or melted, and the bump 6 penetrates the first resin layer 3a. It is mounted on the wiring board by coming into contact with the wiring 4.
- the solder resist 9 under the first resin layer 3a needs to have an elastic modulus at the melting point of the first resin layer 3a of lGPa or more.
- the second resin layer in the present invention functions as the solder resist 9.
- FIG. 11 shows a cross-sectional view of an electronic device using a wiring board having the second resin layer 3b having the wirings 4 and 4a formed on both front and back surfaces as a core layer.
- Solder resist 9 is formed on the back side of second resin layer 3b, while first resin layer 3a made of a thermoplastic resin that functions as a solder resist is formed on the front side.
- the semiconductor chip 5 can be mounted on the wiring board S by bringing the bump 6 and the wiring 4 into contact with each other in the same procedure as described above. According to this example, it is possible to make the first resin layer 3a function both as a solder resist and a sealing resin for the semiconductor chip 5.
- the first resin layer 3a By providing the function as a rudder resist, it is possible to maintain the insulation of the wiring 4 from the outside. It is also possible to use this electronic device as a semiconductor package by providing an opening at a position corresponding to the wiring 4a of the solder resist 9 on the back side of the wiring board and providing a terminal for connection to the outside in this opening. it can.
- FIG. 12 shows an electronic device using a wiring board having a multilayer structure in which the third resin layer 3c is further combined with the first resin layer 3a and the second resin layer 3b.
- the wiring board has five insulating layers, and the three layers on the back side are formed as the second resin layer 3b, of which the second resin layer 3b on the front side is adjacent.
- the first resin layer 3a is laminated and further laminated adjacent to the first resin layer 3a.
- wiring 4 is formed between the resin layers 3a to 3c, and the semiconductor chips 5a and 5b are held in the first resin layer 3a and the third resin layer 3c, respectively.
- a thermoplastic resin, a pre-preda or the like can be used for the first resin layer 3a and the third resin layer 3c.
- the electronic device of this example can be manufactured by the following procedure. First, at the stage where the first resin layer 3a is formed on the second resin layer 3b, the semiconductor chip 5a is pushed into the first resin layer 3a according to the procedure described above, and in this state, the first resin layer 3a is Harden. This completes the mounting of one semiconductor chip 5a. Next, a third resin layer 3c is formed thereon, and the semiconductor chip 5b is pushed into the third resin layer 3c according to the procedure described above, and the third resin layer 3c is cured in this state.
- the elastic modulus of the second resin layer 3b at the melting point of the first resin layer 3a is the same as described above. lGPa or higher.
- the elastic modulus of the first resin layer 3a at the melting point of the third resin layer 3c is lGPa or more.
- the sinking of the wiring 4 can be achieved even in the configuration shown in FIG. Therefore, an electronic device with a high connection reliability between the wiring board and the semiconductor chips 5a and 5b can be obtained.
- the resin layer 3c may be composed of two or more layers, and a semiconductor chip may be inserted into each layer. Even in this case, the relationship between the third resin layers 3c adjacent to each other in the stacking direction is that the material of each third resin layer is such that the lower layer has an elastic modulus of 1 GPa or more at the melting point of the upper layer. Select.
- FIG. 13 also shows a cross-sectional view of an electronic device in which the semiconductor chip 5 is mounted on a multilayer wiring board.
- the wiring board of this example has a core layer 23, and a plurality of insulating layers are laminated on both sides thereof via wirings 4, 4a and 4b, respectively.
- As these insulating layers on the surface side of the core layer 23, the second resin layer 3b formed on the core layer 23 and the two first resin layers 3a formed on the second resin layer 3b are provided.
- solder resist 9 is formed on the outermost surface and the back surface of the wiring board.
- the bump 6 penetrates through the two first resin layers 3 a and is connected to the wiring 4.
- the first resin layer 3a into which the semiconductor chip 5 enters into a plurality of layers, it is possible to add more wiring 4b between these layers, thereby improving the structural and wiring flexibility. That power S.
- this example is different from the first resin layer 3a if the second resin layer 3b has an elastic modulus equal to or higher than lGPa at the melting point of each first resin layer 3a.
- Layer 3a may be composed of the same material or different materials.
- the number of first resin layers 3a is not limited to two, and may be three or more.
- the wiring 4b between the first resin layers 3a may be formed as a ground.
- the wiring 4b in the lower layer is connected to the ground.
- the second resin layer 3b is laminated on both the front and back surfaces of the core layer 23 via the wiring 4a, and further, the first resin layer 3a is laminated on the surface via the wiring 4
- An electronic device using a printed wiring board is shown.
- the two semiconductor chips 5 are inserted into the first and second resin layers 3a on the front and back so that the bumps 6 pass through the first resin layer 3a and come into contact with the wiring 4, respectively.
- each semiconductor chip 5 is mounted in the opposite direction with the bumps 6 facing each other. Yes.
- the solder resist 9 covers the wiring 4b on the surface of each first resin layer 3a.
- the electronic device of this example can be manufactured as follows, for example. First, the semiconductor chip 5 on one side is mounted on the wiring board as described above. Next, the wiring board on which the semiconductor chip 5 is mounted on one side is turned upside down, and another semiconductor chip 5 is placed on the surface of the wiring board opposite to the surface on which the semiconductor chip 5 is already mounted. Mount in the same way.
- two second resin layers 3b and a core layer 23 are interposed between the two first resin layers 3a of the wiring board, and between each first resin layer 3a, It is difficult to transmit heat. As a result, even if the first resin layer 3a into which the semiconductor chip 5 enters is heated in order to mount the second semiconductor chip 5, the first semiconductor chip 5 on the side where the semiconductor chip 5 is already mounted is heated. The resin layer 3a does not soften or melt, and the connection state between the already mounted semiconductor chip 5 and the wiring 4 remains maintained.
- FIG. 15 shows the wiring 4 and the bumps 6 inserted into the first resin layer 3a provided on the second resin layer 3b via the wiring 4 shown in FIG.
- An example is shown in which an additional insulating layer 24 is further laminated on the front side and back side of the connected configuration via the wiring 4a.
- the attached insulating layer 24 may be provided only on the front side or only on the back side.
- the number of attached insulating layers 24 is also arbitrary depending on the characteristics required for the electronic device.
- the additional insulating layer 24 is provided on the surface side, the semiconductor chip 5 is completely contained in the wiring board.
- a resin such as a thermoplastic resin or a pre-preda can be used as the additional insulating layer 24 .
- each additional insulating layer 24 is about 30 to about 100 zm. Also, as shown in Fig. 15, wiring and solder resist 9 may be formed on both the front and back sides. When the device having the configuration shown in FIG. 15 is manufactured, the semiconductor chip 5 is mounted after the first resin layer 3a is formed and before the additional insulating layer 24 is formed on the first resin layer 3a. Is done.
- the device of this example As described above, it has the feature that low manufacturing cost can be realized. Therefore, compared with the case where the semiconductor chip 5 is mounted on a general wiring board, the final product By incorporating a semiconductor chip 5 that can not only reduce costs It is possible to achieve high-density mounting of chip components, and in turn, to reduce the size of products equipped with this device.
- the semiconductor chip 5 since the semiconductor chip 5 is built in, the wirings 4 and 4a are also formed in the inner layer, and as a result, the number of via holes and the accompanying structures for routing the wirings to the inner layer are minimized. As a result, the overall wiring length can be shortened.
- FIG. 16 shows a device in which the region where the semiconductor chip 5 is exposed in the structure shown in FIG. 10 is sealed with a coating resin 25 as an additional insulating layer.
- the other structure that is, the first resin layer 3a as a core layer, has wirings 4 and 4a on both sides, and the wirings 4 and 4a on both sides are covered with solder resist 9, and each solder resist 9 Of these, the side laminated via the wiring 4 connected to the bump 6 functions as the second resin layer, or the semiconductor chip 5 is held in the first resin layer 3a, and the first resin layer 3a is It is the same as the structure shown in Fig. 10 that the bump 6 that has penetrated is mounted by contacting the wiring.
- the coating resin 25 can be formed by a dispense or screen printing method. The coating resin 25 reinforces the upper surface of the semiconductor chip 5 and achieves flattening of the device surface. Also in this example, the effect of incorporating the semiconductor chip 5 is the same as that shown in FIG.
- FIG. 17 shows an example in which another semiconductor chip 26 is further stacked on the device having the structure of FIG. 16 in which the semiconductor chip 5 is sealed with a coating resin 25.
- the other semiconductor chip 26 is mounted on the first resin layer 3a at a position overlapping the semiconductor chip 5 sealed with the coating resin 25, and the wiring 4a on the first resin layer 3a of the wiring board is connected to the semiconductor chip 5. It is connected.
- An underfill resin 27 is filled in the gap between the other semiconductor chip 26 and the wiring board.
- the semiconductor chip 5 is mounted on the wiring board using the method described above.
- Other semiconductor The flip chip pressure welding method which is a conventional method, can be applied to mounting the body chip 26.
- the underfill resin 27 it is desirable to use a resin that cures at a temperature lower than the melting point of the first resin layer 3a.
- a solder fusion method that can be mounted with a low load is applicable.
- reflow soldering is often used for mounting other semiconductor chips 26.
- the first As the material for the resin layer 3a, non-crystalline that can ensure rigidity in a relatively high temperature range such as a melting point of lead-free solder of 220 ° C, or a composite material of non-crystalline and crystalline resin is effective.
- the concave / convex portion below the semiconductor chip 26 leads to the influence on the fluidity of the underfill resin 27 and the generation of voids.
- the coating resin 25 covering the semiconductor chip 5 also has the effect of reducing the unevenness between the two semiconductor chips 5 and 26, thereby enabling effective filling of the underfill resin 27.
- FIG. 18 by applying the configuration shown in FIG. 8, two layers are added via the wiring 4a on the first resin layer 3a around the area where the semiconductor chip 5 is mounted.
- a cross-sectional view of an example using a wiring board in which a typical insulating layer 24 is laminated is shown.
- the wiring board includes a second resin layer 3b, a first resin layer 3a laminated thereon via wiring 4, and an additional layer made of, for example, a resin material laminated thereon via wiring 4. And a typical insulating layer 24.
- the additional insulating layer 24 has an opening formed in a region where the semiconductor chip 5 is mounted.
- the opening portion of the additional insulating layer 24 is formed by, for example, punching or punching a desired insulating layer (in this case, each insulating layer 24) when a wiring board is manufactured by a build-up method. Can be formed.
- the semiconductor chip 5 is inserted into the opening of the auxiliary insulating layer 24 and mounted on the first resin layer 3a in the same manner as described above.
- the first resin layer 3a having a copper foil formed on one side is laminated to form the first resin layer 3a.
- the upper copper foil is patterned to form the wiring 4a, and then an additional insulating layer 24 having a copper foil formed on one side is laminated, and the copper foil on the additional insulating layer 24 is patterned.
- the additive method of forming the wiring 4a by unging can be used.
- a multilayer structure such as a method in which the wirings 4 and 4a are formed in advance on each of the resin layers 3a and 3b and the additional insulating layer 24, and these are stacked together.
- a general method used for manufacturing a manufactured wiring board can be used. However,
- the wirings 4, 4a are not necessarily formed.
- the resin layers 3a and 3b and the additional insulating layer 24 may be layered according to the characteristics and performance required for the device, such as a plurality of additional insulating layers 24 as shown in FIG. The number can be set arbitrarily.
- the semiconductor chip 5 has substantially the same mechanical characteristics as that incorporated in the wiring board, but the surface of the semiconductor chip 5 is exposed through the opening of the wiring board.
- a heat sink (not shown) can be attached to the surface of the semiconductor chip 5 to improve the heat dissipation of the semiconductor chip 5.
- the semiconductor chip 5 can be mounted after a series of processes for manufacturing a wiring board is completed while having substantially the same effect as a chip built-in type device, thus simplifying the manufacturing process. Can do.
- a pad to which a terminal for connection to the outside is connected is formed on the back surface of the wiring board. By providing a terminal on this pad, it can be used as a semiconductor package. .
- FIGS. 19A and 19B show an electronic device in which a plurality of semiconductor chips 5 are mounted on the same first resin layer 3a.
- FIG. 19A is a plan view of the wiring board in a state where the semiconductor chip 5 is not mounted
- FIG. 19B is a cross-sectional view.
- the position where the semiconductor chip 5 is mounted is indicated by a one-dot chain line.
- the device of this example is an application of the configuration shown in Fig. 8, and the outermost conductive pattern formed on the first resin layer 3a is configured as a ground pattern 4g.
- Two semiconductor chips 5 are mounted on the wiring board, and the ground pattern 4g is formed on the entire outside of the two regions on which the semiconductor chips 5 are respectively mounted.
- Under the first resin layer 3a two second resin layers 3b are laminated via wirings 4 and 4a, respectively, and the wirings between the layers are connected via via holes 8.
- the ground pattern 4g and the lowermost wiring 4a are covered with a solder resist 9.
- the bumps of the semiconductor chip 5 are connected to the pads 30 provided at the front end portion of the wiring 4 between the first resin layer 3a and the second resin layer 3b. And bump of semiconductor chip 5 is connected The formed wiring 4 is connected to the bump of the adjacent semiconductor chip 5 or dropped to the lower wiring 4a through the via hole 8.
- the bump of the semiconductor chip 5 is connected to the inner wiring layer 4 in the wiring board in which the outermost conductive pattern is the ground pattern 4g. This eliminates the need to route the wiring 4 connected to the bumps of the semiconductor chip 5 to other layers via the via holes 8, thereby reducing the number of via holes 8 and increasing the density. Implementation can be realized.
- signal lines are 1Z2 to: 1Z3 of the total number of terminals, and the other is a power supply 'ground terminal. Assuming that 50 terminals of a semiconductor chip having 100 external terminals are signal lines, in the conventional configuration in which the semiconductor chip is mounted on the surface layer of the wiring board, all signal lines are connected to via holes.
- the number of terminals for connecting from the surface layer to the inner layer is 50, and the number of terminals for connecting from the inner layer to the surface layer is 50. In total, 100 via holes that are double the number of signal lines are required.
- a direct connection in the same layer is possible to connect a plurality of chip components. This eliminates the need for via holes between the surface layer and the inner layer, and eliminates all 100 via holes between the surface layer and the inner layer.
- the region not covered by the ground pattern 4g can be minimized, and the shielding effect can be obtained. Can be increased.
- it is ideal that the entire periphery of the semiconductor chip 5 is the ground pattern 4g.
- the periphery of the semiconductor chip 5 is raised. Therefore, considering this rise, the edge of the semiconductor chip 5 and the ground pattern 4g
- the gap can be set to about 0.5 mm.
- FIG. 20 shows a cross-sectional view of an example in which the packaged electronic component 35 is mounted on the first resin layer 3a at a position overlapping the semiconductor chip 5 embedded in the wiring board.
- the wiring board is the same as that shown in FIG. 10, and is formed by forming solder resist 9 on both sides of the first resin layer 3a having wirings 4 and 4a on both sides.
- the semiconductor chip 5 is mounted by the bumps penetrating the first resin layer 3a and coming into contact with the wiring 4.
- Tail solder is supplied by a printing method or the like to the pads provided at the ends of the wiring 4a formed on the first resin layer 3a.
- the electronic component 35 is surface-mounted by positioning the lead terminal of the electronic component 35 on the pad and performing reflow soldering.
- the first resin layer 3a when a thermoplastic resin is used for the first resin layer 3a, the first resin layer 3a is lead-free so that the connection part of the semiconductor chip 5 is not damaged even at the reflow temperature. It is desirable to apply a non-crystalline resin or a composite material of non-crystalline resin and crystalline resin that can secure a solder melting point of 220 ° C and rigidity in a relatively high temperature range.
- FIGS. 21A and 21B show an example in which the BGA shown in FIGS. 28A and 28B is applied to the present invention.
- 21A is a plan view of the wiring board in a state where the semiconductor chips 5 and 36 are not mounted
- FIG. 21B is a semiconductor package in which two semiconductor chips 5 and 36 are mounted on the wiring board shown in FIG. 21A. It is sectional drawing. In FIG. 21A, the position where the semiconductor chip 5 is mounted is indicated by a dashed line.
- the bump of the semiconductor chip 5 is connected to the inner layer pad 30 which is the end of the wiring 4 on the second resin layer 3b, and another semiconductor chip 36 is provided on the semiconductor chip 5. It is mounted face up so that its circuit surface is facing upward.
- a pad 33 for connection to another semiconductor chip 36 is formed on the outer periphery of the pad 30, and electrodes (not shown) and pads of the other semiconductor chip 36 are formed. 33 are connected by a bonding wire 34.
- Solder balls 21 are formed in an area not covered with the solder resist 9 on the back surface of the wiring board. In this example, the following effects are achieved by connecting the bumps of the semiconductor chip 5 to the inner layer wiring.
- the wiring connected to the semiconductor chip 5 is routed to the inner layer of the wiring board on the surface layer of the wiring board. Therefore, it is not necessary to form a via hole around the semiconductor chip 5, so that the number of via holes 8 can be reduced.
- the pads 33 for connection with other semiconductor chips 36 can be placed close to the semiconductor chip 5, it is possible to reduce the length of the bonding wires 34.
- high-density mounting can be realized and the number of wiring layers can be reduced.
- Fig. 22 shows a schematic diagram of a functional module 50 to which the present invention is applied, in which semiconductor chips 52 to 55 are mounted on both sides of a wiring board 51, and Fig. 23 shows a comparison with the functional module 50 shown in Fig. 22.
- a schematic diagram of a functional module 70 to which a conventional configuration is applied is shown.
- a functional module 70 shown in FIG. 23 has a general structure in which semiconductor packages 72 to 75 are mounted on both surfaces of a wiring board 71.
- the mainstream of semiconductor packages is a planar size of 5 to 15 mm square and a mounting height of 1.0 to 1.4 mm.
- the dimensions of each of the semiconductor packages 72 to 75 mounted on the wiring board 71 are as follows.
- the semiconductor package 74 has a planar size of 7 mm X 7 mm and a mounting height of 1.2 mm.
- the semiconductor package 75 has a planar size of 15 mm XI 5 mm and a mounting height of 1 5mm
- semiconductor package 72 has a planar size of 10mm x 10mm, mounting height of 1 and 4mm
- semiconductor package 73 has a planar size of 7mm x 7mm and mounting height of 1 and 2mm.
- Wiring board 71 requires a board with 6 wiring layers
- wiring board 71 has a thickness of 0.8 mm
- the plane size is 28 mm considering that the mounting area needs to be about the package size + 3 mm. X 28mm. Therefore, it is easily assumed that the functional module 70 on which the conventional semiconductor packages 72 to 75 are mounted has a plane size of 28 mm ⁇ 28 mm and a thickness of about 3.6 mm.
- the functional module 50 shown in FIG. 22 adopts the above-described method directly on the semiconductor chip sealed in the semiconductor packages 72 to 75 shown in FIG. It is assumed that the electronic device mounted on the wiring board 51 having the resin layer and the second resin layer is provided. Here, it is assumed that the sizes of the semiconductor chips 52 to 55 are 70% of the sizes of the semiconductor packages 73 to 75 shown in FIG. Then, the planar size of each of the semiconductor chips 52 to 55 is 4.9 mm X 4.9 mm for the semiconductor chip 54, 10.5 mm X 10.5 mm for the semiconductor chip 55, 7 mm X 7 mm for the semiconductor chip 52, and 7 mm X 7 mm for the semiconductor chip 53. 4.9mm X 4. 9mm.
- the mounting height of each semiconductor chip 52 to 55 is 0.05 mm. It becomes.
- the wiring board 51 is expected to be able to reduce the wiring layer to four layers by direct connection to the inner layer wiring, which is a feature of the present invention.
- the thickness of the wiring board 51 is 0.6 mm, a plane
- the size is 17.4mm x 17.4mm, where the mounting area is the chip size + lmm.
- the functional module 50 shown in FIG. 22 has a planar size of 17.4 mm X 17.
- the module area ratio can be reduced by 62% and the thickness can be reduced by 81%, and a remarkable reduction in size and thickness can be expected.
- the conventional configuration and the configuration according to the present invention are compared between a functional module on which a semiconductor package is mounted and a functional module on which a semiconductor chip is directly mounted.
- the reason is as follows.
- the land diameter of the via hole at the practical level of the wiring board is 200 ⁇ m, and the arrangement pitch of the via holes is 300 ⁇ m. Therefore, when trying to mount a semiconductor chip directly on a wiring board, a large number of via holes are required especially in a multi-pin semiconductor chip exceeding 300 pins. For this reason, the wiring from the semiconductor chip must be routed to the extent that the via Honoré can be placed, and as a result, the miniaturization effect on the functional module on which the semiconductor package is mounted is limited. Therefore, from the viewpoint of ease of handling and the like, conventionally, a method of configuring a functional module by mounting a packaged component rather than directly mounting a semiconductor chip has been generally performed.
- the number of via holes can be greatly reduced. Even in a directly mounted configuration, dramatic downsizing as described above can be realized.
- the wiring length can be shortened as compared with the conventional case where a semiconductor chip is mounted on the surface of the wiring board. By reducing the wiring length, it is possible to attenuate electrical signals and reduce noise from the wiring. A decrease in signal quality due to mixing can be suppressed.
- the functional module includes a camera module, a liquid crystal module, an RF module, a wireless LAN module, a Bluetooth (registered trademark) module, and a plurality of chips as a module for mobile devices such as mobile phones.
- a camera module a liquid crystal module
- an RF module a wireless LAN module
- a Bluetooth (registered trademark) module a plurality of chips as a module for mobile devices such as mobile phones.
- a variety of modules such as system-in-package, etc. that are mixed and packaged into one package.
- modules such as system-in-package, etc. that are mixed and packaged into one package.
- the electronic device to which the present invention is applied can be applied to all electronic devices, for example, semiconductor chips such as CPU, logic, and memory, regardless of the type of device.
- semiconductor chips such as CPU, logic, and memory
- each semiconductor chip a semiconductor package having the structure of the present invention, as described above, it is possible to realize a small / thin package with high yield, high reliability, and low cost as compared with the conventional semiconductor package.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Metallurgy (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007512417A JPWO2006109383A1 (ja) | 2005-04-05 | 2006-03-14 | 配線基板を有する電子デバイス、その製造方法、および前記電子デバイスに用いられる配線基板 |
CN200680011442XA CN101156237B (zh) | 2005-04-05 | 2006-03-14 | 具有配线基板的电子设备、其制造方法以及用于这种电子设备的配线基板 |
US11/908,460 US20090020870A1 (en) | 2005-04-05 | 2006-03-14 | Electronic device provided with wiring board, method for manufacturing such electronic device and wiring board for such electronic device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005108823 | 2005-04-05 | ||
JP2005-108823 | 2005-04-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006109383A1 true WO2006109383A1 (ja) | 2006-10-19 |
Family
ID=37086676
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2006/304974 WO2006109383A1 (ja) | 2005-04-05 | 2006-03-14 | 配線基板を有する電子デバイス、その製造方法、および前記電子デバイスに用いられる配線基板 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20090020870A1 (ja) |
JP (1) | JPWO2006109383A1 (ja) |
CN (2) | CN101156237B (ja) |
WO (1) | WO2006109383A1 (ja) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009177122A (ja) * | 2007-12-25 | 2009-08-06 | Hitachi Chem Co Ltd | 薄型接合体の製造方法及び薄型接合体 |
EP1981321A3 (en) * | 2007-04-09 | 2009-09-16 | Endicott Interconnect Technologies, Inc. | Circuitized substrate assembly with internal stacked semiconductor chips, method of making same, electrical assembly utilizing same and information handling system utilizing same |
JP2009297950A (ja) * | 2008-06-11 | 2009-12-24 | Canon Inc | 液体吐出装置の製造方法及び液体吐出装置 |
JP2011222553A (ja) * | 2010-04-02 | 2011-11-04 | Denso Corp | 半導体チップ内蔵配線基板及びその製造方法 |
JP2013535093A (ja) * | 2010-05-20 | 2013-09-09 | エーファウ・グループ・エー・タルナー・ゲーエムベーハー | チップスタックを製造するための方法及びその方法を実施するためのキャリア |
DE112007003083B4 (de) * | 2006-12-22 | 2019-05-09 | Tdk Corp. | Mikrofonbaugruppe mit Unterfüllmittel mit niedrigem Wärmeausdehnungskoeffizienten |
TWI661520B (zh) * | 2016-04-01 | 2019-06-01 | 愛爾蘭商艾克斯瑟樂普林特有限公司 | 藉由微轉印之壓力啟動電性互連 |
WO2019167194A1 (ja) * | 2018-02-28 | 2019-09-06 | オリンパス株式会社 | 超音波プローブ及び超音波処置具 |
WO2021242013A1 (ko) * | 2020-05-26 | 2021-12-02 | 엘지이노텍 주식회사 | 패키지 기판 |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9929080B2 (en) * | 2004-11-15 | 2018-03-27 | Intel Corporation | Forming a stress compensation layer and structures formed thereby |
TWI353661B (en) * | 2007-04-09 | 2011-12-01 | Unimicron Technology Corp | Circuit board structure capable of embedding semic |
JP2009170753A (ja) * | 2008-01-18 | 2009-07-30 | Panasonic Corp | 多層プリント配線板とこれを用いた実装体 |
US8222739B2 (en) * | 2009-12-19 | 2012-07-17 | International Business Machines Corporation | System to improve coreless package connections |
AU2010362421B2 (en) | 2010-10-14 | 2015-06-25 | Digital Tags Finland Oy | Method and arrangement for attaching a chip to a printed conductive surface |
DE112013006948B4 (de) | 2013-04-15 | 2021-09-30 | Mitsubishi Electric Corporation | Rotor einer Drehmaschine |
JP5842859B2 (ja) * | 2013-04-15 | 2016-01-13 | 株式会社村田製作所 | 多層配線基板およびこれを備えるモジュール |
GB2524791B (en) * | 2014-04-02 | 2018-10-03 | At & S Austria Tech & Systemtechnik Ag | Placement of component in circuit board intermediate product by flowable adhesive layer on carrier substrate |
US10468363B2 (en) | 2015-08-10 | 2019-11-05 | X-Celeprint Limited | Chiplets with connection posts |
CN109314122B (zh) * | 2016-06-20 | 2023-06-16 | 索尼公司 | 半导体芯片封装件 |
US11064609B2 (en) | 2016-08-04 | 2021-07-13 | X Display Company Technology Limited | Printable 3D electronic structure |
US11469152B2 (en) | 2019-10-14 | 2022-10-11 | Mediatek Inc. | Semiconductor chip package and fabrication method thereof |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000077457A (ja) * | 1998-08-31 | 2000-03-14 | Hitachi Chem Co Ltd | 半導体装置、半導体実装用基板及び半導体装置の製造方法 |
JP2001156110A (ja) * | 1999-11-24 | 2001-06-08 | Omron Corp | 半導体チップの実装方法、並びに、電磁波読み取り可能なデータキャリアの製造方法 |
JP2003174060A (ja) * | 2001-09-27 | 2003-06-20 | Dt Circuit Technology Co Ltd | 半導体装置及びその製造方法 |
JP2004228162A (ja) * | 2003-01-20 | 2004-08-12 | Denso Corp | 電子制御装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08236586A (ja) * | 1994-12-29 | 1996-09-13 | Nitto Denko Corp | 半導体装置及びその製造方法 |
JP4078033B2 (ja) * | 1999-03-26 | 2008-04-23 | 株式会社ルネサステクノロジ | 半導体モジュールの実装方法 |
JP2000309105A (ja) * | 1999-04-27 | 2000-11-07 | Canon Inc | 液体収納容器、液体供給システムおよび前記液体収納容器の製造方法 |
US7034386B2 (en) * | 2001-03-26 | 2006-04-25 | Nec Corporation | Thin planar semiconductor device having electrodes on both surfaces and method of fabricating same |
JP4344952B2 (ja) * | 2003-10-06 | 2009-10-14 | 日本電気株式会社 | 電子デバイスおよびその製造方法 |
-
2006
- 2006-03-14 WO PCT/JP2006/304974 patent/WO2006109383A1/ja active Application Filing
- 2006-03-14 US US11/908,460 patent/US20090020870A1/en not_active Abandoned
- 2006-03-14 CN CN200680011442XA patent/CN101156237B/zh not_active Expired - Fee Related
- 2006-03-14 JP JP2007512417A patent/JPWO2006109383A1/ja active Pending
- 2006-03-14 CN CN2009101379993A patent/CN101567357B/zh not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000077457A (ja) * | 1998-08-31 | 2000-03-14 | Hitachi Chem Co Ltd | 半導体装置、半導体実装用基板及び半導体装置の製造方法 |
JP2001156110A (ja) * | 1999-11-24 | 2001-06-08 | Omron Corp | 半導体チップの実装方法、並びに、電磁波読み取り可能なデータキャリアの製造方法 |
JP2003174060A (ja) * | 2001-09-27 | 2003-06-20 | Dt Circuit Technology Co Ltd | 半導体装置及びその製造方法 |
JP2004228162A (ja) * | 2003-01-20 | 2004-08-12 | Denso Corp | 電子制御装置 |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE112007003083B4 (de) * | 2006-12-22 | 2019-05-09 | Tdk Corp. | Mikrofonbaugruppe mit Unterfüllmittel mit niedrigem Wärmeausdehnungskoeffizienten |
EP1981321A3 (en) * | 2007-04-09 | 2009-09-16 | Endicott Interconnect Technologies, Inc. | Circuitized substrate assembly with internal stacked semiconductor chips, method of making same, electrical assembly utilizing same and information handling system utilizing same |
JP2009177122A (ja) * | 2007-12-25 | 2009-08-06 | Hitachi Chem Co Ltd | 薄型接合体の製造方法及び薄型接合体 |
JP2009297950A (ja) * | 2008-06-11 | 2009-12-24 | Canon Inc | 液体吐出装置の製造方法及び液体吐出装置 |
JP2011222553A (ja) * | 2010-04-02 | 2011-11-04 | Denso Corp | 半導体チップ内蔵配線基板及びその製造方法 |
JP2013535093A (ja) * | 2010-05-20 | 2013-09-09 | エーファウ・グループ・エー・タルナー・ゲーエムベーハー | チップスタックを製造するための方法及びその方法を実施するためのキャリア |
US8932910B2 (en) | 2010-05-20 | 2015-01-13 | Ev Group E. Thallner Gmbh | Method for producing chip stacks, and a carrier for carrying out the method |
TWI661520B (zh) * | 2016-04-01 | 2019-06-01 | 愛爾蘭商艾克斯瑟樂普林特有限公司 | 藉由微轉印之壓力啟動電性互連 |
WO2019167194A1 (ja) * | 2018-02-28 | 2019-09-06 | オリンパス株式会社 | 超音波プローブ及び超音波処置具 |
WO2021242013A1 (ko) * | 2020-05-26 | 2021-12-02 | 엘지이노텍 주식회사 | 패키지 기판 |
Also Published As
Publication number | Publication date |
---|---|
CN101567357B (zh) | 2011-05-11 |
CN101156237B (zh) | 2011-01-19 |
US20090020870A1 (en) | 2009-01-22 |
CN101156237A (zh) | 2008-04-02 |
JPWO2006109383A1 (ja) | 2008-10-09 |
CN101567357A (zh) | 2009-10-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2006109383A1 (ja) | 配線基板を有する電子デバイス、その製造方法、および前記電子デバイスに用いられる配線基板 | |
JP5018826B2 (ja) | 電子デバイスおよびその製造方法 | |
JP5326281B2 (ja) | 半導体搭載用配線基板、その製造方法、及び半導体パッケージ | |
US7816782B2 (en) | Wiring substrate for mounting semiconductors, method of manufacturing the same, and semiconductor package | |
TWI437647B (zh) | 具有凸塊/基座/凸緣層散熱座及增層電路之散熱增益型半導體組體 | |
US8941016B2 (en) | Laminated wiring board and manufacturing method for same | |
US8642393B1 (en) | Package on package devices and methods of forming same | |
JP5262188B2 (ja) | 基板 | |
US9000573B2 (en) | Package on package structure and method for manufacturing same | |
US20070262470A1 (en) | Module With Built-In Semiconductor And Method For Manufacturing The Module | |
US10098243B2 (en) | Printed wiring board and semiconductor package | |
US9105616B2 (en) | External connection terminal, semiconductor package having external connection terminal, and methods for manufacturing the same | |
JP2017034059A (ja) | プリント配線板、半導体パッケージおよびプリント配線板の製造方法 | |
KR102647325B1 (ko) | 회로기판 및 이를 포함하는 반도체 패키지 | |
TW201947722A (zh) | 覆晶封裝基板 | |
JP5440650B2 (ja) | 基板の製造方法 | |
JP4942452B2 (ja) | 回路装置 | |
CN108305864B (zh) | 端子 | |
US9673063B2 (en) | Terminations | |
JP2015219878A (ja) | 複合icカード及びそれに用いる複合icカード用モジュール | |
KR102669579B1 (ko) | 인쇄회로기판 및 이를 포함하는 패키지 기판 | |
US20110211323A1 (en) | Circuit board, semiconductor device, and method of manufacturing the semiconductor device | |
JP2008235839A (ja) | 半導体装置およびその製造方法 | |
KR101651272B1 (ko) | 이방성 접착제를 이용하여 접속영역의 스트레스가 완화되는 연성 패키지 | |
JP2006019606A (ja) | 電子部品の製造方法および電子部品ならびにicカード |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200680011442.X Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 11908460 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2007512417 Country of ref document: JP |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
NENP | Non-entry into the national phase |
Ref country code: RU |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 06715636 Country of ref document: EP Kind code of ref document: A1 |