JP5326281B2 - 半導体搭載用配線基板、その製造方法、及び半導体パッケージ - Google Patents
半導体搭載用配線基板、その製造方法、及び半導体パッケージ Download PDFInfo
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- JP5326281B2 JP5326281B2 JP2007552901A JP2007552901A JP5326281B2 JP 5326281 B2 JP5326281 B2 JP 5326281B2 JP 2007552901 A JP2007552901 A JP 2007552901A JP 2007552901 A JP2007552901 A JP 2007552901A JP 5326281 B2 JP5326281 B2 JP 5326281B2
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- insulating layer
- wiring board
- substrate
- wiring
- semiconductor
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H05K1/02—Details
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- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0263—Details about a collection of particles
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
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- Production Of Multi-Layered Print Wiring Board (AREA)
Description
Claims (1)
- 絶縁膜と、前記絶縁膜中に形成された配線と、前記絶縁膜の表裏面において表面を露出して設けられ、且つ、その側面の少なくとも一部が前記絶縁膜に埋設されている複数個の電極パッドと、前記配線と前記電極パッドとを接続するビアとを有し、
前記絶縁膜中に形成された配線同士を接続する少なくとも1つのビアは、前記配線と前記電極パッドを接続するビアを形成する第1の材料とは異なる第2の材料を含み、
前記絶縁膜は、配線基板の表面に位置する第1の絶縁層と、配線基板の裏面に位置する第2の絶縁層と、配線基板の内部に位置する第3の絶縁層と、前記第1の絶縁層と前記第3の絶縁層との間及び前記第2の絶縁層と前記第3の絶縁層との間の少なくとも一方に設けられた第4の絶縁層とを有し、
前記第3の絶縁層には、前記第3の絶縁層の両表面に埋設された複数個の配線と、これらの配線を相互に接続するビアとが設けられ、
前記第4の絶縁層には、前記第4の絶縁層に埋設された配線と、ビアとが形成され、
前記第1の絶縁層、前記第2の絶縁層、前記第3の絶縁層、及び前記第4の絶縁層は、互いに異なる材料で形成される
半導体搭載用配線基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2007552901A JP5326281B2 (ja) | 2006-01-06 | 2006-12-20 | 半導体搭載用配線基板、その製造方法、及び半導体パッケージ |
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JP2006001921 | 2006-01-06 | ||
JP2006001921 | 2006-01-06 | ||
JP2007552901A JP5326281B2 (ja) | 2006-01-06 | 2006-12-20 | 半導体搭載用配線基板、その製造方法、及び半導体パッケージ |
PCT/JP2006/325348 WO2007077735A1 (ja) | 2006-01-06 | 2006-12-20 | 半導体搭載用配線基板、その製造方法、及び半導体パッケージ |
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JPWO2007077735A1 JPWO2007077735A1 (ja) | 2009-06-11 |
JP5326281B2 true JP5326281B2 (ja) | 2013-10-30 |
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US (1) | US20090046441A1 (ja) |
JP (1) | JP5326281B2 (ja) |
CN (1) | CN101356641B (ja) |
WO (1) | WO2007077735A1 (ja) |
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US6010768A (en) * | 1995-11-10 | 2000-01-04 | Ibiden Co., Ltd. | Multilayer printed circuit board, method of producing multilayer printed circuit board and resin filler |
US6207259B1 (en) * | 1998-11-02 | 2001-03-27 | Kyocera Corporation | Wiring board |
US20060180344A1 (en) * | 2003-01-20 | 2006-08-17 | Shoji Ito | Multilayer printed wiring board and process for producing the same |
JP4203435B2 (ja) * | 2003-05-16 | 2009-01-07 | 日本特殊陶業株式会社 | 多層樹脂配線基板 |
KR100619348B1 (ko) * | 2004-09-21 | 2006-09-12 | 삼성전기주식회사 | 무전해 니켈 도금을 이용한 패키지 기판의 제조 방법 |
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JP2004111536A (ja) * | 2002-09-17 | 2004-04-08 | Nec Electronics Corp | 多層配線基板の製造方法 |
JP2005050882A (ja) * | 2003-07-29 | 2005-02-24 | Kyocera Corp | 積層型配線基板および電気装置並びにその実装構造 |
JP2005294496A (ja) * | 2004-03-31 | 2005-10-20 | Matsushita Electric Ind Co Ltd | 配線基板の連結構造体及びその製造方法 |
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CN101356641A (zh) | 2009-01-28 |
WO2007077735A1 (ja) | 2007-07-12 |
CN101356641B (zh) | 2011-05-18 |
US20090046441A1 (en) | 2009-02-19 |
JPWO2007077735A1 (ja) | 2009-06-11 |
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